Commit | Line | Data |
---|---|---|
bde18a2e KI |
1 | /* |
2 | * Support for IDE interfaces on Celleb platform | |
3 | * | |
4 | * (C) Copyright 2006 TOSHIBA CORPORATION | |
5 | * | |
6 | * This code is based on drivers/ide/pci/siimage.c: | |
7 | * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org> | |
ccd32e22 | 8 | * Copyright (C) 2003 Red Hat |
bde18a2e KI |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License along | |
21 | * with this program; if not, write to the Free Software Foundation, Inc., | |
22 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | |
23 | */ | |
24 | ||
25 | #include <linux/types.h> | |
26 | #include <linux/module.h> | |
27 | #include <linux/pci.h> | |
28 | #include <linux/delay.h> | |
bde18a2e KI |
29 | #include <linux/ide.h> |
30 | #include <linux/init.h> | |
31 | ||
32 | #define PCI_DEVICE_ID_TOSHIBA_SCC_ATA 0x01b4 | |
33 | ||
34 | #define SCC_PATA_NAME "scc IDE" | |
35 | ||
36 | #define TDVHSEL_MASTER 0x00000001 | |
37 | #define TDVHSEL_SLAVE 0x00000004 | |
38 | ||
39 | #define MODE_JCUSFEN 0x00000080 | |
40 | ||
41 | #define CCKCTRL_ATARESET 0x00040000 | |
42 | #define CCKCTRL_BUFCNT 0x00020000 | |
43 | #define CCKCTRL_CRST 0x00010000 | |
44 | #define CCKCTRL_OCLKEN 0x00000100 | |
45 | #define CCKCTRL_ATACLKOEN 0x00000002 | |
46 | #define CCKCTRL_LCLKEN 0x00000001 | |
47 | ||
48 | #define QCHCD_IOS_SS 0x00000001 | |
49 | ||
50 | #define QCHSD_STPDIAG 0x00020000 | |
51 | ||
52 | #define INTMASK_MSK 0xD1000012 | |
53 | #define INTSTS_SERROR 0x80000000 | |
54 | #define INTSTS_PRERR 0x40000000 | |
55 | #define INTSTS_RERR 0x10000000 | |
56 | #define INTSTS_ICERR 0x01000000 | |
57 | #define INTSTS_BMSINT 0x00000010 | |
58 | #define INTSTS_BMHE 0x00000008 | |
59 | #define INTSTS_IOIRQS 0x00000004 | |
60 | #define INTSTS_INTRQ 0x00000002 | |
61 | #define INTSTS_ACTEINT 0x00000001 | |
62 | ||
63 | #define ECMODE_VALUE 0x01 | |
64 | ||
65 | static struct scc_ports { | |
66 | unsigned long ctl, dma; | |
48c3c107 | 67 | struct ide_host *host; /* for removing port from system */ |
bde18a2e KI |
68 | } scc_ports[MAX_HWIFS]; |
69 | ||
70 | /* PIO transfer mode table */ | |
71 | /* JCHST */ | |
72 | static unsigned long JCHSTtbl[2][7] = { | |
73 | {0x0E, 0x05, 0x02, 0x03, 0x02, 0x00, 0x00}, /* 100MHz */ | |
74 | {0x13, 0x07, 0x04, 0x04, 0x03, 0x00, 0x00} /* 133MHz */ | |
75 | }; | |
76 | ||
77 | /* JCHHT */ | |
78 | static unsigned long JCHHTtbl[2][7] = { | |
79 | {0x0E, 0x02, 0x02, 0x02, 0x02, 0x00, 0x00}, /* 100MHz */ | |
80 | {0x13, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00} /* 133MHz */ | |
81 | }; | |
82 | ||
83 | /* JCHCT */ | |
84 | static unsigned long JCHCTtbl[2][7] = { | |
85 | {0x1D, 0x1D, 0x1C, 0x0B, 0x06, 0x00, 0x00}, /* 100MHz */ | |
86 | {0x27, 0x26, 0x26, 0x0E, 0x09, 0x00, 0x00} /* 133MHz */ | |
87 | }; | |
88 | ||
89 | ||
90 | /* DMA transfer mode table */ | |
91 | /* JCHDCTM/JCHDCTS */ | |
92 | static unsigned long JCHDCTxtbl[2][7] = { | |
93 | {0x0A, 0x06, 0x04, 0x03, 0x01, 0x00, 0x00}, /* 100MHz */ | |
94 | {0x0E, 0x09, 0x06, 0x04, 0x02, 0x01, 0x00} /* 133MHz */ | |
95 | }; | |
96 | ||
97 | /* JCSTWTM/JCSTWTS */ | |
98 | static unsigned long JCSTWTxtbl[2][7] = { | |
99 | {0x06, 0x04, 0x03, 0x02, 0x02, 0x02, 0x00}, /* 100MHz */ | |
100 | {0x09, 0x06, 0x04, 0x02, 0x02, 0x02, 0x02} /* 133MHz */ | |
101 | }; | |
102 | ||
103 | /* JCTSS */ | |
104 | static unsigned long JCTSStbl[2][7] = { | |
105 | {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x00}, /* 100MHz */ | |
106 | {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05} /* 133MHz */ | |
107 | }; | |
108 | ||
109 | /* JCENVT */ | |
110 | static unsigned long JCENVTtbl[2][7] = { | |
111 | {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00}, /* 100MHz */ | |
112 | {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02} /* 133MHz */ | |
113 | }; | |
114 | ||
115 | /* JCACTSELS/JCACTSELM */ | |
116 | static unsigned long JCACTSELtbl[2][7] = { | |
117 | {0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00}, /* 100MHz */ | |
118 | {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01} /* 133MHz */ | |
119 | }; | |
120 | ||
121 | ||
122 | static u8 scc_ide_inb(unsigned long port) | |
123 | { | |
124 | u32 data = in_be32((void*)port); | |
125 | return (u8)data; | |
126 | } | |
127 | ||
c6dfa867 BZ |
128 | static void scc_exec_command(ide_hwif_t *hwif, u8 cmd) |
129 | { | |
130 | out_be32((void *)hwif->io_ports.command_addr, cmd); | |
131 | eieio(); | |
132 | in_be32((void *)(hwif->dma_base + 0x01c)); | |
133 | eieio(); | |
134 | } | |
135 | ||
b73c7ee2 BZ |
136 | static u8 scc_read_status(ide_hwif_t *hwif) |
137 | { | |
138 | return (u8)in_be32((void *)hwif->io_ports.status_addr); | |
139 | } | |
140 | ||
1f6d8a0f BZ |
141 | static u8 scc_read_altstatus(ide_hwif_t *hwif) |
142 | { | |
143 | return (u8)in_be32((void *)hwif->io_ports.ctl_addr); | |
144 | } | |
145 | ||
592b5315 | 146 | static u8 scc_dma_sff_read_status(ide_hwif_t *hwif) |
b2f951aa | 147 | { |
cab7f8ed | 148 | return (u8)in_be32((void *)(hwif->dma_base + 4)); |
b2f951aa BZ |
149 | } |
150 | ||
ecf3a31d | 151 | static void scc_write_devctl(ide_hwif_t *hwif, u8 ctl) |
6e6afb3b | 152 | { |
6e6afb3b BZ |
153 | out_be32((void *)hwif->io_ports.ctl_addr, ctl); |
154 | eieio(); | |
155 | in_be32((void *)(hwif->dma_base + 0x01c)); | |
156 | eieio(); | |
157 | } | |
158 | ||
bde18a2e KI |
159 | static void scc_ide_insw(unsigned long port, void *addr, u32 count) |
160 | { | |
161 | u16 *ptr = (u16 *)addr; | |
162 | while (count--) { | |
163 | *ptr++ = le16_to_cpu(in_be32((void*)port)); | |
164 | } | |
165 | } | |
166 | ||
167 | static void scc_ide_insl(unsigned long port, void *addr, u32 count) | |
168 | { | |
169 | u16 *ptr = (u16 *)addr; | |
170 | while (count--) { | |
171 | *ptr++ = le16_to_cpu(in_be32((void*)port)); | |
172 | *ptr++ = le16_to_cpu(in_be32((void*)port)); | |
173 | } | |
174 | } | |
175 | ||
176 | static void scc_ide_outb(u8 addr, unsigned long port) | |
177 | { | |
178 | out_be32((void*)port, addr); | |
179 | } | |
180 | ||
bde18a2e KI |
181 | static void |
182 | scc_ide_outsw(unsigned long port, void *addr, u32 count) | |
183 | { | |
184 | u16 *ptr = (u16 *)addr; | |
185 | while (count--) { | |
186 | out_be32((void*)port, cpu_to_le16(*ptr++)); | |
187 | } | |
188 | } | |
189 | ||
190 | static void | |
191 | scc_ide_outsl(unsigned long port, void *addr, u32 count) | |
192 | { | |
193 | u16 *ptr = (u16 *)addr; | |
194 | while (count--) { | |
195 | out_be32((void*)port, cpu_to_le16(*ptr++)); | |
196 | out_be32((void*)port, cpu_to_le16(*ptr++)); | |
197 | } | |
198 | } | |
199 | ||
bde18a2e | 200 | /** |
88b2b32b BZ |
201 | * scc_set_pio_mode - set host controller for PIO mode |
202 | * @drive: drive | |
203 | * @pio: PIO mode number | |
bde18a2e KI |
204 | * |
205 | * Load the timing settings for this device mode into the | |
206 | * controller. | |
207 | */ | |
208 | ||
88b2b32b | 209 | static void scc_set_pio_mode(ide_drive_t *drive, const u8 pio) |
bde18a2e | 210 | { |
898ec223 | 211 | ide_hwif_t *hwif = drive->hwif; |
bde18a2e KI |
212 | struct scc_ports *ports = ide_get_hwifdata(hwif); |
213 | unsigned long ctl_base = ports->ctl; | |
214 | unsigned long cckctrl_port = ctl_base + 0xff0; | |
215 | unsigned long piosht_port = ctl_base + 0x000; | |
216 | unsigned long pioct_port = ctl_base + 0x004; | |
217 | unsigned long reg; | |
bde18a2e KI |
218 | int offset; |
219 | ||
0ecdca26 | 220 | reg = in_be32((void __iomem *)cckctrl_port); |
bde18a2e KI |
221 | if (reg & CCKCTRL_ATACLKOEN) { |
222 | offset = 1; /* 133MHz */ | |
223 | } else { | |
224 | offset = 0; /* 100MHz */ | |
225 | } | |
3fcece66 | 226 | reg = JCHSTtbl[offset][pio] << 16 | JCHHTtbl[offset][pio]; |
0ecdca26 | 227 | out_be32((void __iomem *)piosht_port, reg); |
3fcece66 | 228 | reg = JCHCTtbl[offset][pio]; |
0ecdca26 | 229 | out_be32((void __iomem *)pioct_port, reg); |
3fcece66 | 230 | } |
bde18a2e | 231 | |
bde18a2e | 232 | /** |
88b2b32b BZ |
233 | * scc_set_dma_mode - set host controller for DMA mode |
234 | * @drive: drive | |
235 | * @speed: DMA mode | |
bde18a2e KI |
236 | * |
237 | * Load the timing settings for this device mode into the | |
238 | * controller. | |
239 | */ | |
240 | ||
88b2b32b | 241 | static void scc_set_dma_mode(ide_drive_t *drive, const u8 speed) |
bde18a2e | 242 | { |
898ec223 | 243 | ide_hwif_t *hwif = drive->hwif; |
bde18a2e KI |
244 | struct scc_ports *ports = ide_get_hwifdata(hwif); |
245 | unsigned long ctl_base = ports->ctl; | |
246 | unsigned long cckctrl_port = ctl_base + 0xff0; | |
247 | unsigned long mdmact_port = ctl_base + 0x008; | |
248 | unsigned long mcrcst_port = ctl_base + 0x00c; | |
249 | unsigned long sdmact_port = ctl_base + 0x010; | |
250 | unsigned long scrcst_port = ctl_base + 0x014; | |
251 | unsigned long udenvt_port = ctl_base + 0x018; | |
252 | unsigned long tdvhsel_port = ctl_base + 0x020; | |
5e7f3a46 | 253 | int is_slave = drive->dn & 1; |
bde18a2e KI |
254 | int offset, idx; |
255 | unsigned long reg; | |
256 | unsigned long jcactsel; | |
257 | ||
0ecdca26 | 258 | reg = in_be32((void __iomem *)cckctrl_port); |
bde18a2e KI |
259 | if (reg & CCKCTRL_ATACLKOEN) { |
260 | offset = 1; /* 133MHz */ | |
261 | } else { | |
262 | offset = 0; /* 100MHz */ | |
263 | } | |
264 | ||
4db90a14 | 265 | idx = speed - XFER_UDMA_0; |
bde18a2e KI |
266 | |
267 | jcactsel = JCACTSELtbl[offset][idx]; | |
268 | if (is_slave) { | |
0ecdca26 BZ |
269 | out_be32((void __iomem *)sdmact_port, JCHDCTxtbl[offset][idx]); |
270 | out_be32((void __iomem *)scrcst_port, JCSTWTxtbl[offset][idx]); | |
271 | jcactsel = jcactsel << 2; | |
272 | out_be32((void __iomem *)tdvhsel_port, (in_be32((void __iomem *)tdvhsel_port) & ~TDVHSEL_SLAVE) | jcactsel); | |
bde18a2e | 273 | } else { |
0ecdca26 BZ |
274 | out_be32((void __iomem *)mdmact_port, JCHDCTxtbl[offset][idx]); |
275 | out_be32((void __iomem *)mcrcst_port, JCSTWTxtbl[offset][idx]); | |
276 | out_be32((void __iomem *)tdvhsel_port, (in_be32((void __iomem *)tdvhsel_port) & ~TDVHSEL_MASTER) | jcactsel); | |
bde18a2e KI |
277 | } |
278 | reg = JCTSStbl[offset][idx] << 16 | JCENVTtbl[offset][idx]; | |
0ecdca26 | 279 | out_be32((void __iomem *)udenvt_port, reg); |
bde18a2e KI |
280 | } |
281 | ||
669185e9 BZ |
282 | static void scc_dma_host_set(ide_drive_t *drive, int on) |
283 | { | |
284 | ide_hwif_t *hwif = drive->hwif; | |
123995b9 | 285 | u8 unit = drive->dn & 1; |
c2ce5ca0 | 286 | u8 dma_stat = scc_dma_sff_read_status(hwif); |
669185e9 BZ |
287 | |
288 | if (on) | |
289 | dma_stat |= (1 << (5 + unit)); | |
290 | else | |
291 | dma_stat &= ~(1 << (5 + unit)); | |
292 | ||
cab7f8ed | 293 | scc_ide_outb(dma_stat, hwif->dma_base + 4); |
669185e9 BZ |
294 | } |
295 | ||
0ecdca26 | 296 | /** |
22981694 | 297 | * scc_dma_setup - begin a DMA phase |
0ecdca26 | 298 | * @drive: target device |
22981694 | 299 | * @cmd: command |
0ecdca26 BZ |
300 | * |
301 | * Build an IDE DMA PRD (IDE speak for scatter gather table) | |
302 | * and then set up the DMA transfer registers. | |
303 | * | |
304 | * Returns 0 on success. If a PIO fallback is required then 1 | |
305 | * is returned. | |
306 | */ | |
307 | ||
22981694 | 308 | static int scc_dma_setup(ide_drive_t *drive, struct ide_cmd *cmd) |
0ecdca26 BZ |
309 | { |
310 | ide_hwif_t *hwif = drive->hwif; | |
22981694 | 311 | u32 rw = (cmd->tf_flags & IDE_TFLAG_WRITE) ? 0 : ATA_DMA_WR; |
0ecdca26 BZ |
312 | u8 dma_stat; |
313 | ||
0ecdca26 | 314 | /* fall back to pio! */ |
11998b31 | 315 | if (ide_build_dmatable(drive, cmd) == 0) |
0ecdca26 | 316 | return 1; |
0ecdca26 BZ |
317 | |
318 | /* PRD table */ | |
55224bc8 | 319 | out_be32((void __iomem *)(hwif->dma_base + 8), hwif->dmatable_dma); |
0ecdca26 BZ |
320 | |
321 | /* specify r/w */ | |
22981694 | 322 | out_be32((void __iomem *)hwif->dma_base, rw); |
0ecdca26 | 323 | |
cab7f8ed | 324 | /* read DMA status for INTR & ERROR flags */ |
c2ce5ca0 | 325 | dma_stat = scc_dma_sff_read_status(hwif); |
0ecdca26 BZ |
326 | |
327 | /* clear INTR & ERROR flags */ | |
cab7f8ed | 328 | out_be32((void __iomem *)(hwif->dma_base + 4), dma_stat | 6); |
88b4132e | 329 | |
0ecdca26 BZ |
330 | return 0; |
331 | } | |
332 | ||
669185e9 BZ |
333 | static void scc_dma_start(ide_drive_t *drive) |
334 | { | |
335 | ide_hwif_t *hwif = drive->hwif; | |
cab7f8ed | 336 | u8 dma_cmd = scc_ide_inb(hwif->dma_base); |
669185e9 BZ |
337 | |
338 | /* start DMA */ | |
cab7f8ed | 339 | scc_ide_outb(dma_cmd | 1, hwif->dma_base); |
669185e9 BZ |
340 | wmb(); |
341 | } | |
342 | ||
343 | static int __scc_dma_end(ide_drive_t *drive) | |
344 | { | |
345 | ide_hwif_t *hwif = drive->hwif; | |
346 | u8 dma_stat, dma_cmd; | |
347 | ||
669185e9 | 348 | /* get DMA command mode */ |
cab7f8ed | 349 | dma_cmd = scc_ide_inb(hwif->dma_base); |
669185e9 | 350 | /* stop DMA */ |
cab7f8ed | 351 | scc_ide_outb(dma_cmd & ~1, hwif->dma_base); |
669185e9 | 352 | /* get DMA status */ |
c2ce5ca0 | 353 | dma_stat = scc_dma_sff_read_status(hwif); |
669185e9 | 354 | /* clear the INTR & ERROR bits */ |
cab7f8ed | 355 | scc_ide_outb(dma_stat | 6, hwif->dma_base + 4); |
669185e9 | 356 | /* verify good DMA status */ |
669185e9 BZ |
357 | wmb(); |
358 | return (dma_stat & 7) != 4 ? (0x10 | dma_stat) : 0; | |
359 | } | |
0ecdca26 | 360 | |
bde18a2e | 361 | /** |
5e37bdc0 | 362 | * scc_dma_end - Stop DMA |
bde18a2e KI |
363 | * @drive: IDE drive |
364 | * | |
365 | * Check and clear INT Status register. | |
669185e9 | 366 | * Then call __scc_dma_end(). |
bde18a2e KI |
367 | */ |
368 | ||
5e37bdc0 | 369 | static int scc_dma_end(ide_drive_t *drive) |
bde18a2e | 370 | { |
898ec223 | 371 | ide_hwif_t *hwif = drive->hwif; |
cab7f8ed | 372 | void __iomem *dma_base = (void __iomem *)hwif->dma_base; |
bde18a2e KI |
373 | unsigned long intsts_port = hwif->dma_base + 0x014; |
374 | u32 reg; | |
4ae41ff8 KI |
375 | int dma_stat, data_loss = 0; |
376 | static int retry = 0; | |
377 | ||
378 | /* errata A308 workaround: Step5 (check data loss) */ | |
379 | /* We don't check non ide_disk because it is limited to UDMA4 */ | |
4c3032d8 | 380 | if (!(in_be32((void __iomem *)hwif->io_ports.ctl_addr) |
3a7d2484 | 381 | & ATA_ERR) && |
4ae41ff8 KI |
382 | drive->media == ide_disk && drive->current_speed > XFER_UDMA_4) { |
383 | reg = in_be32((void __iomem *)intsts_port); | |
384 | if (!(reg & INTSTS_ACTEINT)) { | |
385 | printk(KERN_WARNING "%s: operation failed (transfer data loss)\n", | |
386 | drive->name); | |
387 | data_loss = 1; | |
388 | if (retry++) { | |
b65fac32 | 389 | struct request *rq = hwif->rq; |
2bd24a1c BZ |
390 | ide_drive_t *drive; |
391 | int i; | |
392 | ||
4ae41ff8 KI |
393 | /* ERROR_RESET and drive->crc_count are needed |
394 | * to reduce DMA transfer mode in retry process. | |
395 | */ | |
396 | if (rq) | |
397 | rq->errors |= ERROR_RESET; | |
5e7f3a46 | 398 | |
2bd24a1c | 399 | ide_port_for_each_dev(i, drive, hwif) |
4ae41ff8 | 400 | drive->crc_count++; |
4ae41ff8 KI |
401 | } |
402 | } | |
403 | } | |
bde18a2e KI |
404 | |
405 | while (1) { | |
0ecdca26 | 406 | reg = in_be32((void __iomem *)intsts_port); |
bde18a2e KI |
407 | |
408 | if (reg & INTSTS_SERROR) { | |
409 | printk(KERN_WARNING "%s: SERROR\n", SCC_PATA_NAME); | |
0ecdca26 | 410 | out_be32((void __iomem *)intsts_port, INTSTS_SERROR|INTSTS_BMSINT); |
bde18a2e | 411 | |
cab7f8ed | 412 | out_be32(dma_base, in_be32(dma_base) & ~QCHCD_IOS_SS); |
bde18a2e KI |
413 | continue; |
414 | } | |
415 | ||
416 | if (reg & INTSTS_PRERR) { | |
417 | u32 maea0, maec0; | |
418 | unsigned long ctl_base = hwif->config_data; | |
419 | ||
0ecdca26 BZ |
420 | maea0 = in_be32((void __iomem *)(ctl_base + 0xF50)); |
421 | maec0 = in_be32((void __iomem *)(ctl_base + 0xF54)); | |
bde18a2e KI |
422 | |
423 | printk(KERN_WARNING "%s: PRERR [addr:%x cmd:%x]\n", SCC_PATA_NAME, maea0, maec0); | |
424 | ||
0ecdca26 | 425 | out_be32((void __iomem *)intsts_port, INTSTS_PRERR|INTSTS_BMSINT); |
bde18a2e | 426 | |
cab7f8ed | 427 | out_be32(dma_base, in_be32(dma_base) & ~QCHCD_IOS_SS); |
bde18a2e KI |
428 | continue; |
429 | } | |
430 | ||
431 | if (reg & INTSTS_RERR) { | |
432 | printk(KERN_WARNING "%s: Response Error\n", SCC_PATA_NAME); | |
0ecdca26 | 433 | out_be32((void __iomem *)intsts_port, INTSTS_RERR|INTSTS_BMSINT); |
bde18a2e | 434 | |
cab7f8ed | 435 | out_be32(dma_base, in_be32(dma_base) & ~QCHCD_IOS_SS); |
bde18a2e KI |
436 | continue; |
437 | } | |
438 | ||
439 | if (reg & INTSTS_ICERR) { | |
cab7f8ed | 440 | out_be32(dma_base, in_be32(dma_base) & ~QCHCD_IOS_SS); |
bde18a2e KI |
441 | |
442 | printk(KERN_WARNING "%s: Illegal Configuration\n", SCC_PATA_NAME); | |
0ecdca26 | 443 | out_be32((void __iomem *)intsts_port, INTSTS_ICERR|INTSTS_BMSINT); |
bde18a2e KI |
444 | continue; |
445 | } | |
446 | ||
447 | if (reg & INTSTS_BMSINT) { | |
448 | printk(KERN_WARNING "%s: Internal Bus Error\n", SCC_PATA_NAME); | |
0ecdca26 | 449 | out_be32((void __iomem *)intsts_port, INTSTS_BMSINT); |
bde18a2e KI |
450 | |
451 | ide_do_reset(drive); | |
452 | continue; | |
453 | } | |
454 | ||
455 | if (reg & INTSTS_BMHE) { | |
0ecdca26 | 456 | out_be32((void __iomem *)intsts_port, INTSTS_BMHE); |
bde18a2e KI |
457 | continue; |
458 | } | |
459 | ||
460 | if (reg & INTSTS_ACTEINT) { | |
0ecdca26 | 461 | out_be32((void __iomem *)intsts_port, INTSTS_ACTEINT); |
bde18a2e KI |
462 | continue; |
463 | } | |
464 | ||
465 | if (reg & INTSTS_IOIRQS) { | |
0ecdca26 | 466 | out_be32((void __iomem *)intsts_port, INTSTS_IOIRQS); |
bde18a2e KI |
467 | continue; |
468 | } | |
469 | break; | |
470 | } | |
471 | ||
669185e9 | 472 | dma_stat = __scc_dma_end(drive); |
4ae41ff8 KI |
473 | if (data_loss) |
474 | dma_stat |= 2; /* emulate DMA error (to retry command) */ | |
475 | return dma_stat; | |
bde18a2e KI |
476 | } |
477 | ||
06a9952b AI |
478 | /* returns 1 if dma irq issued, 0 otherwise */ |
479 | static int scc_dma_test_irq(ide_drive_t *drive) | |
480 | { | |
898ec223 | 481 | ide_hwif_t *hwif = drive->hwif; |
4ae41ff8 | 482 | u32 int_stat = in_be32((void __iomem *)hwif->dma_base + 0x014); |
06a9952b | 483 | |
4ae41ff8 | 484 | /* SCC errata A252,A308 workaround: Step4 */ |
4c3032d8 | 485 | if ((in_be32((void __iomem *)hwif->io_ports.ctl_addr) |
3a7d2484 | 486 | & ATA_ERR) && |
4ae41ff8 | 487 | (int_stat & INTSTS_INTRQ)) |
06a9952b AI |
488 | return 1; |
489 | ||
4ae41ff8 KI |
490 | /* SCC errata A308 workaround: Step5 (polling IOIRQS) */ |
491 | if (int_stat & INTSTS_IOIRQS) | |
06a9952b AI |
492 | return 1; |
493 | ||
06a9952b AI |
494 | return 0; |
495 | } | |
496 | ||
4ae41ff8 KI |
497 | static u8 scc_udma_filter(ide_drive_t *drive) |
498 | { | |
499 | ide_hwif_t *hwif = drive->hwif; | |
500 | u8 mask = hwif->ultra_mask; | |
501 | ||
502 | /* errata A308 workaround: limit non ide_disk drive to UDMA4 */ | |
503 | if ((drive->media != ide_disk) && (mask & 0xE0)) { | |
504 | printk(KERN_INFO "%s: limit %s to UDMA4\n", | |
505 | SCC_PATA_NAME, drive->name); | |
5f8b6c34 | 506 | mask = ATA_UDMA4; |
4ae41ff8 KI |
507 | } |
508 | ||
509 | return mask; | |
510 | } | |
511 | ||
bde18a2e KI |
512 | /** |
513 | * setup_mmio_scc - map CTRL/BMID region | |
514 | * @dev: PCI device we are configuring | |
515 | * @name: device name | |
516 | * | |
517 | */ | |
518 | ||
519 | static int setup_mmio_scc (struct pci_dev *dev, const char *name) | |
520 | { | |
0bd8496b AV |
521 | void __iomem *ctl_addr; |
522 | void __iomem *dma_addr; | |
0d1bad21 | 523 | int i, ret; |
bde18a2e KI |
524 | |
525 | for (i = 0; i < MAX_HWIFS; i++) { | |
526 | if (scc_ports[i].ctl == 0) | |
527 | break; | |
528 | } | |
529 | if (i >= MAX_HWIFS) | |
530 | return -ENOMEM; | |
531 | ||
0d1bad21 BZ |
532 | ret = pci_request_selected_regions(dev, (1 << 2) - 1, name); |
533 | if (ret < 0) { | |
534 | printk(KERN_ERR "%s: can't reserve resources\n", name); | |
535 | return ret; | |
bde18a2e KI |
536 | } |
537 | ||
1f1ab274 AV |
538 | ctl_addr = pci_ioremap_bar(dev, 0); |
539 | if (!ctl_addr) | |
0d1bad21 | 540 | goto fail_0; |
bde18a2e | 541 | |
1f1ab274 AV |
542 | dma_addr = pci_ioremap_bar(dev, 1); |
543 | if (!dma_addr) | |
0d1bad21 | 544 | goto fail_1; |
bde18a2e KI |
545 | |
546 | pci_set_master(dev); | |
547 | scc_ports[i].ctl = (unsigned long)ctl_addr; | |
548 | scc_ports[i].dma = (unsigned long)dma_addr; | |
549 | pci_set_drvdata(dev, (void *) &scc_ports[i]); | |
550 | ||
551 | return 1; | |
552 | ||
bde18a2e | 553 | fail_1: |
0d1bad21 | 554 | iounmap(ctl_addr); |
bde18a2e KI |
555 | fail_0: |
556 | return -ENOMEM; | |
557 | } | |
558 | ||
3d53ba87 AI |
559 | static int scc_ide_setup_pci_device(struct pci_dev *dev, |
560 | const struct ide_port_info *d) | |
561 | { | |
562 | struct scc_ports *ports = pci_get_drvdata(dev); | |
48c3c107 | 563 | struct ide_host *host; |
c97c6aca | 564 | hw_regs_t hw, *hws[] = { &hw, NULL, NULL, NULL }; |
6f904d01 | 565 | int i, rc; |
3d53ba87 | 566 | |
3d53ba87 | 567 | memset(&hw, 0, sizeof(hw)); |
4c3032d8 BZ |
568 | for (i = 0; i <= 8; i++) |
569 | hw.io_ports_array[i] = ports->dma + 0x20 + i * 4; | |
3d53ba87 AI |
570 | hw.irq = dev->irq; |
571 | hw.dev = &dev->dev; | |
572 | hw.chipset = ide_pci; | |
3d53ba87 | 573 | |
6f904d01 BZ |
574 | rc = ide_host_add(d, hws, &host); |
575 | if (rc) | |
576 | return rc; | |
48c3c107 BZ |
577 | |
578 | ports->host = host; | |
3d53ba87 AI |
579 | |
580 | return 0; | |
581 | } | |
582 | ||
bde18a2e KI |
583 | /** |
584 | * init_setup_scc - set up an SCC PATA Controller | |
585 | * @dev: PCI device | |
039788e1 | 586 | * @d: IDE port info |
bde18a2e KI |
587 | * |
588 | * Perform the initial set up for this device. | |
589 | */ | |
590 | ||
039788e1 | 591 | static int __devinit init_setup_scc(struct pci_dev *dev, |
85620436 | 592 | const struct ide_port_info *d) |
bde18a2e KI |
593 | { |
594 | unsigned long ctl_base; | |
595 | unsigned long dma_base; | |
596 | unsigned long cckctrl_port; | |
597 | unsigned long intmask_port; | |
598 | unsigned long mode_port; | |
599 | unsigned long ecmode_port; | |
bde18a2e KI |
600 | u32 reg = 0; |
601 | struct scc_ports *ports; | |
602 | int rc; | |
603 | ||
3d53ba87 AI |
604 | rc = pci_enable_device(dev); |
605 | if (rc) | |
606 | goto end; | |
607 | ||
bde18a2e | 608 | rc = setup_mmio_scc(dev, d->name); |
3d53ba87 AI |
609 | if (rc < 0) |
610 | goto end; | |
bde18a2e KI |
611 | |
612 | ports = pci_get_drvdata(dev); | |
613 | ctl_base = ports->ctl; | |
614 | dma_base = ports->dma; | |
615 | cckctrl_port = ctl_base + 0xff0; | |
616 | intmask_port = dma_base + 0x010; | |
617 | mode_port = ctl_base + 0x024; | |
618 | ecmode_port = ctl_base + 0xf00; | |
bde18a2e KI |
619 | |
620 | /* controller initialization */ | |
621 | reg = 0; | |
622 | out_be32((void*)cckctrl_port, reg); | |
623 | reg |= CCKCTRL_ATACLKOEN; | |
624 | out_be32((void*)cckctrl_port, reg); | |
625 | reg |= CCKCTRL_LCLKEN | CCKCTRL_OCLKEN; | |
626 | out_be32((void*)cckctrl_port, reg); | |
627 | reg |= CCKCTRL_CRST; | |
628 | out_be32((void*)cckctrl_port, reg); | |
629 | ||
630 | for (;;) { | |
631 | reg = in_be32((void*)cckctrl_port); | |
632 | if (reg & CCKCTRL_CRST) | |
633 | break; | |
634 | udelay(5000); | |
635 | } | |
636 | ||
637 | reg |= CCKCTRL_ATARESET; | |
638 | out_be32((void*)cckctrl_port, reg); | |
639 | ||
640 | out_be32((void*)ecmode_port, ECMODE_VALUE); | |
641 | out_be32((void*)mode_port, MODE_JCUSFEN); | |
642 | out_be32((void*)intmask_port, INTMASK_MSK); | |
643 | ||
3d53ba87 AI |
644 | rc = scc_ide_setup_pci_device(dev, d); |
645 | ||
646 | end: | |
647 | return rc; | |
bde18a2e KI |
648 | } |
649 | ||
22aa4b32 | 650 | static void scc_tf_load(ide_drive_t *drive, struct ide_cmd *cmd) |
db2432c4 BZ |
651 | { |
652 | struct ide_io_ports *io_ports = &drive->hwif->io_ports; | |
22aa4b32 BZ |
653 | struct ide_taskfile *tf = &cmd->tf; |
654 | u8 HIHI = (cmd->tf_flags & IDE_TFLAG_LBA48) ? 0xE0 : 0xEF; | |
db2432c4 | 655 | |
22aa4b32 | 656 | if (cmd->ftf_flags & IDE_FTFLAG_FLAGGED) |
db2432c4 BZ |
657 | HIHI = 0xFF; |
658 | ||
22aa4b32 | 659 | if (cmd->ftf_flags & IDE_FTFLAG_OUT_DATA) |
7c0daf26 BZ |
660 | out_be32((void *)io_ports->data_addr, |
661 | (tf->hob_data << 8) | tf->data); | |
db2432c4 | 662 | |
22aa4b32 | 663 | if (cmd->tf_flags & IDE_TFLAG_OUT_HOB_FEATURE) |
db2432c4 | 664 | scc_ide_outb(tf->hob_feature, io_ports->feature_addr); |
22aa4b32 | 665 | if (cmd->tf_flags & IDE_TFLAG_OUT_HOB_NSECT) |
db2432c4 | 666 | scc_ide_outb(tf->hob_nsect, io_ports->nsect_addr); |
22aa4b32 | 667 | if (cmd->tf_flags & IDE_TFLAG_OUT_HOB_LBAL) |
db2432c4 | 668 | scc_ide_outb(tf->hob_lbal, io_ports->lbal_addr); |
22aa4b32 | 669 | if (cmd->tf_flags & IDE_TFLAG_OUT_HOB_LBAM) |
db2432c4 | 670 | scc_ide_outb(tf->hob_lbam, io_ports->lbam_addr); |
22aa4b32 | 671 | if (cmd->tf_flags & IDE_TFLAG_OUT_HOB_LBAH) |
db2432c4 BZ |
672 | scc_ide_outb(tf->hob_lbah, io_ports->lbah_addr); |
673 | ||
22aa4b32 | 674 | if (cmd->tf_flags & IDE_TFLAG_OUT_FEATURE) |
db2432c4 | 675 | scc_ide_outb(tf->feature, io_ports->feature_addr); |
22aa4b32 | 676 | if (cmd->tf_flags & IDE_TFLAG_OUT_NSECT) |
db2432c4 | 677 | scc_ide_outb(tf->nsect, io_ports->nsect_addr); |
22aa4b32 | 678 | if (cmd->tf_flags & IDE_TFLAG_OUT_LBAL) |
db2432c4 | 679 | scc_ide_outb(tf->lbal, io_ports->lbal_addr); |
22aa4b32 | 680 | if (cmd->tf_flags & IDE_TFLAG_OUT_LBAM) |
db2432c4 | 681 | scc_ide_outb(tf->lbam, io_ports->lbam_addr); |
22aa4b32 | 682 | if (cmd->tf_flags & IDE_TFLAG_OUT_LBAH) |
db2432c4 BZ |
683 | scc_ide_outb(tf->lbah, io_ports->lbah_addr); |
684 | ||
22aa4b32 | 685 | if (cmd->tf_flags & IDE_TFLAG_OUT_DEVICE) |
7f612f27 | 686 | scc_ide_outb((tf->device & HIHI) | drive->select, |
db2432c4 BZ |
687 | io_ports->device_addr); |
688 | } | |
689 | ||
22aa4b32 | 690 | static void scc_tf_read(ide_drive_t *drive, struct ide_cmd *cmd) |
db2432c4 BZ |
691 | { |
692 | struct ide_io_ports *io_ports = &drive->hwif->io_ports; | |
22aa4b32 | 693 | struct ide_taskfile *tf = &cmd->tf; |
db2432c4 | 694 | |
22aa4b32 | 695 | if (cmd->ftf_flags & IDE_FTFLAG_IN_DATA) { |
7c0daf26 | 696 | u16 data = (u16)in_be32((void *)io_ports->data_addr); |
db2432c4 BZ |
697 | |
698 | tf->data = data & 0xff; | |
699 | tf->hob_data = (data >> 8) & 0xff; | |
700 | } | |
701 | ||
702 | /* be sure we're looking at the low order bits */ | |
4d74c3fc | 703 | scc_ide_outb(ATA_DEVCTL_OBS, io_ports->ctl_addr); |
db2432c4 | 704 | |
22aa4b32 | 705 | if (cmd->tf_flags & IDE_TFLAG_IN_FEATURE) |
92eb4380 | 706 | tf->feature = scc_ide_inb(io_ports->feature_addr); |
22aa4b32 | 707 | if (cmd->tf_flags & IDE_TFLAG_IN_NSECT) |
db2432c4 | 708 | tf->nsect = scc_ide_inb(io_ports->nsect_addr); |
22aa4b32 | 709 | if (cmd->tf_flags & IDE_TFLAG_IN_LBAL) |
db2432c4 | 710 | tf->lbal = scc_ide_inb(io_ports->lbal_addr); |
22aa4b32 | 711 | if (cmd->tf_flags & IDE_TFLAG_IN_LBAM) |
db2432c4 | 712 | tf->lbam = scc_ide_inb(io_ports->lbam_addr); |
22aa4b32 | 713 | if (cmd->tf_flags & IDE_TFLAG_IN_LBAH) |
db2432c4 | 714 | tf->lbah = scc_ide_inb(io_ports->lbah_addr); |
22aa4b32 | 715 | if (cmd->tf_flags & IDE_TFLAG_IN_DEVICE) |
db2432c4 BZ |
716 | tf->device = scc_ide_inb(io_ports->device_addr); |
717 | ||
22aa4b32 | 718 | if (cmd->tf_flags & IDE_TFLAG_LBA48) { |
4d74c3fc | 719 | scc_ide_outb(ATA_HOB | ATA_DEVCTL_OBS, io_ports->ctl_addr); |
db2432c4 | 720 | |
22aa4b32 | 721 | if (cmd->tf_flags & IDE_TFLAG_IN_HOB_FEATURE) |
db2432c4 | 722 | tf->hob_feature = scc_ide_inb(io_ports->feature_addr); |
22aa4b32 | 723 | if (cmd->tf_flags & IDE_TFLAG_IN_HOB_NSECT) |
db2432c4 | 724 | tf->hob_nsect = scc_ide_inb(io_ports->nsect_addr); |
22aa4b32 | 725 | if (cmd->tf_flags & IDE_TFLAG_IN_HOB_LBAL) |
db2432c4 | 726 | tf->hob_lbal = scc_ide_inb(io_ports->lbal_addr); |
22aa4b32 | 727 | if (cmd->tf_flags & IDE_TFLAG_IN_HOB_LBAM) |
db2432c4 | 728 | tf->hob_lbam = scc_ide_inb(io_ports->lbam_addr); |
22aa4b32 | 729 | if (cmd->tf_flags & IDE_TFLAG_IN_HOB_LBAH) |
db2432c4 BZ |
730 | tf->hob_lbah = scc_ide_inb(io_ports->lbah_addr); |
731 | } | |
732 | } | |
733 | ||
adb1af98 | 734 | static void scc_input_data(ide_drive_t *drive, struct ide_cmd *cmd, |
efa3db1b BZ |
735 | void *buf, unsigned int len) |
736 | { | |
737 | unsigned long data_addr = drive->hwif->io_ports.data_addr; | |
738 | ||
739 | len++; | |
740 | ||
741 | if (drive->io_32bit) { | |
742 | scc_ide_insl(data_addr, buf, len / 4); | |
743 | ||
744 | if ((len & 3) >= 2) | |
745 | scc_ide_insw(data_addr, (u8 *)buf + (len & ~3), 1); | |
746 | } else | |
747 | scc_ide_insw(data_addr, buf, len / 2); | |
748 | } | |
749 | ||
adb1af98 | 750 | static void scc_output_data(ide_drive_t *drive, struct ide_cmd *cmd, |
efa3db1b BZ |
751 | void *buf, unsigned int len) |
752 | { | |
753 | unsigned long data_addr = drive->hwif->io_ports.data_addr; | |
754 | ||
755 | len++; | |
756 | ||
757 | if (drive->io_32bit) { | |
758 | scc_ide_outsl(data_addr, buf, len / 4); | |
759 | ||
760 | if ((len & 3) >= 2) | |
761 | scc_ide_outsw(data_addr, (u8 *)buf + (len & ~3), 1); | |
762 | } else | |
763 | scc_ide_outsw(data_addr, buf, len / 2); | |
764 | } | |
765 | ||
bde18a2e KI |
766 | /** |
767 | * init_mmio_iops_scc - set up the iops for MMIO | |
768 | * @hwif: interface to set up | |
769 | * | |
770 | */ | |
771 | ||
772 | static void __devinit init_mmio_iops_scc(ide_hwif_t *hwif) | |
773 | { | |
36501650 | 774 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
bde18a2e KI |
775 | struct scc_ports *ports = pci_get_drvdata(dev); |
776 | unsigned long dma_base = ports->dma; | |
777 | ||
778 | ide_set_hwifdata(hwif, ports); | |
779 | ||
bde18a2e KI |
780 | hwif->dma_base = dma_base; |
781 | hwif->config_data = ports->ctl; | |
bde18a2e KI |
782 | } |
783 | ||
784 | /** | |
785 | * init_iops_scc - set up iops | |
786 | * @hwif: interface to set up | |
787 | * | |
788 | * Do the basic setup for the SCC hardware interface | |
789 | * and then do the MMIO setup. | |
790 | */ | |
791 | ||
792 | static void __devinit init_iops_scc(ide_hwif_t *hwif) | |
793 | { | |
36501650 BZ |
794 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
795 | ||
bde18a2e KI |
796 | hwif->hwif_data = NULL; |
797 | if (pci_get_drvdata(dev) == NULL) | |
798 | return; | |
799 | init_mmio_iops_scc(hwif); | |
800 | } | |
801 | ||
2bbd57ca BZ |
802 | static int __devinit scc_init_dma(ide_hwif_t *hwif, |
803 | const struct ide_port_info *d) | |
804 | { | |
805 | return ide_allocate_dma_engine(hwif); | |
806 | } | |
807 | ||
f454cbe8 | 808 | static u8 scc_cable_detect(ide_hwif_t *hwif) |
b4d1c73d BZ |
809 | { |
810 | return ATA_CBL_PATA80; | |
811 | } | |
812 | ||
bde18a2e KI |
813 | /** |
814 | * init_hwif_scc - set up hwif | |
815 | * @hwif: interface to set up | |
816 | * | |
817 | * We do the basic set up of the interface structure. The SCC | |
818 | * requires several custom handlers so we override the default | |
819 | * ide DMA handlers appropriately. | |
820 | */ | |
821 | ||
822 | static void __devinit init_hwif_scc(ide_hwif_t *hwif) | |
823 | { | |
0ecdca26 BZ |
824 | /* PTERADD */ |
825 | out_be32((void __iomem *)(hwif->dma_base + 0x018), hwif->dmatable_dma); | |
bde18a2e | 826 | |
5f8b6c34 BZ |
827 | if (in_be32((void __iomem *)(hwif->config_data + 0xff0)) & CCKCTRL_ATACLKOEN) |
828 | hwif->ultra_mask = ATA_UDMA6; /* 133MHz */ | |
829 | else | |
830 | hwif->ultra_mask = ATA_UDMA5; /* 100MHz */ | |
bde18a2e KI |
831 | } |
832 | ||
374e042c BZ |
833 | static const struct ide_tp_ops scc_tp_ops = { |
834 | .exec_command = scc_exec_command, | |
835 | .read_status = scc_read_status, | |
836 | .read_altstatus = scc_read_altstatus, | |
ecf3a31d | 837 | .write_devctl = scc_write_devctl, |
374e042c BZ |
838 | |
839 | .tf_load = scc_tf_load, | |
840 | .tf_read = scc_tf_read, | |
841 | ||
842 | .input_data = scc_input_data, | |
843 | .output_data = scc_output_data, | |
844 | }; | |
845 | ||
ac95beed BZ |
846 | static const struct ide_port_ops scc_port_ops = { |
847 | .set_pio_mode = scc_set_pio_mode, | |
848 | .set_dma_mode = scc_set_dma_mode, | |
849 | .udma_filter = scc_udma_filter, | |
850 | .cable_detect = scc_cable_detect, | |
851 | }; | |
852 | ||
f37afdac | 853 | static const struct ide_dma_ops scc_dma_ops = { |
669185e9 | 854 | .dma_host_set = scc_dma_host_set, |
5e37bdc0 | 855 | .dma_setup = scc_dma_setup, |
669185e9 | 856 | .dma_start = scc_dma_start, |
5e37bdc0 BZ |
857 | .dma_end = scc_dma_end, |
858 | .dma_test_irq = scc_dma_test_irq, | |
f37afdac | 859 | .dma_lost_irq = ide_dma_lost_irq, |
22117d6e | 860 | .dma_timer_expiry = ide_dma_sff_timer_expiry, |
592b5315 | 861 | .dma_sff_read_status = scc_dma_sff_read_status, |
5e37bdc0 BZ |
862 | }; |
863 | ||
304ffd6d BZ |
864 | static const struct ide_port_info scc_chipset __devinitdata = { |
865 | .name = "sccIDE", | |
866 | .init_iops = init_iops_scc, | |
867 | .init_dma = scc_init_dma, | |
868 | .init_hwif = init_hwif_scc, | |
869 | .tp_ops = &scc_tp_ops, | |
870 | .port_ops = &scc_port_ops, | |
871 | .dma_ops = &scc_dma_ops, | |
872 | .host_flags = IDE_HFLAG_SINGLE, | |
255115fb | 873 | .irq_flags = IRQF_SHARED, |
304ffd6d | 874 | .pio_mask = ATA_PIO4, |
bde18a2e KI |
875 | }; |
876 | ||
877 | /** | |
878 | * scc_init_one - pci layer discovery entry | |
879 | * @dev: PCI device | |
880 | * @id: ident table entry | |
881 | * | |
882 | * Called by the PCI code when it finds an SCC PATA controller. | |
883 | * We then use the IDE PCI generic helper to do most of the work. | |
884 | */ | |
885 | ||
886 | static int __devinit scc_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
887 | { | |
304ffd6d | 888 | return init_setup_scc(dev, &scc_chipset); |
bde18a2e KI |
889 | } |
890 | ||
891 | /** | |
892 | * scc_remove - pci layer remove entry | |
893 | * @dev: PCI device | |
894 | * | |
895 | * Called by the PCI code when it removes an SCC PATA controller. | |
896 | */ | |
897 | ||
898 | static void __devexit scc_remove(struct pci_dev *dev) | |
899 | { | |
900 | struct scc_ports *ports = pci_get_drvdata(dev); | |
48c3c107 | 901 | struct ide_host *host = ports->host; |
bde18a2e | 902 | |
48c3c107 | 903 | ide_host_remove(host); |
bde18a2e | 904 | |
bde18a2e KI |
905 | iounmap((void*)ports->dma); |
906 | iounmap((void*)ports->ctl); | |
0d1bad21 | 907 | pci_release_selected_regions(dev, (1 << 2) - 1); |
bde18a2e KI |
908 | memset(ports, 0, sizeof(*ports)); |
909 | } | |
910 | ||
9cbcc5e3 BZ |
911 | static const struct pci_device_id scc_pci_tbl[] = { |
912 | { PCI_VDEVICE(TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_SCC_ATA), 0 }, | |
bde18a2e KI |
913 | { 0, }, |
914 | }; | |
915 | MODULE_DEVICE_TABLE(pci, scc_pci_tbl); | |
916 | ||
a9ab09e2 | 917 | static struct pci_driver scc_pci_driver = { |
bde18a2e KI |
918 | .name = "SCC IDE", |
919 | .id_table = scc_pci_tbl, | |
920 | .probe = scc_init_one, | |
a69999e2 | 921 | .remove = __devexit_p(scc_remove), |
bde18a2e KI |
922 | }; |
923 | ||
924 | static int scc_ide_init(void) | |
925 | { | |
a9ab09e2 | 926 | return ide_pci_register_driver(&scc_pci_driver); |
bde18a2e KI |
927 | } |
928 | ||
929 | module_init(scc_ide_init); | |
930 | /* -- No exit code? | |
931 | static void scc_ide_exit(void) | |
932 | { | |
a9ab09e2 | 933 | ide_pci_unregister_driver(&scc_pci_driver); |
bde18a2e KI |
934 | } |
935 | module_exit(scc_ide_exit); | |
936 | */ | |
937 | ||
938 | ||
939 | MODULE_DESCRIPTION("PCI driver module for Toshiba SCC IDE"); | |
940 | MODULE_LICENSE("GPL"); |