Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 | 2 | * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org> |
669165da | 3 | * Copyright (C) 2006-2007, 2009 MontaVista Software, Inc. |
a337c227 | 4 | * Copyright (C) 2007-2010 Bartlomiej Zolnierkiewicz |
1da177e4 | 5 | * |
1da177e4 LT |
6 | * Portions Copyright (C) 1999 Promise Technology, Inc. |
7 | * Author: Frank Tiernan (frankt@promise.com) | |
8 | * Released under terms of General Public License | |
9 | */ | |
10 | ||
1da177e4 LT |
11 | #include <linux/types.h> |
12 | #include <linux/module.h> | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/delay.h> | |
1da177e4 | 15 | #include <linux/blkdev.h> |
1da177e4 LT |
16 | #include <linux/pci.h> |
17 | #include <linux/init.h> | |
18 | #include <linux/ide.h> | |
19 | ||
20 | #include <asm/io.h> | |
1da177e4 | 21 | |
ced3ec8a BZ |
22 | #define DRV_NAME "pdc202xx_old" |
23 | ||
88b2b32b | 24 | static void pdc202xx_set_mode(ide_drive_t *drive, const u8 speed) |
1da177e4 | 25 | { |
898ec223 | 26 | ide_hwif_t *hwif = drive->hwif; |
36501650 | 27 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1da177e4 | 28 | u8 drive_pci = 0x60 + (drive->dn << 2); |
1da177e4 | 29 | |
4fce3164 | 30 | u8 AP = 0, BP = 0, CP = 0; |
1da177e4 LT |
31 | u8 TA = 0, TB = 0, TC = 0; |
32 | ||
4fce3164 BZ |
33 | pci_read_config_byte(dev, drive_pci, &AP); |
34 | pci_read_config_byte(dev, drive_pci + 1, &BP); | |
35 | pci_read_config_byte(dev, drive_pci + 2, &CP); | |
1da177e4 LT |
36 | |
37 | switch(speed) { | |
1da177e4 LT |
38 | case XFER_UDMA_5: |
39 | case XFER_UDMA_4: TB = 0x20; TC = 0x01; break; | |
40 | case XFER_UDMA_2: TB = 0x20; TC = 0x01; break; | |
41 | case XFER_UDMA_3: | |
42 | case XFER_UDMA_1: TB = 0x40; TC = 0x02; break; | |
43 | case XFER_UDMA_0: | |
44 | case XFER_MW_DMA_2: TB = 0x60; TC = 0x03; break; | |
45 | case XFER_MW_DMA_1: TB = 0x60; TC = 0x04; break; | |
4fce3164 | 46 | case XFER_MW_DMA_0: TB = 0xE0; TC = 0x0F; break; |
1da177e4 LT |
47 | case XFER_PIO_4: TA = 0x01; TB = 0x04; break; |
48 | case XFER_PIO_3: TA = 0x02; TB = 0x06; break; | |
49 | case XFER_PIO_2: TA = 0x03; TB = 0x08; break; | |
50 | case XFER_PIO_1: TA = 0x05; TB = 0x0C; break; | |
51 | case XFER_PIO_0: | |
52 | default: TA = 0x09; TB = 0x13; break; | |
53 | } | |
54 | ||
55 | if (speed < XFER_SW_DMA_0) { | |
4fce3164 BZ |
56 | /* |
57 | * preserve SYNC_INT / ERDDY_EN bits while clearing | |
58 | * Prefetch_EN / IORDY_EN / PA[3:0] bits of register A | |
59 | */ | |
60 | AP &= ~0x3f; | |
c9ef59ff | 61 | if (ide_pio_need_iordy(drive, speed - XFER_PIO_0)) |
4fce3164 BZ |
62 | AP |= 0x20; /* set IORDY_EN bit */ |
63 | if (drive->media == ide_disk) | |
64 | AP |= 0x10; /* set Prefetch_EN bit */ | |
65 | /* clear PB[4:0] bits of register B */ | |
66 | BP &= ~0x1f; | |
67 | pci_write_config_byte(dev, drive_pci, AP | TA); | |
68 | pci_write_config_byte(dev, drive_pci + 1, BP | TB); | |
1da177e4 | 69 | } else { |
4fce3164 BZ |
70 | /* clear MB[2:0] bits of register B */ |
71 | BP &= ~0xe0; | |
72 | /* clear MC[3:0] bits of register C */ | |
73 | CP &= ~0x0f; | |
74 | pci_write_config_byte(dev, drive_pci + 1, BP | TB); | |
75 | pci_write_config_byte(dev, drive_pci + 2, CP | TC); | |
1da177e4 | 76 | } |
1da177e4 LT |
77 | } |
78 | ||
e085b3ca | 79 | static void pdc202xx_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) |
1da177e4 | 80 | { |
e085b3ca | 81 | pdc202xx_set_mode(drive, drive->pio_mode); |
1da177e4 LT |
82 | } |
83 | ||
e0321fbe SS |
84 | static int pdc202xx_test_irq(ide_hwif_t *hwif) |
85 | { | |
86 | struct pci_dev *dev = to_pci_dev(hwif->dev); | |
87 | unsigned long high_16 = pci_resource_start(dev, 4); | |
88 | u8 sc1d = inb(high_16 + 0x1d); | |
89 | ||
90 | if (hwif->channel) { | |
91 | /* | |
92 | * bit 7: error, bit 6: interrupting, | |
93 | * bit 5: FIFO full, bit 4: FIFO empty | |
94 | */ | |
95 | return ((sc1d & 0x50) == 0x40) ? 1 : 0; | |
96 | } else { | |
97 | /* | |
98 | * bit 3: error, bit 2: interrupting, | |
99 | * bit 1: FIFO full, bit 0: FIFO empty | |
100 | */ | |
101 | return ((sc1d & 0x05) == 0x04) ? 1 : 0; | |
102 | } | |
103 | } | |
104 | ||
f454cbe8 | 105 | static u8 pdc2026x_cable_detect(ide_hwif_t *hwif) |
1da177e4 | 106 | { |
36501650 | 107 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1bee4d1d | 108 | u16 CIS, mask = hwif->channel ? (1 << 11) : (1 << 10); |
49521f97 | 109 | |
36501650 | 110 | pci_read_config_word(dev, 0x50, &CIS); |
49521f97 BZ |
111 | |
112 | return (CIS & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80; | |
1da177e4 LT |
113 | } |
114 | ||
115 | /* | |
116 | * Set the control register to use the 66MHz system | |
117 | * clock for UDMA 3/4/5 mode operation when necessary. | |
118 | * | |
4fce3164 BZ |
119 | * FIXME: this register is shared by both channels, some locking is needed |
120 | * | |
1da177e4 LT |
121 | * It may also be possible to leave the 66MHz clock on |
122 | * and readjust the timing parameters. | |
123 | */ | |
124 | static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif) | |
125 | { | |
1c029fd6 | 126 | unsigned long clock_reg = hwif->extra_base + 0x01; |
0ecdca26 | 127 | u8 clock = inb(clock_reg); |
1da177e4 | 128 | |
0ecdca26 | 129 | outb(clock | (hwif->channel ? 0x08 : 0x02), clock_reg); |
1da177e4 LT |
130 | } |
131 | ||
132 | static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif) | |
133 | { | |
1c029fd6 | 134 | unsigned long clock_reg = hwif->extra_base + 0x01; |
0ecdca26 | 135 | u8 clock = inb(clock_reg); |
1da177e4 | 136 | |
0ecdca26 | 137 | outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg); |
1da177e4 LT |
138 | } |
139 | ||
a337c227 BZ |
140 | static void pdc2026x_init_hwif(ide_hwif_t *hwif) |
141 | { | |
142 | pdc_old_disable_66MHz_clock(hwif); | |
143 | } | |
144 | ||
5e37bdc0 | 145 | static void pdc202xx_dma_start(ide_drive_t *drive) |
1da177e4 LT |
146 | { |
147 | if (drive->current_speed > XFER_UDMA_2) | |
148 | pdc_old_enable_66MHz_clock(drive->hwif); | |
97100fc8 | 149 | if (drive->media != ide_disk || (drive->dev_flags & IDE_DFLAG_LBA48)) { |
898ec223 | 150 | ide_hwif_t *hwif = drive->hwif; |
b65fac32 | 151 | struct request *rq = hwif->rq; |
1c029fd6 | 152 | unsigned long high_16 = hwif->extra_base - 16; |
1da177e4 LT |
153 | unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20); |
154 | u32 word_count = 0; | |
0ecdca26 | 155 | u8 clock = inb(high_16 + 0x11); |
1da177e4 | 156 | |
0ecdca26 | 157 | outb(clock | (hwif->channel ? 0x08 : 0x02), high_16 + 0x11); |
9780e2dd | 158 | word_count = (blk_rq_sectors(rq) << 8); |
1da177e4 LT |
159 | word_count = (rq_data_dir(rq) == READ) ? |
160 | word_count | 0x05000000 : | |
161 | word_count | 0x06000000; | |
0ecdca26 | 162 | outl(word_count, atapi_reg); |
1da177e4 LT |
163 | } |
164 | ide_dma_start(drive); | |
165 | } | |
166 | ||
5e37bdc0 | 167 | static int pdc202xx_dma_end(ide_drive_t *drive) |
1da177e4 | 168 | { |
97100fc8 | 169 | if (drive->media != ide_disk || (drive->dev_flags & IDE_DFLAG_LBA48)) { |
898ec223 | 170 | ide_hwif_t *hwif = drive->hwif; |
1c029fd6 | 171 | unsigned long high_16 = hwif->extra_base - 16; |
1da177e4 LT |
172 | unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20); |
173 | u8 clock = 0; | |
174 | ||
0ecdca26 BZ |
175 | outl(0, atapi_reg); /* zero out extra */ |
176 | clock = inb(high_16 + 0x11); | |
177 | outb(clock & ~(hwif->channel ? 0x08:0x02), high_16 + 0x11); | |
1da177e4 LT |
178 | } |
179 | if (drive->current_speed > XFER_UDMA_2) | |
180 | pdc_old_disable_66MHz_clock(drive->hwif); | |
653bcf52 | 181 | return ide_dma_end(drive); |
1da177e4 LT |
182 | } |
183 | ||
2ed0ef54 | 184 | static int init_chipset_pdc202xx(struct pci_dev *dev) |
1da177e4 | 185 | { |
73369d2a | 186 | unsigned long dmabase = pci_resource_start(dev, 4); |
1da177e4 LT |
187 | u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0; |
188 | ||
73369d2a BZ |
189 | if (dmabase == 0) |
190 | goto out; | |
1da177e4 | 191 | |
0ecdca26 BZ |
192 | udma_speed_flag = inb(dmabase | 0x1f); |
193 | primary_mode = inb(dmabase | 0x1a); | |
194 | secondary_mode = inb(dmabase | 0x1b); | |
1da177e4 LT |
195 | printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \ |
196 | "Primary %s Mode " \ | |
5e59c236 | 197 | "Secondary %s Mode.\n", pci_name(dev), |
1da177e4 LT |
198 | (udma_speed_flag & 1) ? "EN" : "DIS", |
199 | (primary_mode & 1) ? "MASTER" : "PCI", | |
200 | (secondary_mode & 1) ? "MASTER" : "PCI" ); | |
201 | ||
1da177e4 LT |
202 | if (!(udma_speed_flag & 1)) { |
203 | printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ", | |
5e59c236 | 204 | pci_name(dev), udma_speed_flag, |
1da177e4 | 205 | (udma_speed_flag|1)); |
0ecdca26 BZ |
206 | outb(udma_speed_flag | 1, dmabase | 0x1f); |
207 | printk("%sACTIVE\n", (inb(dmabase | 0x1f) & 1) ? "" : "IN"); | |
1da177e4 | 208 | } |
73369d2a | 209 | out: |
2ed0ef54 | 210 | return 0; |
1da177e4 LT |
211 | } |
212 | ||
97f84baa BZ |
213 | static void __devinit pdc202ata4_fixup_irq(struct pci_dev *dev, |
214 | const char *name) | |
1da177e4 LT |
215 | { |
216 | if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) { | |
217 | u8 irq = 0, irq2 = 0; | |
218 | pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); | |
219 | /* 0xbc */ | |
220 | pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2); | |
221 | if (irq != irq2) { | |
222 | pci_write_config_byte(dev, | |
223 | (PCI_INTERRUPT_LINE)|0x80, irq); /* 0xbc */ | |
28cfd8af BZ |
224 | printk(KERN_INFO "%s %s: PCI config space interrupt " |
225 | "mirror fixed\n", name, pci_name(dev)); | |
1da177e4 LT |
226 | } |
227 | } | |
1da177e4 LT |
228 | } |
229 | ||
4db90a14 BZ |
230 | #define IDE_HFLAGS_PDC202XX \ |
231 | (IDE_HFLAG_ERROR_STOPS_FIFO | \ | |
4db90a14 BZ |
232 | IDE_HFLAG_OFF_BOARD) |
233 | ||
ac95beed BZ |
234 | static const struct ide_port_ops pdc20246_port_ops = { |
235 | .set_pio_mode = pdc202xx_set_pio_mode, | |
236 | .set_dma_mode = pdc202xx_set_mode, | |
e0321fbe | 237 | .test_irq = pdc202xx_test_irq, |
ac95beed BZ |
238 | }; |
239 | ||
240 | static const struct ide_port_ops pdc2026x_port_ops = { | |
241 | .set_pio_mode = pdc202xx_set_pio_mode, | |
242 | .set_dma_mode = pdc202xx_set_mode, | |
ac95beed BZ |
243 | .cable_detect = pdc2026x_cable_detect, |
244 | }; | |
245 | ||
f37afdac BZ |
246 | static const struct ide_dma_ops pdc2026x_dma_ops = { |
247 | .dma_host_set = ide_dma_host_set, | |
248 | .dma_setup = ide_dma_setup, | |
5e37bdc0 BZ |
249 | .dma_start = pdc202xx_dma_start, |
250 | .dma_end = pdc202xx_dma_end, | |
72b9304f | 251 | .dma_test_irq = ide_dma_test_irq, |
1221e241 | 252 | .dma_lost_irq = ide_dma_lost_irq, |
22117d6e | 253 | .dma_timer_expiry = ide_dma_sff_timer_expiry, |
592b5315 | 254 | .dma_sff_read_status = ide_dma_sff_read_status, |
5e37bdc0 BZ |
255 | }; |
256 | ||
6b492496 | 257 | #define DECLARE_PDC2026X_DEV(udma, sectors) \ |
5ef8cb5d | 258 | { \ |
ced3ec8a | 259 | .name = DRV_NAME, \ |
5ef8cb5d | 260 | .init_chipset = init_chipset_pdc202xx, \ |
a337c227 | 261 | .init_hwif = pdc2026x_init_hwif, \ |
ac95beed | 262 | .port_ops = &pdc2026x_port_ops, \ |
5e37bdc0 | 263 | .dma_ops = &pdc2026x_dma_ops, \ |
6b492496 | 264 | .host_flags = IDE_HFLAGS_PDC202XX, \ |
5ef8cb5d BZ |
265 | .pio_mask = ATA_PIO4, \ |
266 | .mwdma_mask = ATA_MWDMA2, \ | |
267 | .udma_mask = udma, \ | |
6b492496 | 268 | .max_sectors = sectors, \ |
5ef8cb5d BZ |
269 | } |
270 | ||
85620436 | 271 | static const struct ide_port_info pdc202xx_chipsets[] __devinitdata = { |
ced3ec8a BZ |
272 | { /* 0: PDC20246 */ |
273 | .name = DRV_NAME, | |
1da177e4 | 274 | .init_chipset = init_chipset_pdc202xx, |
ac95beed | 275 | .port_ops = &pdc20246_port_ops, |
72b9304f | 276 | .dma_ops = &sff_dma_ops, |
4db90a14 | 277 | .host_flags = IDE_HFLAGS_PDC202XX, |
4099d143 | 278 | .pio_mask = ATA_PIO4, |
5f8b6c34 BZ |
279 | .mwdma_mask = ATA_MWDMA2, |
280 | .udma_mask = ATA_UDMA2, | |
5ef8cb5d BZ |
281 | }, |
282 | ||
ced3ec8a BZ |
283 | /* 1: PDC2026{2,3} */ |
284 | DECLARE_PDC2026X_DEV(ATA_UDMA4, 0), | |
6b492496 BZ |
285 | /* 2: PDC2026{5,7}: UDMA5, limit LBA48 requests to 256 sectors */ |
286 | DECLARE_PDC2026X_DEV(ATA_UDMA5, 256), | |
1da177e4 LT |
287 | }; |
288 | ||
289 | /** | |
290 | * pdc202xx_init_one - called when a PDC202xx is found | |
291 | * @dev: the pdc202xx device | |
292 | * @id: the matching pci id | |
293 | * | |
294 | * Called when the PCI registration layer (or the IDE initialization) | |
295 | * finds a device matching our IDE device tables. | |
296 | */ | |
297 | ||
298 | static int __devinit pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
299 | { | |
85620436 | 300 | const struct ide_port_info *d; |
97f84baa BZ |
301 | u8 idx = id->driver_data; |
302 | ||
303 | d = &pdc202xx_chipsets[idx]; | |
304 | ||
ced3ec8a | 305 | if (idx < 2) |
97f84baa BZ |
306 | pdc202ata4_fixup_irq(dev, d->name); |
307 | ||
ced3ec8a | 308 | if (dev->vendor == PCI_DEVICE_ID_PROMISE_20265) { |
97f84baa | 309 | struct pci_dev *bridge = dev->bus->self; |
1da177e4 | 310 | |
97f84baa BZ |
311 | if (bridge && |
312 | bridge->vendor == PCI_VENDOR_ID_INTEL && | |
313 | (bridge->device == PCI_DEVICE_ID_INTEL_I960 || | |
314 | bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) { | |
ced3ec8a | 315 | printk(KERN_INFO DRV_NAME " %s: skipping Promise " |
28cfd8af BZ |
316 | "PDC20265 attached to I2O RAID controller\n", |
317 | pci_name(dev)); | |
97f84baa BZ |
318 | return -ENODEV; |
319 | } | |
320 | } | |
321 | ||
6cdf6eb3 | 322 | return ide_pci_init_one(dev, d, NULL); |
1da177e4 LT |
323 | } |
324 | ||
9cbcc5e3 BZ |
325 | static const struct pci_device_id pdc202xx_pci_tbl[] = { |
326 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 }, | |
327 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 }, | |
ced3ec8a BZ |
328 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 1 }, |
329 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 2 }, | |
330 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 2 }, | |
1da177e4 LT |
331 | { 0, }, |
332 | }; | |
333 | MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl); | |
334 | ||
a9ab09e2 | 335 | static struct pci_driver pdc202xx_pci_driver = { |
1da177e4 LT |
336 | .name = "Promise_Old_IDE", |
337 | .id_table = pdc202xx_pci_tbl, | |
338 | .probe = pdc202xx_init_one, | |
574a1c24 | 339 | .remove = ide_pci_remove, |
feb22b7f BZ |
340 | .suspend = ide_pci_suspend, |
341 | .resume = ide_pci_resume, | |
1da177e4 LT |
342 | }; |
343 | ||
82ab1eec | 344 | static int __init pdc202xx_ide_init(void) |
1da177e4 | 345 | { |
a9ab09e2 | 346 | return ide_pci_register_driver(&pdc202xx_pci_driver); |
1da177e4 LT |
347 | } |
348 | ||
574a1c24 BZ |
349 | static void __exit pdc202xx_ide_exit(void) |
350 | { | |
a9ab09e2 | 351 | pci_unregister_driver(&pdc202xx_pci_driver); |
574a1c24 BZ |
352 | } |
353 | ||
1da177e4 | 354 | module_init(pdc202xx_ide_init); |
574a1c24 | 355 | module_exit(pdc202xx_ide_exit); |
1da177e4 | 356 | |
a337c227 | 357 | MODULE_AUTHOR("Andre Hedrick, Frank Tiernan, Bartlomiej Zolnierkiewicz"); |
1da177e4 LT |
358 | MODULE_DESCRIPTION("PCI driver module for older Promise IDE"); |
359 | MODULE_LICENSE("GPL"); |