[linux-2.6-block.git] / drivers / ide / pdc202xx_new.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 *  Promise TX2/TX4/TX2000/133 IDE driver
 *
 *  Split from:
 *  linux/drivers/ide/pdc202xx.c	Version 0.35	Mar. 30, 2002
 *  Copyright (C) 1998-2002		Andre Hedrick <andre@linux-ide.org>
 *  Copyright (C) 2005-2007		MontaVista Software, Inc.
 *  Portions Copyright (C) 1999 Promise Technology, Inc.
 *  Author: Frank Tiernan (frankt@promise.com)
 *  Released under terms of General Public License
 */

#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ide.h>
#include <linux/ktime.h>

#include <asm/io.h>

#ifdef CONFIG_PPC_PMAC
#include <asm/prom.h>
#endif

#define DRV_NAME "pdc202xx_new"

#undef DEBUG

#ifdef DEBUG
#define DBG(fmt, args...) printk("%s: " fmt, __func__, ## args)
#else
#define DBG(fmt, args...)
#endif

static u8 max_dma_rate(struct pci_dev *pdev)
{
	u8 mode;

	switch(pdev->device) {
		case PCI_DEVICE_ID_PROMISE_20277:
		case PCI_DEVICE_ID_PROMISE_20276:
		case PCI_DEVICE_ID_PROMISE_20275:
		case PCI_DEVICE_ID_PROMISE_20271:
		case PCI_DEVICE_ID_PROMISE_20269:
			mode = 4;
			break;
		case PCI_DEVICE_ID_PROMISE_20270:
		case PCI_DEVICE_ID_PROMISE_20268:
			mode = 3;
			break;
		default:
			return 0;
	}

	return mode;
}

/**
 * get_indexed_reg - Get indexed register
 * @hwif: for the port address
 * @index: index of the indexed register
 */
static u8 get_indexed_reg(ide_hwif_t *hwif, u8 index)
{
	u8 value;

	outb(index, hwif->dma_base + 1);
	value = inb(hwif->dma_base + 3);

	DBG("index[%02X] value[%02X]\n", index, value);
	return value;
}

/**
 * set_indexed_reg - Set indexed register
 * @hwif: for the port address
 * @index: index of the indexed register
 */
static void set_indexed_reg(ide_hwif_t *hwif, u8 index, u8 value)
{
	outb(index, hwif->dma_base + 1);
	outb(value, hwif->dma_base + 3);
	DBG("index[%02X] value[%02X]\n", index, value);
}

/*
 * ATA Timing Tables based on 133 MHz PLL output clock.
 *
 * If the PLL outputs 100 MHz clock, the ASIC hardware will set
 * the timing registers automatically when "set features" command is
 * issued to the device. However, if the PLL output clock is 133 MHz,
 * the following tables must be used.
 */
static struct pio_timing {
	u8 reg0c, reg0d, reg13;
} pio_timings [] = {
	{ 0xfb, 0x2b, 0xac },	/* PIO mode 0, IORDY off, Prefetch off */
	{ 0x46, 0x29, 0xa4 },	/* PIO mode 1, IORDY off, Prefetch off */
	{ 0x23, 0x26, 0x64 },	/* PIO mode 2, IORDY off, Prefetch off */
	{ 0x27, 0x0d, 0x35 },	/* PIO mode 3, IORDY on,  Prefetch off */
	{ 0x23, 0x09, 0x25 },	/* PIO mode 4, IORDY on,  Prefetch off */
};

static struct mwdma_timing {
	u8 reg0e, reg0f;
} mwdma_timings [] = {
	{ 0xdf, 0x5f }, 	/* MWDMA mode 0 */
	{ 0x6b, 0x27 }, 	/* MWDMA mode 1 */
	{ 0x69, 0x25 }, 	/* MWDMA mode 2 */
};

static struct udma_timing {
	u8 reg10, reg11, reg12;
} udma_timings [] = {
	{ 0x4a, 0x0f, 0xd5 },	/* UDMA mode 0 */
	{ 0x3a, 0x0a, 0xd0 },	/* UDMA mode 1 */
	{ 0x2a, 0x07, 0xcd },	/* UDMA mode 2 */
	{ 0x1a, 0x05, 0xcd },	/* UDMA mode 3 */
	{ 0x1a, 0x03, 0xcd },	/* UDMA mode 4 */
	{ 0x1a, 0x02, 0xcb },	/* UDMA mode 5 */
	{ 0x1a, 0x01, 0xcb },	/* UDMA mode 6 */
};

static void pdcnew_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
{
	struct pci_dev *dev	= to_pci_dev(hwif->dev);
	u8 adj			= (drive->dn & 1) ? 0x08 : 0x00;
	const u8 speed		= drive->dma_mode;

	/*
	 * IDE core issues SETFEATURES_XFER to the drive first (thanks to
	 * IDE_HFLAG_POST_SET_MODE in ->host_flags).  PDC202xx hardware will
	 * automatically set the timing registers based on 100 MHz PLL output.
	 *
	 * As we set up the PLL to output 133 MHz for UltraDMA/133 capable
	 * chips, we must override the default register settings...
	 */
	if (max_dma_rate(dev) == 4) {
		u8 mode = speed & 0x07;

		if (speed >= XFER_UDMA_0) {
			set_indexed_reg(hwif, 0x10 + adj,
					udma_timings[mode].reg10);
			set_indexed_reg(hwif, 0x11 + adj,
					udma_timings[mode].reg11);
			set_indexed_reg(hwif, 0x12 + adj,
					udma_timings[mode].reg12);
		} else {
			set_indexed_reg(hwif, 0x0e + adj,
					mwdma_timings[mode].reg0e);
			set_indexed_reg(hwif, 0x0f + adj,
					mwdma_timings[mode].reg0f);
		}
	} else if (speed == XFER_UDMA_2) {
		/* Set tHOLD bit to 0 if using UDMA mode 2 */
		u8 tmp = get_indexed_reg(hwif, 0x10 + adj);

		set_indexed_reg(hwif, 0x10 + adj, tmp & 0x7f);
 	}
}

static void pdcnew_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
{
	struct pci_dev *dev = to_pci_dev(hwif->dev);
	u8 adj = (drive->dn & 1) ? 0x08 : 0x00;
	const u8 pio = drive->pio_mode - XFER_PIO_0;

	if (max_dma_rate(dev) == 4) {
		set_indexed_reg(hwif, 0x0c + adj, pio_timings[pio].reg0c);
		set_indexed_reg(hwif, 0x0d + adj, pio_timings[pio].reg0d);
		set_indexed_reg(hwif, 0x13 + adj, pio_timings[pio].reg13);
	}
}

static u8 pdcnew_cable_detect(ide_hwif_t *hwif)
{
	if (get_indexed_reg(hwif, 0x0b) & 0x04)
		return ATA_CBL_PATA40;
	else
		return ATA_CBL_PATA80;
}

static void pdcnew_reset(ide_drive_t *drive)
{
	/*
	 * Deleted this because it is redundant from the caller.
	 */
	printk(KERN_WARNING "pdc202xx_new: %s channel reset.\n",
		drive->hwif->channel ? "Secondary" : "Primary");
}

/**
 * read_counter - Read the byte count registers
 * @dma_base: for the port address
 */
static long read_counter(u32 dma_base)
{
	u32  pri_dma_base = dma_base, sec_dma_base = dma_base + 0x08;
	u8   cnt0, cnt1, cnt2, cnt3;
	long count = 0, last;
	int  retry = 3;

	do {
		last = count;

		/* Read the current count */
		outb(0x20, pri_dma_base + 0x01);
		cnt0 = inb(pri_dma_base + 0x03);
		outb(0x21, pri_dma_base + 0x01);
		cnt1 = inb(pri_dma_base + 0x03);
		outb(0x20, sec_dma_base + 0x01);
		cnt2 = inb(sec_dma_base + 0x03);
		outb(0x21, sec_dma_base + 0x01);
		cnt3 = inb(sec_dma_base + 0x03);

		count = (cnt3 << 23) | (cnt2 << 15) | (cnt1 << 8) | cnt0;

		/*
		 * The 30-bit decrementing counter is read in 4 pieces.
		 * Incorrect value may be read when the most significant bytes
		 * are changing...
		 */
	} while (retry-- && (((last ^ count) & 0x3fff8000) || last < count));

	DBG("cnt0[%02X] cnt1[%02X] cnt2[%02X] cnt3[%02X]\n",
		  cnt0, cnt1, cnt2, cnt3);

	return count;
}

/**
 * detect_pll_input_clock - Detect the PLL input clock in Hz.
 * @dma_base: for the port address
 * E.g. 16949000 on 33 MHz PCI bus, i.e. half of the PCI clock.
 */
static long detect_pll_input_clock(unsigned long dma_base)
{
	ktime_t start_time, end_time;
	long start_count, end_count;
	long pll_input, usec_elapsed;
	u8 scr1;

	start_count = read_counter(dma_base);
	start_time = ktime_get();

	/* Start the test mode */
	outb(0x01, dma_base + 0x01);
	scr1 = inb(dma_base + 0x03);
	DBG("scr1[%02X]\n", scr1);
	outb(scr1 | 0x40, dma_base + 0x03);

	/* Let the counter run for 10 ms. */
	mdelay(10);

	end_count = read_counter(dma_base);
	end_time = ktime_get();

	/* Stop the test mode */
	outb(0x01, dma_base + 0x01);
	scr1 = inb(dma_base + 0x03);
	DBG("scr1[%02X]\n", scr1);
	outb(scr1 & ~0x40, dma_base + 0x03);

	/*
	 * Calculate the input clock in Hz
	 * (the clock counter is 30 bit wide and counts down)
	 */
	usec_elapsed = ktime_us_delta(end_time, start_time);
	pll_input = ((start_count - end_count) & 0x3fffffff) / 10 *
		(10000000 / usec_elapsed);

	DBG("start[%ld] end[%ld]\n", start_count, end_count);

	return pll_input;
}

#ifdef CONFIG_PPC_PMAC
static void apple_kiwi_init(struct pci_dev *pdev)
{
	struct device_node *np = pci_device_to_OF_node(pdev);
	u8 conf;

	if (np == NULL || !of_device_is_compatible(np, "kiwi-root"))
		return;

	if (pdev->revision >= 0x03) {
		/* Setup chip magic config stuff (from darwin) */
		pci_read_config_byte (pdev, 0x40, &conf);
		pci_write_config_byte(pdev, 0x40, (conf | 0x01));
	}
}
#endif /* CONFIG_PPC_PMAC */

static int init_chipset_pdcnew(struct pci_dev *dev)
{
	const char *name = DRV_NAME;
	unsigned long dma_base = pci_resource_start(dev, 4);
	unsigned long sec_dma_base = dma_base + 0x08;
	long pll_input, pll_output, ratio;
	int f, r;
	u8 pll_ctl0, pll_ctl1;

	if (dma_base == 0)
		return -EFAULT;

#ifdef CONFIG_PPC_PMAC
	apple_kiwi_init(dev);
#endif

	/* Calculate the required PLL output frequency */
	switch(max_dma_rate(dev)) {
		case 4: /* it's 133 MHz for Ultra133 chips */
			pll_output = 133333333;
			break;
		case 3: /* and  100 MHz for Ultra100 chips */
		default:
			pll_output = 100000000;
			break;
	}

	/*
	 * Detect PLL input clock.
	 * On some systems, where PCI bus is running at non-standard clock rate
	 * (e.g. 25 or 40 MHz), we have to adjust the cycle time.
	 * PDC20268 and newer chips employ PLL circuit to help correct timing
	 * registers setting.
	 */
	pll_input = detect_pll_input_clock(dma_base);
	printk(KERN_INFO "%s %s: PLL input clock is %ld kHz\n",
		name, pci_name(dev), pll_input / 1000);

	/* Sanity check */
	if (unlikely(pll_input < 5000000L || pll_input > 70000000L)) {
		printk(KERN_ERR "%s %s: Bad PLL input clock %ld Hz, giving up!"
			"\n", name, pci_name(dev), pll_input);
		goto out;
	}

#ifdef DEBUG
	DBG("pll_output is %ld Hz\n", pll_output);

	/* Show the current clock value of PLL control register
	 * (maybe already configured by the BIOS)
	 */
	outb(0x02, sec_dma_base + 0x01);
	pll_ctl0 = inb(sec_dma_base + 0x03);
	outb(0x03, sec_dma_base + 0x01);
	pll_ctl1 = inb(sec_dma_base + 0x03);

	DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
#endif

	/*
	 * Calculate the ratio of F, R and NO
	 * POUT = (F + 2) / (( R + 2) * NO)
	 */
	ratio = pll_output / (pll_input / 1000);
	if (ratio < 8600L) { /* 8.6x */
		/* Using NO = 0x01, R = 0x0d */
		r = 0x0d;
	} else if (ratio < 12900L) { /* 12.9x */
		/* Using NO = 0x01, R = 0x08 */
		r = 0x08;
	} else if (ratio < 16100L) { /* 16.1x */
		/* Using NO = 0x01, R = 0x06 */
		r = 0x06;
	} else if (ratio < 64000L) { /* 64x */
		r = 0x00;
	} else {
		/* Invalid ratio */
		printk(KERN_ERR "%s %s: Bad ratio %ld, giving up!\n",
			name, pci_name(dev), ratio);
		goto out;
	}

	f = (ratio * (r + 2)) / 1000 - 2;

	DBG("F[%d] R[%d] ratio*1000[%ld]\n", f, r, ratio);

	if (unlikely(f < 0 || f > 127)) {
		/* Invalid F */
		printk(KERN_ERR "%s %s: F[%d] invalid!\n",
			name, pci_name(dev), f);
		goto out;
	}

	pll_ctl0 = (u8) f;
	pll_ctl1 = (u8) r;

	DBG("Writing pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);

	outb(0x02,     sec_dma_base + 0x01);
	outb(pll_ctl0, sec_dma_base + 0x03);
	outb(0x03,     sec_dma_base + 0x01);
	outb(pll_ctl1, sec_dma_base + 0x03);

	/* Wait the PLL circuit to be stable */
	mdelay(30);

#ifdef DEBUG
	/*
	 *  Show the current clock value of PLL control register
	 */
	outb(0x02, sec_dma_base + 0x01);
	pll_ctl0 = inb(sec_dma_base + 0x03);
	outb(0x03, sec_dma_base + 0x01);
	pll_ctl1 = inb(sec_dma_base + 0x03);

	DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
#endif

 out:
	return 0;
}

static struct pci_dev *pdc20270_get_dev2(struct pci_dev *dev)
{
	struct pci_dev *dev2;

	dev2 = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn) + 1,
						PCI_FUNC(dev->devfn)));

	if (dev2 &&
	    dev2->vendor == dev->vendor &&
	    dev2->device == dev->device) {

		if (dev2->irq != dev->irq) {
			dev2->irq = dev->irq;
			printk(KERN_INFO DRV_NAME " %s: PCI config space "
				"interrupt fixed\n", pci_name(dev));
		}

		return dev2;
	}

	return NULL;
}

static const struct ide_port_ops pdcnew_port_ops = {
	.set_pio_mode		= pdcnew_set_pio_mode,
	.set_dma_mode		= pdcnew_set_dma_mode,
	.resetproc		= pdcnew_reset,
	.cable_detect		= pdcnew_cable_detect,
};

#define DECLARE_PDCNEW_DEV(udma) \
	{ \
		.name		= DRV_NAME, \
		.init_chipset	= init_chipset_pdcnew, \
		.port_ops	= &pdcnew_port_ops, \
		.host_flags	= IDE_HFLAG_POST_SET_MODE | \
				  IDE_HFLAG_ERROR_STOPS_FIFO | \
				  IDE_HFLAG_OFF_BOARD, \
		.pio_mask	= ATA_PIO4, \
		.mwdma_mask	= ATA_MWDMA2, \
		.udma_mask	= udma, \
	}

static const struct ide_port_info pdcnew_chipsets[] = {
	/* 0: PDC202{68,70} */		DECLARE_PDCNEW_DEV(ATA_UDMA5),
	/* 1: PDC202{69,71,75,76,77} */	DECLARE_PDCNEW_DEV(ATA_UDMA6),
};

/**
 *	pdc202new_init_one	-	called when a pdc202xx is found
 *	@dev: the pdc202new device
 *	@id: the matching pci id
 *
 *	Called when the PCI registration layer (or the IDE initialization)
 *	finds a device matching our IDE device tables.
 */
 
static int pdc202new_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	const struct ide_port_info *d = &pdcnew_chipsets[id->driver_data];
	struct pci_dev *bridge = dev->bus->self;

	if (dev->device == PCI_DEVICE_ID_PROMISE_20270 && bridge &&
	    bridge->vendor == PCI_VENDOR_ID_DEC &&
	    bridge->device == PCI_DEVICE_ID_DEC_21150) {
		struct pci_dev *dev2;

		if (PCI_SLOT(dev->devfn) & 2)
			return -ENODEV;

		dev2 = pdc20270_get_dev2(dev);

		if (dev2) {
			int ret = ide_pci_init_two(dev, dev2, d, NULL);
			if (ret < 0)
				pci_dev_put(dev2);
			return ret;
		}
	}

	if (dev->device == PCI_DEVICE_ID_PROMISE_20276 && bridge &&
	    bridge->vendor == PCI_VENDOR_ID_INTEL &&
	    (bridge->device == PCI_DEVICE_ID_INTEL_I960 ||
	     bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) {
		printk(KERN_INFO DRV_NAME " %s: attached to I2O RAID controller,"
			" skipping\n", pci_name(dev));
		return -ENODEV;
	}

	return ide_pci_init_one(dev, d, NULL);
}

static void pdc202new_remove(struct pci_dev *dev)
{
	struct ide_host *host = pci_get_drvdata(dev);
	struct pci_dev *dev2 = host->dev[1] ? to_pci_dev(host->dev[1]) : NULL;

	ide_pci_remove(dev);
	pci_dev_put(dev2);
}

static const struct pci_device_id pdc202new_pci_tbl[] = {
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20268), 0 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20269), 1 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20270), 0 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20271), 1 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20275), 1 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20276), 1 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20277), 1 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, pdc202new_pci_tbl);

static struct pci_driver pdc202new_pci_driver = {
	.name		= "Promise_IDE",
	.id_table	= pdc202new_pci_tbl,
	.probe		= pdc202new_init_one,
	.remove		= pdc202new_remove,
	.suspend	= ide_pci_suspend,
	.resume		= ide_pci_resume,
};

static int __init pdc202new_ide_init(void)
{
	return ide_pci_register_driver(&pdc202new_pci_driver);
}

static void __exit pdc202new_ide_exit(void)
{
	pci_unregister_driver(&pdc202new_pci_driver);
}

module_init(pdc202new_ide_init);
module_exit(pdc202new_ide_exit);

MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
MODULE_DESCRIPTION("PCI driver module for Promise PDC20268 and higher");
MODULE_LICENSE("GPL");
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
1da177e4 LT	2	/*
	3	* Promise TX2/TX4/TX2000/133 IDE driver
	4	*
1da177e4 LT	5	* Split from:
	6	* linux/drivers/ide/pdc202xx.c Version 0.35 Mar. 30, 2002
	7	* Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
35198234	8	* Copyright (C) 2005-2007 MontaVista Software, Inc.
1da177e4 LT	9	* Portions Copyright (C) 1999 Promise Technology, Inc.
	10	* Author: Frank Tiernan (frankt@promise.com)
	11	* Released under terms of General Public License
	12	*/
	13
1da177e4 LT	14	#include <linux/module.h>
	15	#include <linux/types.h>
	16	#include <linux/kernel.h>
	17	#include <linux/delay.h>
1da177e4 LT	18	#include <linux/pci.h>
	19	#include <linux/init.h>
	20	#include <linux/ide.h>
353b39d1	21	#include <linux/ktime.h>
1da177e4 LT	22
1da177e4 LT	23	#include <asm/io.h>
1da177e4 LT	24
	25	#ifdef CONFIG_PPC_PMAC
	26	#include <asm/prom.h>
1da177e4 LT	27	#endif
1da177e4 LT	28
ced3ec8a BZ	29	#define DRV_NAME "pdc202xx_new"
ced3ec8a BZ	30
47694bb8 SS	31	#undef DEBUG
	32
	33	#ifdef DEBUG
eb63963a	34	#define DBG(fmt, args...) printk("%s: " fmt, __func__, ## args)
47694bb8 SS	35	#else
	36	#define DBG(fmt, args...)
	37	#endif
	38
47694bb8	39	static u8 max_dma_rate(struct pci_dev *pdev)
1da177e4 LT	40	{
	41	u8 mode;
	42
47694bb8	43	switch(pdev->device) {
1da177e4 LT	44	case PCI_DEVICE_ID_PROMISE_20277:
	45	case PCI_DEVICE_ID_PROMISE_20276:
	46	case PCI_DEVICE_ID_PROMISE_20275:
	47	case PCI_DEVICE_ID_PROMISE_20271:
	48	case PCI_DEVICE_ID_PROMISE_20269:
	49	mode = 4;
	50	break;
	51	case PCI_DEVICE_ID_PROMISE_20270:
	52	case PCI_DEVICE_ID_PROMISE_20268:
	53	mode = 3;
	54	break;
	55	default:
	56	return 0;
	57	}
47694bb8	58
1da177e4 LT	59	return mode;
	60	}
	61
47694bb8 SS	62	/**
	63	* get_indexed_reg - Get indexed register
	64	* @hwif: for the port address
	65	* @index: index of the indexed register
	66	*/
	67	static u8 get_indexed_reg(ide_hwif_t *hwif, u8 index)
	68	{
	69	u8 value;
	70
41051a14 BZ	71	outb(index, hwif->dma_base + 1);
41051a14 BZ	72	value = inb(hwif->dma_base + 3);
47694bb8 SS	73
	74	DBG("index[%02X] value[%02X]\n", index, value);
	75	return value;
	76	}
	77
	78	/**
	79	* set_indexed_reg - Set indexed register
	80	* @hwif: for the port address
	81	* @index: index of the indexed register
	82	*/
	83	static void set_indexed_reg(ide_hwif_t *hwif, u8 index, u8 value)
	84	{
41051a14 BZ	85	outb(index, hwif->dma_base + 1);
41051a14 BZ	86	outb(value, hwif->dma_base + 3);
47694bb8 SS	87	DBG("index[%02X] value[%02X]\n", index, value);
	88	}
	89
	90	/*
	91	* ATA Timing Tables based on 133 MHz PLL output clock.
	92	*
	93	* If the PLL outputs 100 MHz clock, the ASIC hardware will set
	94	* the timing registers automatically when "set features" command is
	95	* issued to the device. However, if the PLL output clock is 133 MHz,
	96	* the following tables must be used.
	97	*/
	98	static struct pio_timing {
	99	u8 reg0c, reg0d, reg13;
	100	} pio_timings [] = {
	101	{ 0xfb, 0x2b, 0xac }, /* PIO mode 0, IORDY off, Prefetch off */
	102	{ 0x46, 0x29, 0xa4 }, /* PIO mode 1, IORDY off, Prefetch off */
	103	{ 0x23, 0x26, 0x64 }, /* PIO mode 2, IORDY off, Prefetch off */
	104	{ 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */
	105	{ 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */
	106	};
	107
	108	static struct mwdma_timing {
	109	u8 reg0e, reg0f;
	110	} mwdma_timings [] = {
	111	{ 0xdf, 0x5f }, /* MWDMA mode 0 */
	112	{ 0x6b, 0x27 }, /* MWDMA mode 1 */
	113	{ 0x69, 0x25 }, /* MWDMA mode 2 */
	114	};
	115
	116	static struct udma_timing {
	117	u8 reg10, reg11, reg12;
	118	} udma_timings [] = {
	119	{ 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */
	120	{ 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */
	121	{ 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */
	122	{ 0x1a, 0x05, 0xcd }, /* UDMA mode 3 */
	123	{ 0x1a, 0x03, 0xcd }, /* UDMA mode 4 */
	124	{ 0x1a, 0x02, 0xcb }, /* UDMA mode 5 */
	125	{ 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */
	126	};
	127
8776168c	128	static void pdcnew_set_dma_mode(ide_hwif_t hwif, ide_drive_t drive)
1da177e4	129	{
36501650	130	struct pci_dev *dev = to_pci_dev(hwif->dev);
47694bb8	131	u8 adj = (drive->dn & 1) ? 0x08 : 0x00;
8776168c	132	const u8 speed = drive->dma_mode;
1da177e4	133
47694bb8	134	/*
88b2b32b BZ	135	* IDE core issues SETFEATURES_XFER to the drive first (thanks to
88b2b32b BZ	136	* IDE_HFLAG_POST_SET_MODE in ->host_flags). PDC202xx hardware will
47694bb8	137	* automatically set the timing registers based on 100 MHz PLL output.
88b2b32b	138	*
47694bb8 SS	139	* As we set up the PLL to output 133 MHz for UltraDMA/133 capable
	140	* chips, we must override the default register settings...
	141	*/
36501650	142	if (max_dma_rate(dev) == 4) {
47694bb8 SS	143	u8 mode = speed & 0x07;
47694bb8 SS	144
4db90a14 BZ	145	if (speed >= XFER_UDMA_0) {
	146	set_indexed_reg(hwif, 0x10 + adj,
	147	udma_timings[mode].reg10);
	148	set_indexed_reg(hwif, 0x11 + adj,
	149	udma_timings[mode].reg11);
	150	set_indexed_reg(hwif, 0x12 + adj,
	151	udma_timings[mode].reg12);
	152	} else {
	153	set_indexed_reg(hwif, 0x0e + adj,
	154	mwdma_timings[mode].reg0e);
	155	set_indexed_reg(hwif, 0x0f + adj,
	156	mwdma_timings[mode].reg0f);
47694bb8 SS	157	}
	158	} else if (speed == XFER_UDMA_2) {
	159	/* Set tHOLD bit to 0 if using UDMA mode 2 */
	160	u8 tmp = get_indexed_reg(hwif, 0x10 + adj);
	161
	162	set_indexed_reg(hwif, 0x10 + adj, tmp & 0x7f);
	163	}
1da177e4 LT	164	}
1da177e4 LT	165
e085b3ca	166	static void pdcnew_set_pio_mode(ide_hwif_t hwif, ide_drive_t drive)
1da177e4	167	{
36501650	168	struct pci_dev *dev = to_pci_dev(hwif->dev);
ad4ba7dc	169	u8 adj = (drive->dn & 1) ? 0x08 : 0x00;
e085b3ca	170	const u8 pio = drive->pio_mode - XFER_PIO_0;
ad4ba7dc	171
36501650	172	if (max_dma_rate(dev) == 4) {
ad4ba7dc BZ	173	set_indexed_reg(hwif, 0x0c + adj, pio_timings[pio].reg0c);
	174	set_indexed_reg(hwif, 0x0d + adj, pio_timings[pio].reg0d);
	175	set_indexed_reg(hwif, 0x13 + adj, pio_timings[pio].reg13);
	176	}
1da177e4 LT	177	}
1da177e4 LT	178
f454cbe8	179	static u8 pdcnew_cable_detect(ide_hwif_t *hwif)
1da177e4	180	{
49521f97 BZ	181	if (get_indexed_reg(hwif, 0x0b) & 0x04)
	182	return ATA_CBL_PATA40;
	183	else
	184	return ATA_CBL_PATA80;
1da177e4	185	}
47694bb8	186
47694bb8	187	static void pdcnew_reset(ide_drive_t *drive)
1da177e4 LT	188	{
	189	/*
	190	* Deleted this because it is redundant from the caller.
	191	*/
47694bb8	192	printk(KERN_WARNING "pdc202xx_new: %s channel reset.\n",
898ec223	193	drive->hwif->channel ? "Secondary" : "Primary");
1da177e4 LT	194	}
1da177e4 LT	195
47694bb8 SS	196	/**
	197	* read_counter - Read the byte count registers
	198	* @dma_base: for the port address
	199	*/
feb22b7f	200	static long read_counter(u32 dma_base)
47694bb8 SS	201	{
	202	u32 pri_dma_base = dma_base, sec_dma_base = dma_base + 0x08;
	203	u8 cnt0, cnt1, cnt2, cnt3;
	204	long count = 0, last;
	205	int retry = 3;
	206
	207	do {
	208	last = count;
	209
	210	/* Read the current count */
	211	outb(0x20, pri_dma_base + 0x01);
	212	cnt0 = inb(pri_dma_base + 0x03);
	213	outb(0x21, pri_dma_base + 0x01);
	214	cnt1 = inb(pri_dma_base + 0x03);
	215	outb(0x20, sec_dma_base + 0x01);
	216	cnt2 = inb(sec_dma_base + 0x03);
	217	outb(0x21, sec_dma_base + 0x01);
	218	cnt3 = inb(sec_dma_base + 0x03);
	219
	220	count = (cnt3 << 23) \| (cnt2 << 15) \| (cnt1 << 8) \| cnt0;
	221
	222	/*
	223	* The 30-bit decrementing counter is read in 4 pieces.
	224	* Incorrect value may be read when the most significant bytes
	225	* are changing...
	226	*/
	227	} while (retry-- && (((last ^ count) & 0x3fff8000) \|\| last < count));
	228
	229	DBG("cnt0[%02X] cnt1[%02X] cnt2[%02X] cnt3[%02X]\n",
	230	cnt0, cnt1, cnt2, cnt3);
	231
	232	return count;
	233	}
	234
	235	/**
	236	* detect_pll_input_clock - Detect the PLL input clock in Hz.
	237	* @dma_base: for the port address
	238	* E.g. 16949000 on 33 MHz PCI bus, i.e. half of the PCI clock.
	239	*/
feb22b7f	240	static long detect_pll_input_clock(unsigned long dma_base)
47694bb8	241	{
353b39d1	242	ktime_t start_time, end_time;
47694bb8	243	long start_count, end_count;
8006bf56	244	long pll_input, usec_elapsed;
47694bb8 SS	245	u8 scr1;
	246
	247	start_count = read_counter(dma_base);
353b39d1	248	start_time = ktime_get();
47694bb8 SS	249
	250	/* Start the test mode */
	251	outb(0x01, dma_base + 0x01);
	252	scr1 = inb(dma_base + 0x03);
	253	DBG("scr1[%02X]\n", scr1);
	254	outb(scr1 \| 0x40, dma_base + 0x03);
	255
	256	/* Let the counter run for 10 ms. */
	257	mdelay(10);
	258
	259	end_count = read_counter(dma_base);
353b39d1	260	end_time = ktime_get();
47694bb8 SS	261
	262	/* Stop the test mode */
	263	outb(0x01, dma_base + 0x01);
	264	scr1 = inb(dma_base + 0x03);
	265	DBG("scr1[%02X]\n", scr1);
	266	outb(scr1 & ~0x40, dma_base + 0x03);
	267
	268	/*
	269	* Calculate the input clock in Hz
	270	* (the clock counter is 30 bit wide and counts down)
	271	*/
353b39d1	272	usec_elapsed = ktime_us_delta(end_time, start_time);
56fe23d5	273	pll_input = ((start_count - end_count) & 0x3fffffff) / 10 *
8006bf56	274	(10000000 / usec_elapsed);
47694bb8 SS	275
	276	DBG("start[%ld] end[%ld]\n", start_count, end_count);
	277
	278	return pll_input;
	279	}
	280
1da177e4	281	#ifdef CONFIG_PPC_PMAC
feb22b7f	282	static void apple_kiwi_init(struct pci_dev *pdev)
1da177e4 LT	283	{
1da177e4 LT	284	struct device_node *np = pci_device_to_OF_node(pdev);
1da177e4 LT	285	u8 conf;
1da177e4 LT	286
55b61fec	287	if (np == NULL \|\| !of_device_is_compatible(np, "kiwi-root"))
1da177e4 LT	288	return;
1da177e4 LT	289
fc212bb1	290	if (pdev->revision >= 0x03) {
1da177e4	291	/* Setup chip magic config stuff (from darwin) */
47694bb8 SS	292	pci_read_config_byte (pdev, 0x40, &conf);
47694bb8 SS	293	pci_write_config_byte(pdev, 0x40, (conf \| 0x01));
1da177e4	294	}
1da177e4 LT	295	}
	296	#endif /* CONFIG_PPC_PMAC */
	297
2ed0ef54	298	static int init_chipset_pdcnew(struct pci_dev *dev)
1da177e4	299	{
a326b02b	300	const char *name = DRV_NAME;
47694bb8 SS	301	unsigned long dma_base = pci_resource_start(dev, 4);
	302	unsigned long sec_dma_base = dma_base + 0x08;
	303	long pll_input, pll_output, ratio;
	304	int f, r;
	305	u8 pll_ctl0, pll_ctl1;
	306
01cc643a BZ	307	if (dma_base == 0)
	308	return -EFAULT;
	309
1da177e4 LT	310	#ifdef CONFIG_PPC_PMAC
	311	apple_kiwi_init(dev);
	312	#endif
	313
47694bb8 SS	314	/* Calculate the required PLL output frequency */
	315	switch(max_dma_rate(dev)) {
	316	case 4: /* it's 133 MHz for Ultra133 chips */
	317	pll_output = 133333333;
	318	break;
	319	case 3: /* and 100 MHz for Ultra100 chips */
	320	default:
	321	pll_output = 100000000;
	322	break;
	323	}
	324
	325	/*
	326	* Detect PLL input clock.
	327	* On some systems, where PCI bus is running at non-standard clock rate
	328	* (e.g. 25 or 40 MHz), we have to adjust the cycle time.
	329	* PDC20268 and newer chips employ PLL circuit to help correct timing
	330	* registers setting.
	331	*/
	332	pll_input = detect_pll_input_clock(dma_base);
28cfd8af BZ	333	printk(KERN_INFO "%s %s: PLL input clock is %ld kHz\n",
28cfd8af BZ	334	name, pci_name(dev), pll_input / 1000);
47694bb8 SS	335
	336	/* Sanity check */
	337	if (unlikely(pll_input < 5000000L \|\| pll_input > 70000000L)) {
28cfd8af BZ	338	printk(KERN_ERR "%s %s: Bad PLL input clock %ld Hz, giving up!"
28cfd8af BZ	339	"\n", name, pci_name(dev), pll_input);
47694bb8 SS	340	goto out;
	341	}
	342
	343	#ifdef DEBUG
	344	DBG("pll_output is %ld Hz\n", pll_output);
	345
	346	/* Show the current clock value of PLL control register
	347	* (maybe already configured by the BIOS)
	348	*/
	349	outb(0x02, sec_dma_base + 0x01);
	350	pll_ctl0 = inb(sec_dma_base + 0x03);
	351	outb(0x03, sec_dma_base + 0x01);
	352	pll_ctl1 = inb(sec_dma_base + 0x03);
	353
	354	DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
	355	#endif
	356
	357	/*
	358	* Calculate the ratio of F, R and NO
	359	* POUT = (F + 2) / (( R + 2) * NO)
	360	*/
	361	ratio = pll_output / (pll_input / 1000);
	362	if (ratio < 8600L) { /* 8.6x */
	363	/* Using NO = 0x01, R = 0x0d */
	364	r = 0x0d;
	365	} else if (ratio < 12900L) { /* 12.9x */
	366	/* Using NO = 0x01, R = 0x08 */
	367	r = 0x08;
	368	} else if (ratio < 16100L) { /* 16.1x */
	369	/* Using NO = 0x01, R = 0x06 */
	370	r = 0x06;
	371	} else if (ratio < 64000L) { /* 64x */
	372	r = 0x00;
	373	} else {
	374	/* Invalid ratio */
28cfd8af BZ	375	printk(KERN_ERR "%s %s: Bad ratio %ld, giving up!\n",
28cfd8af BZ	376	name, pci_name(dev), ratio);
47694bb8 SS	377	goto out;
	378	}
	379
	380	f = (ratio * (r + 2)) / 1000 - 2;
	381
	382	DBG("F[%d] R[%d] ratio*1000[%ld]\n", f, r, ratio);
	383
	384	if (unlikely(f < 0 \|\| f > 127)) {
	385	/* Invalid F */
28cfd8af BZ	386	printk(KERN_ERR "%s %s: F[%d] invalid!\n",
28cfd8af BZ	387	name, pci_name(dev), f);
47694bb8 SS	388	goto out;
	389	}
	390
	391	pll_ctl0 = (u8) f;
	392	pll_ctl1 = (u8) r;
	393
	394	DBG("Writing pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
	395
	396	outb(0x02, sec_dma_base + 0x01);
	397	outb(pll_ctl0, sec_dma_base + 0x03);
	398	outb(0x03, sec_dma_base + 0x01);
	399	outb(pll_ctl1, sec_dma_base + 0x03);
	400
	401	/* Wait the PLL circuit to be stable */
	402	mdelay(30);
	403
	404	#ifdef DEBUG
	405	/*
	406	* Show the current clock value of PLL control register
	407	*/
	408	outb(0x02, sec_dma_base + 0x01);
	409	pll_ctl0 = inb(sec_dma_base + 0x03);
	410	outb(0x03, sec_dma_base + 0x01);
	411	pll_ctl1 = inb(sec_dma_base + 0x03);
	412
	413	DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
	414	#endif
	415
	416	out:
2ed0ef54	417	return 0;
1da177e4 LT	418	}
1da177e4 LT	419
fe31edc8	420	static struct pci_dev pdc20270_get_dev2(struct pci_dev dev)
1da177e4	421	{
099b1f42 BZ	422	struct pci_dev *dev2;
099b1f42 BZ	423
eadb6ecf	424	dev2 = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn) + 1,
099b1f42	425	PCI_FUNC(dev->devfn)));
eadb6ecf	426
099b1f42 BZ	427	if (dev2 &&
	428	dev2->vendor == dev->vendor &&
	429	dev2->device == dev->device) {
	430
	431	if (dev2->irq != dev->irq) {
	432	dev2->irq = dev->irq;
ced3ec8a	433	printk(KERN_INFO DRV_NAME " %s: PCI config space "
28cfd8af	434	"interrupt fixed\n", pci_name(dev));
1da177e4	435	}
07047935	436
099b1f42	437	return dev2;
1da177e4	438	}
099b1f42 BZ	439
099b1f42 BZ	440	return NULL;
1da177e4 LT	441	}
1da177e4 LT	442
ac95beed BZ	443	static const struct ide_port_ops pdcnew_port_ops = {
	444	.set_pio_mode = pdcnew_set_pio_mode,
	445	.set_dma_mode = pdcnew_set_dma_mode,
ac95beed BZ	446	.resetproc = pdcnew_reset,
	447	.cable_detect = pdcnew_cable_detect,
	448	};
	449
ced3ec8a	450	#define DECLARE_PDCNEW_DEV(udma) \
05d7e6cb	451	{ \
ced3ec8a	452	.name = DRV_NAME, \
05d7e6cb	453	.init_chipset = init_chipset_pdcnew, \
ac95beed	454	.port_ops = &pdcnew_port_ops, \
05d7e6cb	455	.host_flags = IDE_HFLAG_POST_SET_MODE \| \
ed67b923	456	IDE_HFLAG_ERROR_STOPS_FIFO \| \
05d7e6cb BZ	457	IDE_HFLAG_OFF_BOARD, \
	458	.pio_mask = ATA_PIO4, \
	459	.mwdma_mask = ATA_MWDMA2, \
	460	.udma_mask = udma, \
1da177e4	461	}
05d7e6cb	462
fe31edc8	463	static const struct ide_port_info pdcnew_chipsets[] = {
ced3ec8a BZ	464	/* 0: PDC202{68,70} */ DECLARE_PDCNEW_DEV(ATA_UDMA5),
ced3ec8a BZ	465	/* 1: PDC202{69,71,75,76,77} */ DECLARE_PDCNEW_DEV(ATA_UDMA6),
1da177e4 LT	466	};
	467
	468	/**
	469	* pdc202new_init_one - called when a pdc202xx is found
	470	* @dev: the pdc202new device
	471	* @id: the matching pci id
	472	*
	473	* Called when the PCI registration layer (or the IDE initialization)
	474	* finds a device matching our IDE device tables.
	475	*/
	476
fe31edc8	477	static int pdc202new_init_one(struct pci_dev dev, const struct pci_device_id id)
1da177e4	478	{
ced3ec8a	479	const struct ide_port_info *d = &pdcnew_chipsets[id->driver_data];
099b1f42	480	struct pci_dev *bridge = dev->bus->self;
099b1f42	481
ced3ec8a	482	if (dev->device == PCI_DEVICE_ID_PROMISE_20270 && bridge &&
099b1f42 BZ	483	bridge->vendor == PCI_VENDOR_ID_DEC &&
	484	bridge->device == PCI_DEVICE_ID_DEC_21150) {
	485	struct pci_dev *dev2;
	486
	487	if (PCI_SLOT(dev->devfn) & 2)
	488	return -ENODEV;
1da177e4	489
099b1f42 BZ	490	dev2 = pdc20270_get_dev2(dev);
	491
	492	if (dev2) {
6cdf6eb3	493	int ret = ide_pci_init_two(dev, dev2, d, NULL);
099b1f42 BZ	494	if (ret < 0)
	495	pci_dev_put(dev2);
	496	return ret;
	497	}
	498	}
	499
ced3ec8a	500	if (dev->device == PCI_DEVICE_ID_PROMISE_20276 && bridge &&
099b1f42 BZ	501	bridge->vendor == PCI_VENDOR_ID_INTEL &&
	502	(bridge->device == PCI_DEVICE_ID_INTEL_I960 \|\|
	503	bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) {
ced3ec8a	504	printk(KERN_INFO DRV_NAME " %s: attached to I2O RAID controller,"
28cfd8af	505	" skipping\n", pci_name(dev));
099b1f42 BZ	506	return -ENODEV;
	507	}
	508
6cdf6eb3	509	return ide_pci_init_one(dev, d, NULL);
1da177e4 LT	510	}
1da177e4 LT	511
fe31edc8	512	static void pdc202new_remove(struct pci_dev *dev)
d69c8f8c BZ	513	{
	514	struct ide_host *host = pci_get_drvdata(dev);
	515	struct pci_dev *dev2 = host->dev[1] ? to_pci_dev(host->dev[1]) : NULL;
	516
	517	ide_pci_remove(dev);
	518	pci_dev_put(dev2);
	519	}
	520
9cbcc5e3 BZ	521	static const struct pci_device_id pdc202new_pci_tbl[] = {
	522	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20268), 0 },
	523	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20269), 1 },
ced3ec8a BZ	524	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20270), 0 },
	525	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20271), 1 },
	526	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20275), 1 },
	527	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20276), 1 },
	528	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20277), 1 },
1da177e4 LT	529	{ 0, },
	530	};
	531	MODULE_DEVICE_TABLE(pci, pdc202new_pci_tbl);
	532
a9ab09e2	533	static struct pci_driver pdc202new_pci_driver = {
1da177e4 LT	534	.name = "Promise_IDE",
	535	.id_table = pdc202new_pci_tbl,
	536	.probe = pdc202new_init_one,
fe31edc8	537	.remove = pdc202new_remove,
feb22b7f BZ	538	.suspend = ide_pci_suspend,
feb22b7f BZ	539	.resume = ide_pci_resume,
1da177e4 LT	540	};
1da177e4 LT	541
82ab1eec	542	static int __init pdc202new_ide_init(void)
1da177e4	543	{
a9ab09e2	544	return ide_pci_register_driver(&pdc202new_pci_driver);
1da177e4 LT	545	}
1da177e4 LT	546
d69c8f8c BZ	547	static void __exit pdc202new_ide_exit(void)
d69c8f8c BZ	548	{
a9ab09e2	549	pci_unregister_driver(&pdc202new_pci_driver);
d69c8f8c BZ	550	}
d69c8f8c BZ	551
1da177e4	552	module_init(pdc202new_ide_init);
d69c8f8c	553	module_exit(pdc202new_ide_exit);
1da177e4 LT	554
	555	MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
	556	MODULE_DESCRIPTION("PCI driver module for Promise PDC20268 and higher");
	557	MODULE_LICENSE("GPL");