Commit | Line | Data |
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1da177e4 | 1 | /* |
0c8de52d | 2 | * linux/drivers/ide/pci/slc90e66.c Version 0.15 Jul 6, 2007 |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2000-2002 Andre Hedrick <andre@linux-ide.org> | |
07af4276 | 5 | * Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com> |
1da177e4 | 6 | * |
44854add | 7 | * This is a look-alike variation of the ICH0 PIIX4 Ultra-66, |
1da177e4 LT |
8 | * but this keeps the ISA-Bridge and slots alive. |
9 | * | |
10 | */ | |
11 | ||
1da177e4 LT |
12 | #include <linux/types.h> |
13 | #include <linux/module.h> | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/ioport.h> | |
16 | #include <linux/pci.h> | |
17 | #include <linux/hdreg.h> | |
18 | #include <linux/ide.h> | |
19 | #include <linux/delay.h> | |
20 | #include <linux/init.h> | |
21 | ||
22 | #include <asm/io.h> | |
23 | ||
1da177e4 LT |
24 | static u8 slc90e66_dma_2_pio (u8 xfer_rate) { |
25 | switch(xfer_rate) { | |
26 | case XFER_UDMA_4: | |
27 | case XFER_UDMA_3: | |
28 | case XFER_UDMA_2: | |
29 | case XFER_UDMA_1: | |
30 | case XFER_UDMA_0: | |
31 | case XFER_MW_DMA_2: | |
1da177e4 LT |
32 | return 4; |
33 | case XFER_MW_DMA_1: | |
1da177e4 LT |
34 | return 3; |
35 | case XFER_SW_DMA_2: | |
1da177e4 LT |
36 | return 2; |
37 | case XFER_MW_DMA_0: | |
38 | case XFER_SW_DMA_1: | |
39 | case XFER_SW_DMA_0: | |
1da177e4 LT |
40 | default: |
41 | return 0; | |
42 | } | |
43 | } | |
44 | ||
07af4276 | 45 | static void slc90e66_tune_pio (ide_drive_t *drive, u8 pio) |
1da177e4 LT |
46 | { |
47 | ide_hwif_t *hwif = HWIF(drive); | |
48 | struct pci_dev *dev = hwif->pci_dev; | |
24e6458d | 49 | int is_slave = drive->dn & 1; |
1da177e4 LT |
50 | int master_port = hwif->channel ? 0x42 : 0x40; |
51 | int slave_port = 0x44; | |
52 | unsigned long flags; | |
53 | u16 master_data; | |
54 | u8 slave_data; | |
24e6458d SS |
55 | int control = 0; |
56 | /* ISP RTC */ | |
f201f504 | 57 | static const u8 timings[][2]= { |
24e6458d SS |
58 | { 0, 0 }, |
59 | { 0, 0 }, | |
60 | { 1, 0 }, | |
61 | { 2, 1 }, | |
62 | { 2, 3 }, }; | |
1da177e4 | 63 | |
1da177e4 LT |
64 | spin_lock_irqsave(&ide_lock, flags); |
65 | pci_read_config_word(dev, master_port, &master_data); | |
24e6458d SS |
66 | |
67 | if (pio > 1) | |
68 | control |= 1; /* Programmable timing on */ | |
69 | if (drive->media == ide_disk) | |
70 | control |= 4; /* Prefetch, post write */ | |
71 | if (pio > 2) | |
72 | control |= 2; /* IORDY */ | |
1da177e4 | 73 | if (is_slave) { |
24e6458d SS |
74 | master_data |= 0x4000; |
75 | master_data &= ~0x0070; | |
76 | if (pio > 1) { | |
07af4276 SS |
77 | /* Set PPE, IE and TIME */ |
78 | master_data |= control << 4; | |
24e6458d | 79 | } |
1da177e4 | 80 | pci_read_config_byte(dev, slave_port, &slave_data); |
07af4276 SS |
81 | slave_data &= hwif->channel ? 0x0f : 0xf0; |
82 | slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << | |
83 | (hwif->channel ? 4 : 0); | |
1da177e4 | 84 | } else { |
24e6458d SS |
85 | master_data &= ~0x3307; |
86 | if (pio > 1) { | |
1da177e4 | 87 | /* enable PPE, IE and TIME */ |
07af4276 | 88 | master_data |= control; |
24e6458d | 89 | } |
07af4276 | 90 | master_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8); |
1da177e4 LT |
91 | } |
92 | pci_write_config_word(dev, master_port, master_data); | |
93 | if (is_slave) | |
94 | pci_write_config_byte(dev, slave_port, slave_data); | |
95 | spin_unlock_irqrestore(&ide_lock, flags); | |
96 | } | |
97 | ||
07af4276 SS |
98 | static void slc90e66_tune_drive (ide_drive_t *drive, u8 pio) |
99 | { | |
2134758d | 100 | pio = ide_get_best_pio_mode(drive, pio, 4); |
07af4276 SS |
101 | slc90e66_tune_pio(drive, pio); |
102 | (void) ide_config_drive_speed(drive, XFER_PIO_0 + pio); | |
103 | } | |
104 | ||
f212ff28 | 105 | static int slc90e66_tune_chipset(ide_drive_t *drive, const u8 speed) |
1da177e4 LT |
106 | { |
107 | ide_hwif_t *hwif = HWIF(drive); | |
108 | struct pci_dev *dev = hwif->pci_dev; | |
109 | u8 maslave = hwif->channel ? 0x42 : 0x40; | |
1da177e4 LT |
110 | int sitre = 0, a_speed = 7 << (drive->dn * 4); |
111 | int u_speed = 0, u_flag = 1 << drive->dn; | |
112 | u16 reg4042, reg44, reg48, reg4a; | |
113 | ||
114 | pci_read_config_word(dev, maslave, ®4042); | |
115 | sitre = (reg4042 & 0x4000) ? 1 : 0; | |
116 | pci_read_config_word(dev, 0x44, ®44); | |
117 | pci_read_config_word(dev, 0x48, ®48); | |
118 | pci_read_config_word(dev, 0x4a, ®4a); | |
119 | ||
120 | switch(speed) { | |
1da177e4 LT |
121 | case XFER_UDMA_4: u_speed = 4 << (drive->dn * 4); break; |
122 | case XFER_UDMA_3: u_speed = 3 << (drive->dn * 4); break; | |
123 | case XFER_UDMA_2: u_speed = 2 << (drive->dn * 4); break; | |
124 | case XFER_UDMA_1: u_speed = 1 << (drive->dn * 4); break; | |
125 | case XFER_UDMA_0: u_speed = 0 << (drive->dn * 4); break; | |
126 | case XFER_MW_DMA_2: | |
127 | case XFER_MW_DMA_1: | |
128 | case XFER_SW_DMA_2: break; | |
1da177e4 LT |
129 | case XFER_PIO_4: |
130 | case XFER_PIO_3: | |
131 | case XFER_PIO_2: | |
0c8de52d | 132 | case XFER_PIO_1: |
1da177e4 LT |
133 | case XFER_PIO_0: break; |
134 | default: return -1; | |
135 | } | |
136 | ||
137 | if (speed >= XFER_UDMA_0) { | |
138 | if (!(reg48 & u_flag)) | |
139 | pci_write_config_word(dev, 0x48, reg48|u_flag); | |
140 | /* FIXME: (reg4a & a_speed) ? */ | |
141 | if ((reg4a & u_speed) != u_speed) { | |
142 | pci_write_config_word(dev, 0x4a, reg4a & ~a_speed); | |
143 | pci_read_config_word(dev, 0x4a, ®4a); | |
144 | pci_write_config_word(dev, 0x4a, reg4a|u_speed); | |
145 | } | |
146 | } else { | |
147 | if (reg48 & u_flag) | |
148 | pci_write_config_word(dev, 0x48, reg48 & ~u_flag); | |
149 | if (reg4a & a_speed) | |
150 | pci_write_config_word(dev, 0x4a, reg4a & ~a_speed); | |
151 | } | |
152 | ||
0c8de52d BZ |
153 | if (speed > XFER_PIO_4) |
154 | slc90e66_tune_pio(drive, slc90e66_dma_2_pio(speed)); | |
155 | else | |
156 | slc90e66_tune_pio(drive, speed - XFER_PIO_0); | |
157 | ||
07af4276 | 158 | return ide_config_drive_speed(drive, speed); |
1da177e4 LT |
159 | } |
160 | ||
1da177e4 LT |
161 | static int slc90e66_config_drive_xfer_rate (ide_drive_t *drive) |
162 | { | |
1da177e4 LT |
163 | drive->init_speed = 0; |
164 | ||
29e744d0 | 165 | if (ide_tune_dma(drive)) |
3608b5d7 | 166 | return 0; |
1da177e4 | 167 | |
d8f4469d | 168 | if (ide_use_fast_pio(drive)) |
07af4276 | 169 | slc90e66_tune_drive(drive, 255); |
d8f4469d | 170 | |
3608b5d7 | 171 | return -1; |
1da177e4 | 172 | } |
1da177e4 | 173 | |
97319630 | 174 | static void __devinit init_hwif_slc90e66 (ide_hwif_t *hwif) |
1da177e4 LT |
175 | { |
176 | u8 reg47 = 0; | |
177 | u8 mask = hwif->channel ? 0x01 : 0x02; /* bit0:Primary */ | |
178 | ||
179 | hwif->autodma = 0; | |
180 | ||
181 | if (!hwif->irq) | |
182 | hwif->irq = hwif->channel ? 15 : 14; | |
183 | ||
184 | hwif->speedproc = &slc90e66_tune_chipset; | |
24e6458d | 185 | hwif->tuneproc = &slc90e66_tune_drive; |
1da177e4 LT |
186 | |
187 | pci_read_config_byte(hwif->pci_dev, 0x47, ®47); | |
188 | ||
189 | if (!hwif->dma_base) { | |
190 | hwif->drives[0].autotune = 1; | |
191 | hwif->drives[1].autotune = 1; | |
192 | return; | |
193 | } | |
194 | ||
195 | hwif->atapi_dma = 1; | |
196 | hwif->ultra_mask = 0x1f; | |
24e6458d SS |
197 | hwif->mwdma_mask = 0x06; |
198 | hwif->swdma_mask = 0x04; | |
1da177e4 | 199 | |
49521f97 | 200 | if (hwif->cbl != ATA_CBL_PATA40_SHORT) |
1da177e4 | 201 | /* bit[0(1)]: 0:80, 1:40 */ |
49521f97 | 202 | hwif->cbl = (reg47 & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80; |
1da177e4 LT |
203 | |
204 | hwif->ide_dma_check = &slc90e66_config_drive_xfer_rate; | |
24e6458d | 205 | |
1da177e4 LT |
206 | if (!noautodma) |
207 | hwif->autodma = 1; | |
208 | hwif->drives[0].autodma = hwif->autodma; | |
209 | hwif->drives[1].autodma = hwif->autodma; | |
1da177e4 LT |
210 | } |
211 | ||
212 | static ide_pci_device_t slc90e66_chipset __devinitdata = { | |
213 | .name = "SLC90E66", | |
214 | .init_hwif = init_hwif_slc90e66, | |
1da177e4 LT |
215 | .autodma = AUTODMA, |
216 | .enablebits = {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, | |
217 | .bootable = ON_BOARD, | |
4099d143 | 218 | .pio_mask = ATA_PIO4, |
1da177e4 LT |
219 | }; |
220 | ||
221 | static int __devinit slc90e66_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
222 | { | |
223 | return ide_setup_pci_device(dev, &slc90e66_chipset); | |
224 | } | |
225 | ||
226 | static struct pci_device_id slc90e66_pci_tbl[] = { | |
f201f504 | 227 | { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1), 0}, |
1da177e4 LT |
228 | { 0, }, |
229 | }; | |
230 | MODULE_DEVICE_TABLE(pci, slc90e66_pci_tbl); | |
231 | ||
232 | static struct pci_driver driver = { | |
233 | .name = "SLC90e66_IDE", | |
234 | .id_table = slc90e66_pci_tbl, | |
235 | .probe = slc90e66_init_one, | |
236 | }; | |
237 | ||
82ab1eec | 238 | static int __init slc90e66_ide_init(void) |
1da177e4 LT |
239 | { |
240 | return ide_pci_register_driver(&driver); | |
241 | } | |
242 | ||
243 | module_init(slc90e66_ide_init); | |
244 | ||
245 | MODULE_AUTHOR("Andre Hedrick"); | |
246 | MODULE_DESCRIPTION("PCI driver module for SLC90E66 IDE"); | |
247 | MODULE_LICENSE("GPL"); |