Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * linux/drivers/ide/pci/sl82c105.c | |
3 | * | |
4 | * SL82C105/Winbond 553 IDE driver | |
5 | * | |
6 | * Maintainer unknown. | |
7 | * | |
8 | * Drive tuning added from Rebel.com's kernel sources | |
9 | * -- Russell King (15/11/98) linux@arm.linux.org.uk | |
10 | * | |
11 | * Merge in Russell's HW workarounds, fix various problems | |
12 | * with the timing registers setup. | |
13 | * -- Benjamin Herrenschmidt (01/11/03) benh@kernel.crashing.org | |
e93df705 SS |
14 | * |
15 | * Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com> | |
1da177e4 LT |
16 | */ |
17 | ||
1da177e4 LT |
18 | #include <linux/types.h> |
19 | #include <linux/module.h> | |
20 | #include <linux/kernel.h> | |
21 | #include <linux/timer.h> | |
22 | #include <linux/mm.h> | |
23 | #include <linux/ioport.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/blkdev.h> | |
26 | #include <linux/hdreg.h> | |
27 | #include <linux/pci.h> | |
28 | #include <linux/ide.h> | |
29 | ||
30 | #include <asm/io.h> | |
31 | #include <asm/dma.h> | |
32 | ||
33 | #undef DEBUG | |
34 | ||
35 | #ifdef DEBUG | |
36 | #define DBG(arg) printk arg | |
37 | #else | |
38 | #define DBG(fmt,...) | |
39 | #endif | |
40 | /* | |
41 | * SL82C105 PCI config register 0x40 bits. | |
42 | */ | |
43 | #define CTRL_IDE_IRQB (1 << 30) | |
44 | #define CTRL_IDE_IRQA (1 << 28) | |
45 | #define CTRL_LEGIRQ (1 << 11) | |
46 | #define CTRL_P1F16 (1 << 5) | |
47 | #define CTRL_P1EN (1 << 4) | |
48 | #define CTRL_P0F16 (1 << 1) | |
49 | #define CTRL_P0EN (1 << 0) | |
50 | ||
51 | /* | |
e93df705 SS |
52 | * Convert a PIO mode and cycle time to the required on/off times |
53 | * for the interface. This has protection against runaway timings. | |
1da177e4 | 54 | */ |
e93df705 | 55 | static unsigned int get_pio_timings(ide_pio_data_t *p) |
1da177e4 | 56 | { |
e93df705 | 57 | unsigned int cmd_on, cmd_off; |
1da177e4 | 58 | |
e93df705 | 59 | cmd_on = (ide_pio_timings[p->pio_mode].active_time + 29) / 30; |
1da177e4 LT |
60 | cmd_off = (p->cycle_time - 30 * cmd_on + 29) / 30; |
61 | ||
1da177e4 LT |
62 | if (cmd_on == 0) |
63 | cmd_on = 1; | |
64 | ||
1da177e4 LT |
65 | if (cmd_off == 0) |
66 | cmd_off = 1; | |
67 | ||
68 | return (cmd_on - 1) << 8 | (cmd_off - 1) | (p->use_iordy ? 0x40 : 0x00); | |
69 | } | |
70 | ||
71 | /* | |
e93df705 | 72 | * Configure the chipset for PIO mode. |
1da177e4 | 73 | */ |
e93df705 | 74 | static u8 sl82c105_tune_pio(ide_drive_t *drive, u8 pio) |
1da177e4 | 75 | { |
e93df705 SS |
76 | struct pci_dev *dev = HWIF(drive)->pci_dev; |
77 | int reg = 0x44 + drive->dn * 4; | |
1da177e4 | 78 | ide_pio_data_t p; |
e93df705 | 79 | u16 drv_ctrl; |
1da177e4 | 80 | |
e93df705 | 81 | DBG(("sl82c105_tune_pio(drive:%s, pio:%u)\n", drive->name, pio)); |
1da177e4 LT |
82 | |
83 | pio = ide_get_best_pio_mode(drive, pio, 5, &p); | |
84 | ||
e93df705 | 85 | drive->drive_data = drv_ctrl = get_pio_timings(&p); |
1da177e4 | 86 | |
e93df705 | 87 | if (!drive->using_dma) { |
1da177e4 LT |
88 | /* |
89 | * If we are actually using MW DMA, then we can not | |
90 | * reprogram the interface drive control register. | |
91 | */ | |
e93df705 SS |
92 | pci_write_config_word(dev, reg, drv_ctrl); |
93 | pci_read_config_word (dev, reg, &drv_ctrl); | |
1da177e4 | 94 | } |
e93df705 SS |
95 | |
96 | printk(KERN_DEBUG "%s: selected %s (%dns) (%04X)\n", drive->name, | |
97 | ide_xfer_verbose(pio + XFER_PIO_0), p.cycle_time, drv_ctrl); | |
98 | ||
99 | return pio; | |
1da177e4 LT |
100 | } |
101 | ||
102 | /* | |
103 | * Configure the drive and the chipset for DMA | |
104 | */ | |
105 | static int config_for_dma (ide_drive_t *drive) | |
106 | { | |
107 | ide_hwif_t *hwif = HWIF(drive); | |
108 | struct pci_dev *dev = hwif->pci_dev; | |
109 | unsigned int reg; | |
110 | ||
111 | DBG(("config_for_dma(drive:%s)\n", drive->name)); | |
112 | ||
113 | reg = (hwif->channel ? 0x4c : 0x44) + (drive->select.b.unit ? 4 : 0); | |
114 | ||
115 | if (ide_config_drive_speed(drive, XFER_MW_DMA_2) != 0) | |
116 | return 1; | |
117 | ||
118 | pci_write_config_word(dev, reg, 0x0240); | |
119 | ||
120 | return 0; | |
121 | } | |
122 | ||
123 | /* | |
124 | * Check to see if the drive and | |
125 | * chipset is capable of DMA mode | |
126 | */ | |
127 | ||
128 | static int sl82c105_check_drive (ide_drive_t *drive) | |
129 | { | |
130 | ide_hwif_t *hwif = HWIF(drive); | |
131 | ||
132 | DBG(("sl82c105_check_drive(drive:%s)\n", drive->name)); | |
133 | ||
134 | do { | |
135 | struct hd_driveid *id = drive->id; | |
136 | ||
137 | if (!drive->autodma) | |
138 | break; | |
139 | ||
140 | if (!id || !(id->capability & 1)) | |
141 | break; | |
142 | ||
143 | /* Consult the list of known "bad" drives */ | |
144 | if (__ide_dma_bad_drive(drive)) | |
145 | break; | |
146 | ||
147 | if (id->field_valid & 2) { | |
148 | if ((id->dma_mword & hwif->mwdma_mask) || | |
149 | (id->dma_1word & hwif->swdma_mask)) | |
3608b5d7 | 150 | return 0; |
1da177e4 LT |
151 | } |
152 | ||
ea266ba1 | 153 | if (__ide_dma_good_drive(drive) && id->eide_dma_time < 150) |
3608b5d7 | 154 | return 0; |
1da177e4 LT |
155 | } while (0); |
156 | ||
3608b5d7 | 157 | return -1; |
1da177e4 LT |
158 | } |
159 | ||
160 | /* | |
161 | * The SL82C105 holds off all IDE interrupts while in DMA mode until | |
162 | * all DMA activity is completed. Sometimes this causes problems (eg, | |
163 | * when the drive wants to report an error condition). | |
164 | * | |
165 | * 0x7e is a "chip testing" register. Bit 2 resets the DMA controller | |
166 | * state machine. We need to kick this to work around various bugs. | |
167 | */ | |
168 | static inline void sl82c105_reset_host(struct pci_dev *dev) | |
169 | { | |
170 | u16 val; | |
171 | ||
172 | pci_read_config_word(dev, 0x7e, &val); | |
173 | pci_write_config_word(dev, 0x7e, val | (1 << 2)); | |
174 | pci_write_config_word(dev, 0x7e, val & ~(1 << 2)); | |
175 | } | |
176 | ||
177 | /* | |
178 | * If we get an IRQ timeout, it might be that the DMA state machine | |
179 | * got confused. Fix from Todd Inglett. Details from Winbond. | |
180 | * | |
181 | * This function is called when the IDE timer expires, the drive | |
182 | * indicates that it is READY, and we were waiting for DMA to complete. | |
183 | */ | |
184 | static int sl82c105_ide_dma_lost_irq(ide_drive_t *drive) | |
185 | { | |
186 | ide_hwif_t *hwif = HWIF(drive); | |
187 | struct pci_dev *dev = hwif->pci_dev; | |
188 | u32 val, mask = hwif->channel ? CTRL_IDE_IRQB : CTRL_IDE_IRQA; | |
189 | unsigned long dma_base = hwif->dma_base; | |
190 | ||
191 | printk("sl82c105: lost IRQ: resetting host\n"); | |
192 | ||
193 | /* | |
194 | * Check the raw interrupt from the drive. | |
195 | */ | |
196 | pci_read_config_dword(dev, 0x40, &val); | |
197 | if (val & mask) | |
198 | printk("sl82c105: drive was requesting IRQ, but host lost it\n"); | |
199 | ||
200 | /* | |
201 | * Was DMA enabled? If so, disable it - we're resetting the | |
202 | * host. The IDE layer will be handling the drive for us. | |
203 | */ | |
0ecdca26 | 204 | val = inb(dma_base); |
1da177e4 LT |
205 | if (val & 1) { |
206 | outb(val & ~1, dma_base); | |
207 | printk("sl82c105: DMA was enabled\n"); | |
208 | } | |
209 | ||
210 | sl82c105_reset_host(dev); | |
211 | ||
212 | /* ide_dmaproc would return 1, so we do as well */ | |
213 | return 1; | |
214 | } | |
215 | ||
216 | /* | |
217 | * ATAPI devices can cause the SL82C105 DMA state machine to go gaga. | |
218 | * Winbond recommend that the DMA state machine is reset prior to | |
219 | * setting the bus master DMA enable bit. | |
220 | * | |
221 | * The generic IDE core will have disabled the BMEN bit before this | |
222 | * function is called. | |
223 | */ | |
224 | static void sl82c105_ide_dma_start(ide_drive_t *drive) | |
225 | { | |
226 | ide_hwif_t *hwif = HWIF(drive); | |
227 | struct pci_dev *dev = hwif->pci_dev; | |
228 | ||
229 | sl82c105_reset_host(dev); | |
230 | ide_dma_start(drive); | |
231 | } | |
232 | ||
233 | static int sl82c105_ide_dma_timeout(ide_drive_t *drive) | |
234 | { | |
235 | ide_hwif_t *hwif = HWIF(drive); | |
236 | struct pci_dev *dev = hwif->pci_dev; | |
237 | ||
238 | DBG(("sl82c105_ide_dma_timeout(drive:%s)\n", drive->name)); | |
239 | ||
240 | sl82c105_reset_host(dev); | |
241 | return __ide_dma_timeout(drive); | |
242 | } | |
243 | ||
244 | static int sl82c105_ide_dma_on (ide_drive_t *drive) | |
245 | { | |
246 | DBG(("sl82c105_ide_dma_on(drive:%s)\n", drive->name)); | |
247 | ||
ea266ba1 SS |
248 | if (config_for_dma(drive)) |
249 | return 1; | |
1da177e4 LT |
250 | printk(KERN_INFO "%s: DMA enabled\n", drive->name); |
251 | return __ide_dma_on(drive); | |
252 | } | |
253 | ||
7469aaf6 | 254 | static void sl82c105_dma_off_quietly(ide_drive_t *drive) |
1da177e4 | 255 | { |
e93df705 SS |
256 | struct pci_dev *dev = HWIF(drive)->pci_dev; |
257 | int reg = 0x44 + drive->dn * 4; | |
1da177e4 | 258 | |
7469aaf6 BZ |
259 | DBG(("sl82c105_dma_off_quietly(drive:%s)\n", drive->name)); |
260 | ||
e93df705 SS |
261 | pci_write_config_word(dev, reg, drive->drive_data); |
262 | ||
7469aaf6 | 263 | ide_dma_off_quietly(drive); |
1da177e4 LT |
264 | } |
265 | ||
266 | /* | |
267 | * Ok, that is nasty, but we must make sure the DMA timings | |
268 | * won't be used for a PIO access. The solution here is | |
269 | * to make sure the 16 bits mode is diabled on the channel | |
270 | * when DMA is enabled, thus causing the chip to use PIO0 | |
271 | * timings for those operations. | |
272 | */ | |
273 | static void sl82c105_selectproc(ide_drive_t *drive) | |
274 | { | |
275 | ide_hwif_t *hwif = HWIF(drive); | |
276 | struct pci_dev *dev = hwif->pci_dev; | |
277 | u32 val, old, mask; | |
278 | ||
279 | //DBG(("sl82c105_selectproc(drive:%s)\n", drive->name)); | |
280 | ||
281 | mask = hwif->channel ? CTRL_P1F16 : CTRL_P0F16; | |
dd607d23 | 282 | old = val = (u32)pci_get_drvdata(dev); |
1da177e4 LT |
283 | if (drive->using_dma) |
284 | val &= ~mask; | |
285 | else | |
286 | val |= mask; | |
287 | if (old != val) { | |
288 | pci_write_config_dword(dev, 0x40, val); | |
dd607d23 | 289 | pci_set_drvdata(dev, (void *)val); |
1da177e4 LT |
290 | } |
291 | } | |
292 | ||
293 | /* | |
294 | * ATA reset will clear the 16 bits mode in the control | |
295 | * register, we need to update our cache | |
296 | */ | |
297 | static void sl82c105_resetproc(ide_drive_t *drive) | |
298 | { | |
dd607d23 | 299 | struct pci_dev *dev = HWIF(drive)->pci_dev; |
1da177e4 LT |
300 | u32 val; |
301 | ||
302 | DBG(("sl82c105_resetproc(drive:%s)\n", drive->name)); | |
303 | ||
304 | pci_read_config_dword(dev, 0x40, &val); | |
dd607d23 | 305 | pci_set_drvdata(dev, (void *)val); |
1da177e4 LT |
306 | } |
307 | ||
308 | /* | |
309 | * We only deal with PIO mode here - DMA mode 'using_dma' is not | |
310 | * initialised at the point that this function is called. | |
311 | */ | |
e93df705 | 312 | static void sl82c105_tune_drive(ide_drive_t *drive, u8 pio) |
1da177e4 | 313 | { |
e93df705 | 314 | DBG(("sl82c105_tune_drive(drive:%s, pio:%u)\n", drive->name, pio)); |
1da177e4 | 315 | |
e93df705 SS |
316 | pio = sl82c105_tune_pio(drive, pio); |
317 | (void) ide_config_drive_speed(drive, XFER_PIO_0 + pio); | |
1da177e4 LT |
318 | } |
319 | ||
320 | /* | |
321 | * Return the revision of the Winbond bridge | |
322 | * which this function is part of. | |
323 | */ | |
324 | static unsigned int sl82c105_bridge_revision(struct pci_dev *dev) | |
325 | { | |
326 | struct pci_dev *bridge; | |
327 | u8 rev; | |
328 | ||
329 | /* | |
330 | * The bridge should be part of the same device, but function 0. | |
331 | */ | |
332 | bridge = pci_find_slot(dev->bus->number, | |
333 | PCI_DEVFN(PCI_SLOT(dev->devfn), 0)); | |
334 | if (!bridge) | |
335 | return -1; | |
336 | ||
337 | /* | |
338 | * Make sure it is a Winbond 553 and is an ISA bridge. | |
339 | */ | |
340 | if (bridge->vendor != PCI_VENDOR_ID_WINBOND || | |
341 | bridge->device != PCI_DEVICE_ID_WINBOND_83C553 || | |
342 | bridge->class >> 8 != PCI_CLASS_BRIDGE_ISA) | |
343 | return -1; | |
344 | ||
345 | /* | |
346 | * We need to find function 0's revision, not function 1 | |
347 | */ | |
348 | pci_read_config_byte(bridge, PCI_REVISION_ID, &rev); | |
349 | ||
350 | return rev; | |
351 | } | |
352 | ||
353 | /* | |
354 | * Enable the PCI device | |
355 | * | |
356 | * --BenH: It's arch fixup code that should enable channels that | |
357 | * have not been enabled by firmware. I decided we can still enable | |
358 | * channel 0 here at least, but channel 1 has to be enabled by | |
359 | * firmware or arch code. We still set both to 16 bits mode. | |
360 | */ | |
34a62246 | 361 | static unsigned int __devinit init_chipset_sl82c105(struct pci_dev *dev, const char *msg) |
1da177e4 LT |
362 | { |
363 | u32 val; | |
364 | ||
365 | DBG(("init_chipset_sl82c105()\n")); | |
366 | ||
367 | pci_read_config_dword(dev, 0x40, &val); | |
368 | val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16; | |
369 | pci_write_config_dword(dev, 0x40, val); | |
dd607d23 | 370 | pci_set_drvdata(dev, (void *)val); |
1da177e4 LT |
371 | |
372 | return dev->irq; | |
373 | } | |
374 | ||
1da177e4 LT |
375 | /* |
376 | * Initialise the chip | |
377 | */ | |
34a62246 | 378 | static void __devinit init_hwif_sl82c105(ide_hwif_t *hwif) |
1da177e4 | 379 | { |
9648f552 | 380 | unsigned int rev; |
dd607d23 | 381 | |
1da177e4 LT |
382 | DBG(("init_hwif_sl82c105(hwif: ide%d)\n", hwif->index)); |
383 | ||
e93df705 SS |
384 | hwif->tuneproc = &sl82c105_tune_drive; |
385 | hwif->selectproc = &sl82c105_selectproc; | |
386 | hwif->resetproc = &sl82c105_resetproc; | |
387 | ||
388 | /* | |
389 | * We support 32-bit I/O on this interface, and | |
390 | * it doesn't have problems with interrupts. | |
391 | */ | |
392 | hwif->drives[0].io_32bit = hwif->drives[1].io_32bit = 1; | |
393 | hwif->drives[0].unmask = hwif->drives[1].unmask = 1; | |
dd607d23 SS |
394 | |
395 | /* | |
dd607d23 SS |
396 | * We always autotune PIO, this is done before DMA is checked, |
397 | * so there's no risk of accidentally disabling DMA | |
398 | */ | |
e93df705 | 399 | hwif->drives[0].autotune = hwif->drives[1].autotune = 1; |
1da177e4 | 400 | |
9648f552 RK |
401 | hwif->atapi_dma = 0; |
402 | hwif->mwdma_mask = 0; | |
403 | hwif->swdma_mask = 0; | |
404 | hwif->autodma = 0; | |
405 | ||
1da177e4 LT |
406 | if (!hwif->dma_base) |
407 | return; | |
408 | ||
9648f552 RK |
409 | rev = sl82c105_bridge_revision(hwif->pci_dev); |
410 | if (rev <= 5) { | |
411 | /* | |
412 | * Never ever EVER under any circumstances enable | |
413 | * DMA when the bridge is this old. | |
414 | */ | |
415 | printk(" %s: Winbond 553 bridge revision %d, BM-DMA disabled\n", | |
416 | hwif->name, rev); | |
417 | } else { | |
9648f552 | 418 | hwif->atapi_dma = 1; |
ea266ba1 | 419 | hwif->mwdma_mask = 0x04; |
9648f552 RK |
420 | |
421 | hwif->ide_dma_check = &sl82c105_check_drive; | |
422 | hwif->ide_dma_on = &sl82c105_ide_dma_on; | |
7469aaf6 | 423 | hwif->dma_off_quietly = &sl82c105_dma_off_quietly; |
9648f552 RK |
424 | hwif->ide_dma_lostirq = &sl82c105_ide_dma_lost_irq; |
425 | hwif->dma_start = &sl82c105_ide_dma_start; | |
426 | hwif->ide_dma_timeout = &sl82c105_ide_dma_timeout; | |
427 | ||
428 | if (!noautodma) | |
429 | hwif->autodma = 1; | |
430 | hwif->drives[0].autodma = hwif->autodma; | |
431 | hwif->drives[1].autodma = hwif->autodma; | |
a1510210 RK |
432 | |
433 | if (hwif->mate) | |
434 | hwif->serialized = hwif->mate->serialized = 1; | |
9648f552 | 435 | } |
1da177e4 LT |
436 | } |
437 | ||
438 | static ide_pci_device_t sl82c105_chipset __devinitdata = { | |
439 | .name = "W82C105", | |
440 | .init_chipset = init_chipset_sl82c105, | |
441 | .init_hwif = init_hwif_sl82c105, | |
1da177e4 LT |
442 | .channels = 2, |
443 | .autodma = NOAUTODMA, | |
444 | .enablebits = {{0x40,0x01,0x01}, {0x40,0x10,0x10}}, | |
445 | .bootable = ON_BOARD, | |
446 | }; | |
447 | ||
448 | static int __devinit sl82c105_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
449 | { | |
450 | return ide_setup_pci_device(dev, &sl82c105_chipset); | |
451 | } | |
452 | ||
453 | static struct pci_device_id sl82c105_pci_tbl[] = { | |
f201f504 | 454 | { PCI_DEVICE(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105), 0}, |
1da177e4 LT |
455 | { 0, }, |
456 | }; | |
457 | MODULE_DEVICE_TABLE(pci, sl82c105_pci_tbl); | |
458 | ||
459 | static struct pci_driver driver = { | |
460 | .name = "W82C105_IDE", | |
461 | .id_table = sl82c105_pci_tbl, | |
462 | .probe = sl82c105_init_one, | |
463 | }; | |
464 | ||
82ab1eec | 465 | static int __init sl82c105_ide_init(void) |
1da177e4 LT |
466 | { |
467 | return ide_pci_register_driver(&driver); | |
468 | } | |
469 | ||
470 | module_init(sl82c105_ide_init); | |
471 | ||
472 | MODULE_DESCRIPTION("PCI driver module for W82C105 IDE"); | |
473 | MODULE_LICENSE("GPL"); |