Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/drzeus/mmc
[linux-2.6-block.git] / drivers / ide / pci / sl82c105.c
CommitLineData
1da177e4
LT
1/*
2 * linux/drivers/ide/pci/sl82c105.c
3 *
4 * SL82C105/Winbond 553 IDE driver
5 *
6 * Maintainer unknown.
7 *
8 * Drive tuning added from Rebel.com's kernel sources
9 * -- Russell King (15/11/98) linux@arm.linux.org.uk
10 *
11 * Merge in Russell's HW workarounds, fix various problems
12 * with the timing registers setup.
13 * -- Benjamin Herrenschmidt (01/11/03) benh@kernel.crashing.org
14 */
15
1da177e4
LT
16#include <linux/types.h>
17#include <linux/module.h>
18#include <linux/kernel.h>
19#include <linux/timer.h>
20#include <linux/mm.h>
21#include <linux/ioport.h>
22#include <linux/interrupt.h>
23#include <linux/blkdev.h>
24#include <linux/hdreg.h>
25#include <linux/pci.h>
26#include <linux/ide.h>
27
28#include <asm/io.h>
29#include <asm/dma.h>
30
31#undef DEBUG
32
33#ifdef DEBUG
34#define DBG(arg) printk arg
35#else
36#define DBG(fmt,...)
37#endif
38/*
39 * SL82C105 PCI config register 0x40 bits.
40 */
41#define CTRL_IDE_IRQB (1 << 30)
42#define CTRL_IDE_IRQA (1 << 28)
43#define CTRL_LEGIRQ (1 << 11)
44#define CTRL_P1F16 (1 << 5)
45#define CTRL_P1EN (1 << 4)
46#define CTRL_P0F16 (1 << 1)
47#define CTRL_P0EN (1 << 0)
48
49/*
50 * Convert a PIO mode and cycle time to the required on/off
51 * times for the interface. This has protection against run-away
52 * timings.
53 */
54static unsigned int get_timing_sl82c105(ide_pio_data_t *p)
55{
56 unsigned int cmd_on;
57 unsigned int cmd_off;
58
59 cmd_on = (ide_pio_timings[p->pio_mode].active_time + 29) / 30;
60 cmd_off = (p->cycle_time - 30 * cmd_on + 29) / 30;
61
62 if (cmd_on > 32)
63 cmd_on = 32;
64 if (cmd_on == 0)
65 cmd_on = 1;
66
67 if (cmd_off > 32)
68 cmd_off = 32;
69 if (cmd_off == 0)
70 cmd_off = 1;
71
72 return (cmd_on - 1) << 8 | (cmd_off - 1) | (p->use_iordy ? 0x40 : 0x00);
73}
74
75/*
76 * Configure the drive and chipset for PIO
77 */
78static void config_for_pio(ide_drive_t *drive, int pio, int report, int chipset_only)
79{
80 ide_hwif_t *hwif = HWIF(drive);
81 struct pci_dev *dev = hwif->pci_dev;
82 ide_pio_data_t p;
83 u16 drv_ctrl = 0x909;
84 unsigned int xfer_mode, reg;
85
86 DBG(("config_for_pio(drive:%s, pio:%d, report:%d, chipset_only:%d)\n",
87 drive->name, pio, report, chipset_only));
88
89 reg = (hwif->channel ? 0x4c : 0x44) + (drive->select.b.unit ? 4 : 0);
90
91 pio = ide_get_best_pio_mode(drive, pio, 5, &p);
92
93 xfer_mode = XFER_PIO_0 + pio;
94
95 if (chipset_only || ide_config_drive_speed(drive, xfer_mode) == 0) {
96 drv_ctrl = get_timing_sl82c105(&p);
97 drive->pio_speed = xfer_mode;
98 } else
99 drive->pio_speed = XFER_PIO_0;
100
101 if (drive->using_dma == 0) {
102 /*
103 * If we are actually using MW DMA, then we can not
104 * reprogram the interface drive control register.
105 */
106 pci_write_config_word(dev, reg, drv_ctrl);
107 pci_read_config_word(dev, reg, &drv_ctrl);
108
109 if (report) {
110 printk("%s: selected %s (%dns) (%04X)\n", drive->name,
111 ide_xfer_verbose(xfer_mode), p.cycle_time, drv_ctrl);
112 }
113 }
114}
115
116/*
117 * Configure the drive and the chipset for DMA
118 */
119static int config_for_dma (ide_drive_t *drive)
120{
121 ide_hwif_t *hwif = HWIF(drive);
122 struct pci_dev *dev = hwif->pci_dev;
123 unsigned int reg;
124
125 DBG(("config_for_dma(drive:%s)\n", drive->name));
126
127 reg = (hwif->channel ? 0x4c : 0x44) + (drive->select.b.unit ? 4 : 0);
128
129 if (ide_config_drive_speed(drive, XFER_MW_DMA_2) != 0)
130 return 1;
131
132 pci_write_config_word(dev, reg, 0x0240);
133
134 return 0;
135}
136
137/*
138 * Check to see if the drive and
139 * chipset is capable of DMA mode
140 */
141
142static int sl82c105_check_drive (ide_drive_t *drive)
143{
144 ide_hwif_t *hwif = HWIF(drive);
145
146 DBG(("sl82c105_check_drive(drive:%s)\n", drive->name));
147
148 do {
149 struct hd_driveid *id = drive->id;
150
151 if (!drive->autodma)
152 break;
153
154 if (!id || !(id->capability & 1))
155 break;
156
157 /* Consult the list of known "bad" drives */
158 if (__ide_dma_bad_drive(drive))
159 break;
160
161 if (id->field_valid & 2) {
162 if ((id->dma_mword & hwif->mwdma_mask) ||
163 (id->dma_1word & hwif->swdma_mask))
3608b5d7 164 return 0;
1da177e4
LT
165 }
166
ea266ba1 167 if (__ide_dma_good_drive(drive) && id->eide_dma_time < 150)
3608b5d7 168 return 0;
1da177e4
LT
169 } while (0);
170
3608b5d7 171 return -1;
1da177e4
LT
172}
173
174/*
175 * The SL82C105 holds off all IDE interrupts while in DMA mode until
176 * all DMA activity is completed. Sometimes this causes problems (eg,
177 * when the drive wants to report an error condition).
178 *
179 * 0x7e is a "chip testing" register. Bit 2 resets the DMA controller
180 * state machine. We need to kick this to work around various bugs.
181 */
182static inline void sl82c105_reset_host(struct pci_dev *dev)
183{
184 u16 val;
185
186 pci_read_config_word(dev, 0x7e, &val);
187 pci_write_config_word(dev, 0x7e, val | (1 << 2));
188 pci_write_config_word(dev, 0x7e, val & ~(1 << 2));
189}
190
191/*
192 * If we get an IRQ timeout, it might be that the DMA state machine
193 * got confused. Fix from Todd Inglett. Details from Winbond.
194 *
195 * This function is called when the IDE timer expires, the drive
196 * indicates that it is READY, and we were waiting for DMA to complete.
197 */
198static int sl82c105_ide_dma_lost_irq(ide_drive_t *drive)
199{
200 ide_hwif_t *hwif = HWIF(drive);
201 struct pci_dev *dev = hwif->pci_dev;
202 u32 val, mask = hwif->channel ? CTRL_IDE_IRQB : CTRL_IDE_IRQA;
203 unsigned long dma_base = hwif->dma_base;
204
205 printk("sl82c105: lost IRQ: resetting host\n");
206
207 /*
208 * Check the raw interrupt from the drive.
209 */
210 pci_read_config_dword(dev, 0x40, &val);
211 if (val & mask)
212 printk("sl82c105: drive was requesting IRQ, but host lost it\n");
213
214 /*
215 * Was DMA enabled? If so, disable it - we're resetting the
216 * host. The IDE layer will be handling the drive for us.
217 */
0ecdca26 218 val = inb(dma_base);
1da177e4
LT
219 if (val & 1) {
220 outb(val & ~1, dma_base);
221 printk("sl82c105: DMA was enabled\n");
222 }
223
224 sl82c105_reset_host(dev);
225
226 /* ide_dmaproc would return 1, so we do as well */
227 return 1;
228}
229
230/*
231 * ATAPI devices can cause the SL82C105 DMA state machine to go gaga.
232 * Winbond recommend that the DMA state machine is reset prior to
233 * setting the bus master DMA enable bit.
234 *
235 * The generic IDE core will have disabled the BMEN bit before this
236 * function is called.
237 */
238static void sl82c105_ide_dma_start(ide_drive_t *drive)
239{
240 ide_hwif_t *hwif = HWIF(drive);
241 struct pci_dev *dev = hwif->pci_dev;
242
243 sl82c105_reset_host(dev);
244 ide_dma_start(drive);
245}
246
247static int sl82c105_ide_dma_timeout(ide_drive_t *drive)
248{
249 ide_hwif_t *hwif = HWIF(drive);
250 struct pci_dev *dev = hwif->pci_dev;
251
252 DBG(("sl82c105_ide_dma_timeout(drive:%s)\n", drive->name));
253
254 sl82c105_reset_host(dev);
255 return __ide_dma_timeout(drive);
256}
257
258static int sl82c105_ide_dma_on (ide_drive_t *drive)
259{
260 DBG(("sl82c105_ide_dma_on(drive:%s)\n", drive->name));
261
ea266ba1
SS
262 if (config_for_dma(drive))
263 return 1;
1da177e4
LT
264 printk(KERN_INFO "%s: DMA enabled\n", drive->name);
265 return __ide_dma_on(drive);
266}
267
7469aaf6 268static void sl82c105_dma_off_quietly(ide_drive_t *drive)
1da177e4
LT
269{
270 u8 speed = XFER_PIO_0;
1da177e4 271
7469aaf6
BZ
272 DBG(("sl82c105_dma_off_quietly(drive:%s)\n", drive->name));
273
274 ide_dma_off_quietly(drive);
1da177e4
LT
275 if (drive->pio_speed)
276 speed = drive->pio_speed - XFER_PIO_0;
277 config_for_pio(drive, speed, 0, 1);
1da177e4
LT
278}
279
280/*
281 * Ok, that is nasty, but we must make sure the DMA timings
282 * won't be used for a PIO access. The solution here is
283 * to make sure the 16 bits mode is diabled on the channel
284 * when DMA is enabled, thus causing the chip to use PIO0
285 * timings for those operations.
286 */
287static void sl82c105_selectproc(ide_drive_t *drive)
288{
289 ide_hwif_t *hwif = HWIF(drive);
290 struct pci_dev *dev = hwif->pci_dev;
291 u32 val, old, mask;
292
293 //DBG(("sl82c105_selectproc(drive:%s)\n", drive->name));
294
295 mask = hwif->channel ? CTRL_P1F16 : CTRL_P0F16;
dd607d23 296 old = val = (u32)pci_get_drvdata(dev);
1da177e4
LT
297 if (drive->using_dma)
298 val &= ~mask;
299 else
300 val |= mask;
301 if (old != val) {
302 pci_write_config_dword(dev, 0x40, val);
dd607d23 303 pci_set_drvdata(dev, (void *)val);
1da177e4
LT
304 }
305}
306
307/*
308 * ATA reset will clear the 16 bits mode in the control
309 * register, we need to update our cache
310 */
311static void sl82c105_resetproc(ide_drive_t *drive)
312{
dd607d23 313 struct pci_dev *dev = HWIF(drive)->pci_dev;
1da177e4
LT
314 u32 val;
315
316 DBG(("sl82c105_resetproc(drive:%s)\n", drive->name));
317
318 pci_read_config_dword(dev, 0x40, &val);
dd607d23 319 pci_set_drvdata(dev, (void *)val);
1da177e4
LT
320}
321
322/*
323 * We only deal with PIO mode here - DMA mode 'using_dma' is not
324 * initialised at the point that this function is called.
325 */
326static void tune_sl82c105(ide_drive_t *drive, u8 pio)
327{
328 DBG(("tune_sl82c105(drive:%s)\n", drive->name));
329
330 config_for_pio(drive, pio, 1, 0);
331
332 /*
333 * We support 32-bit I/O on this interface, and it
334 * doesn't have problems with interrupts.
335 */
336 drive->io_32bit = 1;
337 drive->unmask = 1;
338}
339
340/*
341 * Return the revision of the Winbond bridge
342 * which this function is part of.
343 */
344static unsigned int sl82c105_bridge_revision(struct pci_dev *dev)
345{
346 struct pci_dev *bridge;
347 u8 rev;
348
349 /*
350 * The bridge should be part of the same device, but function 0.
351 */
352 bridge = pci_find_slot(dev->bus->number,
353 PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
354 if (!bridge)
355 return -1;
356
357 /*
358 * Make sure it is a Winbond 553 and is an ISA bridge.
359 */
360 if (bridge->vendor != PCI_VENDOR_ID_WINBOND ||
361 bridge->device != PCI_DEVICE_ID_WINBOND_83C553 ||
362 bridge->class >> 8 != PCI_CLASS_BRIDGE_ISA)
363 return -1;
364
365 /*
366 * We need to find function 0's revision, not function 1
367 */
368 pci_read_config_byte(bridge, PCI_REVISION_ID, &rev);
369
370 return rev;
371}
372
373/*
374 * Enable the PCI device
375 *
376 * --BenH: It's arch fixup code that should enable channels that
377 * have not been enabled by firmware. I decided we can still enable
378 * channel 0 here at least, but channel 1 has to be enabled by
379 * firmware or arch code. We still set both to 16 bits mode.
380 */
34a62246 381static unsigned int __devinit init_chipset_sl82c105(struct pci_dev *dev, const char *msg)
1da177e4
LT
382{
383 u32 val;
384
385 DBG(("init_chipset_sl82c105()\n"));
386
387 pci_read_config_dword(dev, 0x40, &val);
388 val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16;
389 pci_write_config_dword(dev, 0x40, val);
dd607d23 390 pci_set_drvdata(dev, (void *)val);
1da177e4
LT
391
392 return dev->irq;
393}
394
1da177e4
LT
395/*
396 * Initialise the chip
397 */
34a62246 398static void __devinit init_hwif_sl82c105(ide_hwif_t *hwif)
1da177e4 399{
9648f552 400 unsigned int rev;
dd607d23 401
1da177e4
LT
402 DBG(("init_hwif_sl82c105(hwif: ide%d)\n", hwif->index));
403
404 hwif->tuneproc = tune_sl82c105;
405 hwif->selectproc = sl82c105_selectproc;
406 hwif->resetproc = sl82c105_resetproc;
dd607d23
SS
407
408 /*
409 * Default to PIO 0 for fallback unless tuned otherwise.
410 * We always autotune PIO, this is done before DMA is checked,
411 * so there's no risk of accidentally disabling DMA
412 */
1da177e4
LT
413 hwif->drives[0].pio_speed = XFER_PIO_0;
414 hwif->drives[0].autotune = 1;
dd607d23 415 hwif->drives[1].pio_speed = XFER_PIO_0;
1da177e4
LT
416 hwif->drives[1].autotune = 1;
417
9648f552
RK
418 hwif->atapi_dma = 0;
419 hwif->mwdma_mask = 0;
420 hwif->swdma_mask = 0;
421 hwif->autodma = 0;
422
1da177e4
LT
423 if (!hwif->dma_base)
424 return;
425
9648f552
RK
426 rev = sl82c105_bridge_revision(hwif->pci_dev);
427 if (rev <= 5) {
428 /*
429 * Never ever EVER under any circumstances enable
430 * DMA when the bridge is this old.
431 */
432 printk(" %s: Winbond 553 bridge revision %d, BM-DMA disabled\n",
433 hwif->name, rev);
434 } else {
9648f552 435 hwif->atapi_dma = 1;
ea266ba1 436 hwif->mwdma_mask = 0x04;
9648f552
RK
437
438 hwif->ide_dma_check = &sl82c105_check_drive;
439 hwif->ide_dma_on = &sl82c105_ide_dma_on;
7469aaf6 440 hwif->dma_off_quietly = &sl82c105_dma_off_quietly;
9648f552
RK
441 hwif->ide_dma_lostirq = &sl82c105_ide_dma_lost_irq;
442 hwif->dma_start = &sl82c105_ide_dma_start;
443 hwif->ide_dma_timeout = &sl82c105_ide_dma_timeout;
444
445 if (!noautodma)
446 hwif->autodma = 1;
447 hwif->drives[0].autodma = hwif->autodma;
448 hwif->drives[1].autodma = hwif->autodma;
a1510210
RK
449
450 if (hwif->mate)
451 hwif->serialized = hwif->mate->serialized = 1;
9648f552 452 }
1da177e4
LT
453}
454
455static ide_pci_device_t sl82c105_chipset __devinitdata = {
456 .name = "W82C105",
457 .init_chipset = init_chipset_sl82c105,
458 .init_hwif = init_hwif_sl82c105,
1da177e4
LT
459 .channels = 2,
460 .autodma = NOAUTODMA,
461 .enablebits = {{0x40,0x01,0x01}, {0x40,0x10,0x10}},
462 .bootable = ON_BOARD,
463};
464
465static int __devinit sl82c105_init_one(struct pci_dev *dev, const struct pci_device_id *id)
466{
467 return ide_setup_pci_device(dev, &sl82c105_chipset);
468}
469
470static struct pci_device_id sl82c105_pci_tbl[] = {
f201f504 471 { PCI_DEVICE(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105), 0},
1da177e4
LT
472 { 0, },
473};
474MODULE_DEVICE_TABLE(pci, sl82c105_pci_tbl);
475
476static struct pci_driver driver = {
477 .name = "W82C105_IDE",
478 .id_table = sl82c105_pci_tbl,
479 .probe = sl82c105_init_one,
480};
481
82ab1eec 482static int __init sl82c105_ide_init(void)
1da177e4
LT
483{
484 return ide_pci_register_driver(&driver);
485}
486
487module_init(sl82c105_ide_init);
488
489MODULE_DESCRIPTION("PCI driver module for W82C105 IDE");
490MODULE_LICENSE("GPL");