Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org> |
3 | * Copyright (C) 2002 Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer | |
4 | * Copyright (C) 2003 Vojtech Pavlik <vojtech@suse.cz> | |
6b8cf772 BZ |
5 | * Copyright (C) 2007 Bartlomiej Zolnierkiewicz |
6 | * | |
1da177e4 LT |
7 | * May be copied or modified under the terms of the GNU General Public License |
8 | * | |
9 | * | |
10 | * Thanks : | |
11 | * | |
12 | * SiS Taiwan : for direct support and hardware. | |
13 | * Daniela Engert : for initial ATA100 advices and numerous others. | |
14 | * John Fremlin, Manfred Spraul, Dave Morgan, Peter Kjellerstedt : | |
15 | * for checking code correctness, providing patches. | |
16 | * | |
17 | * | |
18 | * Original tests and design on the SiS620 chipset. | |
19 | * ATA100 tests and design on the SiS735 chipset. | |
20 | * ATA16/33 support from specs | |
21 | * ATA133 support for SiS961/962 by L.C. Chang <lcchang@sis.com.tw> | |
22 | * ATA133 961/962/963 fixes by Vojtech Pavlik <vojtech@suse.cz> | |
23 | * | |
24 | * Documentation: | |
25 | * SiS chipset documentation available under NDA to companies only | |
26 | * (not to individuals). | |
27 | */ | |
28 | ||
29 | /* | |
30 | * The original SiS5513 comes from a SiS5511/55112/5513 chipset. The original | |
31 | * SiS5513 was also used in the SiS5596/5513 chipset. Thus if we see a SiS5511 | |
32 | * or SiS5596, we can assume we see the first MWDMA-16 capable SiS5513 chip. | |
33 | * | |
34 | * Later SiS chipsets integrated the 5513 functionality into the NorthBridge, | |
35 | * starting with SiS5571 and up to SiS745. The PCI ID didn't change, though. We | |
36 | * can figure out that we have a more modern and more capable 5513 by looking | |
37 | * for the respective NorthBridge IDs. | |
38 | * | |
39 | * Even later (96x family) SiS chipsets use the MuTIOL link and place the 5513 | |
40 | * into the SouthBrige. Here we cannot rely on looking up the NorthBridge PCI | |
41 | * ID, while the now ATA-133 capable 5513 still has the same PCI ID. | |
42 | * Fortunately the 5513 can be 'unmasked' by fiddling with some config space | |
43 | * bits, changing its device id to the true one - 5517 for 961 and 5518 for | |
44 | * 962/963. | |
45 | */ | |
46 | ||
1da177e4 LT |
47 | #include <linux/types.h> |
48 | #include <linux/module.h> | |
49 | #include <linux/kernel.h> | |
1da177e4 | 50 | #include <linux/hdreg.h> |
1da177e4 LT |
51 | #include <linux/pci.h> |
52 | #include <linux/init.h> | |
53 | #include <linux/ide.h> | |
54 | ||
1da177e4 LT |
55 | /* registers layout and init values are chipset family dependant */ |
56 | ||
57 | #define ATA_16 0x01 | |
58 | #define ATA_33 0x02 | |
59 | #define ATA_66 0x03 | |
1eb3c2ee | 60 | #define ATA_100a 0x04 /* SiS730/SiS550 is ATA100 with ATA66 layout */ |
1da177e4 | 61 | #define ATA_100 0x05 |
1eb3c2ee PC |
62 | #define ATA_133a 0x06 /* SiS961b with 133 support */ |
63 | #define ATA_133 0x07 /* SiS962/963 */ | |
1da177e4 LT |
64 | |
65 | static u8 chipset_family; | |
66 | ||
67 | /* | |
68 | * Devices supported | |
69 | */ | |
70 | static const struct { | |
71 | const char *name; | |
72 | u16 host_id; | |
73 | u8 chipset_family; | |
74 | u8 flags; | |
75 | } SiSHostChipInfo[] = { | |
47d4b906 DW |
76 | { "SiS968", PCI_DEVICE_ID_SI_968, ATA_133 }, |
77 | { "SiS966", PCI_DEVICE_ID_SI_966, ATA_133 }, | |
14351f8e | 78 | { "SiS965", PCI_DEVICE_ID_SI_965, ATA_133 }, |
1da177e4 LT |
79 | { "SiS745", PCI_DEVICE_ID_SI_745, ATA_100 }, |
80 | { "SiS735", PCI_DEVICE_ID_SI_735, ATA_100 }, | |
81 | { "SiS733", PCI_DEVICE_ID_SI_733, ATA_100 }, | |
82 | { "SiS635", PCI_DEVICE_ID_SI_635, ATA_100 }, | |
83 | { "SiS633", PCI_DEVICE_ID_SI_633, ATA_100 }, | |
84 | ||
85 | { "SiS730", PCI_DEVICE_ID_SI_730, ATA_100a }, | |
86 | { "SiS550", PCI_DEVICE_ID_SI_550, ATA_100a }, | |
87 | ||
88 | { "SiS640", PCI_DEVICE_ID_SI_640, ATA_66 }, | |
89 | { "SiS630", PCI_DEVICE_ID_SI_630, ATA_66 }, | |
90 | { "SiS620", PCI_DEVICE_ID_SI_620, ATA_66 }, | |
91 | { "SiS540", PCI_DEVICE_ID_SI_540, ATA_66 }, | |
92 | { "SiS530", PCI_DEVICE_ID_SI_530, ATA_66 }, | |
93 | ||
94 | { "SiS5600", PCI_DEVICE_ID_SI_5600, ATA_33 }, | |
95 | { "SiS5598", PCI_DEVICE_ID_SI_5598, ATA_33 }, | |
96 | { "SiS5597", PCI_DEVICE_ID_SI_5597, ATA_33 }, | |
97 | { "SiS5591/2", PCI_DEVICE_ID_SI_5591, ATA_33 }, | |
98 | { "SiS5582", PCI_DEVICE_ID_SI_5582, ATA_33 }, | |
99 | { "SiS5581", PCI_DEVICE_ID_SI_5581, ATA_33 }, | |
100 | ||
101 | { "SiS5596", PCI_DEVICE_ID_SI_5596, ATA_16 }, | |
102 | { "SiS5571", PCI_DEVICE_ID_SI_5571, ATA_16 }, | |
d266ab88 | 103 | { "SiS5517", PCI_DEVICE_ID_SI_5517, ATA_16 }, |
1da177e4 LT |
104 | { "SiS551x", PCI_DEVICE_ID_SI_5511, ATA_16 }, |
105 | }; | |
106 | ||
107 | /* Cycle time bits and values vary across chip dma capabilities | |
108 | These three arrays hold the register layout and the values to set. | |
109 | Indexed by chipset_family and (dma_mode - XFER_UDMA_0) */ | |
110 | ||
111 | /* {0, ATA_16, ATA_33, ATA_66, ATA_100a, ATA_100, ATA_133} */ | |
1eb3c2ee PC |
112 | static u8 cycle_time_offset[] = { 0, 0, 5, 4, 4, 0, 0 }; |
113 | static u8 cycle_time_range[] = { 0, 0, 2, 3, 3, 4, 4 }; | |
1da177e4 | 114 | static u8 cycle_time_value[][XFER_UDMA_6 - XFER_UDMA_0 + 1] = { |
1eb3c2ee PC |
115 | { 0, 0, 0, 0, 0, 0, 0 }, /* no UDMA */ |
116 | { 0, 0, 0, 0, 0, 0, 0 }, /* no UDMA */ | |
117 | { 3, 2, 1, 0, 0, 0, 0 }, /* ATA_33 */ | |
118 | { 7, 5, 3, 2, 1, 0, 0 }, /* ATA_66 */ | |
119 | { 7, 5, 3, 2, 1, 0, 0 }, /* ATA_100a (730 specific), | |
120 | different cycle_time range and offset */ | |
121 | { 11, 7, 5, 4, 2, 1, 0 }, /* ATA_100 */ | |
122 | { 15, 10, 7, 5, 3, 2, 1 }, /* ATA_133a (earliest 691 southbridges) */ | |
123 | { 15, 10, 7, 5, 3, 2, 1 }, /* ATA_133 */ | |
1da177e4 LT |
124 | }; |
125 | /* CRC Valid Setup Time vary across IDE clock setting 33/66/100/133 | |
126 | See SiS962 data sheet for more detail */ | |
127 | static u8 cvs_time_value[][XFER_UDMA_6 - XFER_UDMA_0 + 1] = { | |
1eb3c2ee PC |
128 | { 0, 0, 0, 0, 0, 0, 0 }, /* no UDMA */ |
129 | { 0, 0, 0, 0, 0, 0, 0 }, /* no UDMA */ | |
130 | { 2, 1, 1, 0, 0, 0, 0 }, | |
131 | { 4, 3, 2, 1, 0, 0, 0 }, | |
132 | { 4, 3, 2, 1, 0, 0, 0 }, | |
133 | { 6, 4, 3, 1, 1, 1, 0 }, | |
134 | { 9, 6, 4, 2, 2, 2, 2 }, | |
135 | { 9, 6, 4, 2, 2, 2, 2 }, | |
1da177e4 LT |
136 | }; |
137 | /* Initialize time, Active time, Recovery time vary across | |
138 | IDE clock settings. These 3 arrays hold the register value | |
139 | for PIO0/1/2/3/4 and DMA0/1/2 mode in order */ | |
140 | static u8 ini_time_value[][8] = { | |
1eb3c2ee PC |
141 | { 0, 0, 0, 0, 0, 0, 0, 0 }, |
142 | { 0, 0, 0, 0, 0, 0, 0, 0 }, | |
143 | { 2, 1, 0, 0, 0, 1, 0, 0 }, | |
144 | { 4, 3, 1, 1, 1, 3, 1, 1 }, | |
145 | { 4, 3, 1, 1, 1, 3, 1, 1 }, | |
146 | { 6, 4, 2, 2, 2, 4, 2, 2 }, | |
147 | { 9, 6, 3, 3, 3, 6, 3, 3 }, | |
148 | { 9, 6, 3, 3, 3, 6, 3, 3 }, | |
1da177e4 LT |
149 | }; |
150 | static u8 act_time_value[][8] = { | |
1eb3c2ee PC |
151 | { 0, 0, 0, 0, 0, 0, 0, 0 }, |
152 | { 0, 0, 0, 0, 0, 0, 0, 0 }, | |
153 | { 9, 9, 9, 2, 2, 7, 2, 2 }, | |
154 | { 19, 19, 19, 5, 4, 14, 5, 4 }, | |
155 | { 19, 19, 19, 5, 4, 14, 5, 4 }, | |
156 | { 28, 28, 28, 7, 6, 21, 7, 6 }, | |
157 | { 38, 38, 38, 10, 9, 28, 10, 9 }, | |
158 | { 38, 38, 38, 10, 9, 28, 10, 9 }, | |
1da177e4 LT |
159 | }; |
160 | static u8 rco_time_value[][8] = { | |
1eb3c2ee PC |
161 | { 0, 0, 0, 0, 0, 0, 0, 0 }, |
162 | { 0, 0, 0, 0, 0, 0, 0, 0 }, | |
163 | { 9, 2, 0, 2, 0, 7, 1, 1 }, | |
164 | { 19, 5, 1, 5, 2, 16, 3, 2 }, | |
165 | { 19, 5, 1, 5, 2, 16, 3, 2 }, | |
166 | { 30, 9, 3, 9, 4, 25, 6, 4 }, | |
167 | { 40, 12, 4, 12, 5, 34, 12, 5 }, | |
168 | { 40, 12, 4, 12, 5, 34, 12, 5 }, | |
1da177e4 LT |
169 | }; |
170 | ||
171 | /* | |
172 | * Printing configuration | |
173 | */ | |
174 | /* Used for chipset type printing at boot time */ | |
1eb3c2ee | 175 | static char *chipset_capability[] = { |
1da177e4 LT |
176 | "ATA", "ATA 16", |
177 | "ATA 33", "ATA 66", | |
178 | "ATA 100 (1st gen)", "ATA 100 (2nd gen)", | |
179 | "ATA 133 (1st gen)", "ATA 133 (2nd gen)" | |
180 | }; | |
181 | ||
1da177e4 LT |
182 | /* |
183 | * Configuration functions | |
184 | */ | |
c77a89cd BZ |
185 | |
186 | static u8 sis_ata133_get_base(ide_drive_t *drive) | |
187 | { | |
36501650 | 188 | struct pci_dev *dev = to_pci_dev(drive->hwif->dev); |
c77a89cd BZ |
189 | u32 reg54 = 0; |
190 | ||
191 | pci_read_config_dword(dev, 0x54, ®54); | |
192 | ||
193 | return ((reg54 & 0x40000000) ? 0x70 : 0x40) + drive->dn * 4; | |
194 | } | |
195 | ||
196 | static void sis_ata16_program_timings(ide_drive_t *drive, const u8 mode) | |
197 | { | |
36501650 | 198 | struct pci_dev *dev = to_pci_dev(drive->hwif->dev); |
c77a89cd BZ |
199 | u16 t1 = 0; |
200 | u8 drive_pci = 0x40 + drive->dn * 2; | |
201 | ||
202 | const u16 pio_timings[] = { 0x000, 0x607, 0x404, 0x303, 0x301 }; | |
203 | const u16 mwdma_timings[] = { 0x008, 0x302, 0x301 }; | |
204 | ||
205 | pci_read_config_word(dev, drive_pci, &t1); | |
206 | ||
207 | /* clear active/recovery timings */ | |
208 | t1 &= ~0x070f; | |
209 | if (mode >= XFER_MW_DMA_0) { | |
210 | if (chipset_family > ATA_16) | |
211 | t1 &= ~0x8000; /* disable UDMA */ | |
212 | t1 |= mwdma_timings[mode - XFER_MW_DMA_0]; | |
213 | } else | |
214 | t1 |= pio_timings[mode - XFER_PIO_0]; | |
215 | ||
216 | pci_write_config_word(dev, drive_pci, t1); | |
217 | } | |
218 | ||
219 | static void sis_ata100_program_timings(ide_drive_t *drive, const u8 mode) | |
220 | { | |
36501650 | 221 | struct pci_dev *dev = to_pci_dev(drive->hwif->dev); |
c77a89cd BZ |
222 | u8 t1, drive_pci = 0x40 + drive->dn * 2; |
223 | ||
224 | /* timing bits: 7:4 active 3:0 recovery */ | |
225 | const u8 pio_timings[] = { 0x00, 0x67, 0x44, 0x33, 0x31 }; | |
226 | const u8 mwdma_timings[] = { 0x08, 0x32, 0x31 }; | |
227 | ||
228 | if (mode >= XFER_MW_DMA_0) { | |
229 | u8 t2 = 0; | |
230 | ||
231 | pci_read_config_byte(dev, drive_pci, &t2); | |
232 | t2 &= ~0x80; /* disable UDMA */ | |
233 | pci_write_config_byte(dev, drive_pci, t2); | |
234 | ||
235 | t1 = mwdma_timings[mode - XFER_MW_DMA_0]; | |
236 | } else | |
237 | t1 = pio_timings[mode - XFER_PIO_0]; | |
238 | ||
239 | pci_write_config_byte(dev, drive_pci + 1, t1); | |
240 | } | |
241 | ||
242 | static void sis_ata133_program_timings(ide_drive_t *drive, const u8 mode) | |
243 | { | |
36501650 | 244 | struct pci_dev *dev = to_pci_dev(drive->hwif->dev); |
c77a89cd BZ |
245 | u32 t1 = 0; |
246 | u8 drive_pci = sis_ata133_get_base(drive), clk, idx; | |
247 | ||
248 | pci_read_config_dword(dev, drive_pci, &t1); | |
249 | ||
250 | t1 &= 0xc0c00fff; | |
251 | clk = (t1 & 0x08) ? ATA_133 : ATA_100; | |
252 | if (mode >= XFER_MW_DMA_0) { | |
253 | t1 &= ~0x04; /* disable UDMA */ | |
254 | idx = mode - XFER_MW_DMA_0 + 5; | |
3dfd6433 | 255 | } else |
c77a89cd BZ |
256 | idx = mode - XFER_PIO_0; |
257 | t1 |= ini_time_value[clk][idx] << 12; | |
258 | t1 |= act_time_value[clk][idx] << 16; | |
259 | t1 |= rco_time_value[clk][idx] << 24; | |
260 | ||
261 | pci_write_config_dword(dev, drive_pci, t1); | |
262 | } | |
263 | ||
264 | static void sis_program_timings(ide_drive_t *drive, const u8 mode) | |
265 | { | |
266 | if (chipset_family < ATA_100) /* ATA_16/33/66/100a */ | |
267 | sis_ata16_program_timings(drive, mode); | |
268 | else if (chipset_family < ATA_133) /* ATA_100/133a */ | |
269 | sis_ata100_program_timings(drive, mode); | |
270 | else /* ATA_133 */ | |
271 | sis_ata133_program_timings(drive, mode); | |
272 | } | |
273 | ||
1eb3c2ee | 274 | static void config_drive_art_rwp(ide_drive_t *drive) |
1da177e4 LT |
275 | { |
276 | ide_hwif_t *hwif = HWIF(drive); | |
36501650 | 277 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1da177e4 | 278 | u8 reg4bh = 0; |
d83fca58 | 279 | u8 rw_prefetch = 0; |
1da177e4 | 280 | |
1da177e4 LT |
281 | pci_read_config_byte(dev, 0x4b, ®4bh); |
282 | ||
d83fca58 BZ |
283 | if (drive->media == ide_disk) |
284 | rw_prefetch = 0x11 << drive->dn; | |
285 | ||
286 | if ((reg4bh & (0x11 << drive->dn)) != rw_prefetch) | |
1da177e4 LT |
287 | pci_write_config_byte(dev, 0x4b, reg4bh|rw_prefetch); |
288 | } | |
289 | ||
88b2b32b | 290 | static void sis_set_pio_mode(ide_drive_t *drive, const u8 pio) |
1da177e4 | 291 | { |
1da177e4 | 292 | config_drive_art_rwp(drive); |
c77a89cd | 293 | sis_program_timings(drive, XFER_PIO_0 + pio); |
1da177e4 LT |
294 | } |
295 | ||
428c6440 | 296 | static void sis_ata133_program_udma_timings(ide_drive_t *drive, const u8 mode) |
1da177e4 | 297 | { |
36501650 | 298 | struct pci_dev *dev = to_pci_dev(drive->hwif->dev); |
428c6440 BZ |
299 | u32 regdw = 0; |
300 | u8 drive_pci = sis_ata133_get_base(drive), clk, idx; | |
301 | ||
302 | pci_read_config_dword(dev, drive_pci, ®dw); | |
303 | ||
304 | regdw |= 0x04; | |
305 | regdw &= 0xfffff00f; | |
306 | /* check if ATA133 enable */ | |
307 | clk = (regdw & 0x08) ? ATA_133 : ATA_100; | |
308 | idx = mode - XFER_UDMA_0; | |
309 | regdw |= cycle_time_value[clk][idx] << 4; | |
310 | regdw |= cvs_time_value[clk][idx] << 8; | |
311 | ||
312 | pci_write_config_dword(dev, drive_pci, regdw); | |
313 | } | |
314 | ||
315 | static void sis_ata33_program_udma_timings(ide_drive_t *drive, const u8 mode) | |
316 | { | |
36501650 | 317 | struct pci_dev *dev = to_pci_dev(drive->hwif->dev); |
428c6440 BZ |
318 | u8 drive_pci = 0x40 + drive->dn * 2, reg = 0, i = chipset_family; |
319 | ||
320 | pci_read_config_byte(dev, drive_pci + 1, ®); | |
321 | ||
322 | /* force the UDMA bit on if we want to use UDMA */ | |
323 | reg |= 0x80; | |
324 | /* clean reg cycle time bits */ | |
325 | reg &= ~((0xff >> (8 - cycle_time_range[i])) << cycle_time_offset[i]); | |
326 | /* set reg cycle time bits */ | |
327 | reg |= cycle_time_value[i][mode - XFER_UDMA_0] << cycle_time_offset[i]; | |
328 | ||
329 | pci_write_config_byte(dev, drive_pci + 1, reg); | |
330 | } | |
1da177e4 | 331 | |
428c6440 BZ |
332 | static void sis_program_udma_timings(ide_drive_t *drive, const u8 mode) |
333 | { | |
334 | if (chipset_family >= ATA_133) /* ATA_133 */ | |
335 | sis_ata133_program_udma_timings(drive, mode); | |
336 | else /* ATA_33/66/100a/100/133a */ | |
337 | sis_ata33_program_udma_timings(drive, mode); | |
338 | } | |
339 | ||
340 | static void sis_set_dma_mode(ide_drive_t *drive, const u8 speed) | |
341 | { | |
4db90a14 BZ |
342 | if (speed >= XFER_UDMA_0) |
343 | sis_program_udma_timings(drive, speed); | |
344 | else | |
345 | sis_program_timings(drive, speed); | |
1da177e4 LT |
346 | } |
347 | ||
ac95beed | 348 | static u8 sis_ata133_udma_filter(ide_drive_t *drive) |
3160d541 | 349 | { |
36501650 | 350 | struct pci_dev *dev = to_pci_dev(drive->hwif->dev); |
c77a89cd BZ |
351 | u32 regdw = 0; |
352 | u8 drive_pci = sis_ata133_get_base(drive); | |
3160d541 | 353 | |
3160d541 BZ |
354 | pci_read_config_dword(dev, drive_pci, ®dw); |
355 | ||
356 | /* if ATA133 disable, we should not set speed above UDMA5 */ | |
357 | return (regdw & 0x08) ? ATA_UDMA6 : ATA_UDMA5; | |
358 | } | |
359 | ||
4764b684 | 360 | static int __devinit sis_find_family(struct pci_dev *dev) |
1da177e4 LT |
361 | { |
362 | struct pci_dev *host; | |
363 | int i = 0; | |
364 | ||
365 | chipset_family = 0; | |
366 | ||
367 | for (i = 0; i < ARRAY_SIZE(SiSHostChipInfo) && !chipset_family; i++) { | |
368 | ||
40cddf2c | 369 | host = pci_get_device(PCI_VENDOR_ID_SI, SiSHostChipInfo[i].host_id, NULL); |
1da177e4 LT |
370 | |
371 | if (!host) | |
372 | continue; | |
373 | ||
374 | chipset_family = SiSHostChipInfo[i].chipset_family; | |
375 | ||
376 | /* Special case for SiS630 : 630S/ET is ATA_100a */ | |
377 | if (SiSHostChipInfo[i].host_id == PCI_DEVICE_ID_SI_630) { | |
44c10138 | 378 | if (host->revision >= 0x30) |
1da177e4 LT |
379 | chipset_family = ATA_100a; |
380 | } | |
40cddf2c | 381 | pci_dev_put(host); |
1eb3c2ee | 382 | |
1da177e4 LT |
383 | printk(KERN_INFO "SIS5513: %s %s controller\n", |
384 | SiSHostChipInfo[i].name, chipset_capability[chipset_family]); | |
385 | } | |
386 | ||
387 | if (!chipset_family) { /* Belongs to pci-quirks */ | |
388 | ||
389 | u32 idemisc; | |
390 | u16 trueid; | |
391 | ||
392 | /* Disable ID masking and register remapping */ | |
393 | pci_read_config_dword(dev, 0x54, &idemisc); | |
394 | pci_write_config_dword(dev, 0x54, (idemisc & 0x7fffffff)); | |
395 | pci_read_config_word(dev, PCI_DEVICE_ID, &trueid); | |
396 | pci_write_config_dword(dev, 0x54, idemisc); | |
397 | ||
398 | if (trueid == 0x5518) { | |
399 | printk(KERN_INFO "SIS5513: SiS 962/963 MuTIOL IDE UDMA133 controller\n"); | |
400 | chipset_family = ATA_133; | |
401 | ||
402 | /* Check for 5513 compability mapping | |
403 | * We must use this, else the port enabled code will fail, | |
404 | * as it expects the enablebits at 0x4a. | |
405 | */ | |
406 | if ((idemisc & 0x40000000) == 0) { | |
407 | pci_write_config_dword(dev, 0x54, idemisc | 0x40000000); | |
408 | printk(KERN_INFO "SIS5513: Switching to 5513 register mapping\n"); | |
409 | } | |
410 | } | |
411 | } | |
412 | ||
413 | if (!chipset_family) { /* Belongs to pci-quirks */ | |
414 | ||
415 | struct pci_dev *lpc_bridge; | |
416 | u16 trueid; | |
417 | u8 prefctl; | |
418 | u8 idecfg; | |
1da177e4 LT |
419 | |
420 | pci_read_config_byte(dev, 0x4a, &idecfg); | |
421 | pci_write_config_byte(dev, 0x4a, idecfg | 0x10); | |
422 | pci_read_config_word(dev, PCI_DEVICE_ID, &trueid); | |
423 | pci_write_config_byte(dev, 0x4a, idecfg); | |
424 | ||
425 | if (trueid == 0x5517) { /* SiS 961/961B */ | |
426 | ||
b1489009 | 427 | lpc_bridge = pci_get_slot(dev->bus, 0x10); /* Bus 0, Dev 2, Fn 0 */ |
1da177e4 | 428 | pci_read_config_byte(dev, 0x49, &prefctl); |
b1489009 | 429 | pci_dev_put(lpc_bridge); |
1da177e4 | 430 | |
44c10138 | 431 | if (lpc_bridge->revision == 0x10 && (prefctl & 0x80)) { |
1da177e4 LT |
432 | printk(KERN_INFO "SIS5513: SiS 961B MuTIOL IDE UDMA133 controller\n"); |
433 | chipset_family = ATA_133a; | |
434 | } else { | |
435 | printk(KERN_INFO "SIS5513: SiS 961 MuTIOL IDE UDMA100 controller\n"); | |
436 | chipset_family = ATA_100; | |
437 | } | |
438 | } | |
439 | } | |
440 | ||
4764b684 BZ |
441 | return chipset_family; |
442 | } | |
1da177e4 | 443 | |
4764b684 BZ |
444 | static unsigned int __devinit init_chipset_sis5513(struct pci_dev *dev, |
445 | const char *name) | |
446 | { | |
1da177e4 LT |
447 | /* Make general config ops here |
448 | 1/ tell IDE channels to operate in Compatibility mode only | |
449 | 2/ tell old chips to allow per drive IDE timings */ | |
450 | ||
1eb3c2ee PC |
451 | u8 reg; |
452 | u16 regw; | |
453 | ||
454 | switch (chipset_family) { | |
455 | case ATA_133: | |
456 | /* SiS962 operation mode */ | |
457 | pci_read_config_word(dev, 0x50, ®w); | |
458 | if (regw & 0x08) | |
459 | pci_write_config_word(dev, 0x50, regw&0xfff7); | |
460 | pci_read_config_word(dev, 0x52, ®w); | |
461 | if (regw & 0x08) | |
462 | pci_write_config_word(dev, 0x52, regw&0xfff7); | |
463 | break; | |
464 | case ATA_133a: | |
465 | case ATA_100: | |
466 | /* Fixup latency */ | |
467 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x80); | |
468 | /* Set compatibility bit */ | |
469 | pci_read_config_byte(dev, 0x49, ®); | |
470 | if (!(reg & 0x01)) | |
471 | pci_write_config_byte(dev, 0x49, reg|0x01); | |
472 | break; | |
473 | case ATA_100a: | |
474 | case ATA_66: | |
475 | /* Fixup latency */ | |
476 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x10); | |
477 | ||
478 | /* On ATA_66 chips the bit was elsewhere */ | |
479 | pci_read_config_byte(dev, 0x52, ®); | |
480 | if (!(reg & 0x04)) | |
481 | pci_write_config_byte(dev, 0x52, reg|0x04); | |
482 | break; | |
483 | case ATA_33: | |
484 | /* On ATA_33 we didn't have a single bit to set */ | |
485 | pci_read_config_byte(dev, 0x09, ®); | |
486 | if ((reg & 0x0f) != 0x00) | |
487 | pci_write_config_byte(dev, 0x09, reg&0xf0); | |
488 | case ATA_16: | |
489 | /* force per drive recovery and active timings | |
490 | needed on ATA_33 and below chips */ | |
491 | pci_read_config_byte(dev, 0x52, ®); | |
492 | if (!(reg & 0x08)) | |
493 | pci_write_config_byte(dev, 0x52, reg|0x08); | |
494 | break; | |
495 | } | |
1da177e4 LT |
496 | |
497 | return 0; | |
498 | } | |
499 | ||
f2befd9e BZ |
500 | struct sis_laptop { |
501 | u16 device; | |
502 | u16 subvendor; | |
503 | u16 subdevice; | |
504 | }; | |
505 | ||
506 | static const struct sis_laptop sis_laptop[] = { | |
507 | /* devid, subvendor, subdev */ | |
508 | { 0x5513, 0x1043, 0x1107 }, /* ASUS A6K */ | |
1955f681 | 509 | { 0x5513, 0x1734, 0x105f }, /* FSC Amilo A1630 */ |
a1d85864 | 510 | { 0x5513, 0x1071, 0x8640 }, /* EasyNote K5305 */ |
f2befd9e BZ |
511 | /* end marker */ |
512 | { 0, } | |
513 | }; | |
514 | ||
ac95beed | 515 | static u8 __devinit sis_cable_detect(ide_hwif_t *hwif) |
1da177e4 | 516 | { |
36501650 | 517 | struct pci_dev *pdev = to_pci_dev(hwif->dev); |
f2befd9e | 518 | const struct sis_laptop *lap = &sis_laptop[0]; |
1da177e4 LT |
519 | u8 ata66 = 0; |
520 | ||
f2befd9e BZ |
521 | while (lap->device) { |
522 | if (lap->device == pdev->device && | |
523 | lap->subvendor == pdev->subsystem_vendor && | |
524 | lap->subdevice == pdev->subsystem_device) | |
525 | return ATA_CBL_PATA40_SHORT; | |
526 | lap++; | |
527 | } | |
528 | ||
1da177e4 LT |
529 | if (chipset_family >= ATA_133) { |
530 | u16 regw = 0; | |
531 | u16 reg_addr = hwif->channel ? 0x52: 0x50; | |
36501650 | 532 | pci_read_config_word(pdev, reg_addr, ®w); |
1da177e4 LT |
533 | ata66 = (regw & 0x8000) ? 0 : 1; |
534 | } else if (chipset_family >= ATA_66) { | |
535 | u8 reg48h = 0; | |
536 | u8 mask = hwif->channel ? 0x20 : 0x10; | |
36501650 | 537 | pci_read_config_byte(pdev, 0x48, ®48h); |
1da177e4 LT |
538 | ata66 = (reg48h & mask) ? 0 : 1; |
539 | } | |
49521f97 BZ |
540 | |
541 | return ata66 ? ATA_CBL_PATA80 : ATA_CBL_PATA40; | |
1da177e4 LT |
542 | } |
543 | ||
ac95beed BZ |
544 | static const struct ide_port_ops sis_port_ops = { |
545 | .set_pio_mode = sis_set_pio_mode, | |
546 | .set_dma_mode = sis_set_dma_mode, | |
547 | .cable_detect = sis_cable_detect, | |
548 | }; | |
3160d541 | 549 | |
ac95beed BZ |
550 | static const struct ide_port_ops sis_ata133_port_ops = { |
551 | .set_pio_mode = sis_set_pio_mode, | |
552 | .set_dma_mode = sis_set_dma_mode, | |
553 | .udma_filter = sis_ata133_udma_filter, | |
554 | .cable_detect = sis_cable_detect, | |
555 | }; | |
1da177e4 | 556 | |
85620436 | 557 | static const struct ide_port_info sis5513_chipset __devinitdata = { |
1da177e4 LT |
558 | .name = "SIS5513", |
559 | .init_chipset = init_chipset_sis5513, | |
1eb3c2ee | 560 | .enablebits = { {0x4a, 0x02, 0x02}, {0x4a, 0x04, 0x04} }, |
5e71d9c5 | 561 | .host_flags = IDE_HFLAG_LEGACY_IRQS | IDE_HFLAG_NO_AUTODMA, |
4099d143 | 562 | .pio_mask = ATA_PIO4, |
5f8b6c34 | 563 | .mwdma_mask = ATA_MWDMA2, |
1da177e4 LT |
564 | }; |
565 | ||
566 | static int __devinit sis5513_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
567 | { | |
4764b684 BZ |
568 | struct ide_port_info d = sis5513_chipset; |
569 | u8 udma_rates[] = { 0x00, 0x00, 0x07, 0x1f, 0x3f, 0x3f, 0x7f, 0x7f }; | |
cd18f69f BZ |
570 | int rc; |
571 | ||
572 | rc = pci_enable_device(dev); | |
573 | if (rc) | |
574 | return rc; | |
4764b684 BZ |
575 | |
576 | if (sis_find_family(dev) == 0) | |
577 | return -ENOTSUPP; | |
578 | ||
ac95beed BZ |
579 | if (chipset_family >= ATA_133) |
580 | d.port_ops = &sis_ata133_port_ops; | |
581 | else | |
582 | d.port_ops = &sis_port_ops; | |
583 | ||
4764b684 BZ |
584 | d.udma_mask = udma_rates[chipset_family]; |
585 | ||
586 | return ide_setup_pci_device(dev, &d); | |
1da177e4 LT |
587 | } |
588 | ||
9cbcc5e3 BZ |
589 | static const struct pci_device_id sis5513_pci_tbl[] = { |
590 | { PCI_VDEVICE(SI, PCI_DEVICE_ID_SI_5513), 0 }, | |
591 | { PCI_VDEVICE(SI, PCI_DEVICE_ID_SI_5518), 0 }, | |
592 | { PCI_VDEVICE(SI, PCI_DEVICE_ID_SI_1180), 0 }, | |
1da177e4 LT |
593 | { 0, }, |
594 | }; | |
595 | MODULE_DEVICE_TABLE(pci, sis5513_pci_tbl); | |
596 | ||
597 | static struct pci_driver driver = { | |
598 | .name = "SIS_IDE", | |
599 | .id_table = sis5513_pci_tbl, | |
600 | .probe = sis5513_init_one, | |
601 | }; | |
602 | ||
82ab1eec | 603 | static int __init sis5513_ide_init(void) |
1da177e4 LT |
604 | { |
605 | return ide_pci_register_driver(&driver); | |
606 | } | |
607 | ||
608 | module_init(sis5513_ide_init); | |
609 | ||
610 | MODULE_AUTHOR("Lionel Bouton, L C Chang, Andre Hedrick, Vojtech Pavlik"); | |
611 | MODULE_DESCRIPTION("PCI driver module for SIS IDE"); | |
612 | MODULE_LICENSE("GPL"); | |
613 | ||
614 | /* | |
615 | * TODO: | |
616 | * - CLEANUP | |
1da177e4 LT |
617 | * - More checks in the config registers (force values instead of |
618 | * relying on the BIOS setting them correctly). | |
619 | * - Further optimisations ? | |
620 | * . for example ATA66+ regs 0x48 & 0x4A | |
621 | */ |