[linux-block.git] / drivers / ide / pci / pdc202xx_old.c

/*
 *  Copyright (C) 1998-2002		Andre Hedrick <andre@linux-ide.org>
 *  Copyright (C) 2006-2007		MontaVista Software, Inc.
 *  Copyright (C) 2007			Bartlomiej Zolnierkiewicz
 *
 *  Portions Copyright (C) 1999 Promise Technology, Inc.
 *  Author: Frank Tiernan (frankt@promise.com)
 *  Released under terms of General Public License
 */

#include <linux/types.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/blkdev.h>
#include <linux/hdreg.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ide.h>

#include <asm/io.h>

#define DRV_NAME "pdc202xx_old"

#define PDC202XX_DEBUG_DRIVE_INFO	0

static const char *pdc_quirk_drives[] = {
	"QUANTUM FIREBALLlct08 08",
	"QUANTUM FIREBALLP KA6.4",
	"QUANTUM FIREBALLP KA9.1",
	"QUANTUM FIREBALLP LM20.4",
	"QUANTUM FIREBALLP KX13.6",
	"QUANTUM FIREBALLP KX20.5",
	"QUANTUM FIREBALLP KX27.3",
	"QUANTUM FIREBALLP LM20.5",
	NULL
};

static void pdc_old_disable_66MHz_clock(ide_hwif_t *);

static void pdc202xx_set_mode(ide_drive_t *drive, const u8 speed)
{
	ide_hwif_t *hwif	= HWIF(drive);
	struct pci_dev *dev	= to_pci_dev(hwif->dev);
	u8 drive_pci		= 0x60 + (drive->dn << 2);

	u8			AP = 0, BP = 0, CP = 0;
	u8			TA = 0, TB = 0, TC = 0;

#if PDC202XX_DEBUG_DRIVE_INFO
	u32			drive_conf = 0;
	pci_read_config_dword(dev, drive_pci, &drive_conf);
#endif

	/*
	 * TODO: do this once per channel
	 */
	if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
		pdc_old_disable_66MHz_clock(hwif);

	pci_read_config_byte(dev, drive_pci,     &AP);
	pci_read_config_byte(dev, drive_pci + 1, &BP);
	pci_read_config_byte(dev, drive_pci + 2, &CP);

	switch(speed) {
		case XFER_UDMA_5:
		case XFER_UDMA_4:	TB = 0x20; TC = 0x01; break;
		case XFER_UDMA_2:	TB = 0x20; TC = 0x01; break;
		case XFER_UDMA_3:
		case XFER_UDMA_1:	TB = 0x40; TC = 0x02; break;
		case XFER_UDMA_0:
		case XFER_MW_DMA_2:	TB = 0x60; TC = 0x03; break;
		case XFER_MW_DMA_1:	TB = 0x60; TC = 0x04; break;
		case XFER_MW_DMA_0:	TB = 0xE0; TC = 0x0F; break;
		case XFER_PIO_4:	TA = 0x01; TB = 0x04; break;
		case XFER_PIO_3:	TA = 0x02; TB = 0x06; break;
		case XFER_PIO_2:	TA = 0x03; TB = 0x08; break;
		case XFER_PIO_1:	TA = 0x05; TB = 0x0C; break;
		case XFER_PIO_0:
		default:		TA = 0x09; TB = 0x13; break;
	}

	if (speed < XFER_SW_DMA_0) {
		/*
		 * preserve SYNC_INT / ERDDY_EN bits while clearing
		 * Prefetch_EN / IORDY_EN / PA[3:0] bits of register A
		 */
		AP &= ~0x3f;
		if (drive->id->capability & 4)
			AP |= 0x20;	/* set IORDY_EN bit */
		if (drive->media == ide_disk)
			AP |= 0x10;	/* set Prefetch_EN bit */
		/* clear PB[4:0] bits of register B */
		BP &= ~0x1f;
		pci_write_config_byte(dev, drive_pci,     AP | TA);
		pci_write_config_byte(dev, drive_pci + 1, BP | TB);
	} else {
		/* clear MB[2:0] bits of register B */
		BP &= ~0xe0;
		/* clear MC[3:0] bits of register C */
		CP &= ~0x0f;
		pci_write_config_byte(dev, drive_pci + 1, BP | TB);
		pci_write_config_byte(dev, drive_pci + 2, CP | TC);
	}

#if PDC202XX_DEBUG_DRIVE_INFO
	printk(KERN_DEBUG "%s: %s drive%d 0x%08x ",
		drive->name, ide_xfer_verbose(speed),
		drive->dn, drive_conf);
	pci_read_config_dword(dev, drive_pci, &drive_conf);
	printk("0x%08x\n", drive_conf);
#endif
}

static void pdc202xx_set_pio_mode(ide_drive_t *drive, const u8 pio)
{
	pdc202xx_set_mode(drive, XFER_PIO_0 + pio);
}

static u8 __devinit pdc2026x_cable_detect(ide_hwif_t *hwif)
{
	struct pci_dev *dev = to_pci_dev(hwif->dev);
	u16 CIS, mask = hwif->channel ? (1 << 11) : (1 << 10);

	pci_read_config_word(dev, 0x50, &CIS);

	return (CIS & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
}

/*
 * Set the control register to use the 66MHz system
 * clock for UDMA 3/4/5 mode operation when necessary.
 *
 * FIXME: this register is shared by both channels, some locking is needed
 *
 * It may also be possible to leave the 66MHz clock on
 * and readjust the timing parameters.
 */
static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
{
	unsigned long clock_reg = hwif->extra_base + 0x01;
	u8 clock = inb(clock_reg);

	outb(clock | (hwif->channel ? 0x08 : 0x02), clock_reg);
}

static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
{
	unsigned long clock_reg = hwif->extra_base + 0x01;
	u8 clock = inb(clock_reg);

	outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
}

static void pdc202xx_quirkproc(ide_drive_t *drive)
{
	const char **list, *model = drive->id->model;

	for (list = pdc_quirk_drives; *list != NULL; list++)
		if (strstr(model, *list) != NULL) {
			drive->quirk_list = 2;
			return;
		}

	drive->quirk_list = 0;
}

static void pdc202xx_dma_start(ide_drive_t *drive)
{
	if (drive->current_speed > XFER_UDMA_2)
		pdc_old_enable_66MHz_clock(drive->hwif);
	if (drive->media != ide_disk || drive->addressing == 1) {
		struct request *rq	= HWGROUP(drive)->rq;
		ide_hwif_t *hwif	= HWIF(drive);
		unsigned long high_16	= hwif->extra_base - 16;
		unsigned long atapi_reg	= high_16 + (hwif->channel ? 0x24 : 0x20);
		u32 word_count	= 0;
		u8 clock = inb(high_16 + 0x11);

		outb(clock | (hwif->channel ? 0x08 : 0x02), high_16 + 0x11);
		word_count = (rq->nr_sectors << 8);
		word_count = (rq_data_dir(rq) == READ) ?
					word_count | 0x05000000 :
					word_count | 0x06000000;
		outl(word_count, atapi_reg);
	}
	ide_dma_start(drive);
}

static int pdc202xx_dma_end(ide_drive_t *drive)
{
	if (drive->media != ide_disk || drive->addressing == 1) {
		ide_hwif_t *hwif	= HWIF(drive);
		unsigned long high_16	= hwif->extra_base - 16;
		unsigned long atapi_reg	= high_16 + (hwif->channel ? 0x24 : 0x20);
		u8 clock		= 0;

		outl(0, atapi_reg); /* zero out extra */
		clock = inb(high_16 + 0x11);
		outb(clock & ~(hwif->channel ? 0x08:0x02), high_16 + 0x11);
	}
	if (drive->current_speed > XFER_UDMA_2)
		pdc_old_disable_66MHz_clock(drive->hwif);
	return __ide_dma_end(drive);
}

static int pdc202xx_dma_test_irq(ide_drive_t *drive)
{
	ide_hwif_t *hwif	= HWIF(drive);
	unsigned long high_16	= hwif->extra_base - 16;
	u8 dma_stat		= inb(hwif->dma_base + ATA_DMA_STATUS);
	u8 sc1d			= inb(high_16 + 0x001d);

	if (hwif->channel) {
		/* bit7: Error, bit6: Interrupting, bit5: FIFO Full, bit4: FIFO Empty */
		if ((sc1d & 0x50) == 0x50)
			goto somebody_else;
		else if ((sc1d & 0x40) == 0x40)
			return (dma_stat & 4) == 4;
	} else {
		/* bit3: Error, bit2: Interrupting, bit1: FIFO Full, bit0: FIFO Empty */
		if ((sc1d & 0x05) == 0x05)
			goto somebody_else;
		else if ((sc1d & 0x04) == 0x04)
			return (dma_stat & 4) == 4;
	}
somebody_else:
	return (dma_stat & 4) == 4;	/* return 1 if INTR asserted */
}

static void pdc202xx_reset_host (ide_hwif_t *hwif)
{
	unsigned long high_16	= hwif->extra_base - 16;
	u8 udma_speed_flag	= inb(high_16 | 0x001f);

	outb(udma_speed_flag | 0x10, high_16 | 0x001f);
	mdelay(100);
	outb(udma_speed_flag & ~0x10, high_16 | 0x001f);
	mdelay(2000);	/* 2 seconds ?! */

	printk(KERN_WARNING "PDC202XX: %s channel reset.\n",
		hwif->channel ? "Secondary" : "Primary");
}

static void pdc202xx_reset (ide_drive_t *drive)
{
	ide_hwif_t *hwif	= HWIF(drive);
	ide_hwif_t *mate	= hwif->mate;

	pdc202xx_reset_host(hwif);
	pdc202xx_reset_host(mate);

	ide_set_max_pio(drive);
}

static void pdc202xx_dma_lost_irq(ide_drive_t *drive)
{
	pdc202xx_reset(drive);
	ide_dma_lost_irq(drive);
}

static void pdc202xx_dma_timeout(ide_drive_t *drive)
{
	pdc202xx_reset(drive);
	ide_dma_timeout(drive);
}

static unsigned int __devinit init_chipset_pdc202xx(struct pci_dev *dev)
{
	unsigned long dmabase = pci_resource_start(dev, 4);
	u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0;

	if (dmabase == 0)
		goto out;

	udma_speed_flag	= inb(dmabase | 0x1f);
	primary_mode	= inb(dmabase | 0x1a);
	secondary_mode	= inb(dmabase | 0x1b);
	printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
		"Primary %s Mode " \
		"Secondary %s Mode.\n", pci_name(dev),
		(udma_speed_flag & 1) ? "EN" : "DIS",
		(primary_mode & 1) ? "MASTER" : "PCI",
		(secondary_mode & 1) ? "MASTER" : "PCI" );

	if (!(udma_speed_flag & 1)) {
		printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
			pci_name(dev), udma_speed_flag,
			(udma_speed_flag|1));
		outb(udma_speed_flag | 1, dmabase | 0x1f);
		printk("%sACTIVE\n", (inb(dmabase | 0x1f) & 1) ? "" : "IN");
	}
out:
	return dev->irq;
}

static void __devinit pdc202ata4_fixup_irq(struct pci_dev *dev,
					   const char *name)
{
	if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
		u8 irq = 0, irq2 = 0;
		pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
		/* 0xbc */
		pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2);
		if (irq != irq2) {
			pci_write_config_byte(dev,
				(PCI_INTERRUPT_LINE)|0x80, irq);     /* 0xbc */
			printk(KERN_INFO "%s %s: PCI config space interrupt "
				"mirror fixed\n", name, pci_name(dev));
		}
	}
}

#define IDE_HFLAGS_PDC202XX \
	(IDE_HFLAG_ERROR_STOPS_FIFO | \
	 IDE_HFLAG_OFF_BOARD)

static const struct ide_port_ops pdc20246_port_ops = {
	.set_pio_mode		= pdc202xx_set_pio_mode,
	.set_dma_mode		= pdc202xx_set_mode,
	.quirkproc		= pdc202xx_quirkproc,
};

static const struct ide_port_ops pdc2026x_port_ops = {
	.set_pio_mode		= pdc202xx_set_pio_mode,
	.set_dma_mode		= pdc202xx_set_mode,
	.quirkproc		= pdc202xx_quirkproc,
	.resetproc		= pdc202xx_reset,
	.cable_detect		= pdc2026x_cable_detect,
};

static const struct ide_dma_ops pdc20246_dma_ops = {
	.dma_host_set		= ide_dma_host_set,
	.dma_setup		= ide_dma_setup,
	.dma_exec_cmd		= ide_dma_exec_cmd,
	.dma_start		= ide_dma_start,
	.dma_end		= __ide_dma_end,
	.dma_test_irq		= pdc202xx_dma_test_irq,
	.dma_lost_irq		= pdc202xx_dma_lost_irq,
	.dma_timeout		= pdc202xx_dma_timeout,
};

static const struct ide_dma_ops pdc2026x_dma_ops = {
	.dma_host_set		= ide_dma_host_set,
	.dma_setup		= ide_dma_setup,
	.dma_exec_cmd		= ide_dma_exec_cmd,
	.dma_start		= pdc202xx_dma_start,
	.dma_end		= pdc202xx_dma_end,
	.dma_test_irq		= pdc202xx_dma_test_irq,
	.dma_lost_irq		= pdc202xx_dma_lost_irq,
	.dma_timeout		= pdc202xx_dma_timeout,
};

#define DECLARE_PDC2026X_DEV(udma, extra_flags) \
	{ \
		.name		= DRV_NAME, \
		.init_chipset	= init_chipset_pdc202xx, \
		.port_ops	= &pdc2026x_port_ops, \
		.dma_ops	= &pdc2026x_dma_ops, \
		.host_flags	= IDE_HFLAGS_PDC202XX | extra_flags, \
		.pio_mask	= ATA_PIO4, \
		.mwdma_mask	= ATA_MWDMA2, \
		.udma_mask	= udma, \
	}

static const struct ide_port_info pdc202xx_chipsets[] __devinitdata = {
	{	/* 0: PDC20246 */
		.name		= DRV_NAME,
		.init_chipset	= init_chipset_pdc202xx,
		.port_ops	= &pdc20246_port_ops,
		.dma_ops	= &pdc20246_dma_ops,
		.host_flags	= IDE_HFLAGS_PDC202XX,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA2,
	},

	/* 1: PDC2026{2,3} */
	DECLARE_PDC2026X_DEV(ATA_UDMA4, 0),
	/* 2: PDC2026{5,7} */
	DECLARE_PDC2026X_DEV(ATA_UDMA5, IDE_HFLAG_RQSIZE_256),
};

/**
 *	pdc202xx_init_one	-	called when a PDC202xx is found
 *	@dev: the pdc202xx device
 *	@id: the matching pci id
 *
 *	Called when the PCI registration layer (or the IDE initialization)
 *	finds a device matching our IDE device tables.
 */
 
static int __devinit pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	const struct ide_port_info *d;
	u8 idx = id->driver_data;

	d = &pdc202xx_chipsets[idx];

	if (idx < 2)
		pdc202ata4_fixup_irq(dev, d->name);

	if (dev->vendor == PCI_DEVICE_ID_PROMISE_20265) {
		struct pci_dev *bridge = dev->bus->self;

		if (bridge &&
		    bridge->vendor == PCI_VENDOR_ID_INTEL &&
		    (bridge->device == PCI_DEVICE_ID_INTEL_I960 ||
		     bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) {
			printk(KERN_INFO DRV_NAME " %s: skipping Promise "
				"PDC20265 attached to I2O RAID controller\n",
				pci_name(dev));
			return -ENODEV;
		}
	}

	return ide_pci_init_one(dev, d, NULL);
}

static const struct pci_device_id pdc202xx_pci_tbl[] = {
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 1 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 2 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 2 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl);

static struct pci_driver driver = {
	.name		= "Promise_Old_IDE",
	.id_table	= pdc202xx_pci_tbl,
	.probe		= pdc202xx_init_one,
	.remove		= ide_pci_remove,
};

static int __init pdc202xx_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}

static void __exit pdc202xx_ide_exit(void)
{
	pci_unregister_driver(&driver);
}

module_init(pdc202xx_ide_init);
module_exit(pdc202xx_ide_exit);

MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
1da177e4	2	* Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
fed21641	3	* Copyright (C) 2006-2007 MontaVista Software, Inc.
4fce3164	4	* Copyright (C) 2007 Bartlomiej Zolnierkiewicz
1da177e4	5	*
1da177e4 LT	6	* Portions Copyright (C) 1999 Promise Technology, Inc.
	7	* Author: Frank Tiernan (frankt@promise.com)
	8	* Released under terms of General Public License
	9	*/
	10
1da177e4 LT	11	#include <linux/types.h>
	12	#include <linux/module.h>
	13	#include <linux/kernel.h>
	14	#include <linux/delay.h>
1da177e4 LT	15	#include <linux/blkdev.h>
1da177e4 LT	16	#include <linux/hdreg.h>
1da177e4 LT	17	#include <linux/pci.h>
	18	#include <linux/init.h>
	19	#include <linux/ide.h>
	20
	21	#include <asm/io.h>
1da177e4	22
ced3ec8a BZ	23	#define DRV_NAME "pdc202xx_old"
ced3ec8a BZ	24
1da177e4 LT	25	#define PDC202XX_DEBUG_DRIVE_INFO 0
	26
	27	static const char *pdc_quirk_drives[] = {
	28	"QUANTUM FIREBALLlct08 08",
	29	"QUANTUM FIREBALLP KA6.4",
	30	"QUANTUM FIREBALLP KA9.1",
	31	"QUANTUM FIREBALLP LM20.4",
	32	"QUANTUM FIREBALLP KX13.6",
	33	"QUANTUM FIREBALLP KX20.5",
	34	"QUANTUM FIREBALLP KX27.3",
	35	"QUANTUM FIREBALLP LM20.5",
	36	NULL
	37	};
	38
4fce3164	39	static void pdc_old_disable_66MHz_clock(ide_hwif_t *);
1da177e4	40
88b2b32b	41	static void pdc202xx_set_mode(ide_drive_t *drive, const u8 speed)
1da177e4 LT	42	{
1da177e4 LT	43	ide_hwif_t *hwif = HWIF(drive);
36501650	44	struct pci_dev *dev = to_pci_dev(hwif->dev);
1da177e4	45	u8 drive_pci = 0x60 + (drive->dn << 2);
1da177e4	46
4fce3164	47	u8 AP = 0, BP = 0, CP = 0;
1da177e4 LT	48	u8 TA = 0, TB = 0, TC = 0;
1da177e4 LT	49
4fce3164 BZ	50	#if PDC202XX_DEBUG_DRIVE_INFO
4fce3164 BZ	51	u32 drive_conf = 0;
1da177e4	52	pci_read_config_dword(dev, drive_pci, &drive_conf);
4fce3164	53	#endif
1da177e4	54
4fce3164 BZ	55	/*
	56	* TODO: do this once per channel
	57	*/
	58	if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
	59	pdc_old_disable_66MHz_clock(hwif);
1da177e4	60
4fce3164 BZ	61	pci_read_config_byte(dev, drive_pci, &AP);
	62	pci_read_config_byte(dev, drive_pci + 1, &BP);
	63	pci_read_config_byte(dev, drive_pci + 2, &CP);
1da177e4 LT	64
1da177e4 LT	65	switch(speed) {
1da177e4 LT	66	case XFER_UDMA_5:
	67	case XFER_UDMA_4: TB = 0x20; TC = 0x01; break;
	68	case XFER_UDMA_2: TB = 0x20; TC = 0x01; break;
	69	case XFER_UDMA_3:
	70	case XFER_UDMA_1: TB = 0x40; TC = 0x02; break;
	71	case XFER_UDMA_0:
	72	case XFER_MW_DMA_2: TB = 0x60; TC = 0x03; break;
	73	case XFER_MW_DMA_1: TB = 0x60; TC = 0x04; break;
4fce3164	74	case XFER_MW_DMA_0: TB = 0xE0; TC = 0x0F; break;
1da177e4 LT	75	case XFER_PIO_4: TA = 0x01; TB = 0x04; break;
	76	case XFER_PIO_3: TA = 0x02; TB = 0x06; break;
	77	case XFER_PIO_2: TA = 0x03; TB = 0x08; break;
	78	case XFER_PIO_1: TA = 0x05; TB = 0x0C; break;
	79	case XFER_PIO_0:
	80	default: TA = 0x09; TB = 0x13; break;
	81	}
	82
	83	if (speed < XFER_SW_DMA_0) {
4fce3164 BZ	84	/*
	85	* preserve SYNC_INT / ERDDY_EN bits while clearing
	86	* Prefetch_EN / IORDY_EN / PA[3:0] bits of register A
	87	*/
	88	AP &= ~0x3f;
	89	if (drive->id->capability & 4)
	90	AP \|= 0x20; /* set IORDY_EN bit */
	91	if (drive->media == ide_disk)
	92	AP \|= 0x10; /* set Prefetch_EN bit */
	93	/* clear PB[4:0] bits of register B */
	94	BP &= ~0x1f;
	95	pci_write_config_byte(dev, drive_pci, AP \| TA);
	96	pci_write_config_byte(dev, drive_pci + 1, BP \| TB);
1da177e4	97	} else {
4fce3164 BZ	98	/* clear MB[2:0] bits of register B */
	99	BP &= ~0xe0;
	100	/* clear MC[3:0] bits of register C */
	101	CP &= ~0x0f;
	102	pci_write_config_byte(dev, drive_pci + 1, BP \| TB);
	103	pci_write_config_byte(dev, drive_pci + 2, CP \| TC);
1da177e4 LT	104	}
	105
	106	#if PDC202XX_DEBUG_DRIVE_INFO
	107	printk(KERN_DEBUG "%s: %s drive%d 0x%08x ",
	108	drive->name, ide_xfer_verbose(speed),
	109	drive->dn, drive_conf);
4fce3164	110	pci_read_config_dword(dev, drive_pci, &drive_conf);
1da177e4	111	printk("0x%08x\n", drive_conf);
4fce3164	112	#endif
1da177e4 LT	113	}
1da177e4 LT	114
26bcb879	115	static void pdc202xx_set_pio_mode(ide_drive_t *drive, const u8 pio)
1da177e4	116	{
88b2b32b	117	pdc202xx_set_mode(drive, XFER_PIO_0 + pio);
1da177e4 LT	118	}
1da177e4 LT	119
ac95beed	120	static u8 __devinit pdc2026x_cable_detect(ide_hwif_t *hwif)
1da177e4	121	{
36501650	122	struct pci_dev *dev = to_pci_dev(hwif->dev);
1bee4d1d	123	u16 CIS, mask = hwif->channel ? (1 << 11) : (1 << 10);
49521f97	124
36501650	125	pci_read_config_word(dev, 0x50, &CIS);
49521f97 BZ	126
49521f97 BZ	127	return (CIS & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
1da177e4 LT	128	}
	129
	130	/*
	131	* Set the control register to use the 66MHz system
	132	* clock for UDMA 3/4/5 mode operation when necessary.
	133	*
4fce3164 BZ	134	* FIXME: this register is shared by both channels, some locking is needed
4fce3164 BZ	135	*
1da177e4 LT	136	* It may also be possible to leave the 66MHz clock on
	137	* and readjust the timing parameters.
	138	*/
	139	static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
	140	{
1c029fd6	141	unsigned long clock_reg = hwif->extra_base + 0x01;
0ecdca26	142	u8 clock = inb(clock_reg);
1da177e4	143
0ecdca26	144	outb(clock \| (hwif->channel ? 0x08 : 0x02), clock_reg);
1da177e4 LT	145	}
	146
	147	static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
	148	{
1c029fd6	149	unsigned long clock_reg = hwif->extra_base + 0x01;
0ecdca26	150	u8 clock = inb(clock_reg);
1da177e4	151
0ecdca26	152	outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
1da177e4 LT	153	}
1da177e4 LT	154
f01393e4	155	static void pdc202xx_quirkproc(ide_drive_t *drive)
1da177e4	156	{
d24ec426 SS	157	const char *list, model = drive->id->model;
	158
	159	for (list = pdc_quirk_drives; *list != NULL; list++)
f01393e4 BZ	160	if (strstr(model, *list) != NULL) {
	161	drive->quirk_list = 2;
	162	return;
	163	}
	164
	165	drive->quirk_list = 0;
1da177e4 LT	166	}
1da177e4 LT	167
5e37bdc0	168	static void pdc202xx_dma_start(ide_drive_t *drive)
1da177e4 LT	169	{
	170	if (drive->current_speed > XFER_UDMA_2)
	171	pdc_old_enable_66MHz_clock(drive->hwif);
f3d5b34c	172	if (drive->media != ide_disk \|\| drive->addressing == 1) {
1da177e4 LT	173	struct request *rq = HWGROUP(drive)->rq;
1da177e4 LT	174	ide_hwif_t *hwif = HWIF(drive);
1c029fd6	175	unsigned long high_16 = hwif->extra_base - 16;
1da177e4 LT	176	unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
1da177e4 LT	177	u32 word_count = 0;
0ecdca26	178	u8 clock = inb(high_16 + 0x11);
1da177e4	179
0ecdca26	180	outb(clock \| (hwif->channel ? 0x08 : 0x02), high_16 + 0x11);
1da177e4 LT	181	word_count = (rq->nr_sectors << 8);
	182	word_count = (rq_data_dir(rq) == READ) ?
	183	word_count \| 0x05000000 :
	184	word_count \| 0x06000000;
0ecdca26	185	outl(word_count, atapi_reg);
1da177e4 LT	186	}
	187	ide_dma_start(drive);
	188	}
	189
5e37bdc0	190	static int pdc202xx_dma_end(ide_drive_t *drive)
1da177e4	191	{
f3d5b34c	192	if (drive->media != ide_disk \|\| drive->addressing == 1) {
1da177e4	193	ide_hwif_t *hwif = HWIF(drive);
1c029fd6	194	unsigned long high_16 = hwif->extra_base - 16;
1da177e4 LT	195	unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
	196	u8 clock = 0;
	197
0ecdca26 BZ	198	outl(0, atapi_reg); /* zero out extra */
	199	clock = inb(high_16 + 0x11);
	200	outb(clock & ~(hwif->channel ? 0x08:0x02), high_16 + 0x11);
1da177e4 LT	201	}
	202	if (drive->current_speed > XFER_UDMA_2)
	203	pdc_old_disable_66MHz_clock(drive->hwif);
	204	return __ide_dma_end(drive);
	205	}
	206
5e37bdc0	207	static int pdc202xx_dma_test_irq(ide_drive_t *drive)
1da177e4 LT	208	{
1da177e4 LT	209	ide_hwif_t *hwif = HWIF(drive);
1c029fd6	210	unsigned long high_16 = hwif->extra_base - 16;
cab7f8ed	211	u8 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
0ecdca26	212	u8 sc1d = inb(high_16 + 0x001d);
1da177e4 LT	213
	214	if (hwif->channel) {
	215	/* bit7: Error, bit6: Interrupting, bit5: FIFO Full, bit4: FIFO Empty */
	216	if ((sc1d & 0x50) == 0x50)
	217	goto somebody_else;
	218	else if ((sc1d & 0x40) == 0x40)
	219	return (dma_stat & 4) == 4;
	220	} else {
	221	/* bit3: Error, bit2: Interrupting, bit1: FIFO Full, bit0: FIFO Empty */
	222	if ((sc1d & 0x05) == 0x05)
	223	goto somebody_else;
	224	else if ((sc1d & 0x04) == 0x04)
	225	return (dma_stat & 4) == 4;
	226	}
	227	somebody_else:
	228	return (dma_stat & 4) == 4; /* return 1 if INTR asserted */
	229	}
	230
1da177e4 LT	231	static void pdc202xx_reset_host (ide_hwif_t *hwif)
1da177e4 LT	232	{
1c029fd6	233	unsigned long high_16 = hwif->extra_base - 16;
0ecdca26	234	u8 udma_speed_flag = inb(high_16 \| 0x001f);
1da177e4	235
0ecdca26	236	outb(udma_speed_flag \| 0x10, high_16 \| 0x001f);
1da177e4	237	mdelay(100);
0ecdca26	238	outb(udma_speed_flag & ~0x10, high_16 \| 0x001f);
1da177e4 LT	239	mdelay(2000); /* 2 seconds ?! */
	240
	241	printk(KERN_WARNING "PDC202XX: %s channel reset.\n",
	242	hwif->channel ? "Secondary" : "Primary");
	243	}
	244
	245	static void pdc202xx_reset (ide_drive_t *drive)
	246	{
	247	ide_hwif_t *hwif = HWIF(drive);
	248	ide_hwif_t *mate = hwif->mate;
26bcb879	249
1da177e4 LT	250	pdc202xx_reset_host(hwif);
1da177e4 LT	251	pdc202xx_reset_host(mate);
26bcb879 BZ	252
26bcb879 BZ	253	ide_set_max_pio(drive);
1da177e4 LT	254	}
1da177e4 LT	255
ac95beed BZ	256	static void pdc202xx_dma_lost_irq(ide_drive_t *drive)
	257	{
	258	pdc202xx_reset(drive);
	259	ide_dma_lost_irq(drive);
	260	}
	261
	262	static void pdc202xx_dma_timeout(ide_drive_t *drive)
	263	{
	264	pdc202xx_reset(drive);
	265	ide_dma_timeout(drive);
	266	}
	267
a326b02b	268	static unsigned int __devinit init_chipset_pdc202xx(struct pci_dev *dev)
1da177e4	269	{
73369d2a	270	unsigned long dmabase = pci_resource_start(dev, 4);
1da177e4 LT	271	u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0;
1da177e4 LT	272
73369d2a BZ	273	if (dmabase == 0)
73369d2a BZ	274	goto out;
1da177e4	275
0ecdca26 BZ	276	udma_speed_flag = inb(dmabase \| 0x1f);
	277	primary_mode = inb(dmabase \| 0x1a);
	278	secondary_mode = inb(dmabase \| 0x1b);
1da177e4 LT	279	printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
1da177e4 LT	280	"Primary %s Mode " \
5e59c236	281	"Secondary %s Mode.\n", pci_name(dev),
1da177e4 LT	282	(udma_speed_flag & 1) ? "EN" : "DIS",
	283	(primary_mode & 1) ? "MASTER" : "PCI",
	284	(secondary_mode & 1) ? "MASTER" : "PCI" );
	285
1da177e4 LT	286	if (!(udma_speed_flag & 1)) {
1da177e4 LT	287	printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
5e59c236	288	pci_name(dev), udma_speed_flag,
1da177e4	289	(udma_speed_flag\|1));
0ecdca26 BZ	290	outb(udma_speed_flag \| 1, dmabase \| 0x1f);
0ecdca26 BZ	291	printk("%sACTIVE\n", (inb(dmabase \| 0x1f) & 1) ? "" : "IN");
1da177e4	292	}
73369d2a BZ	293	out:
73369d2a BZ	294	return dev->irq;
1da177e4 LT	295	}
1da177e4 LT	296
97f84baa BZ	297	static void __devinit pdc202ata4_fixup_irq(struct pci_dev *dev,
97f84baa BZ	298	const char *name)
1da177e4 LT	299	{
	300	if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
	301	u8 irq = 0, irq2 = 0;
	302	pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
	303	/* 0xbc */
	304	pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)\|0x80, &irq2);
	305	if (irq != irq2) {
	306	pci_write_config_byte(dev,
	307	(PCI_INTERRUPT_LINE)\|0x80, irq); /* 0xbc */
28cfd8af BZ	308	printk(KERN_INFO "%s %s: PCI config space interrupt "
28cfd8af BZ	309	"mirror fixed\n", name, pci_name(dev));
1da177e4 LT	310	}
1da177e4 LT	311	}
1da177e4 LT	312	}
1da177e4 LT	313
4db90a14 BZ	314	#define IDE_HFLAGS_PDC202XX \
4db90a14 BZ	315	(IDE_HFLAG_ERROR_STOPS_FIFO \| \
4db90a14 BZ	316	IDE_HFLAG_OFF_BOARD)
4db90a14 BZ	317
ac95beed BZ	318	static const struct ide_port_ops pdc20246_port_ops = {
	319	.set_pio_mode = pdc202xx_set_pio_mode,
	320	.set_dma_mode = pdc202xx_set_mode,
	321	.quirkproc = pdc202xx_quirkproc,
	322	};
	323
	324	static const struct ide_port_ops pdc2026x_port_ops = {
	325	.set_pio_mode = pdc202xx_set_pio_mode,
	326	.set_dma_mode = pdc202xx_set_mode,
	327	.quirkproc = pdc202xx_quirkproc,
	328	.resetproc = pdc202xx_reset,
	329	.cable_detect = pdc2026x_cable_detect,
	330	};
	331
f37afdac BZ	332	static const struct ide_dma_ops pdc20246_dma_ops = {
	333	.dma_host_set = ide_dma_host_set,
	334	.dma_setup = ide_dma_setup,
	335	.dma_exec_cmd = ide_dma_exec_cmd,
	336	.dma_start = ide_dma_start,
	337	.dma_end = __ide_dma_end,
5e37bdc0 BZ	338	.dma_test_irq = pdc202xx_dma_test_irq,
	339	.dma_lost_irq = pdc202xx_dma_lost_irq,
	340	.dma_timeout = pdc202xx_dma_timeout,
	341	};
	342
f37afdac BZ	343	static const struct ide_dma_ops pdc2026x_dma_ops = {
	344	.dma_host_set = ide_dma_host_set,
	345	.dma_setup = ide_dma_setup,
	346	.dma_exec_cmd = ide_dma_exec_cmd,
5e37bdc0 BZ	347	.dma_start = pdc202xx_dma_start,
	348	.dma_end = pdc202xx_dma_end,
	349	.dma_test_irq = pdc202xx_dma_test_irq,
	350	.dma_lost_irq = pdc202xx_dma_lost_irq,
	351	.dma_timeout = pdc202xx_dma_timeout,
	352	};
	353
ced3ec8a	354	#define DECLARE_PDC2026X_DEV(udma, extra_flags) \
5ef8cb5d	355	{ \
ced3ec8a	356	.name = DRV_NAME, \
5ef8cb5d	357	.init_chipset = init_chipset_pdc202xx, \
ac95beed	358	.port_ops = &pdc2026x_port_ops, \
5e37bdc0	359	.dma_ops = &pdc2026x_dma_ops, \
4db90a14	360	.host_flags = IDE_HFLAGS_PDC202XX \| extra_flags, \
5ef8cb5d BZ	361	.pio_mask = ATA_PIO4, \
	362	.mwdma_mask = ATA_MWDMA2, \
	363	.udma_mask = udma, \
	364	}
	365
85620436	366	static const struct ide_port_info pdc202xx_chipsets[] __devinitdata = {
ced3ec8a BZ	367	{ /* 0: PDC20246 */
ced3ec8a BZ	368	.name = DRV_NAME,
1da177e4	369	.init_chipset = init_chipset_pdc202xx,
ac95beed	370	.port_ops = &pdc20246_port_ops,
5e37bdc0	371	.dma_ops = &pdc20246_dma_ops,
4db90a14	372	.host_flags = IDE_HFLAGS_PDC202XX,
4099d143	373	.pio_mask = ATA_PIO4,
5f8b6c34 BZ	374	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	375	.udma_mask = ATA_UDMA2,
5ef8cb5d BZ	376	},
5ef8cb5d BZ	377
ced3ec8a BZ	378	/* 1: PDC2026{2,3} */
	379	DECLARE_PDC2026X_DEV(ATA_UDMA4, 0),
	380	/* 2: PDC2026{5,7} */
	381	DECLARE_PDC2026X_DEV(ATA_UDMA5, IDE_HFLAG_RQSIZE_256),
1da177e4 LT	382	};
	383
	384	/**
	385	* pdc202xx_init_one - called when a PDC202xx is found
	386	* @dev: the pdc202xx device
	387	* @id: the matching pci id
	388	*
	389	* Called when the PCI registration layer (or the IDE initialization)
	390	* finds a device matching our IDE device tables.
	391	*/
	392
	393	static int __devinit pdc202xx_init_one(struct pci_dev dev, const struct pci_device_id id)
	394	{
85620436	395	const struct ide_port_info *d;
97f84baa BZ	396	u8 idx = id->driver_data;
	397
	398	d = &pdc202xx_chipsets[idx];
	399
ced3ec8a	400	if (idx < 2)
97f84baa BZ	401	pdc202ata4_fixup_irq(dev, d->name);
97f84baa BZ	402
ced3ec8a	403	if (dev->vendor == PCI_DEVICE_ID_PROMISE_20265) {
97f84baa	404	struct pci_dev *bridge = dev->bus->self;
1da177e4	405
97f84baa BZ	406	if (bridge &&
	407	bridge->vendor == PCI_VENDOR_ID_INTEL &&
	408	(bridge->device == PCI_DEVICE_ID_INTEL_I960 \|\|
	409	bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) {
ced3ec8a	410	printk(KERN_INFO DRV_NAME " %s: skipping Promise "
28cfd8af BZ	411	"PDC20265 attached to I2O RAID controller\n",
28cfd8af BZ	412	pci_name(dev));
97f84baa BZ	413	return -ENODEV;
	414	}
	415	}
	416
6cdf6eb3	417	return ide_pci_init_one(dev, d, NULL);
1da177e4 LT	418	}
1da177e4 LT	419
9cbcc5e3 BZ	420	static const struct pci_device_id pdc202xx_pci_tbl[] = {
	421	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 },
	422	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 },
ced3ec8a BZ	423	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 1 },
	424	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 2 },
	425	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 2 },
1da177e4 LT	426	{ 0, },
	427	};
	428	MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl);
	429
	430	static struct pci_driver driver = {
	431	.name = "Promise_Old_IDE",
	432	.id_table = pdc202xx_pci_tbl,
	433	.probe = pdc202xx_init_one,
574a1c24	434	.remove = ide_pci_remove,
1da177e4 LT	435	};
1da177e4 LT	436
82ab1eec	437	static int __init pdc202xx_ide_init(void)
1da177e4 LT	438	{
	439	return ide_pci_register_driver(&driver);
	440	}
	441
574a1c24 BZ	442	static void __exit pdc202xx_ide_exit(void)
	443	{
	444	pci_unregister_driver(&driver);
	445	}
	446
1da177e4	447	module_init(pdc202xx_ide_init);
574a1c24	448	module_exit(pdc202xx_ide_exit);
1da177e4 LT	449
	450	MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
	451	MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
	452	MODULE_LICENSE("GPL");