[linux-2.6-block.git] / drivers / ide / pci / pdc202xx_new.c

/*
 *  Promise TX2/TX4/TX2000/133 IDE driver
 *
 *  This program is free software; you can redistribute it and/or
 *  modify it under the terms of the GNU General Public License
 *  as published by the Free Software Foundation; either version
 *  2 of the License, or (at your option) any later version.
 *
 *  Split from:
 *  linux/drivers/ide/pdc202xx.c	Version 0.35	Mar. 30, 2002
 *  Copyright (C) 1998-2002		Andre Hedrick <andre@linux-ide.org>
 *  Copyright (C) 2005-2006		MontaVista Software, Inc.
 *  Portions Copyright (C) 1999 Promise Technology, Inc.
 *  Author: Frank Tiernan (frankt@promise.com)
 *  Released under terms of General Public License
 */

#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/timer.h>
#include <linux/mm.h>
#include <linux/ioport.h>
#include <linux/blkdev.h>
#include <linux/hdreg.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ide.h>

#include <asm/io.h>
#include <asm/irq.h>

#ifdef CONFIG_PPC_PMAC
#include <asm/prom.h>
#include <asm/pci-bridge.h>
#endif

#undef DEBUG

#ifdef DEBUG
#define DBG(fmt, args...) printk("%s: " fmt, __FUNCTION__, ## args)
#else
#define DBG(fmt, args...)
#endif

static const char *pdc_quirk_drives[] = {
	"QUANTUM FIREBALLlct08 08",
	"QUANTUM FIREBALLP KA6.4",
	"QUANTUM FIREBALLP KA9.1",
	"QUANTUM FIREBALLP LM20.4",
	"QUANTUM FIREBALLP KX13.6",
	"QUANTUM FIREBALLP KX20.5",
	"QUANTUM FIREBALLP KX27.3",
	"QUANTUM FIREBALLP LM20.5",
	NULL
};

static u8 max_dma_rate(struct pci_dev *pdev)
{
	u8 mode;

	switch(pdev->device) {
		case PCI_DEVICE_ID_PROMISE_20277:
		case PCI_DEVICE_ID_PROMISE_20276:
		case PCI_DEVICE_ID_PROMISE_20275:
		case PCI_DEVICE_ID_PROMISE_20271:
		case PCI_DEVICE_ID_PROMISE_20269:
			mode = 4;
			break;
		case PCI_DEVICE_ID_PROMISE_20270:
		case PCI_DEVICE_ID_PROMISE_20268:
			mode = 3;
			break;
		default:
			return 0;
	}

	return mode;
}

/**
 * get_indexed_reg - Get indexed register
 * @hwif: for the port address
 * @index: index of the indexed register
 */
static u8 get_indexed_reg(ide_hwif_t *hwif, u8 index)
{
	u8 value;

	outb(index, hwif->dma_vendor1);
	value = inb(hwif->dma_vendor3);

	DBG("index[%02X] value[%02X]\n", index, value);
	return value;
}

/**
 * set_indexed_reg - Set indexed register
 * @hwif: for the port address
 * @index: index of the indexed register
 */
static void set_indexed_reg(ide_hwif_t *hwif, u8 index, u8 value)
{
	outb(index, hwif->dma_vendor1);
	outb(value, hwif->dma_vendor3);
	DBG("index[%02X] value[%02X]\n", index, value);
}

/*
 * ATA Timing Tables based on 133 MHz PLL output clock.
 *
 * If the PLL outputs 100 MHz clock, the ASIC hardware will set
 * the timing registers automatically when "set features" command is
 * issued to the device. However, if the PLL output clock is 133 MHz,
 * the following tables must be used.
 */
static struct pio_timing {
	u8 reg0c, reg0d, reg13;
} pio_timings [] = {
	{ 0xfb, 0x2b, 0xac },	/* PIO mode 0, IORDY off, Prefetch off */
	{ 0x46, 0x29, 0xa4 },	/* PIO mode 1, IORDY off, Prefetch off */
	{ 0x23, 0x26, 0x64 },	/* PIO mode 2, IORDY off, Prefetch off */
	{ 0x27, 0x0d, 0x35 },	/* PIO mode 3, IORDY on,  Prefetch off */
	{ 0x23, 0x09, 0x25 },	/* PIO mode 4, IORDY on,  Prefetch off */
};

static struct mwdma_timing {
	u8 reg0e, reg0f;
} mwdma_timings [] = {
	{ 0xdf, 0x5f }, 	/* MWDMA mode 0 */
	{ 0x6b, 0x27 }, 	/* MWDMA mode 1 */
	{ 0x69, 0x25 }, 	/* MWDMA mode 2 */
};

static struct udma_timing {
	u8 reg10, reg11, reg12;
} udma_timings [] = {
	{ 0x4a, 0x0f, 0xd5 },	/* UDMA mode 0 */
	{ 0x3a, 0x0a, 0xd0 },	/* UDMA mode 1 */
	{ 0x2a, 0x07, 0xcd },	/* UDMA mode 2 */
	{ 0x1a, 0x05, 0xcd },	/* UDMA mode 3 */
	{ 0x1a, 0x03, 0xcd },	/* UDMA mode 4 */
	{ 0x1a, 0x02, 0xcb },	/* UDMA mode 5 */
	{ 0x1a, 0x01, 0xcb },	/* UDMA mode 6 */
};

static int pdcnew_tune_chipset(ide_drive_t *drive, u8 speed)
{
	ide_hwif_t *hwif	= HWIF(drive);
	u8 adj			= (drive->dn & 1) ? 0x08 : 0x00;
	int			err;

	speed = ide_rate_filter(drive, speed);

	/*
	 * Issue SETFEATURES_XFER to the drive first. PDC202xx hardware will
	 * automatically set the timing registers based on 100 MHz PLL output.
	 */
 	err = ide_config_drive_speed(drive, speed);

	/*
	 * As we set up the PLL to output 133 MHz for UltraDMA/133 capable
	 * chips, we must override the default register settings...
	 */
	if (max_dma_rate(hwif->pci_dev) == 4) {
		u8 mode = speed & 0x07;

		switch (speed) {
			case XFER_UDMA_6:
			case XFER_UDMA_5:
			case XFER_UDMA_4:
			case XFER_UDMA_3:
			case XFER_UDMA_2:
			case XFER_UDMA_1:
			case XFER_UDMA_0:
				set_indexed_reg(hwif, 0x10 + adj,
						udma_timings[mode].reg10);
				set_indexed_reg(hwif, 0x11 + adj,
						udma_timings[mode].reg11);
				set_indexed_reg(hwif, 0x12 + adj,
						udma_timings[mode].reg12);
				break;

			case XFER_MW_DMA_2:
			case XFER_MW_DMA_1:
			case XFER_MW_DMA_0:
				set_indexed_reg(hwif, 0x0e + adj,
						mwdma_timings[mode].reg0e);
				set_indexed_reg(hwif, 0x0f + adj,
						mwdma_timings[mode].reg0f);
				break;
			case XFER_PIO_4:
			case XFER_PIO_3:
			case XFER_PIO_2:
			case XFER_PIO_1:
			case XFER_PIO_0:
				set_indexed_reg(hwif, 0x0c + adj,
						pio_timings[mode].reg0c);
				set_indexed_reg(hwif, 0x0d + adj,
						pio_timings[mode].reg0d);
				set_indexed_reg(hwif, 0x13 + adj,
						pio_timings[mode].reg13);
				break;
			default:
				printk(KERN_ERR "pdc202xx_new: "
				       "Unknown speed %d ignored\n", speed);
		}
	} else if (speed == XFER_UDMA_2) {
		/* Set tHOLD bit to 0 if using UDMA mode 2 */
		u8 tmp = get_indexed_reg(hwif, 0x10 + adj);

		set_indexed_reg(hwif, 0x10 + adj, tmp & 0x7f);
 	}

	return err;
}

static void pdcnew_tune_drive(ide_drive_t *drive, u8 pio)
{
	pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
	(void)pdcnew_tune_chipset(drive, XFER_PIO_0 + pio);
}

static u8 pdcnew_cable_detect(ide_hwif_t *hwif)
{
	return get_indexed_reg(hwif, 0x0b) & 0x04;
}

static int pdcnew_config_drive_xfer_rate(ide_drive_t *drive)
{
	drive->init_speed = 0;

	if (ide_tune_dma(drive))
		return 0;

	if (ide_use_fast_pio(drive))
		pdcnew_tune_drive(drive, 255);

	return -1;
}

static int pdcnew_quirkproc(ide_drive_t *drive)
{
	const char **list, *model = drive->id->model;

	for (list = pdc_quirk_drives; *list != NULL; list++)
		if (strstr(model, *list) != NULL)
			return 2;
	return 0;
}

static void pdcnew_reset(ide_drive_t *drive)
{
	/*
	 * Deleted this because it is redundant from the caller.
	 */
	printk(KERN_WARNING "pdc202xx_new: %s channel reset.\n",
		HWIF(drive)->channel ? "Secondary" : "Primary");
}

/**
 * read_counter - Read the byte count registers
 * @dma_base: for the port address
 */
static long __devinit read_counter(u32 dma_base)
{
	u32  pri_dma_base = dma_base, sec_dma_base = dma_base + 0x08;
	u8   cnt0, cnt1, cnt2, cnt3;
	long count = 0, last;
	int  retry = 3;

	do {
		last = count;

		/* Read the current count */
		outb(0x20, pri_dma_base + 0x01);
		cnt0 = inb(pri_dma_base + 0x03);
		outb(0x21, pri_dma_base + 0x01);
		cnt1 = inb(pri_dma_base + 0x03);
		outb(0x20, sec_dma_base + 0x01);
		cnt2 = inb(sec_dma_base + 0x03);
		outb(0x21, sec_dma_base + 0x01);
		cnt3 = inb(sec_dma_base + 0x03);

		count = (cnt3 << 23) | (cnt2 << 15) | (cnt1 << 8) | cnt0;

		/*
		 * The 30-bit decrementing counter is read in 4 pieces.
		 * Incorrect value may be read when the most significant bytes
		 * are changing...
		 */
	} while (retry-- && (((last ^ count) & 0x3fff8000) || last < count));

	DBG("cnt0[%02X] cnt1[%02X] cnt2[%02X] cnt3[%02X]\n",
		  cnt0, cnt1, cnt2, cnt3);

	return count;
}

/**
 * detect_pll_input_clock - Detect the PLL input clock in Hz.
 * @dma_base: for the port address
 * E.g. 16949000 on 33 MHz PCI bus, i.e. half of the PCI clock.
 */
static long __devinit detect_pll_input_clock(unsigned long dma_base)
{
	long start_count, end_count;
	long pll_input;
	u8 scr1;

	start_count = read_counter(dma_base);

	/* Start the test mode */
	outb(0x01, dma_base + 0x01);
	scr1 = inb(dma_base + 0x03);
	DBG("scr1[%02X]\n", scr1);
	outb(scr1 | 0x40, dma_base + 0x03);

	/* Let the counter run for 10 ms. */
	mdelay(10);

	end_count = read_counter(dma_base);

	/* Stop the test mode */
	outb(0x01, dma_base + 0x01);
	scr1 = inb(dma_base + 0x03);
	DBG("scr1[%02X]\n", scr1);
	outb(scr1 & ~0x40, dma_base + 0x03);

	/*
	 * Calculate the input clock in Hz
	 * (the clock counter is 30 bit wide and counts down)
	 */
	pll_input = ((start_count - end_count) & 0x3ffffff) * 100;

	DBG("start[%ld] end[%ld]\n", start_count, end_count);

	return pll_input;
}

#ifdef CONFIG_PPC_PMAC
static void __devinit apple_kiwi_init(struct pci_dev *pdev)
{
	struct device_node *np = pci_device_to_OF_node(pdev);
	unsigned int class_rev = 0;
	u8 conf;

	if (np == NULL || !of_device_is_compatible(np, "kiwi-root"))
		return;

	pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class_rev);
	class_rev &= 0xff;

	if (class_rev >= 0x03) {
		/* Setup chip magic config stuff (from darwin) */
		pci_read_config_byte (pdev, 0x40, &conf);
		pci_write_config_byte(pdev, 0x40, (conf | 0x01));
	}
}
#endif /* CONFIG_PPC_PMAC */

static unsigned int __devinit init_chipset_pdcnew(struct pci_dev *dev, const char *name)
{
	unsigned long dma_base = pci_resource_start(dev, 4);
	unsigned long sec_dma_base = dma_base + 0x08;
	long pll_input, pll_output, ratio;
	int f, r;
	u8 pll_ctl0, pll_ctl1;

	if (dev->resource[PCI_ROM_RESOURCE].start) {
		pci_write_config_dword(dev, PCI_ROM_ADDRESS,
			dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
		printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n", name,
			(unsigned long)dev->resource[PCI_ROM_RESOURCE].start);
	}

#ifdef CONFIG_PPC_PMAC
	apple_kiwi_init(dev);
#endif

	/* Calculate the required PLL output frequency */
	switch(max_dma_rate(dev)) {
		case 4: /* it's 133 MHz for Ultra133 chips */
			pll_output = 133333333;
			break;
		case 3: /* and  100 MHz for Ultra100 chips */
		default:
			pll_output = 100000000;
			break;
	}

	/*
	 * Detect PLL input clock.
	 * On some systems, where PCI bus is running at non-standard clock rate
	 * (e.g. 25 or 40 MHz), we have to adjust the cycle time.
	 * PDC20268 and newer chips employ PLL circuit to help correct timing
	 * registers setting.
	 */
	pll_input = detect_pll_input_clock(dma_base);
	printk("%s: PLL input clock is %ld kHz\n", name, pll_input / 1000);

	/* Sanity check */
	if (unlikely(pll_input < 5000000L || pll_input > 70000000L)) {
		printk(KERN_ERR "%s: Bad PLL input clock %ld Hz, giving up!\n",
		       name, pll_input);
		goto out;
	}

#ifdef DEBUG
	DBG("pll_output is %ld Hz\n", pll_output);

	/* Show the current clock value of PLL control register
	 * (maybe already configured by the BIOS)
	 */
	outb(0x02, sec_dma_base + 0x01);
	pll_ctl0 = inb(sec_dma_base + 0x03);
	outb(0x03, sec_dma_base + 0x01);
	pll_ctl1 = inb(sec_dma_base + 0x03);

	DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
#endif

	/*
	 * Calculate the ratio of F, R and NO
	 * POUT = (F + 2) / (( R + 2) * NO)
	 */
	ratio = pll_output / (pll_input / 1000);
	if (ratio < 8600L) { /* 8.6x */
		/* Using NO = 0x01, R = 0x0d */
		r = 0x0d;
	} else if (ratio < 12900L) { /* 12.9x */
		/* Using NO = 0x01, R = 0x08 */
		r = 0x08;
	} else if (ratio < 16100L) { /* 16.1x */
		/* Using NO = 0x01, R = 0x06 */
		r = 0x06;
	} else if (ratio < 64000L) { /* 64x */
		r = 0x00;
	} else {
		/* Invalid ratio */
		printk(KERN_ERR "%s: Bad ratio %ld, giving up!\n", name, ratio);
		goto out;
	}

	f = (ratio * (r + 2)) / 1000 - 2;

	DBG("F[%d] R[%d] ratio*1000[%ld]\n", f, r, ratio);

	if (unlikely(f < 0 || f > 127)) {
		/* Invalid F */
		printk(KERN_ERR "%s: F[%d] invalid!\n", name, f);
		goto out;
	}

	pll_ctl0 = (u8) f;
	pll_ctl1 = (u8) r;

	DBG("Writing pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);

	outb(0x02,     sec_dma_base + 0x01);
	outb(pll_ctl0, sec_dma_base + 0x03);
	outb(0x03,     sec_dma_base + 0x01);
	outb(pll_ctl1, sec_dma_base + 0x03);

	/* Wait the PLL circuit to be stable */
	mdelay(30);

#ifdef DEBUG
	/*
	 *  Show the current clock value of PLL control register
	 */
	outb(0x02, sec_dma_base + 0x01);
	pll_ctl0 = inb(sec_dma_base + 0x03);
	outb(0x03, sec_dma_base + 0x01);
	pll_ctl1 = inb(sec_dma_base + 0x03);

	DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
#endif

 out:
	return dev->irq;
}

static void __devinit init_hwif_pdc202new(ide_hwif_t *hwif)
{
	hwif->autodma = 0;

	hwif->tuneproc  = &pdcnew_tune_drive;
	hwif->quirkproc = &pdcnew_quirkproc;
	hwif->speedproc = &pdcnew_tune_chipset;
	hwif->resetproc = &pdcnew_reset;

	hwif->drives[0].autotune = hwif->drives[1].autotune = 1;

	hwif->atapi_dma  = 1;

	hwif->ultra_mask = hwif->cds->udma_mask;
	hwif->mwdma_mask = 0x07;

	hwif->err_stops_fifo = 1;

	hwif->ide_dma_check = &pdcnew_config_drive_xfer_rate;

	if (!hwif->udma_four)
		hwif->udma_four = pdcnew_cable_detect(hwif) ? 0 : 1;

	if (!noautodma)
		hwif->autodma = 1;
	hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
}

static int __devinit init_setup_pdcnew(struct pci_dev *dev, ide_pci_device_t *d)
{
	return ide_setup_pci_device(dev, d);
}

static int __devinit init_setup_pdc20270(struct pci_dev *dev,
					 ide_pci_device_t *d)
{
	struct pci_dev *findev = NULL;
	int ret;

	if ((dev->bus->self &&
	     dev->bus->self->vendor == PCI_VENDOR_ID_DEC) &&
	    (dev->bus->self->device == PCI_DEVICE_ID_DEC_21150)) {
		if (PCI_SLOT(dev->devfn) & 2)
			return -ENODEV;
		d->extra = 0;
		while ((findev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, findev)) != NULL) {
			if ((findev->vendor == dev->vendor) &&
			    (findev->device == dev->device) &&
			    (PCI_SLOT(findev->devfn) & 2)) {
				if (findev->irq != dev->irq) {
					findev->irq = dev->irq;
				}
				ret = ide_setup_pci_devices(dev, findev, d);
				pci_dev_put(findev);
				return ret;
			}
		}
	}
	return ide_setup_pci_device(dev, d);
}

static int __devinit init_setup_pdc20276(struct pci_dev *dev,
					 ide_pci_device_t *d)
{
	if ((dev->bus->self) &&
	    (dev->bus->self->vendor == PCI_VENDOR_ID_INTEL) &&
	    ((dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960) ||
	     (dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960RM))) {
		printk(KERN_INFO "ide: Skipping Promise PDC20276 "
			"attached to I2O RAID controller.\n");
		return -ENODEV;
	}
	return ide_setup_pci_device(dev, d);
}

static ide_pci_device_t pdcnew_chipsets[] __devinitdata = {
	{	/* 0 */
		.name		= "PDC20268",
		.init_setup	= init_setup_pdcnew,
		.init_chipset	= init_chipset_pdcnew,
		.init_hwif	= init_hwif_pdc202new,
		.channels	= 2,
		.autodma	= AUTODMA,
		.bootable	= OFF_BOARD,
		.udma_mask	= 0x3f, /* udma0-5 */
	},{	/* 1 */
		.name		= "PDC20269",
		.init_setup	= init_setup_pdcnew,
		.init_chipset	= init_chipset_pdcnew,
		.init_hwif	= init_hwif_pdc202new,
		.channels	= 2,
		.autodma	= AUTODMA,
		.bootable	= OFF_BOARD,
		.udma_mask	= 0x7f, /* udma0-6*/
	},{	/* 2 */
		.name		= "PDC20270",
		.init_setup	= init_setup_pdc20270,
		.init_chipset	= init_chipset_pdcnew,
		.init_hwif	= init_hwif_pdc202new,
		.channels	= 2,
		.autodma	= AUTODMA,
		.bootable	= OFF_BOARD,
		.udma_mask	= 0x3f, /* udma0-5 */
	},{	/* 3 */
		.name		= "PDC20271",
		.init_setup	= init_setup_pdcnew,
		.init_chipset	= init_chipset_pdcnew,
		.init_hwif	= init_hwif_pdc202new,
		.channels	= 2,
		.autodma	= AUTODMA,
		.bootable	= OFF_BOARD,
		.udma_mask	= 0x7f, /* udma0-6*/
	},{	/* 4 */
		.name		= "PDC20275",
		.init_setup	= init_setup_pdcnew,
		.init_chipset	= init_chipset_pdcnew,
		.init_hwif	= init_hwif_pdc202new,
		.channels	= 2,
		.autodma	= AUTODMA,
		.bootable	= OFF_BOARD,
		.udma_mask	= 0x7f, /* udma0-6*/
	},{	/* 5 */
		.name		= "PDC20276",
		.init_setup	= init_setup_pdc20276,
		.init_chipset	= init_chipset_pdcnew,
		.init_hwif	= init_hwif_pdc202new,
		.channels	= 2,
		.autodma	= AUTODMA,
		.bootable	= OFF_BOARD,
		.udma_mask	= 0x7f, /* udma0-6*/
	},{	/* 6 */
		.name		= "PDC20277",
		.init_setup	= init_setup_pdcnew,
		.init_chipset	= init_chipset_pdcnew,
		.init_hwif	= init_hwif_pdc202new,
		.channels	= 2,
		.autodma	= AUTODMA,
		.bootable	= OFF_BOARD,
		.udma_mask	= 0x7f, /* udma0-6*/
	}
};

/**
 *	pdc202new_init_one	-	called when a pdc202xx is found
 *	@dev: the pdc202new device
 *	@id: the matching pci id
 *
 *	Called when the PCI registration layer (or the IDE initialization)
 *	finds a device matching our IDE device tables.
 */
 
static int __devinit pdc202new_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	ide_pci_device_t *d = &pdcnew_chipsets[id->driver_data];

	return d->init_setup(dev, d);
}

static struct pci_device_id pdc202new_pci_tbl[] = {
	{ PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20268, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
	{ PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20269, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
	{ PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20270, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
	{ PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20271, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
	{ PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20275, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
	{ PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20276, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
	{ PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20277, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6},
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, pdc202new_pci_tbl);

static struct pci_driver driver = {
	.name		= "Promise_IDE",
	.id_table	= pdc202new_pci_tbl,
	.probe		= pdc202new_init_one,
};

static int __init pdc202new_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}

module_init(pdc202new_ide_init);

MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
MODULE_DESCRIPTION("PCI driver module for Promise PDC20268 and higher");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Promise TX2/TX4/TX2000/133 IDE driver
	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License
	6	* as published by the Free Software Foundation; either version
	7	* 2 of the License, or (at your option) any later version.
	8	*
	9	* Split from:
	10	* linux/drivers/ide/pdc202xx.c Version 0.35 Mar. 30, 2002
	11	* Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
b10a0686	12	* Copyright (C) 2005-2006 MontaVista Software, Inc.
1da177e4 LT	13	* Portions Copyright (C) 1999 Promise Technology, Inc.
	14	* Author: Frank Tiernan (frankt@promise.com)
	15	* Released under terms of General Public License
	16	*/
	17
1da177e4 LT	18	#include <linux/module.h>
	19	#include <linux/types.h>
	20	#include <linux/kernel.h>
	21	#include <linux/delay.h>
	22	#include <linux/timer.h>
	23	#include <linux/mm.h>
	24	#include <linux/ioport.h>
	25	#include <linux/blkdev.h>
	26	#include <linux/hdreg.h>
	27	#include <linux/interrupt.h>
	28	#include <linux/pci.h>
	29	#include <linux/init.h>
	30	#include <linux/ide.h>
	31
	32	#include <asm/io.h>
	33	#include <asm/irq.h>
	34
	35	#ifdef CONFIG_PPC_PMAC
	36	#include <asm/prom.h>
	37	#include <asm/pci-bridge.h>
	38	#endif
	39
47694bb8 SS	40	#undef DEBUG
	41
	42	#ifdef DEBUG
	43	#define DBG(fmt, args...) printk("%s: " fmt, __FUNCTION__, ## args)
	44	#else
	45	#define DBG(fmt, args...)
	46	#endif
	47
3c6bee1d	48	static const char *pdc_quirk_drives[] = {
1da177e4 LT	49	"QUANTUM FIREBALLlct08 08",
	50	"QUANTUM FIREBALLP KA6.4",
	51	"QUANTUM FIREBALLP KA9.1",
	52	"QUANTUM FIREBALLP LM20.4",
	53	"QUANTUM FIREBALLP KX13.6",
	54	"QUANTUM FIREBALLP KX20.5",
	55	"QUANTUM FIREBALLP KX27.3",
	56	"QUANTUM FIREBALLP LM20.5",
	57	NULL
	58	};
	59
47694bb8	60	static u8 max_dma_rate(struct pci_dev *pdev)
1da177e4 LT	61	{
	62	u8 mode;
	63
47694bb8	64	switch(pdev->device) {
1da177e4 LT	65	case PCI_DEVICE_ID_PROMISE_20277:
	66	case PCI_DEVICE_ID_PROMISE_20276:
	67	case PCI_DEVICE_ID_PROMISE_20275:
	68	case PCI_DEVICE_ID_PROMISE_20271:
	69	case PCI_DEVICE_ID_PROMISE_20269:
	70	mode = 4;
	71	break;
	72	case PCI_DEVICE_ID_PROMISE_20270:
	73	case PCI_DEVICE_ID_PROMISE_20268:
	74	mode = 3;
	75	break;
	76	default:
	77	return 0;
	78	}
47694bb8	79
1da177e4 LT	80	return mode;
	81	}
	82
47694bb8 SS	83	/**
	84	* get_indexed_reg - Get indexed register
	85	* @hwif: for the port address
	86	* @index: index of the indexed register
	87	*/
	88	static u8 get_indexed_reg(ide_hwif_t *hwif, u8 index)
	89	{
	90	u8 value;
	91
0ecdca26 BZ	92	outb(index, hwif->dma_vendor1);
0ecdca26 BZ	93	value = inb(hwif->dma_vendor3);
47694bb8 SS	94
	95	DBG("index[%02X] value[%02X]\n", index, value);
	96	return value;
	97	}
	98
	99	/**
	100	* set_indexed_reg - Set indexed register
	101	* @hwif: for the port address
	102	* @index: index of the indexed register
	103	*/
	104	static void set_indexed_reg(ide_hwif_t *hwif, u8 index, u8 value)
	105	{
0ecdca26 BZ	106	outb(index, hwif->dma_vendor1);
0ecdca26 BZ	107	outb(value, hwif->dma_vendor3);
47694bb8 SS	108	DBG("index[%02X] value[%02X]\n", index, value);
	109	}
	110
	111	/*
	112	* ATA Timing Tables based on 133 MHz PLL output clock.
	113	*
	114	* If the PLL outputs 100 MHz clock, the ASIC hardware will set
	115	* the timing registers automatically when "set features" command is
	116	* issued to the device. However, if the PLL output clock is 133 MHz,
	117	* the following tables must be used.
	118	*/
	119	static struct pio_timing {
	120	u8 reg0c, reg0d, reg13;
	121	} pio_timings [] = {
	122	{ 0xfb, 0x2b, 0xac }, /* PIO mode 0, IORDY off, Prefetch off */
	123	{ 0x46, 0x29, 0xa4 }, /* PIO mode 1, IORDY off, Prefetch off */
	124	{ 0x23, 0x26, 0x64 }, /* PIO mode 2, IORDY off, Prefetch off */
	125	{ 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */
	126	{ 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */
	127	};
	128
	129	static struct mwdma_timing {
	130	u8 reg0e, reg0f;
	131	} mwdma_timings [] = {
	132	{ 0xdf, 0x5f }, /* MWDMA mode 0 */
	133	{ 0x6b, 0x27 }, /* MWDMA mode 1 */
	134	{ 0x69, 0x25 }, /* MWDMA mode 2 */
	135	};
	136
	137	static struct udma_timing {
	138	u8 reg10, reg11, reg12;
	139	} udma_timings [] = {
	140	{ 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */
	141	{ 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */
	142	{ 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */
	143	{ 0x1a, 0x05, 0xcd }, /* UDMA mode 3 */
	144	{ 0x1a, 0x03, 0xcd }, /* UDMA mode 4 */
	145	{ 0x1a, 0x02, 0xcb }, /* UDMA mode 5 */
	146	{ 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */
	147	};
	148
	149	static int pdcnew_tune_chipset(ide_drive_t *drive, u8 speed)
1da177e4 LT	150	{
1da177e4 LT	151	ide_hwif_t *hwif = HWIF(drive);
47694bb8 SS	152	u8 adj = (drive->dn & 1) ? 0x08 : 0x00;
47694bb8 SS	153	int err;
1da177e4	154
2d5eaa6d	155	speed = ide_rate_filter(drive, speed);
1da177e4	156
47694bb8 SS	157	/*
	158	* Issue SETFEATURES_XFER to the drive first. PDC202xx hardware will
	159	* automatically set the timing registers based on 100 MHz PLL output.
	160	*/
	161	err = ide_config_drive_speed(drive, speed);
	162
	163	/*
	164	* As we set up the PLL to output 133 MHz for UltraDMA/133 capable
	165	* chips, we must override the default register settings...
	166	*/
	167	if (max_dma_rate(hwif->pci_dev) == 4) {
	168	u8 mode = speed & 0x07;
	169
	170	switch (speed) {
	171	case XFER_UDMA_6:
	172	case XFER_UDMA_5:
	173	case XFER_UDMA_4:
	174	case XFER_UDMA_3:
	175	case XFER_UDMA_2:
	176	case XFER_UDMA_1:
	177	case XFER_UDMA_0:
	178	set_indexed_reg(hwif, 0x10 + adj,
	179	udma_timings[mode].reg10);
	180	set_indexed_reg(hwif, 0x11 + adj,
	181	udma_timings[mode].reg11);
	182	set_indexed_reg(hwif, 0x12 + adj,
	183	udma_timings[mode].reg12);
	184	break;
	185
	186	case XFER_MW_DMA_2:
	187	case XFER_MW_DMA_1:
	188	case XFER_MW_DMA_0:
	189	set_indexed_reg(hwif, 0x0e + adj,
	190	mwdma_timings[mode].reg0e);
	191	set_indexed_reg(hwif, 0x0f + adj,
	192	mwdma_timings[mode].reg0f);
	193	break;
	194	case XFER_PIO_4:
	195	case XFER_PIO_3:
	196	case XFER_PIO_2:
	197	case XFER_PIO_1:
	198	case XFER_PIO_0:
	199	set_indexed_reg(hwif, 0x0c + adj,
	200	pio_timings[mode].reg0c);
	201	set_indexed_reg(hwif, 0x0d + adj,
	202	pio_timings[mode].reg0d);
	203	set_indexed_reg(hwif, 0x13 + adj,
	204	pio_timings[mode].reg13);
	205	break;
	206	default:
	207	printk(KERN_ERR "pdc202xx_new: "
	208	"Unknown speed %d ignored\n", speed);
	209	}
	210	} else if (speed == XFER_UDMA_2) {
	211	/* Set tHOLD bit to 0 if using UDMA mode 2 */
	212	u8 tmp = get_indexed_reg(hwif, 0x10 + adj);
	213
	214	set_indexed_reg(hwif, 0x10 + adj, tmp & 0x7f);
	215	}
	216
	217	return err;
1da177e4 LT	218	}
1da177e4 LT	219
1da177e4 LT	220	static void pdcnew_tune_drive(ide_drive_t *drive, u8 pio)
1da177e4 LT	221	{
b10a0686	222	pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
47694bb8	223	(void)pdcnew_tune_chipset(drive, XFER_PIO_0 + pio);
1da177e4 LT	224	}
1da177e4 LT	225
47694bb8	226	static u8 pdcnew_cable_detect(ide_hwif_t *hwif)
1da177e4	227	{
47694bb8	228	return get_indexed_reg(hwif, 0x0b) & 0x04;
1da177e4	229	}
47694bb8	230
47694bb8	231	static int pdcnew_config_drive_xfer_rate(ide_drive_t *drive)
1da177e4	232	{
1da177e4 LT	233	drive->init_speed = 0;
1da177e4 LT	234
7f86723a	235	if (ide_tune_dma(drive))
3608b5d7	236	return 0;
1da177e4	237
d8f4469d	238	if (ide_use_fast_pio(drive))
3608b5d7	239	pdcnew_tune_drive(drive, 255);
d8f4469d	240
3608b5d7	241	return -1;
1da177e4 LT	242	}
1da177e4 LT	243
47694bb8	244	static int pdcnew_quirkproc(ide_drive_t *drive)
1da177e4	245	{
d24ec426 SS	246	const char *list, model = drive->id->model;
	247
	248	for (list = pdc_quirk_drives; *list != NULL; list++)
	249	if (strstr(model, *list) != NULL)
	250	return 2;
	251	return 0;
1da177e4 LT	252	}
1da177e4 LT	253
47694bb8	254	static void pdcnew_reset(ide_drive_t *drive)
1da177e4 LT	255	{
	256	/*
	257	* Deleted this because it is redundant from the caller.
	258	*/
47694bb8	259	printk(KERN_WARNING "pdc202xx_new: %s channel reset.\n",
1da177e4 LT	260	HWIF(drive)->channel ? "Secondary" : "Primary");
	261	}
	262
47694bb8 SS	263	/**
	264	* read_counter - Read the byte count registers
	265	* @dma_base: for the port address
	266	*/
	267	static long __devinit read_counter(u32 dma_base)
	268	{
	269	u32 pri_dma_base = dma_base, sec_dma_base = dma_base + 0x08;
	270	u8 cnt0, cnt1, cnt2, cnt3;
	271	long count = 0, last;
	272	int retry = 3;
	273
	274	do {
	275	last = count;
	276
	277	/* Read the current count */
	278	outb(0x20, pri_dma_base + 0x01);
	279	cnt0 = inb(pri_dma_base + 0x03);
	280	outb(0x21, pri_dma_base + 0x01);
	281	cnt1 = inb(pri_dma_base + 0x03);
	282	outb(0x20, sec_dma_base + 0x01);
	283	cnt2 = inb(sec_dma_base + 0x03);
	284	outb(0x21, sec_dma_base + 0x01);
	285	cnt3 = inb(sec_dma_base + 0x03);
	286
	287	count = (cnt3 << 23) \| (cnt2 << 15) \| (cnt1 << 8) \| cnt0;
	288
	289	/*
	290	* The 30-bit decrementing counter is read in 4 pieces.
	291	* Incorrect value may be read when the most significant bytes
	292	* are changing...
	293	*/
	294	} while (retry-- && (((last ^ count) & 0x3fff8000) \|\| last < count));
	295
	296	DBG("cnt0[%02X] cnt1[%02X] cnt2[%02X] cnt3[%02X]\n",
	297	cnt0, cnt1, cnt2, cnt3);
	298
	299	return count;
	300	}
	301
	302	/**
	303	* detect_pll_input_clock - Detect the PLL input clock in Hz.
	304	* @dma_base: for the port address
	305	* E.g. 16949000 on 33 MHz PCI bus, i.e. half of the PCI clock.
	306	*/
	307	static long __devinit detect_pll_input_clock(unsigned long dma_base)
	308	{
	309	long start_count, end_count;
	310	long pll_input;
	311	u8 scr1;
	312
	313	start_count = read_counter(dma_base);
	314
	315	/* Start the test mode */
	316	outb(0x01, dma_base + 0x01);
	317	scr1 = inb(dma_base + 0x03);
	318	DBG("scr1[%02X]\n", scr1);
	319	outb(scr1 \| 0x40, dma_base + 0x03);
	320
	321	/* Let the counter run for 10 ms. */
	322	mdelay(10);
	323
	324	end_count = read_counter(dma_base);
	325
	326	/* Stop the test mode */
327	outb(0x01, dma_base + 0x01);
328	scr1 = inb(dma_base + 0x03);
329	DBG("scr1[%02X]\n", scr1);
330	outb(scr1 & ~0x40, dma_base + 0x03);
331
332	/*
333	* Calculate the input clock in Hz
334	* (the clock counter is 30 bit wide and counts down)
335	*/
336	pll_input = ((start_count - end_count) & 0x3ffffff) * 100;
337
338	DBG("start[%ld] end[%ld]\n", start_count, end_count);
339
340	return pll_input;
341	}
342
1da177e4 LT	343	#ifdef CONFIG_PPC_PMAC
	344	static void __devinit apple_kiwi_init(struct pci_dev *pdev)
	345	{
	346	struct device_node *np = pci_device_to_OF_node(pdev);
	347	unsigned int class_rev = 0;
1da177e4 LT	348	u8 conf;
1da177e4 LT	349
55b61fec	350	if (np == NULL \|\| !of_device_is_compatible(np, "kiwi-root"))
1da177e4 LT	351	return;
	352
	353	pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class_rev);
	354	class_rev &= 0xff;
	355
	356	if (class_rev >= 0x03) {
	357	/* Setup chip magic config stuff (from darwin) */
47694bb8 SS	358	pci_read_config_byte (pdev, 0x40, &conf);
47694bb8 SS	359	pci_write_config_byte(pdev, 0x40, (conf \| 0x01));
1da177e4	360	}
1da177e4 LT	361	}
	362	#endif /* CONFIG_PPC_PMAC */
	363
	364	static unsigned int __devinit init_chipset_pdcnew(struct pci_dev dev, const char name)
	365	{
47694bb8 SS	366	unsigned long dma_base = pci_resource_start(dev, 4);
	367	unsigned long sec_dma_base = dma_base + 0x08;
	368	long pll_input, pll_output, ratio;
	369	int f, r;
	370	u8 pll_ctl0, pll_ctl1;
	371
1da177e4 LT	372	if (dev->resource[PCI_ROM_RESOURCE].start) {
	373	pci_write_config_dword(dev, PCI_ROM_ADDRESS,
	374	dev->resource[PCI_ROM_RESOURCE].start \| PCI_ROM_ADDRESS_ENABLE);
08f46de9 GKH	375	printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n", name,
08f46de9 GKH	376	(unsigned long)dev->resource[PCI_ROM_RESOURCE].start);
1da177e4 LT	377	}
	378
	379	#ifdef CONFIG_PPC_PMAC
	380	apple_kiwi_init(dev);
	381	#endif
	382
47694bb8 SS	383	/* Calculate the required PLL output frequency */
	384	switch(max_dma_rate(dev)) {
	385	case 4: /* it's 133 MHz for Ultra133 chips */
	386	pll_output = 133333333;
	387	break;
	388	case 3: /* and 100 MHz for Ultra100 chips */
	389	default:
	390	pll_output = 100000000;
	391	break;
	392	}
	393
	394	/*
	395	* Detect PLL input clock.
	396	* On some systems, where PCI bus is running at non-standard clock rate
	397	* (e.g. 25 or 40 MHz), we have to adjust the cycle time.
	398	* PDC20268 and newer chips employ PLL circuit to help correct timing
	399	* registers setting.
	400	*/
	401	pll_input = detect_pll_input_clock(dma_base);
	402	printk("%s: PLL input clock is %ld kHz\n", name, pll_input / 1000);
	403
	404	/* Sanity check */
	405	if (unlikely(pll_input < 5000000L \|\| pll_input > 70000000L)) {
	406	printk(KERN_ERR "%s: Bad PLL input clock %ld Hz, giving up!\n",
	407	name, pll_input);
	408	goto out;
	409	}
	410
	411	#ifdef DEBUG
	412	DBG("pll_output is %ld Hz\n", pll_output);
	413
	414	/* Show the current clock value of PLL control register
	415	* (maybe already configured by the BIOS)
	416	*/
	417	outb(0x02, sec_dma_base + 0x01);
	418	pll_ctl0 = inb(sec_dma_base + 0x03);
	419	outb(0x03, sec_dma_base + 0x01);
	420	pll_ctl1 = inb(sec_dma_base + 0x03);
	421
	422	DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
	423	#endif
	424
	425	/*
	426	* Calculate the ratio of F, R and NO
	427	* POUT = (F + 2) / (( R + 2) * NO)
	428	*/
	429	ratio = pll_output / (pll_input / 1000);
	430	if (ratio < 8600L) { /* 8.6x */
	431	/* Using NO = 0x01, R = 0x0d */
	432	r = 0x0d;
	433	} else if (ratio < 12900L) { /* 12.9x */
	434	/* Using NO = 0x01, R = 0x08 */
	435	r = 0x08;
	436	} else if (ratio < 16100L) { /* 16.1x */
	437	/* Using NO = 0x01, R = 0x06 */
	438	r = 0x06;
	439	} else if (ratio < 64000L) { /* 64x */
	440	r = 0x00;
	441	} else {
	442	/* Invalid ratio */
	443	printk(KERN_ERR "%s: Bad ratio %ld, giving up!\n", name, ratio);
	444	goto out;
	445	}
	446
447	f = (ratio * (r + 2)) / 1000 - 2;
448
449	DBG("F[%d] R[%d] ratio*1000[%ld]\n", f, r, ratio);
450
451	if (unlikely(f < 0 \|\| f > 127)) {
452	/* Invalid F */
453	printk(KERN_ERR "%s: F[%d] invalid!\n", name, f);
454	goto out;
455	}
456
457	pll_ctl0 = (u8) f;
458	pll_ctl1 = (u8) r;
459
460	DBG("Writing pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
461
462	outb(0x02, sec_dma_base + 0x01);
463	outb(pll_ctl0, sec_dma_base + 0x03);
464	outb(0x03, sec_dma_base + 0x01);
465	outb(pll_ctl1, sec_dma_base + 0x03);
466
467	/* Wait the PLL circuit to be stable */
468	mdelay(30);
469
470	#ifdef DEBUG
471	/*
472	* Show the current clock value of PLL control register
473	*/
474	outb(0x02, sec_dma_base + 0x01);
475	pll_ctl0 = inb(sec_dma_base + 0x03);
476	outb(0x03, sec_dma_base + 0x01);
477	pll_ctl1 = inb(sec_dma_base + 0x03);
478
479	DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
480	#endif
481
482	out:
1da177e4 LT	483	return dev->irq;
	484	}
	485
	486	static void __devinit init_hwif_pdc202new(ide_hwif_t *hwif)
	487	{
	488	hwif->autodma = 0;
	489
	490	hwif->tuneproc = &pdcnew_tune_drive;
	491	hwif->quirkproc = &pdcnew_quirkproc;
47694bb8 SS	492	hwif->speedproc = &pdcnew_tune_chipset;
47694bb8 SS	493	hwif->resetproc = &pdcnew_reset;
1da177e4 LT	494
	495	hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
	496
362ebd83	497	hwif->atapi_dma = 1;
18137207 BZ	498
18137207 BZ	499	hwif->ultra_mask = hwif->cds->udma_mask;
1da177e4 LT	500	hwif->mwdma_mask = 0x07;
1da177e4 LT	501
3706a872 AC	502	hwif->err_stops_fifo = 1;
3706a872 AC	503
1da177e4	504	hwif->ide_dma_check = &pdcnew_config_drive_xfer_rate;
47694bb8 SS	505
	506	if (!hwif->udma_four)
	507	hwif->udma_four = pdcnew_cable_detect(hwif) ? 0 : 1;
	508
1da177e4 LT	509	if (!noautodma)
	510	hwif->autodma = 1;
	511	hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
1da177e4 LT	512	}
	513
	514	static int __devinit init_setup_pdcnew(struct pci_dev dev, ide_pci_device_t d)
	515	{
	516	return ide_setup_pci_device(dev, d);
	517	}
	518
	519	static int __devinit init_setup_pdc20270(struct pci_dev *dev,
	520	ide_pci_device_t *d)
	521	{
	522	struct pci_dev *findev = NULL;
b1489009	523	int ret;
1da177e4 LT	524
	525	if ((dev->bus->self &&
	526	dev->bus->self->vendor == PCI_VENDOR_ID_DEC) &&
	527	(dev->bus->self->device == PCI_DEVICE_ID_DEC_21150)) {
	528	if (PCI_SLOT(dev->devfn) & 2)
	529	return -ENODEV;
	530	d->extra = 0;
b1489009	531	while ((findev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, findev)) != NULL) {
1da177e4 LT	532	if ((findev->vendor == dev->vendor) &&
	533	(findev->device == dev->device) &&
	534	(PCI_SLOT(findev->devfn) & 2)) {
	535	if (findev->irq != dev->irq) {
	536	findev->irq = dev->irq;
	537	}
b1489009 AC	538	ret = ide_setup_pci_devices(dev, findev, d);
	539	pci_dev_put(findev);
	540	return ret;
1da177e4 LT	541	}
	542	}
	543	}
	544	return ide_setup_pci_device(dev, d);
	545	}
	546
	547	static int __devinit init_setup_pdc20276(struct pci_dev *dev,
	548	ide_pci_device_t *d)
	549	{
	550	if ((dev->bus->self) &&
	551	(dev->bus->self->vendor == PCI_VENDOR_ID_INTEL) &&
	552	((dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960) \|\|
	553	(dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960RM))) {
	554	printk(KERN_INFO "ide: Skipping Promise PDC20276 "
	555	"attached to I2O RAID controller.\n");
	556	return -ENODEV;
	557	}
	558	return ide_setup_pci_device(dev, d);
	559	}
	560
	561	static ide_pci_device_t pdcnew_chipsets[] __devinitdata = {
	562	{ /* 0 */
	563	.name = "PDC20268",
	564	.init_setup = init_setup_pdcnew,
	565	.init_chipset = init_chipset_pdcnew,
	566	.init_hwif = init_hwif_pdc202new,
	567	.channels = 2,
	568	.autodma = AUTODMA,
	569	.bootable = OFF_BOARD,
18137207	570	.udma_mask = 0x3f, /* udma0-5 */
1da177e4 LT	571	},{ /* 1 */
	572	.name = "PDC20269",
	573	.init_setup = init_setup_pdcnew,
	574	.init_chipset = init_chipset_pdcnew,
	575	.init_hwif = init_hwif_pdc202new,
	576	.channels = 2,
	577	.autodma = AUTODMA,
	578	.bootable = OFF_BOARD,
18137207	579	.udma_mask = 0x7f, /* udma0-6*/
1da177e4 LT	580	},{ /* 2 */
	581	.name = "PDC20270",
	582	.init_setup = init_setup_pdc20270,
	583	.init_chipset = init_chipset_pdcnew,
	584	.init_hwif = init_hwif_pdc202new,
	585	.channels = 2,
	586	.autodma = AUTODMA,
1da177e4	587	.bootable = OFF_BOARD,
18137207	588	.udma_mask = 0x3f, /* udma0-5 */
1da177e4 LT	589	},{ /* 3 */
	590	.name = "PDC20271",
	591	.init_setup = init_setup_pdcnew,
	592	.init_chipset = init_chipset_pdcnew,
	593	.init_hwif = init_hwif_pdc202new,
	594	.channels = 2,
	595	.autodma = AUTODMA,
	596	.bootable = OFF_BOARD,
18137207	597	.udma_mask = 0x7f, /* udma0-6*/
1da177e4 LT	598	},{ /* 4 */
	599	.name = "PDC20275",
	600	.init_setup = init_setup_pdcnew,
	601	.init_chipset = init_chipset_pdcnew,
	602	.init_hwif = init_hwif_pdc202new,
	603	.channels = 2,
	604	.autodma = AUTODMA,
	605	.bootable = OFF_BOARD,
18137207	606	.udma_mask = 0x7f, /* udma0-6*/
1da177e4 LT	607	},{ /* 5 */
	608	.name = "PDC20276",
	609	.init_setup = init_setup_pdc20276,
	610	.init_chipset = init_chipset_pdcnew,
	611	.init_hwif = init_hwif_pdc202new,
	612	.channels = 2,
	613	.autodma = AUTODMA,
1da177e4	614	.bootable = OFF_BOARD,
18137207	615	.udma_mask = 0x7f, /* udma0-6*/
1da177e4 LT	616	},{ /* 6 */
	617	.name = "PDC20277",
	618	.init_setup = init_setup_pdcnew,
	619	.init_chipset = init_chipset_pdcnew,
	620	.init_hwif = init_hwif_pdc202new,
	621	.channels = 2,
	622	.autodma = AUTODMA,
	623	.bootable = OFF_BOARD,
18137207	624	.udma_mask = 0x7f, /* udma0-6*/
1da177e4 LT	625	}
	626	};
	627
	628	/**
	629	* pdc202new_init_one - called when a pdc202xx is found
	630	* @dev: the pdc202new device
	631	* @id: the matching pci id
	632	*
	633	* Called when the PCI registration layer (or the IDE initialization)
	634	* finds a device matching our IDE device tables.
	635	*/
	636
	637	static int __devinit pdc202new_init_one(struct pci_dev dev, const struct pci_device_id id)
	638	{
	639	ide_pci_device_t *d = &pdcnew_chipsets[id->driver_data];
	640
	641	return d->init_setup(dev, d);
	642	}
	643
	644	static struct pci_device_id pdc202new_pci_tbl[] = {
	645	{ PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20268, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
	646	{ PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20269, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
	647	{ PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20270, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
	648	{ PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20271, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
	649	{ PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20275, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
	650	{ PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20276, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
	651	{ PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20277, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6},
	652	{ 0, },
	653	};
	654	MODULE_DEVICE_TABLE(pci, pdc202new_pci_tbl);
	655
	656	static struct pci_driver driver = {
	657	.name = "Promise_IDE",
	658	.id_table = pdc202new_pci_tbl,
	659	.probe = pdc202new_init_one,
	660	};
	661
82ab1eec	662	static int __init pdc202new_ide_init(void)
1da177e4 LT	663	{
	664	return ide_pci_register_driver(&driver);
	665	}
	666
	667	module_init(pdc202new_ide_init);
	668
	669	MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
	670	MODULE_DESCRIPTION("PCI driver module for Promise PDC20268 and higher");
	671	MODULE_LICENSE("GPL");