[linux-2.6-block.git] / drivers / ide / pci / opti621.c

/*
 *  Copyright (C) 1996-1998  Linus Torvalds & authors (see below)
 */

/*
 * Authors:
 * Jaromir Koutek <miri@punknet.cz>,
 * Jan Harkes <jaharkes@cwi.nl>,
 * Mark Lord <mlord@pobox.com>
 * Some parts of code are from ali14xx.c and from rz1000.c.
 *
 * OPTi is trademark of OPTi, Octek is trademark of Octek.
 *
 * I used docs from OPTi databook, from ftp.opti.com, file 9123-0002.ps
 * and disassembled/traced setupvic.exe (DOS program).
 * It increases kernel code about 2 kB.
 * I don't have this card no more, but I hope I can get some in case
 * of needed development.
 * My card is Octek PIDE 1.01 (on card) or OPTiViC (program).
 * It has a place for a secondary connector in circuit, but nothing
 * is there. Also BIOS says no address for
 * secondary controller (see bellow in ide_init_opti621).
 * I've only tested this on my system, which only has one disk.
 * It's Western Digital WDAC2850, with PIO mode 3. The PCI bus
 * is at 20 MHz (I have DX2/80, I tried PCI at 40, but I got random
 * lockups). I tried the OCTEK double speed CD-ROM and
 * it does not work! But I can't boot DOS also, so it's probably
 * hardware fault. I have connected Conner 80MB, the Seagate 850MB (no
 * problems) and Seagate 1GB (as slave, WD as master). My experiences
 * with the third, 1GB drive: I got 3MB/s (hdparm), but sometimes
 * it slows to about 100kB/s! I don't know why and I have
 * not this drive now, so I can't try it again.
 * I write this driver because I lost the paper ("manual") with
 * settings of jumpers on the card and I have to boot Linux with
 * Loadlin except LILO, cause I have to run the setupvic.exe program
 * already or I get disk errors (my test: rpm -Vf
 * /usr/X11R6/bin/XF86_SVGA - or any big file).
 * Some numbers from hdparm -t /dev/hda:
 * Timing buffer-cache reads:   32 MB in  3.02 seconds =10.60 MB/sec
 * Timing buffered disk reads:  16 MB in  5.52 seconds = 2.90 MB/sec
 * I have 4 Megs/s before, but I don't know why (maybe changes
 * in hdparm test).
 * After release of 0.1, I got some successful reports, so it might work.
 *
 * The main problem with OPTi is that some timings for master
 * and slave must be the same. For example, if you have master
 * PIO 3 and slave PIO 0, driver have to set some timings of
 * master for PIO 0. Second problem is that opti621_set_pio_mode
 * got only one drive to set, but have to set both drives.
 * This is solved in compute_pios. If you don't set
 * the second drive, compute_pios use ide_get_best_pio_mode
 * for autoselect mode (you can change it to PIO 0, if you want).
 * If you then set the second drive to another PIO, the old value
 * (automatically selected) will be overrided by yours.
 * There is a 25/33MHz switch in configuration
 * register, but driver is written for use at any frequency.
 *
 * Version 0.1, Nov 8, 1996
 * by Jaromir Koutek, for 2.1.8.
 * Initial version of driver.
 *
 * Version 0.2
 * Number 0.2 skipped.
 *
 * Version 0.3, Nov 29, 1997
 * by Mark Lord (probably), for 2.1.68
 * Updates for use with new IDE block driver.
 *
 * Version 0.4, Dec 14, 1997
 * by Jan Harkes
 * Fixed some errors and cleaned the code.
 *
 * Version 0.5, Jan 2, 1998
 * by Jaromir Koutek
 * Updates for use with (again) new IDE block driver.
 * Update of documentation.
 *
 * Version 0.6, Jan 2, 1999
 * by Jaromir Koutek
 * Reversed to version 0.3 of the driver, because
 * 0.5 doesn't work.
 */

#define OPTI621_DEBUG		/* define for debug messages */

#include <linux/types.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/hdreg.h>
#include <linux/ide.h>

#include <asm/io.h>

//#define OPTI621_MAX_PIO 3
/* In fact, I do not have any PIO 4 drive
 * (address: 25 ns, data: 70 ns, recovery: 35 ns),
 * but OPTi 82C621 is programmable and it can do (minimal values):
 * on 40MHz PCI bus (pulse 25 ns):
 *  address: 25 ns, data: 25 ns, recovery: 50 ns;
 * on 20MHz PCI bus (pulse 50 ns):
 *  address: 50 ns, data: 50 ns, recovery: 100 ns.
 */

#define READ_REG 0	/* index of Read cycle timing register */
#define WRITE_REG 1	/* index of Write cycle timing register */
#define CNTRL_REG 3	/* index of Control register */
#define STRAP_REG 5	/* index of Strap register */
#define MISC_REG 6	/* index of Miscellaneous register */

static int reg_base;

#define PIO_NOT_EXIST 254
#define PIO_DONT_KNOW 255

static DEFINE_SPINLOCK(opti621_lock);

/* there are stored pio numbers from other calls of opti621_set_pio_mode */
static void compute_pios(ide_drive_t *drive, const u8 pio)
/* Store values into drive->drive_data
 *	second_contr - 0 for primary controller, 1 for secondary
 *	slave_drive - 0 -> pio is for master, 1 -> pio is for slave
 *	pio - PIO mode for selected drive (for other we don't know)
 */
{
	int d;
	ide_hwif_t *hwif = HWIF(drive);

	drive->drive_data = pio;

	for (d = 0; d < 2; ++d) {
		drive = &hwif->drives[d];
		if (drive->present) {
			if (drive->drive_data == PIO_DONT_KNOW)
				drive->drive_data = ide_get_best_pio_mode(drive, 255, 3);
#ifdef OPTI621_DEBUG
			printk("%s: Selected PIO mode %d\n",
				drive->name, drive->drive_data);
#endif
		} else {
			drive->drive_data = PIO_NOT_EXIST;
		}
	}
}

static int cmpt_clk(int time, int bus_speed)
/* Returns (rounded up) time in clocks for time in ns,
 * with bus_speed in MHz.
 * Example: bus_speed = 40 MHz, time = 80 ns
 * 1000/40 = 25 ns (clk value),
 * 80/25 = 3.2, rounded up to 4 (I hope ;-)).
 * Use idebus=xx to select right frequency.
 */
{
	return ((time*bus_speed+999)/1000);
}

/* Write value to register reg, base of register
 * is at reg_base (0x1f0 primary, 0x170 secondary,
 * if not changed by PCI configuration).
 * This is from setupvic.exe program.
 */
static void write_reg(u8 value, int reg)
{
	inw(reg_base + 1);
	inw(reg_base + 1);
	outb(3, reg_base + 2);
	outb(value, reg_base + reg);
	outb(0x83, reg_base + 2);
}

/* Read value from register reg, base of register
 * is at reg_base (0x1f0 primary, 0x170 secondary,
 * if not changed by PCI configuration).
 * This is from setupvic.exe program.
 */
static u8 read_reg(int reg)
{
	u8 ret = 0;

	inw(reg_base + 1);
	inw(reg_base + 1);
	outb(3, reg_base + 2);
	ret = inb(reg_base + reg);
	outb(0x83, reg_base + 2);

	return ret;
}

typedef struct pio_clocks_s {
	int	address_time;	/* Address setup (clocks) */
	int	data_time;	/* Active/data pulse (clocks) */
	int	recovery_time;	/* Recovery time (clocks) */
} pio_clocks_t;

static void compute_clocks(int pio, pio_clocks_t *clks, int bus_speed)
{
	if (pio != PIO_NOT_EXIST) {
		int adr_setup, data_pls;

		adr_setup = ide_pio_timings[pio].setup_time;
		data_pls = ide_pio_timings[pio].active_time;
		clks->address_time = cmpt_clk(adr_setup, bus_speed);
		clks->data_time = cmpt_clk(data_pls, bus_speed);
		clks->recovery_time = cmpt_clk(ide_pio_timings[pio].cycle_time
			- adr_setup-data_pls, bus_speed);
		if (clks->address_time < 1)
			clks->address_time = 1;
		if (clks->address_time > 4)
			clks->address_time = 4;
		if (clks->data_time < 1)
			clks->data_time = 1;
		if (clks->data_time > 16)
			clks->data_time = 16;
		if (clks->recovery_time < 2)
			clks->recovery_time = 2;
		if (clks->recovery_time > 17)
			clks->recovery_time = 17;
	} else {
		clks->address_time = 1;
		clks->data_time = 1;
		clks->recovery_time = 2;
		/* minimal values */
	}
}

static void opti621_set_pio_mode(ide_drive_t *drive, const u8 pio)
{
	/* primary and secondary drives share some registers,
	 * so we have to program both drives
	 */
	unsigned long flags;
	u8 pio1 = 0, pio2 = 0;
	pio_clocks_t first, second;
	int ax, drdy;
	u8 cycle1, cycle2, misc, clk;
	ide_hwif_t *hwif = HWIF(drive);

	/* sets drive->drive_data for both drives */
	compute_pios(drive, pio);
	pio1 = hwif->drives[0].drive_data;
	pio2 = hwif->drives[1].drive_data;

	spin_lock_irqsave(&opti621_lock, flags);

	reg_base = hwif->io_ports.data_addr;

	/* allow Register-B */
	outb(0xc0, reg_base + CNTRL_REG);
	/* hmm, setupvic.exe does this ;-) */
	outb(0xff, reg_base + 5);
	/* if reads 0xff, adapter not exist? */
	(void)inb(reg_base + CNTRL_REG);
	/* if reads 0xc0, no interface exist? */
	read_reg(CNTRL_REG);

	/* check CLK speed */
	clk = read_reg(STRAP_REG) & 1;

	printk(KERN_INFO "%s: CLK = %d MHz\n", hwif->name, clk ? 25 : 33);

	compute_clocks(pio1, &first,  clk ? 25 : 33);
	compute_clocks(pio2, &second, clk ? 25 : 33);

	/* ax = max(a1,a2) */
	ax = (first.address_time < second.address_time) ? second.address_time : first.address_time;

	drdy = 2; /* DRDY is default 2 (by OPTi Databook) */

	cycle1 = ((first.data_time-1)<<4)  | (first.recovery_time-2);
	cycle2 = ((second.data_time-1)<<4) | (second.recovery_time-2);

	misc = ((ax - 1) << 4) | ((drdy - 2) << 1);

#ifdef OPTI621_DEBUG
	printk("%s: master: address: %d, data: %d, "
		"recovery: %d, drdy: %d [clk]\n",
		hwif->name, ax, first.data_time,
		first.recovery_time, drdy);
	printk("%s: slave:  address: %d, data: %d, "
		"recovery: %d, drdy: %d [clk]\n",
		hwif->name, ax, second.data_time,
		second.recovery_time, drdy);
#endif

	/* program primary drive */
	/* select Index-0 for Register-A */
	write_reg(0, MISC_REG);
	/* set read cycle timings */
	write_reg(cycle1, READ_REG);
	/* set write cycle timings */
	write_reg(cycle1, WRITE_REG);

	/* program secondary drive */
	/* select Index-1 for Register-B */
	write_reg(1, MISC_REG);
	/* set read cycle timings */
	write_reg(cycle2, READ_REG);
	/* set write cycle timings */
	write_reg(cycle2, WRITE_REG);

	/* use Register-A for drive 0 */
	/* use Register-B for drive 1 */
	write_reg(0x85, CNTRL_REG);

	/* set address setup, DRDY timings,   */
	/*  and read prefetch for both drives */
	write_reg(misc, MISC_REG);

	spin_unlock_irqrestore(&opti621_lock, flags);
}

static void __devinit opti621_port_init_devs(ide_hwif_t *hwif)
{
	hwif->drives[0].drive_data = PIO_DONT_KNOW;
	hwif->drives[1].drive_data = PIO_DONT_KNOW;
}

static const struct ide_port_ops opti621_port_ops = {
	.port_init_devs		= opti621_port_init_devs,
	.set_pio_mode		= opti621_set_pio_mode,
};

static const struct ide_port_info opti621_chipsets[] __devinitdata = {
	{	/* 0 */
		.name		= "OPTI621",
		.enablebits	= { {0x45, 0x80, 0x00}, {0x40, 0x08, 0x00} },
		.port_ops	= &opti621_port_ops,
		.host_flags	= IDE_HFLAG_NO_DMA,
		.pio_mask	= ATA_PIO3,
	}, {	/* 1 */
		.name		= "OPTI621X",
		.enablebits	= { {0x45, 0x80, 0x00}, {0x40, 0x08, 0x00} },
		.port_ops	= &opti621_port_ops,
		.host_flags	= IDE_HFLAG_NO_DMA,
		.pio_mask	= ATA_PIO3,
	}
};

static int __devinit opti621_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	return ide_setup_pci_device(dev, &opti621_chipsets[id->driver_data]);
}

static const struct pci_device_id opti621_pci_tbl[] = {
	{ PCI_VDEVICE(OPTI, PCI_DEVICE_ID_OPTI_82C621), 0 },
	{ PCI_VDEVICE(OPTI, PCI_DEVICE_ID_OPTI_82C825), 1 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, opti621_pci_tbl);

static struct pci_driver driver = {
	.name		= "Opti621_IDE",
	.id_table	= opti621_pci_tbl,
	.probe		= opti621_init_one,
};

static int __init opti621_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}

module_init(opti621_ide_init);

MODULE_AUTHOR("Jaromir Koutek, Jan Harkes, Mark Lord");
MODULE_DESCRIPTION("PCI driver module for Opti621 IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	* Copyright (C) 1996-1998 Linus Torvalds & authors (see below)
	3	*/
	4
	5	/*
	6	* Authors:
	7	* Jaromir Koutek <miri@punknet.cz>,
	8	* Jan Harkes <jaharkes@cwi.nl>,
	9	* Mark Lord <mlord@pobox.com>
	10	* Some parts of code are from ali14xx.c and from rz1000.c.
	11	*
	12	* OPTi is trademark of OPTi, Octek is trademark of Octek.
	13	*
	14	* I used docs from OPTi databook, from ftp.opti.com, file 9123-0002.ps
	15	* and disassembled/traced setupvic.exe (DOS program).
	16	* It increases kernel code about 2 kB.
	17	* I don't have this card no more, but I hope I can get some in case
	18	* of needed development.
	19	* My card is Octek PIDE 1.01 (on card) or OPTiViC (program).
	20	* It has a place for a secondary connector in circuit, but nothing
	21	* is there. Also BIOS says no address for
	22	* secondary controller (see bellow in ide_init_opti621).
	23	* I've only tested this on my system, which only has one disk.
	24	* It's Western Digital WDAC2850, with PIO mode 3. The PCI bus
	25	* is at 20 MHz (I have DX2/80, I tried PCI at 40, but I got random
	26	* lockups). I tried the OCTEK double speed CD-ROM and
	27	* it does not work! But I can't boot DOS also, so it's probably
	28	* hardware fault. I have connected Conner 80MB, the Seagate 850MB (no
	29	* problems) and Seagate 1GB (as slave, WD as master). My experiences
	30	* with the third, 1GB drive: I got 3MB/s (hdparm), but sometimes
	31	* it slows to about 100kB/s! I don't know why and I have
	32	* not this drive now, so I can't try it again.
	33	* I write this driver because I lost the paper ("manual") with
	34	* settings of jumpers on the card and I have to boot Linux with
	35	* Loadlin except LILO, cause I have to run the setupvic.exe program
	36	* already or I get disk errors (my test: rpm -Vf
	37	* /usr/X11R6/bin/XF86_SVGA - or any big file).
	38	* Some numbers from hdparm -t /dev/hda:
	39	* Timing buffer-cache reads: 32 MB in 3.02 seconds =10.60 MB/sec
	40	* Timing buffered disk reads: 16 MB in 5.52 seconds = 2.90 MB/sec
	41	* I have 4 Megs/s before, but I don't know why (maybe changes
	42	* in hdparm test).
	43	* After release of 0.1, I got some successful reports, so it might work.
	44	*
	45	* The main problem with OPTi is that some timings for master
	46	* and slave must be the same. For example, if you have master
	47	* PIO 3 and slave PIO 0, driver have to set some timings of
26bcb879	48	* master for PIO 0. Second problem is that opti621_set_pio_mode
1da177e4 LT	49	* got only one drive to set, but have to set both drives.
	50	* This is solved in compute_pios. If you don't set
	51	* the second drive, compute_pios use ide_get_best_pio_mode
	52	* for autoselect mode (you can change it to PIO 0, if you want).
	53	* If you then set the second drive to another PIO, the old value
	54	* (automatically selected) will be overrided by yours.
	55	* There is a 25/33MHz switch in configuration
73f1ad86	56	* register, but driver is written for use at any frequency.
1da177e4 LT	57	*
1da177e4 LT	58	* Version 0.1, Nov 8, 1996
4eb68a25	59	* by Jaromir Koutek, for 2.1.8.
1da177e4	60	* Initial version of driver.
4eb68a25	61	*
1da177e4 LT	62	* Version 0.2
	63	* Number 0.2 skipped.
	64	*
	65	* Version 0.3, Nov 29, 1997
	66	* by Mark Lord (probably), for 2.1.68
	67	* Updates for use with new IDE block driver.
	68	*
	69	* Version 0.4, Dec 14, 1997
	70	* by Jan Harkes
	71	* Fixed some errors and cleaned the code.
	72	*
	73	* Version 0.5, Jan 2, 1998
	74	* by Jaromir Koutek
	75	* Updates for use with (again) new IDE block driver.
	76	* Update of documentation.
4eb68a25	77	*
1da177e4 LT	78	* Version 0.6, Jan 2, 1999
	79	* by Jaromir Koutek
	80	* Reversed to version 0.3 of the driver, because
	81	* 0.5 doesn't work.
	82	*/
	83
1da177e4 LT	84	#define OPTI621_DEBUG /* define for debug messages */
	85
	86	#include <linux/types.h>
	87	#include <linux/module.h>
	88	#include <linux/kernel.h>
1da177e4 LT	89	#include <linux/pci.h>
	90	#include <linux/hdreg.h>
	91	#include <linux/ide.h>
	92
	93	#include <asm/io.h>
	94
26bcb879	95	//#define OPTI621_MAX_PIO 3
1da177e4 LT	96	/* In fact, I do not have any PIO 4 drive
	97	* (address: 25 ns, data: 70 ns, recovery: 35 ns),
	98	* but OPTi 82C621 is programmable and it can do (minimal values):
	99	* on 40MHz PCI bus (pulse 25 ns):
	100	* address: 25 ns, data: 25 ns, recovery: 50 ns;
	101	* on 20MHz PCI bus (pulse 50 ns):
	102	* address: 50 ns, data: 50 ns, recovery: 100 ns.
	103	*/
	104
1da177e4 LT	105	#define READ_REG 0 /* index of Read cycle timing register */
	106	#define WRITE_REG 1 /* index of Write cycle timing register */
	107	#define CNTRL_REG 3 /* index of Control register */
	108	#define STRAP_REG 5 /* index of Strap register */
	109	#define MISC_REG 6 /* index of Miscellaneous register */
	110
	111	static int reg_base;
	112
	113	#define PIO_NOT_EXIST 254
	114	#define PIO_DONT_KNOW 255
	115
e65dde71 BZ	116	static DEFINE_SPINLOCK(opti621_lock);
e65dde71 BZ	117
26bcb879 BZ	118	/* there are stored pio numbers from other calls of opti621_set_pio_mode */
26bcb879 BZ	119	static void compute_pios(ide_drive_t *drive, const u8 pio)
1da177e4 LT	120	/* Store values into drive->drive_data
	121	* second_contr - 0 for primary controller, 1 for secondary
	122	* slave_drive - 0 -> pio is for master, 1 -> pio is for slave
	123	* pio - PIO mode for selected drive (for other we don't know)
	124	*/
	125	{
	126	int d;
	127	ide_hwif_t *hwif = HWIF(drive);
	128
26bcb879 BZ	129	drive->drive_data = pio;
26bcb879 BZ	130
1da177e4 LT	131	for (d = 0; d < 2; ++d) {
	132	drive = &hwif->drives[d];
	133	if (drive->present) {
	134	if (drive->drive_data == PIO_DONT_KNOW)
26bcb879	135	drive->drive_data = ide_get_best_pio_mode(drive, 255, 3);
1da177e4 LT	136	#ifdef OPTI621_DEBUG
	137	printk("%s: Selected PIO mode %d\n",
	138	drive->name, drive->drive_data);
	139	#endif
	140	} else {
	141	drive->drive_data = PIO_NOT_EXIST;
	142	}
	143	}
	144	}
	145
	146	static int cmpt_clk(int time, int bus_speed)
	147	/* Returns (rounded up) time in clocks for time in ns,
	148	* with bus_speed in MHz.
	149	* Example: bus_speed = 40 MHz, time = 80 ns
	150	* 1000/40 = 25 ns (clk value),
	151	* 80/25 = 3.2, rounded up to 4 (I hope ;-)).
	152	* Use idebus=xx to select right frequency.
	153	*/
	154	{
	155	return ((time*bus_speed+999)/1000);
	156	}
	157
1da177e4 LT	158	/* Write value to register reg, base of register
	159	* is at reg_base (0x1f0 primary, 0x170 secondary,
	160	* if not changed by PCI configuration).
	161	* This is from setupvic.exe program.
	162	*/
0ecdca26	163	static void write_reg(u8 value, int reg)
1da177e4	164	{
0ecdca26 BZ	165	inw(reg_base + 1);
	166	inw(reg_base + 1);
	167	outb(3, reg_base + 2);
	168	outb(value, reg_base + reg);
	169	outb(0x83, reg_base + 2);
1da177e4 LT	170	}
1da177e4 LT	171
1da177e4 LT	172	/* Read value from register reg, base of register
	173	* is at reg_base (0x1f0 primary, 0x170 secondary,
	174	* if not changed by PCI configuration).
	175	* This is from setupvic.exe program.
	176	*/
0ecdca26	177	static u8 read_reg(int reg)
1da177e4 LT	178	{
	179	u8 ret = 0;
	180
0ecdca26 BZ	181	inw(reg_base + 1);
	182	inw(reg_base + 1);
	183	outb(3, reg_base + 2);
	184	ret = inb(reg_base + reg);
	185	outb(0x83, reg_base + 2);
	186
1da177e4 LT	187	return ret;
	188	}
	189
	190	typedef struct pio_clocks_s {
	191	int address_time; /* Address setup (clocks) */
	192	int data_time; /* Active/data pulse (clocks) */
	193	int recovery_time; /* Recovery time (clocks) */
	194	} pio_clocks_t;
	195
21bd33a6	196	static void compute_clocks(int pio, pio_clocks_t *clks, int bus_speed)
1da177e4	197	{
4eb68a25 PC	198	if (pio != PIO_NOT_EXIST) {
4eb68a25 PC	199	int adr_setup, data_pls;
1da177e4	200
4eb68a25 PC	201	adr_setup = ide_pio_timings[pio].setup_time;
	202	data_pls = ide_pio_timings[pio].active_time;
	203	clks->address_time = cmpt_clk(adr_setup, bus_speed);
	204	clks->data_time = cmpt_clk(data_pls, bus_speed);
	205	clks->recovery_time = cmpt_clk(ide_pio_timings[pio].cycle_time
	206	- adr_setup-data_pls, bus_speed);
	207	if (clks->address_time < 1)
	208	clks->address_time = 1;
	209	if (clks->address_time > 4)
	210	clks->address_time = 4;
	211	if (clks->data_time < 1)
	212	clks->data_time = 1;
	213	if (clks->data_time > 16)
	214	clks->data_time = 16;
	215	if (clks->recovery_time < 2)
	216	clks->recovery_time = 2;
	217	if (clks->recovery_time > 17)
	218	clks->recovery_time = 17;
1da177e4 LT	219	} else {
	220	clks->address_time = 1;
	221	clks->data_time = 1;
	222	clks->recovery_time = 2;
	223	/* minimal values */
	224	}
1da177e4 LT	225	}
1da177e4 LT	226
26bcb879	227	static void opti621_set_pio_mode(ide_drive_t *drive, const u8 pio)
1da177e4 LT	228	{
	229	/* primary and secondary drives share some registers,
	230	* so we have to program both drives
	231	*/
	232	unsigned long flags;
	233	u8 pio1 = 0, pio2 = 0;
	234	pio_clocks_t first, second;
	235	int ax, drdy;
21bd33a6	236	u8 cycle1, cycle2, misc, clk;
1da177e4 LT	237	ide_hwif_t *hwif = HWIF(drive);
	238
	239	/* sets drive->drive_data for both drives */
	240	compute_pios(drive, pio);
4eb68a25 PC	241	pio1 = hwif->drives[0].drive_data;
4eb68a25 PC	242	pio2 = hwif->drives[1].drive_data;
1da177e4	243
21bd33a6 BZ	244	spin_lock_irqsave(&opti621_lock, flags);
	245
	246	reg_base = hwif->io_ports.data_addr;
	247
	248	/* allow Register-B */
	249	outb(0xc0, reg_base + CNTRL_REG);
	250	/* hmm, setupvic.exe does this ;-) */
	251	outb(0xff, reg_base + 5);
	252	/* if reads 0xff, adapter not exist? */
	253	(void)inb(reg_base + CNTRL_REG);
	254	/* if reads 0xc0, no interface exist? */
	255	read_reg(CNTRL_REG);
	256
	257	/* check CLK speed */
	258	clk = read_reg(STRAP_REG) & 1;
	259
	260	printk(KERN_INFO "%s: CLK = %d MHz\n", hwif->name, clk ? 25 : 33);
	261
	262	compute_clocks(pio1, &first, clk ? 25 : 33);
	263	compute_clocks(pio2, &second, clk ? 25 : 33);
1da177e4 LT	264
	265	/* ax = max(a1,a2) */
	266	ax = (first.address_time < second.address_time) ? second.address_time : first.address_time;
	267
	268	drdy = 2; /* DRDY is default 2 (by OPTi Databook) */
	269
	270	cycle1 = ((first.data_time-1)<<4) \| (first.recovery_time-2);
	271	cycle2 = ((second.data_time-1)<<4) \| (second.recovery_time-2);
62128b2c BZ	272
62128b2c BZ	273	misc = ((ax - 1) << 4) \| ((drdy - 2) << 1);
1da177e4 LT	274
	275	#ifdef OPTI621_DEBUG
	276	printk("%s: master: address: %d, data: %d, "
	277	"recovery: %d, drdy: %d [clk]\n",
	278	hwif->name, ax, first.data_time,
	279	first.recovery_time, drdy);
	280	printk("%s: slave: address: %d, data: %d, "
	281	"recovery: %d, drdy: %d [clk]\n",
	282	hwif->name, ax, second.data_time,
	283	second.recovery_time, drdy);
	284	#endif
	285
1da177e4	286	/* program primary drive */
0ecdca26 BZ	287	/* select Index-0 for Register-A */
	288	write_reg(0, MISC_REG);
	289	/* set read cycle timings */
	290	write_reg(cycle1, READ_REG);
	291	/* set write cycle timings */
	292	write_reg(cycle1, WRITE_REG);
1da177e4 LT	293
1da177e4 LT	294	/* program secondary drive */
0ecdca26 BZ	295	/* select Index-1 for Register-B */
	296	write_reg(1, MISC_REG);
	297	/* set read cycle timings */
	298	write_reg(cycle2, READ_REG);
	299	/* set write cycle timings */
	300	write_reg(cycle2, WRITE_REG);
1da177e4 LT	301
	302	/* use Register-A for drive 0 */
	303	/* use Register-B for drive 1 */
0ecdca26	304	write_reg(0x85, CNTRL_REG);
1da177e4 LT	305
	306	/* set address setup, DRDY timings, */
	307	/* and read prefetch for both drives */
0ecdca26	308	write_reg(misc, MISC_REG);
1da177e4	309
e65dde71	310	spin_unlock_irqrestore(&opti621_lock, flags);
1da177e4 LT	311	}
1da177e4 LT	312
1f2cf8b0 BZ	313	static void __devinit opti621_port_init_devs(ide_hwif_t *hwif)
	314	{
	315	hwif->drives[0].drive_data = PIO_DONT_KNOW;
	316	hwif->drives[1].drive_data = PIO_DONT_KNOW;
	317	}
	318
ac95beed BZ	319	static const struct ide_port_ops opti621_port_ops = {
	320	.port_init_devs = opti621_port_init_devs,
	321	.set_pio_mode = opti621_set_pio_mode,
	322	};
1da177e4	323
85620436	324	static const struct ide_port_info opti621_chipsets[] __devinitdata = {
1da177e4 LT	325	{ /* 0 */
1da177e4 LT	326	.name = "OPTI621",
4eb68a25	327	.enablebits = { {0x45, 0x80, 0x00}, {0x40, 0x08, 0x00} },
ac95beed	328	.port_ops = &opti621_port_ops,
f3610376	329	.host_flags = IDE_HFLAG_NO_DMA,
4099d143	330	.pio_mask = ATA_PIO3,
4eb68a25	331	}, { /* 1 */
1da177e4	332	.name = "OPTI621X",
4eb68a25	333	.enablebits = { {0x45, 0x80, 0x00}, {0x40, 0x08, 0x00} },
ac95beed	334	.port_ops = &opti621_port_ops,
f3610376	335	.host_flags = IDE_HFLAG_NO_DMA,
4099d143	336	.pio_mask = ATA_PIO3,
1da177e4 LT	337	}
	338	};
	339
	340	static int __devinit opti621_init_one(struct pci_dev dev, const struct pci_device_id id)
	341	{
	342	return ide_setup_pci_device(dev, &opti621_chipsets[id->driver_data]);
	343	}
	344
9cbcc5e3 BZ	345	static const struct pci_device_id opti621_pci_tbl[] = {
	346	{ PCI_VDEVICE(OPTI, PCI_DEVICE_ID_OPTI_82C621), 0 },
	347	{ PCI_VDEVICE(OPTI, PCI_DEVICE_ID_OPTI_82C825), 1 },
1da177e4 LT	348	{ 0, },
	349	};
	350	MODULE_DEVICE_TABLE(pci, opti621_pci_tbl);
	351
	352	static struct pci_driver driver = {
	353	.name = "Opti621_IDE",
	354	.id_table = opti621_pci_tbl,
	355	.probe = opti621_init_one,
	356	};
	357
82ab1eec	358	static int __init opti621_ide_init(void)
1da177e4 LT	359	{
	360	return ide_pci_register_driver(&driver);
	361	}
	362
	363	module_init(opti621_ide_init);
	364
	365	MODULE_AUTHOR("Jaromir Koutek, Jan Harkes, Mark Lord");
	366	MODULE_DESCRIPTION("PCI driver module for Opti621 IDE");
	367	MODULE_LICENSE("GPL");