Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Copyright (C) 1997-1998 Mark Lord <mlord@pobox.com> |
3 | * Copyright (C) 1998 Eddie C. Dost <ecd@skynet.be> | |
4 | * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org> | |
5 | * Copyright (C) 2004 Grant Grundler <grundler at parisc-linux.org> | |
6 | * | |
7 | * Inspired by an earlier effort from David S. Miller <davem@redhat.com> | |
8 | */ | |
9 | ||
1da177e4 LT |
10 | #include <linux/module.h> |
11 | #include <linux/types.h> | |
12 | #include <linux/kernel.h> | |
1da177e4 | 13 | #include <linux/interrupt.h> |
1da177e4 LT |
14 | #include <linux/hdreg.h> |
15 | #include <linux/pci.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/ide.h> | |
18 | #include <linux/init.h> | |
19 | ||
20 | #include <asm/io.h> | |
21 | ||
22 | #ifdef CONFIG_SUPERIO | |
23 | /* SUPERIO 87560 is a PoS chip that NatSem denies exists. | |
24 | * Unfortunately, it's built-in on all Astro-based PA-RISC workstations | |
25 | * which use the integrated NS87514 cell for CD-ROM support. | |
26 | * i.e we have to support for CD-ROM installs. | |
27 | * See drivers/parisc/superio.c for more gory details. | |
28 | */ | |
29 | #include <asm/superio.h> | |
30 | ||
31 | static unsigned long superio_ide_status[2]; | |
32 | static unsigned long superio_ide_select[2]; | |
33 | static unsigned long superio_ide_dma_status[2]; | |
34 | ||
35 | #define SUPERIO_IDE_MAX_RETRIES 25 | |
36 | ||
37 | /* Because of a defect in Super I/O, all reads of the PCI DMA status | |
38 | * registers, IDE status register and the IDE select register need to be | |
39 | * retried | |
40 | */ | |
41 | static u8 superio_ide_inb (unsigned long port) | |
42 | { | |
43 | if (port == superio_ide_status[0] || | |
44 | port == superio_ide_status[1] || | |
45 | port == superio_ide_select[0] || | |
46 | port == superio_ide_select[1] || | |
47 | port == superio_ide_dma_status[0] || | |
48 | port == superio_ide_dma_status[1]) { | |
49 | u8 tmp; | |
50 | int retries = SUPERIO_IDE_MAX_RETRIES; | |
51 | ||
52 | /* printk(" [ reading port 0x%x with retry ] ", port); */ | |
53 | ||
54 | do { | |
55 | tmp = inb(port); | |
56 | if (tmp == 0) | |
57 | udelay(50); | |
58 | } while (tmp == 0 && retries-- > 0); | |
59 | ||
60 | return tmp; | |
61 | } | |
62 | ||
63 | return inb(port); | |
64 | } | |
65 | ||
b73c7ee2 BZ |
66 | static u8 superio_read_status(ide_hwif_t *hwif) |
67 | { | |
68 | return superio_ide_inb(hwif->io_ports.status_addr); | |
69 | } | |
70 | ||
b2f951aa BZ |
71 | static u8 superio_read_sff_dma_status(ide_hwif_t *hwif) |
72 | { | |
cab7f8ed | 73 | return superio_ide_inb(hwif->dma_base + ATA_DMA_STATUS); |
b2f951aa BZ |
74 | } |
75 | ||
ea23b8ba BZ |
76 | static void superio_tf_read(ide_drive_t *drive, ide_task_t *task) |
77 | { | |
78 | struct ide_io_ports *io_ports = &drive->hwif->io_ports; | |
79 | struct ide_taskfile *tf = &task->tf; | |
80 | ||
81 | if (task->tf_flags & IDE_TFLAG_IN_DATA) { | |
82 | u16 data = inw(io_ports->data_addr); | |
83 | ||
84 | tf->data = data & 0xff; | |
85 | tf->hob_data = (data >> 8) & 0xff; | |
86 | } | |
87 | ||
88 | /* be sure we're looking at the low order bits */ | |
ff074883 | 89 | outb(ATA_DEVCTL_OBS & ~0x80, io_ports->ctl_addr); |
ea23b8ba BZ |
90 | |
91 | if (task->tf_flags & IDE_TFLAG_IN_NSECT) | |
92 | tf->nsect = inb(io_ports->nsect_addr); | |
93 | if (task->tf_flags & IDE_TFLAG_IN_LBAL) | |
94 | tf->lbal = inb(io_ports->lbal_addr); | |
95 | if (task->tf_flags & IDE_TFLAG_IN_LBAM) | |
96 | tf->lbam = inb(io_ports->lbam_addr); | |
97 | if (task->tf_flags & IDE_TFLAG_IN_LBAH) | |
98 | tf->lbah = inb(io_ports->lbah_addr); | |
99 | if (task->tf_flags & IDE_TFLAG_IN_DEVICE) | |
100 | tf->device = superio_ide_inb(io_ports->device_addr); | |
101 | ||
102 | if (task->tf_flags & IDE_TFLAG_LBA48) { | |
ff074883 | 103 | outb(ATA_DEVCTL_OBS | 0x80, io_ports->ctl_addr); |
ea23b8ba BZ |
104 | |
105 | if (task->tf_flags & IDE_TFLAG_IN_HOB_FEATURE) | |
106 | tf->hob_feature = inb(io_ports->feature_addr); | |
107 | if (task->tf_flags & IDE_TFLAG_IN_HOB_NSECT) | |
108 | tf->hob_nsect = inb(io_ports->nsect_addr); | |
109 | if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAL) | |
110 | tf->hob_lbal = inb(io_ports->lbal_addr); | |
111 | if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAM) | |
112 | tf->hob_lbam = inb(io_ports->lbam_addr); | |
113 | if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAH) | |
114 | tf->hob_lbah = inb(io_ports->lbah_addr); | |
115 | } | |
116 | } | |
117 | ||
1da177e4 LT |
118 | static void __devinit superio_ide_init_iops (struct hwif_s *hwif) |
119 | { | |
36501650 | 120 | struct pci_dev *pdev = to_pci_dev(hwif->dev); |
1da177e4 | 121 | u32 base, dmabase; |
36501650 | 122 | u8 port = hwif->channel, tmp; |
1da177e4 LT |
123 | |
124 | base = pci_resource_start(pdev, port * 2) & ~3; | |
125 | dmabase = pci_resource_start(pdev, 4) & ~3; | |
126 | ||
4c3032d8 BZ |
127 | superio_ide_status[port] = base + 7; |
128 | superio_ide_select[port] = base + 6; | |
1da177e4 LT |
129 | superio_ide_dma_status[port] = dmabase + (!port ? 2 : 0xa); |
130 | ||
131 | /* Clear error/interrupt, enable dma */ | |
132 | tmp = superio_ide_inb(superio_ide_dma_status[port]); | |
133 | outb(tmp | 0x66, superio_ide_dma_status[port]); | |
134 | ||
b73c7ee2 | 135 | hwif->read_status = superio_read_status; |
b2f951aa BZ |
136 | hwif->read_sff_dma_status = superio_read_sff_dma_status; |
137 | ||
ea23b8ba BZ |
138 | hwif->tf_read = superio_tf_read; |
139 | ||
1da177e4 LT |
140 | /* We need to override inb to workaround a SuperIO errata */ |
141 | hwif->INB = superio_ide_inb; | |
142 | } | |
143 | ||
144 | static void __devinit init_iops_ns87415(ide_hwif_t *hwif) | |
145 | { | |
36501650 BZ |
146 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
147 | ||
148 | if (PCI_SLOT(dev->devfn) == 0xE) | |
1da177e4 LT |
149 | /* Built-in - assume it's under superio. */ |
150 | superio_ide_init_iops(hwif); | |
1da177e4 LT |
151 | } |
152 | #endif | |
153 | ||
154 | static unsigned int ns87415_count = 0, ns87415_control[MAX_HWIFS] = { 0 }; | |
155 | ||
156 | /* | |
157 | * This routine either enables/disables (according to drive->present) | |
158 | * the IRQ associated with the port (HWIF(drive)), | |
159 | * and selects either PIO or DMA handshaking for the next I/O operation. | |
160 | */ | |
161 | static void ns87415_prepare_drive (ide_drive_t *drive, unsigned int use_dma) | |
162 | { | |
163 | ide_hwif_t *hwif = HWIF(drive); | |
36501650 | 164 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1da177e4 | 165 | unsigned int bit, other, new, *old = (unsigned int *) hwif->select_data; |
1da177e4 LT |
166 | unsigned long flags; |
167 | ||
168 | local_irq_save(flags); | |
169 | new = *old; | |
170 | ||
171 | /* Adjust IRQ enable bit */ | |
172 | bit = 1 << (8 + hwif->channel); | |
173 | new = drive->present ? (new & ~bit) : (new | bit); | |
174 | ||
175 | /* Select PIO or DMA, DMA may only be selected for one drive/channel. */ | |
176 | bit = 1 << (20 + drive->select.b.unit + (hwif->channel << 1)); | |
177 | other = 1 << (20 + (1 - drive->select.b.unit) + (hwif->channel << 1)); | |
178 | new = use_dma ? ((new & ~other) | bit) : (new & ~bit); | |
179 | ||
180 | if (new != *old) { | |
181 | unsigned char stat; | |
182 | ||
183 | /* | |
184 | * Don't change DMA engine settings while Write Buffers | |
185 | * are busy. | |
186 | */ | |
187 | (void) pci_read_config_byte(dev, 0x43, &stat); | |
188 | while (stat & 0x03) { | |
189 | udelay(1); | |
190 | (void) pci_read_config_byte(dev, 0x43, &stat); | |
191 | } | |
192 | ||
193 | *old = new; | |
194 | (void) pci_write_config_dword(dev, 0x40, new); | |
195 | ||
196 | /* | |
197 | * And let things settle... | |
198 | */ | |
199 | udelay(10); | |
200 | } | |
201 | ||
202 | local_irq_restore(flags); | |
203 | } | |
204 | ||
205 | static void ns87415_selectproc (ide_drive_t *drive) | |
206 | { | |
207 | ns87415_prepare_drive (drive, drive->using_dma); | |
208 | } | |
209 | ||
5e37bdc0 | 210 | static int ns87415_dma_end(ide_drive_t *drive) |
1da177e4 LT |
211 | { |
212 | ide_hwif_t *hwif = HWIF(drive); | |
213 | u8 dma_stat = 0, dma_cmd = 0; | |
214 | ||
215 | drive->waiting_for_dma = 0; | |
b2f951aa | 216 | dma_stat = hwif->read_sff_dma_status(hwif); |
cab7f8ed BZ |
217 | /* get DMA command mode */ |
218 | dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD); | |
1da177e4 | 219 | /* stop DMA */ |
cab7f8ed | 220 | outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD); |
1da177e4 | 221 | /* from ERRATA: clear the INTR & ERROR bits */ |
cab7f8ed BZ |
222 | dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD); |
223 | outb(dma_cmd | 6, hwif->dma_base + ATA_DMA_CMD); | |
1da177e4 LT |
224 | /* and free any DMA resources */ |
225 | ide_destroy_dmatable(drive); | |
226 | /* verify good DMA status */ | |
227 | return (dma_stat & 7) != 4; | |
228 | } | |
229 | ||
5e37bdc0 | 230 | static int ns87415_dma_setup(ide_drive_t *drive) |
1da177e4 LT |
231 | { |
232 | /* select DMA xfer */ | |
233 | ns87415_prepare_drive(drive, 1); | |
234 | if (!ide_dma_setup(drive)) | |
235 | return 0; | |
236 | /* DMA failed: select PIO xfer */ | |
237 | ns87415_prepare_drive(drive, 0); | |
238 | return 1; | |
239 | } | |
240 | ||
c20530ed | 241 | static void __devinit init_hwif_ns87415 (ide_hwif_t *hwif) |
1da177e4 | 242 | { |
36501650 | 243 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1da177e4 LT |
244 | unsigned int ctrl, using_inta; |
245 | u8 progif; | |
246 | #ifdef __sparc_v9__ | |
247 | int timeout; | |
248 | u8 stat; | |
249 | #endif | |
250 | ||
1da177e4 LT |
251 | /* |
252 | * We cannot probe for IRQ: both ports share common IRQ on INTA. | |
253 | * Also, leave IRQ masked during drive probing, to prevent infinite | |
254 | * interrupts from a potentially floating INTA.. | |
255 | * | |
256 | * IRQs get unmasked in selectproc when drive is first used. | |
257 | */ | |
258 | (void) pci_read_config_dword(dev, 0x40, &ctrl); | |
259 | (void) pci_read_config_byte(dev, 0x09, &progif); | |
260 | /* is irq in "native" mode? */ | |
261 | using_inta = progif & (1 << (hwif->channel << 1)); | |
262 | if (!using_inta) | |
263 | using_inta = ctrl & (1 << (4 + hwif->channel)); | |
264 | if (hwif->mate) { | |
265 | hwif->select_data = hwif->mate->select_data; | |
266 | } else { | |
267 | hwif->select_data = (unsigned long) | |
268 | &ns87415_control[ns87415_count++]; | |
269 | ctrl |= (1 << 8) | (1 << 9); /* mask both IRQs */ | |
270 | if (using_inta) | |
271 | ctrl &= ~(1 << 6); /* unmask INTA */ | |
272 | *((unsigned int *)hwif->select_data) = ctrl; | |
273 | (void) pci_write_config_dword(dev, 0x40, ctrl); | |
274 | ||
275 | /* | |
276 | * Set prefetch size to 512 bytes for both ports, | |
277 | * but don't turn on/off prefetching here. | |
278 | */ | |
279 | pci_write_config_byte(dev, 0x55, 0xee); | |
280 | ||
281 | #ifdef __sparc_v9__ | |
282 | /* | |
9d501529 BZ |
283 | * XXX: Reset the device, if we don't it will not respond to |
284 | * SELECT_DRIVE() properly during first ide_probe_port(). | |
1da177e4 LT |
285 | */ |
286 | timeout = 10000; | |
4c3032d8 | 287 | outb(12, hwif->io_ports.ctl_addr); |
1da177e4 | 288 | udelay(10); |
4c3032d8 | 289 | outb(8, hwif->io_ports.ctl_addr); |
1da177e4 LT |
290 | do { |
291 | udelay(50); | |
b73c7ee2 | 292 | stat = hwif->read_status(hwif); |
1da177e4 LT |
293 | if (stat == 0xff) |
294 | break; | |
295 | } while ((stat & BUSY_STAT) && --timeout); | |
296 | #endif | |
297 | } | |
298 | ||
299 | if (!using_inta) | |
a861beb1 | 300 | hwif->irq = __ide_default_irq(hwif->io_ports.data_addr); |
1da177e4 LT |
301 | else if (!hwif->irq && hwif->mate && hwif->mate->irq) |
302 | hwif->irq = hwif->mate->irq; /* share IRQ with mate */ | |
303 | ||
304 | if (!hwif->dma_base) | |
305 | return; | |
306 | ||
cab7f8ed | 307 | outb(0x60, hwif->dma_base + ATA_DMA_STATUS); |
1da177e4 LT |
308 | } |
309 | ||
ac95beed BZ |
310 | static const struct ide_port_ops ns87415_port_ops = { |
311 | .selectproc = ns87415_selectproc, | |
312 | }; | |
313 | ||
f37afdac BZ |
314 | static const struct ide_dma_ops ns87415_dma_ops = { |
315 | .dma_host_set = ide_dma_host_set, | |
5e37bdc0 | 316 | .dma_setup = ns87415_dma_setup, |
f37afdac BZ |
317 | .dma_exec_cmd = ide_dma_exec_cmd, |
318 | .dma_start = ide_dma_start, | |
5e37bdc0 | 319 | .dma_end = ns87415_dma_end, |
f37afdac BZ |
320 | .dma_test_irq = ide_dma_test_irq, |
321 | .dma_lost_irq = ide_dma_lost_irq, | |
322 | .dma_timeout = ide_dma_timeout, | |
5e37bdc0 BZ |
323 | }; |
324 | ||
85620436 | 325 | static const struct ide_port_info ns87415_chipset __devinitdata = { |
1da177e4 LT |
326 | .name = "NS87415", |
327 | #ifdef CONFIG_SUPERIO | |
328 | .init_iops = init_iops_ns87415, | |
329 | #endif | |
330 | .init_hwif = init_hwif_ns87415, | |
ac95beed | 331 | .port_ops = &ns87415_port_ops, |
5e37bdc0 | 332 | .dma_ops = &ns87415_dma_ops, |
33c1002e | 333 | .host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA | |
5e71d9c5 | 334 | IDE_HFLAG_NO_ATAPI_DMA, |
1da177e4 LT |
335 | }; |
336 | ||
337 | static int __devinit ns87415_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
338 | { | |
339 | return ide_setup_pci_device(dev, &ns87415_chipset); | |
340 | } | |
341 | ||
9cbcc5e3 BZ |
342 | static const struct pci_device_id ns87415_pci_tbl[] = { |
343 | { PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_87415), 0 }, | |
1da177e4 LT |
344 | { 0, }, |
345 | }; | |
346 | MODULE_DEVICE_TABLE(pci, ns87415_pci_tbl); | |
347 | ||
348 | static struct pci_driver driver = { | |
349 | .name = "NS87415_IDE", | |
350 | .id_table = ns87415_pci_tbl, | |
351 | .probe = ns87415_init_one, | |
352 | }; | |
353 | ||
82ab1eec | 354 | static int __init ns87415_ide_init(void) |
1da177e4 LT |
355 | { |
356 | return ide_pci_register_driver(&driver); | |
357 | } | |
358 | ||
359 | module_init(ns87415_ide_init); | |
360 | ||
361 | MODULE_AUTHOR("Mark Lord, Eddie Dost, Andre Hedrick"); | |
362 | MODULE_DESCRIPTION("PCI driver module for NS87415 IDE"); | |
363 | MODULE_LICENSE("GPL"); |