Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Copyright (C) 1998-2000 Andreas S. Krebs (akrebs@altavista.net), Maintainer |
3 | * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>, Integrator | |
4 | * | |
5 | * CYPRESS CY82C693 chipset IDE controller | |
6 | * | |
7 | * The CY82C693 chipset is used on Digital's PC-Alpha 164SX boards. | |
8 | * Writing the driver was quite simple, since most of the job is | |
175f354b | 9 | * done by the generic pci-ide support. |
1da177e4 LT |
10 | * The hard part was finding the CY82C693's datasheet on Cypress's |
11 | * web page :-(. But Altavista solved this problem :-). | |
12 | * | |
13 | * | |
14 | * Notes: | |
15 | * - I recently got a 16.8G IBM DTTA, so I was able to test it with | |
16 | * a large and fast disk - the results look great, so I'd say the | |
17 | * driver is working fine :-) | |
175f354b PC |
18 | * hdparm -t reports 8.17 MB/sec at about 6% CPU usage for the DTTA |
19 | * - this is my first linux driver, so there's probably a lot of room | |
1da177e4 | 20 | * for optimizations and bug fixing, so feel free to do it. |
175f354b | 21 | * - if using PIO mode it's a good idea to set the PIO mode and |
1da177e4 LT |
22 | * 32-bit I/O support (if possible), e.g. hdparm -p2 -c1 /dev/hda |
23 | * - I had some problems with my IBM DHEA with PIO modes < 2 | |
24 | * (lost interrupts) ????? | |
25 | * - first tests with DMA look okay, they seem to work, but there is a | |
26 | * problem with sound - the BusMaster IDE TimeOut should fixed this | |
27 | * | |
28 | * Ancient History: | |
29 | * AMH@1999-08-24: v0.34 init_cy82c693_chip moved to pci_init_cy82c693 | |
30 | * ASK@1999-01-23: v0.33 made a few minor code clean ups | |
31 | * removed DMA clock speed setting by default | |
32 | * added boot message | |
33 | * ASK@1998-11-01: v0.32 added support to set BusMaster IDE TimeOut | |
34 | * added support to set DMA Controller Clock Speed | |
35 | * ASK@1998-10-31: v0.31 fixed problem with setting to high DMA modes | |
36 | * on some drives. | |
37 | * ASK@1998-10-29: v0.3 added support to set DMA modes | |
38 | * ASK@1998-10-28: v0.2 added support to set PIO modes | |
39 | * ASK@1998-10-27: v0.1 first version - chipset detection | |
40 | * | |
41 | */ | |
42 | ||
1da177e4 LT |
43 | #include <linux/module.h> |
44 | #include <linux/types.h> | |
45 | #include <linux/pci.h> | |
1da177e4 LT |
46 | #include <linux/ide.h> |
47 | #include <linux/init.h> | |
48 | ||
49 | #include <asm/io.h> | |
50 | ||
51 | /* the current version */ | |
52 | #define CY82_VERSION "CY82C693U driver v0.34 99-13-12 Andreas S. Krebs (akrebs@altavista.net)" | |
53 | ||
54 | /* | |
55 | * The following are used to debug the driver. | |
56 | */ | |
57 | #define CY82C693_DEBUG_LOGS 0 | |
58 | #define CY82C693_DEBUG_INFO 0 | |
59 | ||
60 | /* define CY82C693_SETDMA_CLOCK to set DMA Controller Clock Speed to ATCLK */ | |
61 | #undef CY82C693_SETDMA_CLOCK | |
62 | ||
63 | /* | |
64 | * NOTE: the value for busmaster timeout is tricky and I got it by | |
65 | * trial and error! By using a to low value will cause DMA timeouts | |
66 | * and drop IDE performance, and by using a to high value will cause | |
67 | * audio playback to scatter. | |
68 | * If you know a better value or how to calc it, please let me know. | |
69 | */ | |
70 | ||
71 | /* twice the value written in cy82c693ub datasheet */ | |
72 | #define BUSMASTER_TIMEOUT 0x50 | |
73 | /* | |
74 | * the value above was tested on my machine and it seems to work okay | |
75 | */ | |
76 | ||
77 | /* here are the offset definitions for the registers */ | |
78 | #define CY82_IDE_CMDREG 0x04 | |
79 | #define CY82_IDE_ADDRSETUP 0x48 | |
80 | #define CY82_IDE_MASTER_IOR 0x4C | |
81 | #define CY82_IDE_MASTER_IOW 0x4D | |
82 | #define CY82_IDE_SLAVE_IOR 0x4E | |
83 | #define CY82_IDE_SLAVE_IOW 0x4F | |
84 | #define CY82_IDE_MASTER_8BIT 0x50 | |
85 | #define CY82_IDE_SLAVE_8BIT 0x51 | |
86 | ||
87 | #define CY82_INDEX_PORT 0x22 | |
88 | #define CY82_DATA_PORT 0x23 | |
89 | ||
90 | #define CY82_INDEX_CTRLREG1 0x01 | |
91 | #define CY82_INDEX_CHANNEL0 0x30 | |
92 | #define CY82_INDEX_CHANNEL1 0x31 | |
93 | #define CY82_INDEX_TIMEOUT 0x32 | |
94 | ||
1da177e4 LT |
95 | /* the min and max PCI bus speed in MHz - from datasheet */ |
96 | #define CY82C963_MIN_BUS_SPEED 25 | |
97 | #define CY82C963_MAX_BUS_SPEED 33 | |
98 | ||
99 | /* the struct for the PIO mode timings */ | |
100 | typedef struct pio_clocks_s { | |
101 | u8 address_time; /* Address setup (clocks) */ | |
102 | u8 time_16r; /* clocks for 16bit IOR (0xF0=Active/data, 0x0F=Recovery) */ | |
103 | u8 time_16w; /* clocks for 16bit IOW (0xF0=Active/data, 0x0F=Recovery) */ | |
104 | u8 time_8; /* clocks for 8bit (0xF0=Active/data, 0x0F=Recovery) */ | |
105 | } pio_clocks_t; | |
106 | ||
107 | /* | |
108 | * calc clocks using bus_speed | |
109 | * returns (rounded up) time in bus clocks for time in ns | |
110 | */ | |
175f354b | 111 | static int calc_clk(int time, int bus_speed) |
1da177e4 LT |
112 | { |
113 | int clocks; | |
114 | ||
175f354b | 115 | clocks = (time*bus_speed+999)/1000 - 1; |
1da177e4 LT |
116 | |
117 | if (clocks < 0) | |
118 | clocks = 0; | |
119 | ||
120 | if (clocks > 0x0F) | |
121 | clocks = 0x0F; | |
122 | ||
123 | return clocks; | |
124 | } | |
125 | ||
126 | /* | |
127 | * compute the values for the clock registers for PIO | |
128 | * mode and pci_clk [MHz] speed | |
129 | * | |
130 | * NOTE: for mode 0,1 and 2 drives 8-bit IDE command control registers are used | |
131 | * for mode 3 and 4 drives 8 and 16-bit timings are the same | |
132 | * | |
175f354b PC |
133 | */ |
134 | static void compute_clocks(u8 pio, pio_clocks_t *p_pclk) | |
1da177e4 LT |
135 | { |
136 | int clk1, clk2; | |
ebae41a5 | 137 | int bus_speed = ide_pci_clk ? ide_pci_clk : system_bus_clock(); |
1da177e4 LT |
138 | |
139 | /* we don't check against CY82C693's min and max speed, | |
140 | * so you can play with the idebus=xx parameter | |
141 | */ | |
142 | ||
1da177e4 LT |
143 | /* let's calc the address setup time clocks */ |
144 | p_pclk->address_time = (u8)calc_clk(ide_pio_timings[pio].setup_time, bus_speed); | |
145 | ||
146 | /* let's calc the active and recovery time clocks */ | |
147 | clk1 = calc_clk(ide_pio_timings[pio].active_time, bus_speed); | |
148 | ||
149 | /* calc recovery timing */ | |
150 | clk2 = ide_pio_timings[pio].cycle_time - | |
151 | ide_pio_timings[pio].active_time - | |
152 | ide_pio_timings[pio].setup_time; | |
153 | ||
154 | clk2 = calc_clk(clk2, bus_speed); | |
155 | ||
156 | clk1 = (clk1<<4)|clk2; /* combine active and recovery clocks */ | |
157 | ||
158 | /* note: we use the same values for 16bit IOR and IOW | |
175f354b | 159 | * those are all the same, since I don't have other |
1da177e4 LT |
160 | * timings than those from ide-lib.c |
161 | */ | |
162 | ||
163 | p_pclk->time_16r = (u8)clk1; | |
164 | p_pclk->time_16w = (u8)clk1; | |
165 | ||
166 | /* what are good values for 8bit ?? */ | |
167 | p_pclk->time_8 = (u8)clk1; | |
168 | } | |
169 | ||
170 | /* | |
171 | * set DMA mode a specific channel for CY82C693 | |
172 | */ | |
173 | ||
8704de8f | 174 | static void cy82c693_set_dma_mode(ide_drive_t *drive, const u8 mode) |
1da177e4 | 175 | { |
8704de8f BZ |
176 | ide_hwif_t *hwif = drive->hwif; |
177 | u8 single = (mode & 0x10) >> 4, index = 0, data = 0; | |
1da177e4 | 178 | |
8704de8f | 179 | index = hwif->channel ? CY82_INDEX_CHANNEL1 : CY82_INDEX_CHANNEL0; |
1da177e4 LT |
180 | |
181 | #if CY82C693_DEBUG_LOGS | |
182 | /* for debug let's show the previous values */ | |
183 | ||
0ecdca26 BZ |
184 | outb(index, CY82_INDEX_PORT); |
185 | data = inb(CY82_DATA_PORT); | |
1da177e4 | 186 | |
175f354b | 187 | printk(KERN_INFO "%s (ch=%d, dev=%d): DMA mode is %d (single=%d)\n", |
1da177e4 LT |
188 | drive->name, HWIF(drive)->channel, drive->select.b.unit, |
189 | (data&0x3), ((data>>2)&1)); | |
190 | #endif /* CY82C693_DEBUG_LOGS */ | |
191 | ||
8704de8f | 192 | data = (mode & 3) | (single << 2); |
1da177e4 | 193 | |
0ecdca26 BZ |
194 | outb(index, CY82_INDEX_PORT); |
195 | outb(data, CY82_DATA_PORT); | |
1da177e4 LT |
196 | |
197 | #if CY82C693_DEBUG_INFO | |
198 | printk(KERN_INFO "%s (ch=%d, dev=%d): set DMA mode to %d (single=%d)\n", | |
199 | drive->name, HWIF(drive)->channel, drive->select.b.unit, | |
8704de8f | 200 | mode & 3, single); |
1da177e4 LT |
201 | #endif /* CY82C693_DEBUG_INFO */ |
202 | ||
175f354b | 203 | /* |
1da177e4 LT |
204 | * note: below we set the value for Bus Master IDE TimeOut Register |
205 | * I'm not absolutly sure what this does, but it solved my problem | |
206 | * with IDE DMA and sound, so I now can play sound and work with | |
207 | * my IDE driver at the same time :-) | |
208 | * | |
209 | * If you know the correct (best) value for this register please | |
210 | * let me know - ASK | |
211 | */ | |
212 | ||
213 | data = BUSMASTER_TIMEOUT; | |
0ecdca26 BZ |
214 | outb(CY82_INDEX_TIMEOUT, CY82_INDEX_PORT); |
215 | outb(data, CY82_DATA_PORT); | |
1da177e4 | 216 | |
175f354b PC |
217 | #if CY82C693_DEBUG_INFO |
218 | printk(KERN_INFO "%s: Set IDE Bus Master TimeOut Register to 0x%X\n", | |
1da177e4 LT |
219 | drive->name, data); |
220 | #endif /* CY82C693_DEBUG_INFO */ | |
221 | } | |
222 | ||
26bcb879 | 223 | static void cy82c693_set_pio_mode(ide_drive_t *drive, const u8 pio) |
1da177e4 LT |
224 | { |
225 | ide_hwif_t *hwif = HWIF(drive); | |
36501650 | 226 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1da177e4 LT |
227 | pio_clocks_t pclk; |
228 | unsigned int addrCtrl; | |
229 | ||
230 | /* select primary or secondary channel */ | |
231 | if (hwif->index > 0) { /* drive is on the secondary channel */ | |
652aa162 | 232 | dev = pci_get_slot(dev->bus, dev->devfn+1); |
1da177e4 LT |
233 | if (!dev) { |
234 | printk(KERN_ERR "%s: tune_drive: " | |
235 | "Cannot find secondary interface!\n", | |
236 | drive->name); | |
237 | return; | |
238 | } | |
239 | } | |
240 | ||
241 | #if CY82C693_DEBUG_LOGS | |
242 | /* for debug let's show the register values */ | |
175f354b PC |
243 | |
244 | if (drive->select.b.unit == 0) { | |
1da177e4 | 245 | /* |
175f354b | 246 | * get master drive registers |
1da177e4 LT |
247 | * address setup control register |
248 | * is 32 bit !!! | |
175f354b PC |
249 | */ |
250 | pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl); | |
1da177e4 LT |
251 | addrCtrl &= 0x0F; |
252 | ||
253 | /* now let's get the remaining registers */ | |
254 | pci_read_config_byte(dev, CY82_IDE_MASTER_IOR, &pclk.time_16r); | |
255 | pci_read_config_byte(dev, CY82_IDE_MASTER_IOW, &pclk.time_16w); | |
256 | pci_read_config_byte(dev, CY82_IDE_MASTER_8BIT, &pclk.time_8); | |
257 | } else { | |
258 | /* | |
259 | * set slave drive registers | |
260 | * address setup control register | |
261 | * is 32 bit !!! | |
175f354b | 262 | */ |
1da177e4 LT |
263 | pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl); |
264 | ||
265 | addrCtrl &= 0xF0; | |
266 | addrCtrl >>= 4; | |
267 | ||
268 | /* now let's get the remaining registers */ | |
269 | pci_read_config_byte(dev, CY82_IDE_SLAVE_IOR, &pclk.time_16r); | |
270 | pci_read_config_byte(dev, CY82_IDE_SLAVE_IOW, &pclk.time_16w); | |
271 | pci_read_config_byte(dev, CY82_IDE_SLAVE_8BIT, &pclk.time_8); | |
272 | } | |
273 | ||
274 | printk(KERN_INFO "%s (ch=%d, dev=%d): PIO timing is " | |
275 | "(addr=0x%X, ior=0x%X, iow=0x%X, 8bit=0x%X)\n", | |
276 | drive->name, hwif->channel, drive->select.b.unit, | |
277 | addrCtrl, pclk.time_16r, pclk.time_16w, pclk.time_8); | |
278 | #endif /* CY82C693_DEBUG_LOGS */ | |
279 | ||
1da177e4 LT |
280 | /* let's calc the values for this PIO mode */ |
281 | compute_clocks(pio, &pclk); | |
282 | ||
283 | /* now let's write the clocks registers */ | |
284 | if (drive->select.b.unit == 0) { | |
285 | /* | |
286 | * set master drive | |
287 | * address setup control register | |
288 | * is 32 bit !!! | |
175f354b | 289 | */ |
1da177e4 | 290 | pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl); |
175f354b | 291 | |
1da177e4 LT |
292 | addrCtrl &= (~0xF); |
293 | addrCtrl |= (unsigned int)pclk.address_time; | |
294 | pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl); | |
295 | ||
296 | /* now let's set the remaining registers */ | |
297 | pci_write_config_byte(dev, CY82_IDE_MASTER_IOR, pclk.time_16r); | |
298 | pci_write_config_byte(dev, CY82_IDE_MASTER_IOW, pclk.time_16w); | |
299 | pci_write_config_byte(dev, CY82_IDE_MASTER_8BIT, pclk.time_8); | |
175f354b | 300 | |
1da177e4 LT |
301 | addrCtrl &= 0xF; |
302 | } else { | |
303 | /* | |
304 | * set slave drive | |
305 | * address setup control register | |
306 | * is 32 bit !!! | |
175f354b | 307 | */ |
1da177e4 LT |
308 | pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl); |
309 | ||
310 | addrCtrl &= (~0xF0); | |
311 | addrCtrl |= ((unsigned int)pclk.address_time<<4); | |
312 | pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl); | |
313 | ||
314 | /* now let's set the remaining registers */ | |
315 | pci_write_config_byte(dev, CY82_IDE_SLAVE_IOR, pclk.time_16r); | |
316 | pci_write_config_byte(dev, CY82_IDE_SLAVE_IOW, pclk.time_16w); | |
317 | pci_write_config_byte(dev, CY82_IDE_SLAVE_8BIT, pclk.time_8); | |
318 | ||
319 | addrCtrl >>= 4; | |
320 | addrCtrl &= 0xF; | |
175f354b | 321 | } |
1da177e4 LT |
322 | |
323 | #if CY82C693_DEBUG_INFO | |
324 | printk(KERN_INFO "%s (ch=%d, dev=%d): set PIO timing to " | |
325 | "(addr=0x%X, ior=0x%X, iow=0x%X, 8bit=0x%X)\n", | |
326 | drive->name, hwif->channel, drive->select.b.unit, | |
327 | addrCtrl, pclk.time_16r, pclk.time_16w, pclk.time_8); | |
328 | #endif /* CY82C693_DEBUG_INFO */ | |
329 | } | |
330 | ||
331 | /* | |
332 | * this function is called during init and is used to setup the cy82c693 chip | |
333 | */ | |
ddbc9fb4 | 334 | static unsigned int __devinit init_chipset_cy82c693(struct pci_dev *dev, const char *name) |
1da177e4 LT |
335 | { |
336 | if (PCI_FUNC(dev->devfn) != 1) | |
337 | return 0; | |
338 | ||
339 | #ifdef CY82C693_SETDMA_CLOCK | |
340 | u8 data = 0; | |
175f354b | 341 | #endif /* CY82C693_SETDMA_CLOCK */ |
1da177e4 LT |
342 | |
343 | /* write info about this verion of the driver */ | |
344 | printk(KERN_INFO CY82_VERSION "\n"); | |
345 | ||
346 | #ifdef CY82C693_SETDMA_CLOCK | |
347 | /* okay let's set the DMA clock speed */ | |
175f354b PC |
348 | |
349 | outb(CY82_INDEX_CTRLREG1, CY82_INDEX_PORT); | |
350 | data = inb(CY82_DATA_PORT); | |
1da177e4 LT |
351 | |
352 | #if CY82C693_DEBUG_INFO | |
353 | printk(KERN_INFO "%s: Peripheral Configuration Register: 0x%X\n", | |
354 | name, data); | |
355 | #endif /* CY82C693_DEBUG_INFO */ | |
356 | ||
175f354b | 357 | /* |
1da177e4 LT |
358 | * for some reason sometimes the DMA controller |
359 | * speed is set to ATCLK/2 ???? - we fix this here | |
175f354b | 360 | * |
1da177e4 LT |
361 | * note: i don't know what causes this strange behaviour, |
362 | * but even changing the dma speed doesn't solve it :-( | |
175f354b PC |
363 | * the ide performance is still only half the normal speed |
364 | * | |
1da177e4 LT |
365 | * if anybody knows what goes wrong with my machine, please |
366 | * let me know - ASK | |
175f354b | 367 | */ |
1da177e4 LT |
368 | |
369 | data |= 0x03; | |
370 | ||
175f354b PC |
371 | outb(CY82_INDEX_CTRLREG1, CY82_INDEX_PORT); |
372 | outb(data, CY82_DATA_PORT); | |
1da177e4 LT |
373 | |
374 | #if CY82C693_DEBUG_INFO | |
175f354b | 375 | printk(KERN_INFO "%s: New Peripheral Configuration Register: 0x%X\n", |
1da177e4 LT |
376 | name, data); |
377 | #endif /* CY82C693_DEBUG_INFO */ | |
378 | ||
379 | #endif /* CY82C693_SETDMA_CLOCK */ | |
380 | return 0; | |
381 | } | |
382 | ||
e851b620 | 383 | static void __devinit init_iops_cy82c693(ide_hwif_t *hwif) |
1da177e4 | 384 | { |
f32d26ae | 385 | static ide_hwif_t *primary; |
36501650 | 386 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
f32d26ae | 387 | |
36501650 | 388 | if (PCI_FUNC(dev->devfn) == 1) |
1da177e4 LT |
389 | primary = hwif; |
390 | else { | |
391 | hwif->mate = primary; | |
392 | hwif->channel = 1; | |
393 | } | |
394 | } | |
395 | ||
ac95beed BZ |
396 | static const struct ide_port_ops cy82c693_port_ops = { |
397 | .set_pio_mode = cy82c693_set_pio_mode, | |
398 | .set_dma_mode = cy82c693_set_dma_mode, | |
399 | }; | |
400 | ||
85620436 | 401 | static const struct ide_port_info cy82c693_chipset __devinitdata = { |
7b77d864 BZ |
402 | .name = "CY82C693", |
403 | .init_chipset = init_chipset_cy82c693, | |
404 | .init_iops = init_iops_cy82c693, | |
ac95beed | 405 | .port_ops = &cy82c693_port_ops, |
528a572d | 406 | .chipset = ide_cy82c693, |
951784b6 | 407 | .host_flags = IDE_HFLAG_SINGLE, |
4099d143 | 408 | .pio_mask = ATA_PIO4, |
8704de8f BZ |
409 | .swdma_mask = ATA_SWDMA2, |
410 | .mwdma_mask = ATA_MWDMA2, | |
1da177e4 LT |
411 | }; |
412 | ||
413 | static int __devinit cy82c693_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
414 | { | |
1da177e4 LT |
415 | struct pci_dev *dev2; |
416 | int ret = -ENODEV; | |
417 | ||
418 | /* CY82C693 is more than only a IDE controller. | |
419 | Function 1 is primary IDE channel, function 2 - secondary. */ | |
175f354b | 420 | if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE && |
1da177e4 | 421 | PCI_FUNC(dev->devfn) == 1) { |
652aa162 | 422 | dev2 = pci_get_slot(dev->bus, dev->devfn + 1); |
7b77d864 | 423 | ret = ide_setup_pci_devices(dev, dev2, &cy82c693_chipset); |
652aa162 | 424 | /* We leak pci refs here but thats ok - we can't be unloaded */ |
1da177e4 LT |
425 | } |
426 | return ret; | |
427 | } | |
428 | ||
9cbcc5e3 BZ |
429 | static const struct pci_device_id cy82c693_pci_tbl[] = { |
430 | { PCI_VDEVICE(CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693), 0 }, | |
1da177e4 LT |
431 | { 0, }, |
432 | }; | |
433 | MODULE_DEVICE_TABLE(pci, cy82c693_pci_tbl); | |
434 | ||
435 | static struct pci_driver driver = { | |
436 | .name = "Cypress_IDE", | |
437 | .id_table = cy82c693_pci_tbl, | |
438 | .probe = cy82c693_init_one, | |
439 | }; | |
440 | ||
82ab1eec | 441 | static int __init cy82c693_ide_init(void) |
1da177e4 LT |
442 | { |
443 | return ide_pci_register_driver(&driver); | |
444 | } | |
445 | ||
446 | module_init(cy82c693_ide_init); | |
447 | ||
448 | MODULE_AUTHOR("Andreas Krebs, Andre Hedrick"); | |
449 | MODULE_DESCRIPTION("PCI driver module for the Cypress CY82C693 IDE"); | |
450 | MODULE_LICENSE("GPL"); |