[linux-2.6-block.git] / drivers / ide / pci / cy82c693.c

/*
 * linux/drivers/ide/pci/cy82c693.c		Version 0.40	Sep. 10, 2002
 *
 *  Copyright (C) 1998-2000 Andreas S. Krebs (akrebs@altavista.net), Maintainer
 *  Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>, Integrator
 *
 * CYPRESS CY82C693 chipset IDE controller
 *
 * The CY82C693 chipset is used on Digital's PC-Alpha 164SX boards.
 * Writing the driver was quite simple, since most of the job is
 * done by the generic pci-ide support. 
 * The hard part was finding the CY82C693's datasheet on Cypress's
 * web page :-(. But Altavista solved this problem :-).
 *
 *
 * Notes:
 * - I recently got a 16.8G IBM DTTA, so I was able to test it with
 *   a large and fast disk - the results look great, so I'd say the
 *   driver is working fine :-)
 *   hdparm -t reports 8.17 MB/sec at about 6% CPU usage for the DTTA 
 * - this is my first linux driver, so there's probably a lot  of room 
 *   for optimizations and bug fixing, so feel free to do it.
 * - use idebus=xx parameter to set PCI bus speed - needed to calc
 *   timings for PIO modes (default will be 40)
 * - if using PIO mode it's a good idea to set the PIO mode and 
 *   32-bit I/O support (if possible), e.g. hdparm -p2 -c1 /dev/hda
 * - I had some problems with my IBM DHEA with PIO modes < 2
 *   (lost interrupts) ?????
 * - first tests with DMA look okay, they seem to work, but there is a
 *   problem with sound - the BusMaster IDE TimeOut should fixed this
 *
 * Ancient History:
 * AMH@1999-08-24: v0.34 init_cy82c693_chip moved to pci_init_cy82c693
 * ASK@1999-01-23: v0.33 made a few minor code clean ups
 *                       removed DMA clock speed setting by default
 *                       added boot message
 * ASK@1998-11-01: v0.32 added support to set BusMaster IDE TimeOut
 *                       added support to set DMA Controller Clock Speed
 * ASK@1998-10-31: v0.31 fixed problem with setting to high DMA modes
 *                       on some drives.
 * ASK@1998-10-29: v0.3 added support to set DMA modes
 * ASK@1998-10-28: v0.2 added support to set PIO modes
 * ASK@1998-10-27: v0.1 first version - chipset detection
 *
 */

#include <linux/module.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/ide.h>
#include <linux/init.h>

#include <asm/io.h>

/* the current version */
#define CY82_VERSION	"CY82C693U driver v0.34 99-13-12 Andreas S. Krebs (akrebs@altavista.net)"

/*
 *	The following are used to debug the driver.
 */
#define CY82C693_DEBUG_LOGS	0
#define CY82C693_DEBUG_INFO	0

/* define CY82C693_SETDMA_CLOCK to set DMA Controller Clock Speed to ATCLK */
#undef CY82C693_SETDMA_CLOCK

/*
 *	NOTE: the value for busmaster timeout is tricky and I got it by
 *	trial and error!  By using a to low value will cause DMA timeouts
 *	and drop IDE performance, and by using a to high value will cause
 *	audio playback to scatter.
 *	If you know a better value or how to calc it, please let me know.
 */

/* twice the value written in cy82c693ub datasheet */
#define BUSMASTER_TIMEOUT	0x50
/*
 * the value above was tested on my machine and it seems to work okay
 */

/* here are the offset definitions for the registers */
#define CY82_IDE_CMDREG		0x04
#define CY82_IDE_ADDRSETUP	0x48
#define CY82_IDE_MASTER_IOR	0x4C
#define CY82_IDE_MASTER_IOW	0x4D
#define CY82_IDE_SLAVE_IOR	0x4E
#define CY82_IDE_SLAVE_IOW	0x4F
#define CY82_IDE_MASTER_8BIT	0x50
#define CY82_IDE_SLAVE_8BIT	0x51

#define CY82_INDEX_PORT		0x22
#define CY82_DATA_PORT		0x23

#define CY82_INDEX_CTRLREG1	0x01
#define CY82_INDEX_CHANNEL0	0x30
#define CY82_INDEX_CHANNEL1	0x31
#define CY82_INDEX_TIMEOUT	0x32

/* the min and max PCI bus speed in MHz - from datasheet */
#define CY82C963_MIN_BUS_SPEED	25
#define CY82C963_MAX_BUS_SPEED	33

/* the struct for the PIO mode timings */
typedef struct pio_clocks_s {
	u8	address_time;	/* Address setup (clocks) */
	u8	time_16r;	/* clocks for 16bit IOR (0xF0=Active/data, 0x0F=Recovery) */
	u8	time_16w;	/* clocks for 16bit IOW (0xF0=Active/data, 0x0F=Recovery) */
	u8	time_8;		/* clocks for 8bit (0xF0=Active/data, 0x0F=Recovery) */
} pio_clocks_t;

/*
 * calc clocks using bus_speed
 * returns (rounded up) time in bus clocks for time in ns
 */
static int calc_clk (int time, int bus_speed)
{
	int clocks;

	clocks = (time*bus_speed+999)/1000 -1;

	if (clocks < 0)
		clocks = 0;

	if (clocks > 0x0F)
		clocks = 0x0F;

	return clocks;
}

/*
 * compute the values for the clock registers for PIO
 * mode and pci_clk [MHz] speed
 *
 * NOTE: for mode 0,1 and 2 drives 8-bit IDE command control registers are used
 *       for mode 3 and 4 drives 8 and 16-bit timings are the same
 *
 */ 
static void compute_clocks (u8 pio, pio_clocks_t *p_pclk)
{
	int clk1, clk2;
	int bus_speed = system_bus_clock();	/* get speed of PCI bus */

	/* we don't check against CY82C693's min and max speed,
	 * so you can play with the idebus=xx parameter
	 */

	/* let's calc the address setup time clocks */
	p_pclk->address_time = (u8)calc_clk(ide_pio_timings[pio].setup_time, bus_speed);

	/* let's calc the active and recovery time clocks */
	clk1 = calc_clk(ide_pio_timings[pio].active_time, bus_speed);

	/* calc recovery timing */
	clk2 =	ide_pio_timings[pio].cycle_time -
		ide_pio_timings[pio].active_time -
		ide_pio_timings[pio].setup_time;

	clk2 = calc_clk(clk2, bus_speed);

	clk1 = (clk1<<4)|clk2;	/* combine active and recovery clocks */

	/* note: we use the same values for 16bit IOR and IOW
         *	those are all the same, since I don't have other
	 *	timings than those from ide-lib.c
	 */

	p_pclk->time_16r = (u8)clk1;
	p_pclk->time_16w = (u8)clk1;

	/* what are good values for 8bit ?? */
	p_pclk->time_8 = (u8)clk1;
}

/*
 * set DMA mode a specific channel for CY82C693
 */

static void cy82c693_dma_enable (ide_drive_t *drive, int mode, int single)
{
	u8 index = 0, data = 0;

	if (mode>2)	/* make sure we set a valid mode */
		mode = 2;
			   
	if (mode > drive->id->tDMA)  /* to be absolutly sure we have a valid mode */
		mode = drive->id->tDMA;
	
	index = (HWIF(drive)->channel==0) ? CY82_INDEX_CHANNEL0 : CY82_INDEX_CHANNEL1;

#if CY82C693_DEBUG_LOGS
	/* for debug let's show the previous values */

	outb(index, CY82_INDEX_PORT);
	data = inb(CY82_DATA_PORT);

	printk (KERN_INFO "%s (ch=%d, dev=%d): DMA mode is %d (single=%d)\n",
		drive->name, HWIF(drive)->channel, drive->select.b.unit,
		(data&0x3), ((data>>2)&1));
#endif /* CY82C693_DEBUG_LOGS */

	data = (u8)mode|(u8)(single<<2);

	outb(index, CY82_INDEX_PORT);
	outb(data, CY82_DATA_PORT);

#if CY82C693_DEBUG_INFO
	printk(KERN_INFO "%s (ch=%d, dev=%d): set DMA mode to %d (single=%d)\n",
		drive->name, HWIF(drive)->channel, drive->select.b.unit,
		mode, single);
#endif /* CY82C693_DEBUG_INFO */

	/* 
	 * note: below we set the value for Bus Master IDE TimeOut Register
	 * I'm not absolutly sure what this does, but it solved my problem
	 * with IDE DMA and sound, so I now can play sound and work with
	 * my IDE driver at the same time :-)
	 *
	 * If you know the correct (best) value for this register please
	 * let me know - ASK
	 */

	data = BUSMASTER_TIMEOUT;
	outb(CY82_INDEX_TIMEOUT, CY82_INDEX_PORT);
	outb(data, CY82_DATA_PORT);

#if CY82C693_DEBUG_INFO	
	printk (KERN_INFO "%s: Set IDE Bus Master TimeOut Register to 0x%X\n",
		drive->name, data);
#endif /* CY82C693_DEBUG_INFO */
}

/* 
 * used to set DMA mode for CY82C693 (single and multi modes)
 */
static int cy82c693_ide_dma_on (ide_drive_t *drive)
{
	struct hd_driveid *id = drive->id;

#if CY82C693_DEBUG_INFO
	printk (KERN_INFO "dma_on: %s\n", drive->name);
#endif /* CY82C693_DEBUG_INFO */

	if (id != NULL) {		
		/* Enable DMA on any drive that has DMA
		 * (multi or single) enabled
		 */
		if (id->field_valid & 2) {	/* regular DMA */
			int mmode, smode;

			mmode = id->dma_mword & (id->dma_mword >> 8);
			smode = id->dma_1word & (id->dma_1word >> 8);
			       		      
			if (mmode != 0) {
				/* enable multi */
				cy82c693_dma_enable(drive, (mmode >> 1), 0);
			} else if (smode != 0) {
				/* enable single */
				cy82c693_dma_enable(drive, (smode >> 1), 1);
			}
		}
	}
        return __ide_dma_on(drive);
}

static void cy82c693_set_pio_mode(ide_drive_t *drive, const u8 pio)
{
	ide_hwif_t *hwif = HWIF(drive);
	struct pci_dev *dev = hwif->pci_dev;
	pio_clocks_t pclk;
	unsigned int addrCtrl;

	/* select primary or secondary channel */
	if (hwif->index > 0) {  /* drive is on the secondary channel */
		dev = pci_get_slot(dev->bus, dev->devfn+1);
		if (!dev) {
			printk(KERN_ERR "%s: tune_drive: "
				"Cannot find secondary interface!\n",
				drive->name);
			return;
		}
	}

#if CY82C693_DEBUG_LOGS
	/* for debug let's show the register values */
	
       	if (drive->select.b.unit == 0) {
		/*
		 * get master drive registers               	
		 * address setup control register
		 * is 32 bit !!!
		 */ 
	  	pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);                
		addrCtrl &= 0x0F;

		/* now let's get the remaining registers */
		pci_read_config_byte(dev, CY82_IDE_MASTER_IOR, &pclk.time_16r);
		pci_read_config_byte(dev, CY82_IDE_MASTER_IOW, &pclk.time_16w);
		pci_read_config_byte(dev, CY82_IDE_MASTER_8BIT, &pclk.time_8);
	} else {
		/*
		 * set slave drive registers
		 * address setup control register
		 * is 32 bit !!!
		 */ 
		pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);

		addrCtrl &= 0xF0;
		addrCtrl >>= 4;

		/* now let's get the remaining registers */
		pci_read_config_byte(dev, CY82_IDE_SLAVE_IOR, &pclk.time_16r);
		pci_read_config_byte(dev, CY82_IDE_SLAVE_IOW, &pclk.time_16w);
		pci_read_config_byte(dev, CY82_IDE_SLAVE_8BIT, &pclk.time_8);
	}

	printk(KERN_INFO "%s (ch=%d, dev=%d): PIO timing is "
		"(addr=0x%X, ior=0x%X, iow=0x%X, 8bit=0x%X)\n",
		drive->name, hwif->channel, drive->select.b.unit,
		addrCtrl, pclk.time_16r, pclk.time_16w, pclk.time_8);
#endif /* CY82C693_DEBUG_LOGS */

	/* let's calc the values for this PIO mode */
	compute_clocks(pio, &pclk);

	/* now let's write  the clocks registers */
	if (drive->select.b.unit == 0) {
		/*
		 * set master drive
		 * address setup control register
		 * is 32 bit !!!
		 */ 
		pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
		
		addrCtrl &= (~0xF);
		addrCtrl |= (unsigned int)pclk.address_time;
		pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl);

		/* now let's set the remaining registers */
		pci_write_config_byte(dev, CY82_IDE_MASTER_IOR, pclk.time_16r);
		pci_write_config_byte(dev, CY82_IDE_MASTER_IOW, pclk.time_16w);
		pci_write_config_byte(dev, CY82_IDE_MASTER_8BIT, pclk.time_8);
		
		addrCtrl &= 0xF;
	} else {
		/*
		 * set slave drive
		 * address setup control register
		 * is 32 bit !!!
		 */ 
		pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);

		addrCtrl &= (~0xF0);
		addrCtrl |= ((unsigned int)pclk.address_time<<4);
		pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl);

		/* now let's set the remaining registers */
		pci_write_config_byte(dev, CY82_IDE_SLAVE_IOR, pclk.time_16r);
		pci_write_config_byte(dev, CY82_IDE_SLAVE_IOW, pclk.time_16w);
		pci_write_config_byte(dev, CY82_IDE_SLAVE_8BIT, pclk.time_8);

		addrCtrl >>= 4;
		addrCtrl &= 0xF;
	}	

#if CY82C693_DEBUG_INFO
	printk(KERN_INFO "%s (ch=%d, dev=%d): set PIO timing to "
		"(addr=0x%X, ior=0x%X, iow=0x%X, 8bit=0x%X)\n",
		drive->name, hwif->channel, drive->select.b.unit,
		addrCtrl, pclk.time_16r, pclk.time_16w, pclk.time_8);
#endif /* CY82C693_DEBUG_INFO */
}

/*
 * this function is called during init and is used to setup the cy82c693 chip
 */
static unsigned int __devinit init_chipset_cy82c693(struct pci_dev *dev, const char *name)
{
	if (PCI_FUNC(dev->devfn) != 1)
		return 0;

#ifdef CY82C693_SETDMA_CLOCK
	u8 data = 0;
#endif /* CY82C693_SETDMA_CLOCK */ 

	/* write info about this verion of the driver */
	printk(KERN_INFO CY82_VERSION "\n");

#ifdef CY82C693_SETDMA_CLOCK
       /* okay let's set the DMA clock speed */
        
        outb(CY82_INDEX_CTRLREG1, CY82_INDEX_PORT);
        data = inb(CY82_DATA_PORT);

#if CY82C693_DEBUG_INFO
	printk(KERN_INFO "%s: Peripheral Configuration Register: 0x%X\n",
		name, data);
#endif /* CY82C693_DEBUG_INFO */

        /*
	 * for some reason sometimes the DMA controller
	 * speed is set to ATCLK/2 ???? - we fix this here
	 * 
	 * note: i don't know what causes this strange behaviour,
	 *       but even changing the dma speed doesn't solve it :-(
	 *       the ide performance is still only half the normal speed 
	 * 
	 *       if anybody knows what goes wrong with my machine, please
	 *       let me know - ASK
         */

	data |= 0x03;

        outb(CY82_INDEX_CTRLREG1, CY82_INDEX_PORT);
        outb(data, CY82_DATA_PORT);

#if CY82C693_DEBUG_INFO
	printk (KERN_INFO "%s: New Peripheral Configuration Register: 0x%X\n",
		name, data);
#endif /* CY82C693_DEBUG_INFO */

#endif /* CY82C693_SETDMA_CLOCK */
	return 0;
}

/*
 * the init function - called for each ide channel once
 */
static void __devinit init_hwif_cy82c693(ide_hwif_t *hwif)
{
	hwif->chipset = ide_cy82c693;
	hwif->set_pio_mode = &cy82c693_set_pio_mode;

	if (!hwif->dma_base) {
		hwif->drives[0].autotune = 1;
		hwif->drives[1].autotune = 1;
		return;
	}

	hwif->mwdma_mask = 0x04;
	hwif->swdma_mask = 0x04;

	hwif->ide_dma_on = &cy82c693_ide_dma_on;
}

static __devinitdata ide_hwif_t *primary;

static void __devinit init_iops_cy82c693(ide_hwif_t *hwif)
{
	if (PCI_FUNC(hwif->pci_dev->devfn) == 1)
		primary = hwif;
	else {
		hwif->mate = primary;
		hwif->channel = 1;
	}
}

static ide_pci_device_t cy82c693_chipset __devinitdata = {
	.name		= "CY82C693",
	.init_chipset	= init_chipset_cy82c693,
	.init_iops	= init_iops_cy82c693,
	.init_hwif	= init_hwif_cy82c693,
	.host_flags	= IDE_HFLAG_SINGLE | IDE_HFLAG_TRUST_BIOS_FOR_DMA |
			  IDE_HFLAG_BOOTABLE,
	.pio_mask	= ATA_PIO4,
};

static int __devinit cy82c693_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	struct pci_dev *dev2;
	int ret = -ENODEV;

	/* CY82C693 is more than only a IDE controller.
	   Function 1 is primary IDE channel, function 2 - secondary. */
        if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE &&
	    PCI_FUNC(dev->devfn) == 1) {
		dev2 = pci_get_slot(dev->bus, dev->devfn + 1);
		ret = ide_setup_pci_devices(dev, dev2, &cy82c693_chipset);
		/* We leak pci refs here but thats ok - we can't be unloaded */
	}
	return ret;
}

static const struct pci_device_id cy82c693_pci_tbl[] = {
	{ PCI_VDEVICE(CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693), 0 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, cy82c693_pci_tbl);

static struct pci_driver driver = {
	.name		= "Cypress_IDE",
	.id_table	= cy82c693_pci_tbl,
	.probe		= cy82c693_init_one,
};

static int __init cy82c693_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}

module_init(cy82c693_ide_init);

MODULE_AUTHOR("Andreas Krebs, Andre Hedrick");
MODULE_DESCRIPTION("PCI driver module for the Cypress CY82C693 IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/drivers/ide/pci/cy82c693.c Version 0.40 Sep. 10, 2002
	3	*
	4	* Copyright (C) 1998-2000 Andreas S. Krebs (akrebs@altavista.net), Maintainer
	5	* Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>, Integrator
	6	*
	7	* CYPRESS CY82C693 chipset IDE controller
	8	*
	9	* The CY82C693 chipset is used on Digital's PC-Alpha 164SX boards.
	10	* Writing the driver was quite simple, since most of the job is
	11	* done by the generic pci-ide support.
	12	* The hard part was finding the CY82C693's datasheet on Cypress's
	13	* web page :-(. But Altavista solved this problem :-).
	14	*
	15	*
	16	* Notes:
	17	* - I recently got a 16.8G IBM DTTA, so I was able to test it with
	18	* a large and fast disk - the results look great, so I'd say the
	19	* driver is working fine :-)
	20	* hdparm -t reports 8.17 MB/sec at about 6% CPU usage for the DTTA
	21	* - this is my first linux driver, so there's probably a lot of room
	22	* for optimizations and bug fixing, so feel free to do it.
	23	* - use idebus=xx parameter to set PCI bus speed - needed to calc
	24	* timings for PIO modes (default will be 40)
	25	* - if using PIO mode it's a good idea to set the PIO mode and
	26	* 32-bit I/O support (if possible), e.g. hdparm -p2 -c1 /dev/hda
	27	* - I had some problems with my IBM DHEA with PIO modes < 2
	28	* (lost interrupts) ?????
	29	* - first tests with DMA look okay, they seem to work, but there is a
	30	* problem with sound - the BusMaster IDE TimeOut should fixed this
	31	*
	32	* Ancient History:
	33	* AMH@1999-08-24: v0.34 init_cy82c693_chip moved to pci_init_cy82c693
	34	* ASK@1999-01-23: v0.33 made a few minor code clean ups
	35	* removed DMA clock speed setting by default
	36	* added boot message
	37	* ASK@1998-11-01: v0.32 added support to set BusMaster IDE TimeOut
	38	* added support to set DMA Controller Clock Speed
	39	* ASK@1998-10-31: v0.31 fixed problem with setting to high DMA modes
	40	* on some drives.
	41	* ASK@1998-10-29: v0.3 added support to set DMA modes
	42	* ASK@1998-10-28: v0.2 added support to set PIO modes
	43	* ASK@1998-10-27: v0.1 first version - chipset detection
	44	*
	45	*/
	46
1da177e4 LT	47	#include <linux/module.h>
	48	#include <linux/types.h>
	49	#include <linux/pci.h>
	50	#include <linux/delay.h>
	51	#include <linux/ide.h>
	52	#include <linux/init.h>
	53
	54	#include <asm/io.h>
	55
	56	/* the current version */
	57	#define CY82_VERSION "CY82C693U driver v0.34 99-13-12 Andreas S. Krebs (akrebs@altavista.net)"
	58
	59	/*
	60	* The following are used to debug the driver.
	61	*/
	62	#define CY82C693_DEBUG_LOGS 0
	63	#define CY82C693_DEBUG_INFO 0
	64
	65	/* define CY82C693_SETDMA_CLOCK to set DMA Controller Clock Speed to ATCLK */
	66	#undef CY82C693_SETDMA_CLOCK
	67
	68	/*
	69	* NOTE: the value for busmaster timeout is tricky and I got it by
	70	* trial and error! By using a to low value will cause DMA timeouts
	71	* and drop IDE performance, and by using a to high value will cause
	72	* audio playback to scatter.
	73	* If you know a better value or how to calc it, please let me know.
	74	*/
	75
	76	/* twice the value written in cy82c693ub datasheet */
	77	#define BUSMASTER_TIMEOUT 0x50
	78	/*
	79	* the value above was tested on my machine and it seems to work okay
	80	*/
	81
	82	/* here are the offset definitions for the registers */
	83	#define CY82_IDE_CMDREG 0x04
	84	#define CY82_IDE_ADDRSETUP 0x48
	85	#define CY82_IDE_MASTER_IOR 0x4C
	86	#define CY82_IDE_MASTER_IOW 0x4D
	87	#define CY82_IDE_SLAVE_IOR 0x4E
	88	#define CY82_IDE_SLAVE_IOW 0x4F
	89	#define CY82_IDE_MASTER_8BIT 0x50
	90	#define CY82_IDE_SLAVE_8BIT 0x51
	91
	92	#define CY82_INDEX_PORT 0x22
	93	#define CY82_DATA_PORT 0x23
	94
	95	#define CY82_INDEX_CTRLREG1 0x01
	96	#define CY82_INDEX_CHANNEL0 0x30
	97	#define CY82_INDEX_CHANNEL1 0x31
	98	#define CY82_INDEX_TIMEOUT 0x32
	99
1da177e4 LT	100	/* the min and max PCI bus speed in MHz - from datasheet */
	101	#define CY82C963_MIN_BUS_SPEED 25
	102	#define CY82C963_MAX_BUS_SPEED 33
	103
	104	/* the struct for the PIO mode timings */
	105	typedef struct pio_clocks_s {
	106	u8 address_time; /* Address setup (clocks) */
	107	u8 time_16r; /* clocks for 16bit IOR (0xF0=Active/data, 0x0F=Recovery) */
	108	u8 time_16w; /* clocks for 16bit IOW (0xF0=Active/data, 0x0F=Recovery) */
	109	u8 time_8; /* clocks for 8bit (0xF0=Active/data, 0x0F=Recovery) */
	110	} pio_clocks_t;
	111
	112	/*
	113	* calc clocks using bus_speed
	114	* returns (rounded up) time in bus clocks for time in ns
	115	*/
	116	static int calc_clk (int time, int bus_speed)
	117	{
	118	int clocks;
	119
	120	clocks = (time*bus_speed+999)/1000 -1;
	121
	122	if (clocks < 0)
	123	clocks = 0;
	124
	125	if (clocks > 0x0F)
	126	clocks = 0x0F;
	127
	128	return clocks;
	129	}
	130
	131	/*
	132	* compute the values for the clock registers for PIO
	133	* mode and pci_clk [MHz] speed
	134	*
	135	* NOTE: for mode 0,1 and 2 drives 8-bit IDE command control registers are used
	136	* for mode 3 and 4 drives 8 and 16-bit timings are the same
	137	*
	138	*/
	139	static void compute_clocks (u8 pio, pio_clocks_t *p_pclk)
	140	{
	141	int clk1, clk2;
	142	int bus_speed = system_bus_clock(); /* get speed of PCI bus */
	143
	144	/* we don't check against CY82C693's min and max speed,
	145	* so you can play with the idebus=xx parameter
	146	*/
	147
1da177e4 LT	148	/* let's calc the address setup time clocks */
	149	p_pclk->address_time = (u8)calc_clk(ide_pio_timings[pio].setup_time, bus_speed);
	150
	151	/* let's calc the active and recovery time clocks */
	152	clk1 = calc_clk(ide_pio_timings[pio].active_time, bus_speed);
	153
	154	/* calc recovery timing */
	155	clk2 = ide_pio_timings[pio].cycle_time -
	156	ide_pio_timings[pio].active_time -
	157	ide_pio_timings[pio].setup_time;
	158
	159	clk2 = calc_clk(clk2, bus_speed);
	160
	161	clk1 = (clk1<<4)\|clk2; /* combine active and recovery clocks */
	162
	163	/* note: we use the same values for 16bit IOR and IOW
	164	* those are all the same, since I don't have other
	165	* timings than those from ide-lib.c
	166	*/
	167
	168	p_pclk->time_16r = (u8)clk1;
	169	p_pclk->time_16w = (u8)clk1;
	170
	171	/* what are good values for 8bit ?? */
	172	p_pclk->time_8 = (u8)clk1;
	173	}
	174
	175	/*
	176	* set DMA mode a specific channel for CY82C693
	177	*/
	178
	179	static void cy82c693_dma_enable (ide_drive_t *drive, int mode, int single)
	180	{
	181	u8 index = 0, data = 0;
	182
	183	if (mode>2) /* make sure we set a valid mode */
	184	mode = 2;
	185
	186	if (mode > drive->id->tDMA) /* to be absolutly sure we have a valid mode */
	187	mode = drive->id->tDMA;
	188
	189	index = (HWIF(drive)->channel==0) ? CY82_INDEX_CHANNEL0 : CY82_INDEX_CHANNEL1;
	190
	191	#if CY82C693_DEBUG_LOGS
	192	/* for debug let's show the previous values */
	193
0ecdca26 BZ	194	outb(index, CY82_INDEX_PORT);
0ecdca26 BZ	195	data = inb(CY82_DATA_PORT);
1da177e4 LT	196
	197	printk (KERN_INFO "%s (ch=%d, dev=%d): DMA mode is %d (single=%d)\n",
	198	drive->name, HWIF(drive)->channel, drive->select.b.unit,
	199	(data&0x3), ((data>>2)&1));
	200	#endif /* CY82C693_DEBUG_LOGS */
	201
	202	data = (u8)mode\|(u8)(single<<2);
	203
0ecdca26 BZ	204	outb(index, CY82_INDEX_PORT);
0ecdca26 BZ	205	outb(data, CY82_DATA_PORT);
1da177e4 LT	206
	207	#if CY82C693_DEBUG_INFO
	208	printk(KERN_INFO "%s (ch=%d, dev=%d): set DMA mode to %d (single=%d)\n",
	209	drive->name, HWIF(drive)->channel, drive->select.b.unit,
	210	mode, single);
	211	#endif /* CY82C693_DEBUG_INFO */
	212
	213	/*
	214	* note: below we set the value for Bus Master IDE TimeOut Register
	215	* I'm not absolutly sure what this does, but it solved my problem
	216	* with IDE DMA and sound, so I now can play sound and work with
	217	* my IDE driver at the same time :-)
	218	*
	219	* If you know the correct (best) value for this register please
	220	* let me know - ASK
	221	*/
	222
	223	data = BUSMASTER_TIMEOUT;
0ecdca26 BZ	224	outb(CY82_INDEX_TIMEOUT, CY82_INDEX_PORT);
0ecdca26 BZ	225	outb(data, CY82_DATA_PORT);
1da177e4 LT	226
	227	#if CY82C693_DEBUG_INFO
	228	printk (KERN_INFO "%s: Set IDE Bus Master TimeOut Register to 0x%X\n",
	229	drive->name, data);
	230	#endif /* CY82C693_DEBUG_INFO */
	231	}
	232
	233	/*
	234	* used to set DMA mode for CY82C693 (single and multi modes)
	235	*/
	236	static int cy82c693_ide_dma_on (ide_drive_t *drive)
	237	{
	238	struct hd_driveid *id = drive->id;
	239
	240	#if CY82C693_DEBUG_INFO
	241	printk (KERN_INFO "dma_on: %s\n", drive->name);
	242	#endif /* CY82C693_DEBUG_INFO */
	243
	244	if (id != NULL) {
	245	/* Enable DMA on any drive that has DMA
	246	* (multi or single) enabled
	247	*/
	248	if (id->field_valid & 2) { /* regular DMA */
	249	int mmode, smode;
	250
	251	mmode = id->dma_mword & (id->dma_mword >> 8);
	252	smode = id->dma_1word & (id->dma_1word >> 8);
	253
	254	if (mmode != 0) {
	255	/* enable multi */
	256	cy82c693_dma_enable(drive, (mmode >> 1), 0);
	257	} else if (smode != 0) {
	258	/* enable single */
	259	cy82c693_dma_enable(drive, (smode >> 1), 1);
	260	}
	261	}
	262	}
	263	return __ide_dma_on(drive);
	264	}
	265
26bcb879	266	static void cy82c693_set_pio_mode(ide_drive_t *drive, const u8 pio)
1da177e4 LT	267	{
	268	ide_hwif_t *hwif = HWIF(drive);
	269	struct pci_dev *dev = hwif->pci_dev;
	270	pio_clocks_t pclk;
	271	unsigned int addrCtrl;
	272
	273	/* select primary or secondary channel */
	274	if (hwif->index > 0) { /* drive is on the secondary channel */
652aa162	275	dev = pci_get_slot(dev->bus, dev->devfn+1);
1da177e4 LT	276	if (!dev) {
	277	printk(KERN_ERR "%s: tune_drive: "
	278	"Cannot find secondary interface!\n",
	279	drive->name);
	280	return;
	281	}
	282	}
	283
	284	#if CY82C693_DEBUG_LOGS
	285	/* for debug let's show the register values */
	286
	287	if (drive->select.b.unit == 0) {
	288	/*
	289	* get master drive registers
	290	* address setup control register
	291	* is 32 bit !!!
	292	*/
	293	pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
	294	addrCtrl &= 0x0F;
	295
	296	/* now let's get the remaining registers */
	297	pci_read_config_byte(dev, CY82_IDE_MASTER_IOR, &pclk.time_16r);
	298	pci_read_config_byte(dev, CY82_IDE_MASTER_IOW, &pclk.time_16w);
	299	pci_read_config_byte(dev, CY82_IDE_MASTER_8BIT, &pclk.time_8);
	300	} else {
	301	/*
	302	* set slave drive registers
	303	* address setup control register
	304	* is 32 bit !!!
	305	*/
	306	pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
	307
	308	addrCtrl &= 0xF0;
	309	addrCtrl >>= 4;
	310
	311	/* now let's get the remaining registers */
	312	pci_read_config_byte(dev, CY82_IDE_SLAVE_IOR, &pclk.time_16r);
	313	pci_read_config_byte(dev, CY82_IDE_SLAVE_IOW, &pclk.time_16w);
	314	pci_read_config_byte(dev, CY82_IDE_SLAVE_8BIT, &pclk.time_8);
	315	}
	316
	317	printk(KERN_INFO "%s (ch=%d, dev=%d): PIO timing is "
	318	"(addr=0x%X, ior=0x%X, iow=0x%X, 8bit=0x%X)\n",
	319	drive->name, hwif->channel, drive->select.b.unit,
	320	addrCtrl, pclk.time_16r, pclk.time_16w, pclk.time_8);
	321	#endif /* CY82C693_DEBUG_LOGS */
	322
1da177e4 LT	323	/* let's calc the values for this PIO mode */
	324	compute_clocks(pio, &pclk);
	325
	326	/* now let's write the clocks registers */
	327	if (drive->select.b.unit == 0) {
	328	/*
	329	* set master drive
	330	* address setup control register
	331	* is 32 bit !!!
	332	*/
	333	pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
	334
	335	addrCtrl &= (~0xF);
	336	addrCtrl \|= (unsigned int)pclk.address_time;
	337	pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl);
	338
	339	/* now let's set the remaining registers */
	340	pci_write_config_byte(dev, CY82_IDE_MASTER_IOR, pclk.time_16r);
	341	pci_write_config_byte(dev, CY82_IDE_MASTER_IOW, pclk.time_16w);
	342	pci_write_config_byte(dev, CY82_IDE_MASTER_8BIT, pclk.time_8);
	343
	344	addrCtrl &= 0xF;
	345	} else {
	346	/*
	347	* set slave drive
	348	* address setup control register
	349	* is 32 bit !!!
	350	*/
	351	pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
	352
	353	addrCtrl &= (~0xF0);
	354	addrCtrl \|= ((unsigned int)pclk.address_time<<4);
	355	pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl);
	356
	357	/* now let's set the remaining registers */
	358	pci_write_config_byte(dev, CY82_IDE_SLAVE_IOR, pclk.time_16r);
	359	pci_write_config_byte(dev, CY82_IDE_SLAVE_IOW, pclk.time_16w);
	360	pci_write_config_byte(dev, CY82_IDE_SLAVE_8BIT, pclk.time_8);
	361
	362	addrCtrl >>= 4;
	363	addrCtrl &= 0xF;
	364	}
	365
	366	#if CY82C693_DEBUG_INFO
	367	printk(KERN_INFO "%s (ch=%d, dev=%d): set PIO timing to "
	368	"(addr=0x%X, ior=0x%X, iow=0x%X, 8bit=0x%X)\n",
	369	drive->name, hwif->channel, drive->select.b.unit,
	370	addrCtrl, pclk.time_16r, pclk.time_16w, pclk.time_8);
	371	#endif /* CY82C693_DEBUG_INFO */
	372	}
	373
	374	/*
	375	* this function is called during init and is used to setup the cy82c693 chip
	376	*/
ddbc9fb4	377	static unsigned int __devinit init_chipset_cy82c693(struct pci_dev dev, const char name)
1da177e4 LT	378	{
	379	if (PCI_FUNC(dev->devfn) != 1)
	380	return 0;
	381
	382	#ifdef CY82C693_SETDMA_CLOCK
	383	u8 data = 0;
	384	#endif /* CY82C693_SETDMA_CLOCK */
	385
	386	/* write info about this verion of the driver */
	387	printk(KERN_INFO CY82_VERSION "\n");
	388
	389	#ifdef CY82C693_SETDMA_CLOCK
	390	/* okay let's set the DMA clock speed */
	391
	392	outb(CY82_INDEX_CTRLREG1, CY82_INDEX_PORT);
	393	data = inb(CY82_DATA_PORT);
	394
	395	#if CY82C693_DEBUG_INFO
	396	printk(KERN_INFO "%s: Peripheral Configuration Register: 0x%X\n",
	397	name, data);
	398	#endif /* CY82C693_DEBUG_INFO */
	399
	400	/*
	401	* for some reason sometimes the DMA controller
	402	* speed is set to ATCLK/2 ???? - we fix this here
	403	*
	404	* note: i don't know what causes this strange behaviour,
	405	* but even changing the dma speed doesn't solve it :-(
	406	* the ide performance is still only half the normal speed
	407	*
	408	* if anybody knows what goes wrong with my machine, please
	409	* let me know - ASK
	410	*/
	411
	412	data \|= 0x03;
	413
	414	outb(CY82_INDEX_CTRLREG1, CY82_INDEX_PORT);
	415	outb(data, CY82_DATA_PORT);
	416
	417	#if CY82C693_DEBUG_INFO
	418	printk (KERN_INFO "%s: New Peripheral Configuration Register: 0x%X\n",
	419	name, data);
	420	#endif /* CY82C693_DEBUG_INFO */
	421
	422	#endif /* CY82C693_SETDMA_CLOCK */
	423	return 0;
	424	}
	425
	426	/*
	427	* the init function - called for each ide channel once
	428	*/
ddbc9fb4	429	static void __devinit init_hwif_cy82c693(ide_hwif_t *hwif)
1da177e4	430	{
1da177e4	431	hwif->chipset = ide_cy82c693;
26bcb879	432	hwif->set_pio_mode = &cy82c693_set_pio_mode;
1da177e4 LT	433
	434	if (!hwif->dma_base) {
	435	hwif->drives[0].autotune = 1;
	436	hwif->drives[1].autotune = 1;
	437	return;
	438	}
	439
1da177e4 LT	440	hwif->mwdma_mask = 0x04;
	441	hwif->swdma_mask = 0x04;
	442
	443	hwif->ide_dma_on = &cy82c693_ide_dma_on;
1da177e4 LT	444	}
1da177e4 LT	445
ddbc9fb4	446	static __devinitdata ide_hwif_t *primary;
1da177e4	447
e851b620	448	static void __devinit init_iops_cy82c693(ide_hwif_t *hwif)
1da177e4 LT	449	{
	450	if (PCI_FUNC(hwif->pci_dev->devfn) == 1)
	451	primary = hwif;
	452	else {
	453	hwif->mate = primary;
	454	hwif->channel = 1;
	455	}
	456	}
	457
7b77d864 BZ	458	static ide_pci_device_t cy82c693_chipset __devinitdata = {
	459	.name = "CY82C693",
	460	.init_chipset = init_chipset_cy82c693,
	461	.init_iops = init_iops_cy82c693,
	462	.init_hwif = init_hwif_cy82c693,
7cab14a7 BZ	463	.host_flags = IDE_HFLAG_SINGLE \| IDE_HFLAG_TRUST_BIOS_FOR_DMA \|
7cab14a7 BZ	464	IDE_HFLAG_BOOTABLE,
4099d143	465	.pio_mask = ATA_PIO4,
1da177e4 LT	466	};
	467
	468	static int __devinit cy82c693_init_one(struct pci_dev dev, const struct pci_device_id id)
	469	{
1da177e4 LT	470	struct pci_dev *dev2;
	471	int ret = -ENODEV;
	472
	473	/* CY82C693 is more than only a IDE controller.
	474	Function 1 is primary IDE channel, function 2 - secondary. */
	475	if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE &&
	476	PCI_FUNC(dev->devfn) == 1) {
652aa162	477	dev2 = pci_get_slot(dev->bus, dev->devfn + 1);
7b77d864	478	ret = ide_setup_pci_devices(dev, dev2, &cy82c693_chipset);
652aa162	479	/* We leak pci refs here but thats ok - we can't be unloaded */
1da177e4 LT	480	}
	481	return ret;
	482	}
	483
9cbcc5e3 BZ	484	static const struct pci_device_id cy82c693_pci_tbl[] = {
9cbcc5e3 BZ	485	{ PCI_VDEVICE(CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693), 0 },
1da177e4 LT	486	{ 0, },
	487	};
	488	MODULE_DEVICE_TABLE(pci, cy82c693_pci_tbl);
	489
	490	static struct pci_driver driver = {
	491	.name = "Cypress_IDE",
	492	.id_table = cy82c693_pci_tbl,
	493	.probe = cy82c693_init_one,
	494	};
	495
82ab1eec	496	static int __init cy82c693_ide_init(void)
1da177e4 LT	497	{
	498	return ide_pci_register_driver(&driver);
	499	}
	500
	501	module_init(cy82c693_ide_init);
	502
	503	MODULE_AUTHOR("Andreas Krebs, Andre Hedrick");
	504	MODULE_DESCRIPTION("PCI driver module for the Cypress CY82C693 IDE");
	505	MODULE_LICENSE("GPL");