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26a940e2 PP |
1 | /* |
2 | * linux/drivers/ide/mips/au1xxx-ide.c version 01.30.00 Aug. 02 2005 | |
3 | * | |
4 | * BRIEF MODULE DESCRIPTION | |
5 | * AMD Alchemy Au1xxx IDE interface routines over the Static Bus | |
6 | * | |
7 | * Copyright (c) 2003-2005 AMD, Personal Connectivity Solutions | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it under | |
10 | * the terms of the GNU General Public License as published by the Free Software | |
11 | * Foundation; either version 2 of the License, or (at your option) any later | |
12 | * version. | |
13 | * | |
14 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, | |
15 | * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND | |
16 | * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR | |
17 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
18 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
19 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
20 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | |
21 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
22 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | |
23 | * POSSIBILITY OF SUCH DAMAGE. | |
24 | * | |
25 | * You should have received a copy of the GNU General Public License along with | |
26 | * this program; if not, write to the Free Software Foundation, Inc., | |
27 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
28 | * | |
29 | * Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE | |
30 | * Interface and Linux Device Driver" Application Note. | |
31 | */ | |
26a940e2 PP |
32 | #include <linux/types.h> |
33 | #include <linux/module.h> | |
34 | #include <linux/kernel.h> | |
35 | #include <linux/delay.h> | |
8f29e650 JC |
36 | #include <linux/platform_device.h> |
37 | ||
26a940e2 PP |
38 | #include <linux/init.h> |
39 | #include <linux/ide.h> | |
40 | #include <linux/sysdev.h> | |
41 | ||
42 | #include <linux/dma-mapping.h> | |
43 | ||
8f29e650 JC |
44 | #include "ide-timing.h" |
45 | ||
26a940e2 PP |
46 | #include <asm/io.h> |
47 | #include <asm/mach-au1x00/au1xxx.h> | |
48 | #include <asm/mach-au1x00/au1xxx_dbdma.h> | |
49 | ||
26a940e2 PP |
50 | #include <asm/mach-au1x00/au1xxx_ide.h> |
51 | ||
52 | #define DRV_NAME "au1200-ide" | |
53 | #define DRV_VERSION "1.0" | |
8f29e650 | 54 | #define DRV_AUTHOR "Enrico Walther <enrico.walther@amd.com> / Pete Popov <ppopov@embeddedalley.com>" |
26a940e2 | 55 | |
8f29e650 JC |
56 | /* enable the burstmode in the dbdma */ |
57 | #define IDE_AU1XXX_BURSTMODE 1 | |
26a940e2 | 58 | |
8f29e650 JC |
59 | static _auide_hwif auide_hwif; |
60 | static int dbdma_init_done; | |
26a940e2 | 61 | |
26a940e2 PP |
62 | #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA) |
63 | ||
8f29e650 | 64 | void auide_insw(unsigned long port, void *addr, u32 count) |
26a940e2 | 65 | { |
8f29e650 JC |
66 | _auide_hwif *ahwif = &auide_hwif; |
67 | chan_tab_t *ctp; | |
68 | au1x_ddma_desc_t *dp; | |
26a940e2 | 69 | |
8f29e650 JC |
70 | if(!put_dest_flags(ahwif->rx_chan, (void*)addr, count << 1, |
71 | DDMA_FLAGS_NOIE)) { | |
72 | printk(KERN_ERR "%s failed %d\n", __FUNCTION__, __LINE__); | |
73 | return; | |
74 | } | |
75 | ctp = *((chan_tab_t **)ahwif->rx_chan); | |
76 | dp = ctp->cur_ptr; | |
77 | while (dp->dscr_cmd0 & DSCR_CMD0_V) | |
78 | ; | |
79 | ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp); | |
26a940e2 PP |
80 | } |
81 | ||
8f29e650 | 82 | void auide_outsw(unsigned long port, void *addr, u32 count) |
26a940e2 | 83 | { |
8f29e650 JC |
84 | _auide_hwif *ahwif = &auide_hwif; |
85 | chan_tab_t *ctp; | |
86 | au1x_ddma_desc_t *dp; | |
26a940e2 | 87 | |
8f29e650 JC |
88 | if(!put_source_flags(ahwif->tx_chan, (void*)addr, |
89 | count << 1, DDMA_FLAGS_NOIE)) { | |
90 | printk(KERN_ERR "%s failed %d\n", __FUNCTION__, __LINE__); | |
91 | return; | |
92 | } | |
93 | ctp = *((chan_tab_t **)ahwif->tx_chan); | |
94 | dp = ctp->cur_ptr; | |
95 | while (dp->dscr_cmd0 & DSCR_CMD0_V) | |
96 | ; | |
97 | ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp); | |
26a940e2 PP |
98 | } |
99 | ||
26a940e2 | 100 | #endif |
26a940e2 | 101 | |
26bcb879 | 102 | static void au1xxx_set_pio_mode(ide_drive_t *drive, const u8 pio) |
26a940e2 | 103 | { |
88b2b32b | 104 | int mem_sttime = 0, mem_stcfg = au_readl(MEM_STCFG2); |
8f29e650 JC |
105 | |
106 | /* set pio mode! */ | |
107 | switch(pio) { | |
108 | case 0: | |
109 | mem_sttime = SBC_IDE_TIMING(PIO0); | |
110 | ||
111 | /* set configuration for RCS2# */ | |
112 | mem_stcfg |= TS_MASK; | |
113 | mem_stcfg &= ~TCSOE_MASK; | |
114 | mem_stcfg &= ~TOECS_MASK; | |
115 | mem_stcfg |= SBC_IDE_PIO0_TCSOE | SBC_IDE_PIO0_TOECS; | |
116 | break; | |
117 | ||
118 | case 1: | |
119 | mem_sttime = SBC_IDE_TIMING(PIO1); | |
120 | ||
121 | /* set configuration for RCS2# */ | |
122 | mem_stcfg |= TS_MASK; | |
123 | mem_stcfg &= ~TCSOE_MASK; | |
124 | mem_stcfg &= ~TOECS_MASK; | |
125 | mem_stcfg |= SBC_IDE_PIO1_TCSOE | SBC_IDE_PIO1_TOECS; | |
126 | break; | |
127 | ||
128 | case 2: | |
129 | mem_sttime = SBC_IDE_TIMING(PIO2); | |
130 | ||
131 | /* set configuration for RCS2# */ | |
132 | mem_stcfg &= ~TS_MASK; | |
133 | mem_stcfg &= ~TCSOE_MASK; | |
134 | mem_stcfg &= ~TOECS_MASK; | |
135 | mem_stcfg |= SBC_IDE_PIO2_TCSOE | SBC_IDE_PIO2_TOECS; | |
136 | break; | |
137 | ||
138 | case 3: | |
139 | mem_sttime = SBC_IDE_TIMING(PIO3); | |
140 | ||
141 | /* set configuration for RCS2# */ | |
142 | mem_stcfg &= ~TS_MASK; | |
143 | mem_stcfg &= ~TCSOE_MASK; | |
144 | mem_stcfg &= ~TOECS_MASK; | |
145 | mem_stcfg |= SBC_IDE_PIO3_TCSOE | SBC_IDE_PIO3_TOECS; | |
146 | ||
147 | break; | |
148 | ||
149 | case 4: | |
150 | mem_sttime = SBC_IDE_TIMING(PIO4); | |
151 | ||
152 | /* set configuration for RCS2# */ | |
153 | mem_stcfg &= ~TS_MASK; | |
154 | mem_stcfg &= ~TCSOE_MASK; | |
155 | mem_stcfg &= ~TOECS_MASK; | |
156 | mem_stcfg |= SBC_IDE_PIO4_TCSOE | SBC_IDE_PIO4_TOECS; | |
157 | break; | |
158 | } | |
159 | ||
160 | au_writel(mem_sttime,MEM_STTIME2); | |
161 | au_writel(mem_stcfg,MEM_STCFG2); | |
26a940e2 PP |
162 | } |
163 | ||
88b2b32b | 164 | static void auide_set_dma_mode(ide_drive_t *drive, const u8 speed) |
26a940e2 | 165 | { |
88b2b32b | 166 | int mem_sttime = 0, mem_stcfg = au_readl(MEM_STCFG2); |
26a940e2 | 167 | |
8f29e650 | 168 | switch(speed) { |
26a940e2 | 169 | #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA |
8f29e650 JC |
170 | case XFER_MW_DMA_2: |
171 | mem_sttime = SBC_IDE_TIMING(MDMA2); | |
172 | ||
173 | /* set configuration for RCS2# */ | |
174 | mem_stcfg &= ~TS_MASK; | |
175 | mem_stcfg &= ~TCSOE_MASK; | |
176 | mem_stcfg &= ~TOECS_MASK; | |
177 | mem_stcfg |= SBC_IDE_MDMA2_TCSOE | SBC_IDE_MDMA2_TOECS; | |
178 | ||
8f29e650 JC |
179 | break; |
180 | case XFER_MW_DMA_1: | |
181 | mem_sttime = SBC_IDE_TIMING(MDMA1); | |
182 | ||
183 | /* set configuration for RCS2# */ | |
184 | mem_stcfg &= ~TS_MASK; | |
185 | mem_stcfg &= ~TCSOE_MASK; | |
186 | mem_stcfg &= ~TOECS_MASK; | |
187 | mem_stcfg |= SBC_IDE_MDMA1_TCSOE | SBC_IDE_MDMA1_TOECS; | |
188 | ||
8f29e650 JC |
189 | break; |
190 | case XFER_MW_DMA_0: | |
191 | mem_sttime = SBC_IDE_TIMING(MDMA0); | |
192 | ||
193 | /* set configuration for RCS2# */ | |
194 | mem_stcfg |= TS_MASK; | |
195 | mem_stcfg &= ~TCSOE_MASK; | |
196 | mem_stcfg &= ~TOECS_MASK; | |
197 | mem_stcfg |= SBC_IDE_MDMA0_TCSOE | SBC_IDE_MDMA0_TOECS; | |
198 | ||
8f29e650 | 199 | break; |
26a940e2 | 200 | #endif |
8f29e650 | 201 | } |
a523a175 | 202 | |
8f29e650 JC |
203 | au_writel(mem_sttime,MEM_STTIME2); |
204 | au_writel(mem_stcfg,MEM_STCFG2); | |
26a940e2 PP |
205 | } |
206 | ||
207 | /* | |
208 | * Multi-Word DMA + DbDMA functions | |
209 | */ | |
26a940e2 | 210 | |
8f29e650 | 211 | #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA |
26a940e2 PP |
212 | |
213 | static int auide_build_sglist(ide_drive_t *drive, struct request *rq) | |
214 | { | |
8f29e650 JC |
215 | ide_hwif_t *hwif = drive->hwif; |
216 | _auide_hwif *ahwif = (_auide_hwif*)hwif->hwif_data; | |
217 | struct scatterlist *sg = hwif->sg_table; | |
26a940e2 | 218 | |
8f29e650 | 219 | ide_map_sg(drive, rq); |
26a940e2 | 220 | |
8f29e650 JC |
221 | if (rq_data_dir(rq) == READ) |
222 | hwif->sg_dma_direction = DMA_FROM_DEVICE; | |
223 | else | |
224 | hwif->sg_dma_direction = DMA_TO_DEVICE; | |
26a940e2 | 225 | |
8f29e650 JC |
226 | return dma_map_sg(ahwif->dev, sg, hwif->sg_nents, |
227 | hwif->sg_dma_direction); | |
26a940e2 PP |
228 | } |
229 | ||
230 | static int auide_build_dmatable(ide_drive_t *drive) | |
231 | { | |
8f29e650 JC |
232 | int i, iswrite, count = 0; |
233 | ide_hwif_t *hwif = HWIF(drive); | |
234 | ||
235 | struct request *rq = HWGROUP(drive)->rq; | |
236 | ||
237 | _auide_hwif *ahwif = (_auide_hwif*)hwif->hwif_data; | |
238 | struct scatterlist *sg; | |
239 | ||
240 | iswrite = (rq_data_dir(rq) == WRITE); | |
241 | /* Save for interrupt context */ | |
242 | ahwif->drive = drive; | |
243 | ||
244 | /* Build sglist */ | |
245 | hwif->sg_nents = i = auide_build_sglist(drive, rq); | |
246 | ||
247 | if (!i) | |
248 | return 0; | |
249 | ||
250 | /* fill the descriptors */ | |
251 | sg = hwif->sg_table; | |
252 | while (i && sg_dma_len(sg)) { | |
253 | u32 cur_addr; | |
254 | u32 cur_len; | |
255 | ||
256 | cur_addr = sg_dma_address(sg); | |
257 | cur_len = sg_dma_len(sg); | |
258 | ||
259 | while (cur_len) { | |
260 | u32 flags = DDMA_FLAGS_NOIE; | |
261 | unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00; | |
262 | ||
263 | if (++count >= PRD_ENTRIES) { | |
264 | printk(KERN_WARNING "%s: DMA table too small\n", | |
265 | drive->name); | |
266 | goto use_pio_instead; | |
267 | } | |
268 | ||
269 | /* Lets enable intr for the last descriptor only */ | |
270 | if (1==i) | |
271 | flags = DDMA_FLAGS_IE; | |
272 | else | |
273 | flags = DDMA_FLAGS_NOIE; | |
274 | ||
275 | if (iswrite) { | |
276 | if(!put_source_flags(ahwif->tx_chan, | |
45711f1a | 277 | (void*) sg_virt(sg), |
8f29e650 JC |
278 | tc, flags)) { |
279 | printk(KERN_ERR "%s failed %d\n", | |
280 | __FUNCTION__, __LINE__); | |
26a940e2 | 281 | } |
8f29e650 | 282 | } else |
26a940e2 | 283 | { |
8f29e650 | 284 | if(!put_dest_flags(ahwif->rx_chan, |
45711f1a | 285 | (void*) sg_virt(sg), |
8f29e650 JC |
286 | tc, flags)) { |
287 | printk(KERN_ERR "%s failed %d\n", | |
288 | __FUNCTION__, __LINE__); | |
26a940e2 | 289 | } |
8f29e650 | 290 | } |
26a940e2 | 291 | |
8f29e650 JC |
292 | cur_addr += tc; |
293 | cur_len -= tc; | |
294 | } | |
55c16a70 | 295 | sg = sg_next(sg); |
8f29e650 JC |
296 | i--; |
297 | } | |
26a940e2 | 298 | |
8f29e650 JC |
299 | if (count) |
300 | return 1; | |
26a940e2 | 301 | |
8f29e650 JC |
302 | use_pio_instead: |
303 | dma_unmap_sg(ahwif->dev, | |
304 | hwif->sg_table, | |
305 | hwif->sg_nents, | |
306 | hwif->sg_dma_direction); | |
26a940e2 | 307 | |
8f29e650 | 308 | return 0; /* revert to PIO for this request */ |
26a940e2 PP |
309 | } |
310 | ||
311 | static int auide_dma_end(ide_drive_t *drive) | |
312 | { | |
8f29e650 JC |
313 | ide_hwif_t *hwif = HWIF(drive); |
314 | _auide_hwif *ahwif = (_auide_hwif*)hwif->hwif_data; | |
26a940e2 | 315 | |
8f29e650 JC |
316 | if (hwif->sg_nents) { |
317 | dma_unmap_sg(ahwif->dev, hwif->sg_table, hwif->sg_nents, | |
318 | hwif->sg_dma_direction); | |
319 | hwif->sg_nents = 0; | |
320 | } | |
26a940e2 | 321 | |
8f29e650 | 322 | return 0; |
26a940e2 PP |
323 | } |
324 | ||
325 | static void auide_dma_start(ide_drive_t *drive ) | |
326 | { | |
26a940e2 PP |
327 | } |
328 | ||
26a940e2 PP |
329 | |
330 | static void auide_dma_exec_cmd(ide_drive_t *drive, u8 command) | |
331 | { | |
8f29e650 JC |
332 | /* issue cmd to drive */ |
333 | ide_execute_command(drive, command, &ide_dma_intr, | |
334 | (2*WAIT_CMD), NULL); | |
26a940e2 PP |
335 | } |
336 | ||
337 | static int auide_dma_setup(ide_drive_t *drive) | |
8f29e650 JC |
338 | { |
339 | struct request *rq = HWGROUP(drive)->rq; | |
26a940e2 | 340 | |
8f29e650 JC |
341 | if (!auide_build_dmatable(drive)) { |
342 | ide_map_sg(drive, rq); | |
343 | return 1; | |
344 | } | |
26a940e2 | 345 | |
8f29e650 JC |
346 | drive->waiting_for_dma = 1; |
347 | return 0; | |
26a940e2 PP |
348 | } |
349 | ||
8446f659 | 350 | static u8 auide_mdma_filter(ide_drive_t *drive) |
26a940e2 | 351 | { |
8446f659 BZ |
352 | /* |
353 | * FIXME: ->white_list and ->black_list are based on completely bogus | |
354 | * ->ide_dma_check implementation which didn't set neither the host | |
355 | * controller timings nor the device for the desired transfer mode. | |
356 | * | |
357 | * They should be either removed or 0x00 MWDMA mask should be | |
358 | * returned for devices on the ->black_list. | |
359 | */ | |
8f29e650 | 360 | |
8446f659 | 361 | if (dbdma_init_done == 0) { |
8f29e650 JC |
362 | auide_hwif.white_list = ide_in_drive_list(drive->id, |
363 | dma_white_list); | |
364 | auide_hwif.black_list = ide_in_drive_list(drive->id, | |
365 | dma_black_list); | |
366 | auide_hwif.drive = drive; | |
367 | auide_ddma_init(&auide_hwif); | |
368 | dbdma_init_done = 1; | |
369 | } | |
26a940e2 | 370 | |
8f29e650 | 371 | /* Is the drive in our DMA black list? */ |
8446f659 | 372 | if (auide_hwif.black_list) |
8f29e650 | 373 | printk(KERN_WARNING "%s: Disabling DMA for %s (blacklisted)\n", |
8446f659 | 374 | drive->name, drive->id->model); |
8f29e650 | 375 | |
8446f659 BZ |
376 | return drive->hwif->mwdma_mask; |
377 | } | |
378 | ||
26a940e2 | 379 | static int auide_dma_test_irq(ide_drive_t *drive) |
8f29e650 JC |
380 | { |
381 | if (drive->waiting_for_dma == 0) | |
382 | printk(KERN_WARNING "%s: ide_dma_test_irq \ | |
26a940e2 PP |
383 | called while not waiting\n", drive->name); |
384 | ||
8f29e650 JC |
385 | /* If dbdma didn't execute the STOP command yet, the |
386 | * active bit is still set | |
26a940e2 | 387 | */ |
8f29e650 JC |
388 | drive->waiting_for_dma++; |
389 | if (drive->waiting_for_dma >= DMA_WAIT_TIMEOUT) { | |
390 | printk(KERN_WARNING "%s: timeout waiting for ddma to \ | |
26a940e2 | 391 | complete\n", drive->name); |
8f29e650 JC |
392 | return 1; |
393 | } | |
394 | udelay(10); | |
395 | return 0; | |
26a940e2 PP |
396 | } |
397 | ||
ccf35289 | 398 | static void auide_dma_host_on(ide_drive_t *drive) |
26a940e2 | 399 | { |
26a940e2 PP |
400 | } |
401 | ||
402 | static int auide_dma_on(ide_drive_t *drive) | |
403 | { | |
8f29e650 | 404 | drive->using_dma = 1; |
ccf35289 BZ |
405 | |
406 | return 0; | |
26a940e2 PP |
407 | } |
408 | ||
7469aaf6 | 409 | static void auide_dma_host_off(ide_drive_t *drive) |
26a940e2 | 410 | { |
26a940e2 PP |
411 | } |
412 | ||
7469aaf6 | 413 | static void auide_dma_off_quietly(ide_drive_t *drive) |
26a940e2 | 414 | { |
8f29e650 | 415 | drive->using_dma = 0; |
26a940e2 PP |
416 | } |
417 | ||
841d2a9b | 418 | static void auide_dma_lost_irq(ide_drive_t *drive) |
26a940e2 | 419 | { |
8f29e650 | 420 | printk(KERN_ERR "%s: IRQ lost\n", drive->name); |
26a940e2 PP |
421 | } |
422 | ||
53e62d3a | 423 | static void auide_ddma_tx_callback(int irq, void *param) |
26a940e2 | 424 | { |
8f29e650 JC |
425 | _auide_hwif *ahwif = (_auide_hwif*)param; |
426 | ahwif->drive->waiting_for_dma = 0; | |
26a940e2 PP |
427 | } |
428 | ||
53e62d3a | 429 | static void auide_ddma_rx_callback(int irq, void *param) |
26a940e2 | 430 | { |
8f29e650 JC |
431 | _auide_hwif *ahwif = (_auide_hwif*)param; |
432 | ahwif->drive->waiting_for_dma = 0; | |
433 | } | |
434 | ||
435 | #endif /* end CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */ | |
26a940e2 | 436 | |
8f29e650 JC |
437 | static void auide_init_dbdma_dev(dbdev_tab_t *dev, u32 dev_id, u32 tsize, u32 devwidth, u32 flags) |
438 | { | |
439 | dev->dev_id = dev_id; | |
440 | dev->dev_physaddr = (u32)AU1XXX_ATA_PHYS_ADDR; | |
441 | dev->dev_intlevel = 0; | |
442 | dev->dev_intpolarity = 0; | |
443 | dev->dev_tsize = tsize; | |
444 | dev->dev_devwidth = devwidth; | |
445 | dev->dev_flags = flags; | |
26a940e2 | 446 | } |
8f29e650 JC |
447 | |
448 | #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA) | |
26a940e2 | 449 | |
c283f5db | 450 | static void auide_dma_timeout(ide_drive_t *drive) |
26a940e2 | 451 | { |
c283f5db | 452 | ide_hwif_t *hwif = HWIF(drive); |
26a940e2 | 453 | |
8f29e650 | 454 | printk(KERN_ERR "%s: DMA timeout occurred: ", drive->name); |
26a940e2 | 455 | |
c283f5db SS |
456 | if (hwif->ide_dma_test_irq(drive)) |
457 | return; | |
26a940e2 | 458 | |
c283f5db | 459 | hwif->ide_dma_end(drive); |
26a940e2 | 460 | } |
8f29e650 | 461 | |
26a940e2 | 462 | |
8f29e650 JC |
463 | static int auide_ddma_init(_auide_hwif *auide) { |
464 | ||
465 | dbdev_tab_t source_dev_tab, target_dev_tab; | |
466 | u32 dev_id, tsize, devwidth, flags; | |
467 | ide_hwif_t *hwif = auide->hwif; | |
26a940e2 | 468 | |
8f29e650 | 469 | dev_id = AU1XXX_ATA_DDMA_REQ; |
26a940e2 | 470 | |
8f29e650 JC |
471 | if (auide->white_list || auide->black_list) { |
472 | tsize = 8; | |
473 | devwidth = 32; | |
474 | } | |
475 | else { | |
476 | tsize = 1; | |
477 | devwidth = 16; | |
478 | ||
479 | printk(KERN_ERR "au1xxx-ide: %s is not on ide driver whitelist.\n",auide_hwif.drive->id->model); | |
480 | printk(KERN_ERR " please read 'Documentation/mips/AU1xxx_IDE.README'"); | |
481 | } | |
26a940e2 | 482 | |
8f29e650 JC |
483 | #ifdef IDE_AU1XXX_BURSTMODE |
484 | flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE; | |
26a940e2 | 485 | #else |
8f29e650 | 486 | flags = DEV_FLAGS_SYNC; |
26a940e2 PP |
487 | #endif |
488 | ||
8f29e650 JC |
489 | /* setup dev_tab for tx channel */ |
490 | auide_init_dbdma_dev( &source_dev_tab, | |
491 | dev_id, | |
492 | tsize, devwidth, DEV_FLAGS_OUT | flags); | |
493 | auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab ); | |
494 | ||
495 | auide_init_dbdma_dev( &source_dev_tab, | |
496 | dev_id, | |
497 | tsize, devwidth, DEV_FLAGS_IN | flags); | |
498 | auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab ); | |
499 | ||
500 | /* We also need to add a target device for the DMA */ | |
501 | auide_init_dbdma_dev( &target_dev_tab, | |
502 | (u32)DSCR_CMD0_ALWAYS, | |
503 | tsize, devwidth, DEV_FLAGS_ANYUSE); | |
504 | auide->target_dev_id = au1xxx_ddma_add_device(&target_dev_tab); | |
505 | ||
506 | /* Get a channel for TX */ | |
507 | auide->tx_chan = au1xxx_dbdma_chan_alloc(auide->target_dev_id, | |
508 | auide->tx_dev_id, | |
509 | auide_ddma_tx_callback, | |
510 | (void*)auide); | |
511 | ||
512 | /* Get a channel for RX */ | |
513 | auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id, | |
514 | auide->target_dev_id, | |
515 | auide_ddma_rx_callback, | |
516 | (void*)auide); | |
517 | ||
518 | auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan, | |
519 | NUM_DESCRIPTORS); | |
520 | auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan, | |
521 | NUM_DESCRIPTORS); | |
522 | ||
523 | hwif->dmatable_cpu = dma_alloc_coherent(auide->dev, | |
524 | PRD_ENTRIES * PRD_BYTES, /* 1 Page */ | |
525 | &hwif->dmatable_dma, GFP_KERNEL); | |
526 | ||
527 | au1xxx_dbdma_start( auide->tx_chan ); | |
528 | au1xxx_dbdma_start( auide->rx_chan ); | |
529 | ||
530 | return 0; | |
531 | } | |
26a940e2 | 532 | #else |
8f29e650 JC |
533 | |
534 | static int auide_ddma_init( _auide_hwif *auide ) | |
535 | { | |
536 | dbdev_tab_t source_dev_tab; | |
537 | int flags; | |
26a940e2 | 538 | |
8f29e650 JC |
539 | #ifdef IDE_AU1XXX_BURSTMODE |
540 | flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE; | |
541 | #else | |
542 | flags = DEV_FLAGS_SYNC; | |
26a940e2 | 543 | #endif |
26a940e2 | 544 | |
8f29e650 JC |
545 | /* setup dev_tab for tx channel */ |
546 | auide_init_dbdma_dev( &source_dev_tab, | |
547 | (u32)DSCR_CMD0_ALWAYS, | |
548 | 8, 32, DEV_FLAGS_OUT | flags); | |
549 | auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab ); | |
550 | ||
551 | auide_init_dbdma_dev( &source_dev_tab, | |
552 | (u32)DSCR_CMD0_ALWAYS, | |
553 | 8, 32, DEV_FLAGS_IN | flags); | |
554 | auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab ); | |
555 | ||
556 | /* Get a channel for TX */ | |
557 | auide->tx_chan = au1xxx_dbdma_chan_alloc(DSCR_CMD0_ALWAYS, | |
558 | auide->tx_dev_id, | |
559 | NULL, | |
560 | (void*)auide); | |
561 | ||
562 | /* Get a channel for RX */ | |
563 | auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id, | |
564 | DSCR_CMD0_ALWAYS, | |
565 | NULL, | |
566 | (void*)auide); | |
567 | ||
568 | auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan, | |
569 | NUM_DESCRIPTORS); | |
570 | auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan, | |
571 | NUM_DESCRIPTORS); | |
572 | ||
573 | au1xxx_dbdma_start( auide->tx_chan ); | |
574 | au1xxx_dbdma_start( auide->rx_chan ); | |
575 | ||
576 | return 0; | |
26a940e2 | 577 | } |
8f29e650 | 578 | #endif |
26a940e2 PP |
579 | |
580 | static void auide_setup_ports(hw_regs_t *hw, _auide_hwif *ahwif) | |
581 | { | |
8f29e650 JC |
582 | int i; |
583 | unsigned long *ata_regs = hw->io_ports; | |
584 | ||
585 | /* FIXME? */ | |
586 | for (i = 0; i < IDE_CONTROL_OFFSET; i++) { | |
587 | *ata_regs++ = ahwif->regbase + (i << AU1XXX_ATA_REG_OFFSET); | |
588 | } | |
589 | ||
590 | /* set the Alternative Status register */ | |
591 | *ata_regs = ahwif->regbase + (14 << AU1XXX_ATA_REG_OFFSET); | |
26a940e2 PP |
592 | } |
593 | ||
594 | static int au_ide_probe(struct device *dev) | |
595 | { | |
596 | struct platform_device *pdev = to_platform_device(dev); | |
8f29e650 JC |
597 | _auide_hwif *ahwif = &auide_hwif; |
598 | ide_hwif_t *hwif; | |
26a940e2 PP |
599 | struct resource *res; |
600 | int ret = 0; | |
8447d9d5 | 601 | u8 idx[4] = { 0xff, 0xff, 0xff, 0xff }; |
9239b333 | 602 | hw_regs_t hw; |
26a940e2 PP |
603 | |
604 | #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA) | |
8f29e650 | 605 | char *mode = "MWDMA2"; |
26a940e2 | 606 | #elif defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA) |
8f29e650 | 607 | char *mode = "PIO+DDMA(offload)"; |
26a940e2 PP |
608 | #endif |
609 | ||
8f29e650 JC |
610 | memset(&auide_hwif, 0, sizeof(_auide_hwif)); |
611 | auide_hwif.dev = 0; | |
26a940e2 PP |
612 | |
613 | ahwif->dev = dev; | |
614 | ahwif->irq = platform_get_irq(pdev, 0); | |
615 | ||
616 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
617 | ||
618 | if (res == NULL) { | |
619 | pr_debug("%s %d: no base address\n", DRV_NAME, pdev->id); | |
620 | ret = -ENODEV; | |
48944738 DV |
621 | goto out; |
622 | } | |
623 | if (ahwif->irq < 0) { | |
624 | pr_debug("%s %d: no IRQ\n", DRV_NAME, pdev->id); | |
625 | ret = -ENODEV; | |
26a940e2 PP |
626 | goto out; |
627 | } | |
628 | ||
8f29e650 | 629 | if (!request_mem_region (res->start, res->end-res->start, pdev->name)) { |
26a940e2 | 630 | pr_debug("%s: request_mem_region failed\n", DRV_NAME); |
8f29e650 | 631 | ret = -EBUSY; |
26a940e2 | 632 | goto out; |
8f29e650 | 633 | } |
26a940e2 PP |
634 | |
635 | ahwif->regbase = (u32)ioremap(res->start, res->end-res->start); | |
636 | if (ahwif->regbase == 0) { | |
637 | ret = -ENOMEM; | |
638 | goto out; | |
639 | } | |
640 | ||
8f29e650 JC |
641 | /* FIXME: This might possibly break PCMCIA IDE devices */ |
642 | ||
643 | hwif = &ide_hwifs[pdev->id]; | |
9239b333 | 644 | hwif->irq = ahwif->irq; |
8f29e650 | 645 | hwif->chipset = ide_au1xxx; |
26a940e2 | 646 | |
9239b333 BZ |
647 | memset(&hw, 0, sizeof(hw)); |
648 | auide_setup_ports(&hw, ahwif); | |
649 | memcpy(hwif->io_ports, hw.io_ports, sizeof(hwif->io_ports)); | |
26a940e2 | 650 | |
8f29e650 | 651 | hwif->ultra_mask = 0x0; /* Disable Ultra DMA */ |
26a940e2 | 652 | #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA |
8f29e650 JC |
653 | hwif->mwdma_mask = 0x07; /* Multimode-2 DMA */ |
654 | hwif->swdma_mask = 0x00; | |
26a940e2 | 655 | #else |
8f29e650 JC |
656 | hwif->mwdma_mask = 0x0; |
657 | hwif->swdma_mask = 0x0; | |
658 | #endif | |
659 | ||
4099d143 | 660 | hwif->pio_mask = ATA_PIO4; |
88b2b32b | 661 | hwif->host_flags = IDE_HFLAG_POST_SET_MODE; |
4099d143 | 662 | |
8f29e650 JC |
663 | hwif->noprobe = 0; |
664 | hwif->drives[0].unmask = 1; | |
665 | hwif->drives[1].unmask = 1; | |
666 | ||
667 | /* hold should be on in all cases */ | |
668 | hwif->hold = 1; | |
2ad1e558 BZ |
669 | |
670 | hwif->mmio = 1; | |
8f29e650 JC |
671 | |
672 | /* If the user has selected DDMA assisted copies, | |
673 | then set up a few local I/O function entry points | |
674 | */ | |
675 | ||
676 | #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA | |
677 | hwif->INSW = auide_insw; | |
678 | hwif->OUTSW = auide_outsw; | |
26a940e2 | 679 | #endif |
8f29e650 | 680 | |
26bcb879 | 681 | hwif->set_pio_mode = &au1xxx_set_pio_mode; |
88b2b32b | 682 | hwif->set_dma_mode = &auide_set_dma_mode; |
26a940e2 PP |
683 | |
684 | #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA | |
7469aaf6 | 685 | hwif->dma_off_quietly = &auide_dma_off_quietly; |
c283f5db | 686 | hwif->dma_timeout = &auide_dma_timeout; |
8f29e650 | 687 | |
8446f659 BZ |
688 | hwif->mdma_filter = &auide_mdma_filter; |
689 | ||
8f29e650 JC |
690 | hwif->dma_exec_cmd = &auide_dma_exec_cmd; |
691 | hwif->dma_start = &auide_dma_start; | |
692 | hwif->ide_dma_end = &auide_dma_end; | |
693 | hwif->dma_setup = &auide_dma_setup; | |
694 | hwif->ide_dma_test_irq = &auide_dma_test_irq; | |
7469aaf6 | 695 | hwif->dma_host_off = &auide_dma_host_off; |
ccf35289 | 696 | hwif->dma_host_on = &auide_dma_host_on; |
841d2a9b | 697 | hwif->dma_lost_irq = &auide_dma_lost_irq; |
8f29e650 | 698 | hwif->ide_dma_on = &auide_dma_on; |
26a940e2 | 699 | #else /* !CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */ |
8f29e650 JC |
700 | hwif->channel = 0; |
701 | hwif->hold = 1; | |
702 | hwif->select_data = 0; /* no chipset-specific code */ | |
703 | hwif->config_data = 0; /* no chipset-specific code */ | |
704 | ||
8f29e650 | 705 | hwif->drives[0].autotune = 1; /* 1=autotune, 2=noautotune, 0=default */ |
a05e2faa | 706 | hwif->drives[1].autotune = 1; |
26a940e2 | 707 | #endif |
a05e2faa BZ |
708 | hwif->drives[0].no_io_32bit = 1; |
709 | hwif->drives[1].no_io_32bit = 1; | |
26a940e2 | 710 | |
8f29e650 JC |
711 | auide_hwif.hwif = hwif; |
712 | hwif->hwif_data = &auide_hwif; | |
26a940e2 | 713 | |
8f29e650 JC |
714 | #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA |
715 | auide_ddma_init(&auide_hwif); | |
716 | dbdma_init_done = 1; | |
26a940e2 PP |
717 | #endif |
718 | ||
8447d9d5 | 719 | idx[0] = hwif->index; |
5cbf79cd | 720 | |
8447d9d5 | 721 | ide_device_add(idx); |
5cbf79cd | 722 | |
26a940e2 PP |
723 | dev_set_drvdata(dev, hwif); |
724 | ||
8f29e650 | 725 | printk(KERN_INFO "Au1xxx IDE(builtin) configured for %s\n", mode ); |
26a940e2 | 726 | |
8f29e650 JC |
727 | out: |
728 | return ret; | |
26a940e2 PP |
729 | } |
730 | ||
731 | static int au_ide_remove(struct device *dev) | |
732 | { | |
733 | struct platform_device *pdev = to_platform_device(dev); | |
734 | struct resource *res; | |
735 | ide_hwif_t *hwif = dev_get_drvdata(dev); | |
8f29e650 | 736 | _auide_hwif *ahwif = &auide_hwif; |
26a940e2 PP |
737 | |
738 | ide_unregister(hwif - ide_hwifs); | |
739 | ||
740 | iounmap((void *)ahwif->regbase); | |
741 | ||
742 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
743 | release_mem_region(res->start, res->end - res->start); | |
744 | ||
745 | return 0; | |
746 | } | |
747 | ||
748 | static struct device_driver au1200_ide_driver = { | |
749 | .name = "au1200-ide", | |
750 | .bus = &platform_bus_type, | |
751 | .probe = au_ide_probe, | |
752 | .remove = au_ide_remove, | |
753 | }; | |
754 | ||
755 | static int __init au_ide_init(void) | |
756 | { | |
757 | return driver_register(&au1200_ide_driver); | |
758 | } | |
759 | ||
8f29e650 | 760 | static void __exit au_ide_exit(void) |
26a940e2 PP |
761 | { |
762 | driver_unregister(&au1200_ide_driver); | |
763 | } | |
764 | ||
26a940e2 PP |
765 | MODULE_LICENSE("GPL"); |
766 | MODULE_DESCRIPTION("AU1200 IDE driver"); | |
767 | ||
768 | module_init(au_ide_init); | |
769 | module_exit(au_ide_exit); |