[linux-2.6-block.git] / drivers / ide / ide-timings.c

/*
 *  Copyright (c) 1999-2001 Vojtech Pavlik
 *  Copyright (c) 2007-2008 Bartlomiej Zolnierkiewicz
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 *
 * Should you need to contact me, the author, you can do so either by
 * e-mail - mail your message to <vojtech@ucw.cz>, or by paper mail:
 * Vojtech Pavlik, Simunkova 1594, Prague 8, 182 00 Czech Republic
 */

#include <linux/kernel.h>
#include <linux/ide.h>
#include <linux/module.h>

/*
 * PIO 0-5, MWDMA 0-2 and UDMA 0-6 timings (in nanoseconds).
 * These were taken from ATA/ATAPI-6 standard, rev 0a, except
 * for PIO 5, which is a nonstandard extension and UDMA6, which
 * is currently supported only by Maxtor drives.
 */

static struct ide_timing ide_timing[] = {

	{ XFER_UDMA_6,     0,   0,   0,   0,   0,   0,   0,  15 },
	{ XFER_UDMA_5,     0,   0,   0,   0,   0,   0,   0,  20 },
	{ XFER_UDMA_4,     0,   0,   0,   0,   0,   0,   0,  30 },
	{ XFER_UDMA_3,     0,   0,   0,   0,   0,   0,   0,  45 },

	{ XFER_UDMA_2,     0,   0,   0,   0,   0,   0,   0,  60 },
	{ XFER_UDMA_1,     0,   0,   0,   0,   0,   0,   0,  80 },
	{ XFER_UDMA_0,     0,   0,   0,   0,   0,   0,   0, 120 },

	{ XFER_MW_DMA_2,  25,   0,   0,   0,  70,  25, 120,   0 },
	{ XFER_MW_DMA_1,  45,   0,   0,   0,  80,  50, 150,   0 },
	{ XFER_MW_DMA_0,  60,   0,   0,   0, 215, 215, 480,   0 },

	{ XFER_SW_DMA_2,  60,   0,   0,   0, 120, 120, 240,   0 },
	{ XFER_SW_DMA_1,  90,   0,   0,   0, 240, 240, 480,   0 },
	{ XFER_SW_DMA_0, 120,   0,   0,   0, 480, 480, 960,   0 },

	{ XFER_PIO_5,     20,  50,  30, 100,  50,  30, 100,   0 },
	{ XFER_PIO_4,     25,  70,  25, 120,  70,  25, 120,   0 },
	{ XFER_PIO_3,     30,  80,  70, 180,  80,  70, 180,   0 },

	{ XFER_PIO_2,     30, 290,  40, 330, 100,  90, 240,   0 },
	{ XFER_PIO_1,     50, 290,  93, 383, 125, 100, 383,   0 },
	{ XFER_PIO_0,     70, 290, 240, 600, 165, 150, 600,   0 },

	{ XFER_PIO_SLOW, 120, 290, 240, 960, 290, 240, 960,   0 },

	{ 0xff }
};

struct ide_timing *ide_timing_find_mode(u8 speed)
{
	struct ide_timing *t;

	for (t = ide_timing; t->mode != speed; t++)
		if (t->mode == 0xff)
			return NULL;
	return t;
}
EXPORT_SYMBOL_GPL(ide_timing_find_mode);

u16 ide_pio_cycle_time(ide_drive_t *drive, u8 pio)
{
	u16 *id = drive->id;
	struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio);
	u16 cycle = 0;

	if (id[ATA_ID_FIELD_VALID] & 2) {
		if (ata_id_has_iordy(drive->id))
			cycle = id[ATA_ID_EIDE_PIO_IORDY];
		else
			cycle = id[ATA_ID_EIDE_PIO];

		/* conservative "downgrade" for all pre-ATA2 drives */
		if (pio < 3 && cycle < t->cycle)
			cycle = 0; /* use standard timing */
	}

	return cycle ? cycle : t->cycle;
}
EXPORT_SYMBOL_GPL(ide_pio_cycle_time);

#define ENOUGH(v, unit)		(((v) - 1) / (unit) + 1)
#define EZ(v, unit)		((v) ? ENOUGH(v, unit) : 0)

static void ide_timing_quantize(struct ide_timing *t, struct ide_timing *q,
				int T, int UT)
{
	q->setup   = EZ(t->setup   * 1000,  T);
	q->act8b   = EZ(t->act8b   * 1000,  T);
	q->rec8b   = EZ(t->rec8b   * 1000,  T);
	q->cyc8b   = EZ(t->cyc8b   * 1000,  T);
	q->active  = EZ(t->active  * 1000,  T);
	q->recover = EZ(t->recover * 1000,  T);
	q->cycle   = EZ(t->cycle   * 1000,  T);
	q->udma    = EZ(t->udma    * 1000, UT);
}

void ide_timing_merge(struct ide_timing *a, struct ide_timing *b,
		      struct ide_timing *m, unsigned int what)
{
	if (what & IDE_TIMING_SETUP)
		m->setup   = max(a->setup,   b->setup);
	if (what & IDE_TIMING_ACT8B)
		m->act8b   = max(a->act8b,   b->act8b);
	if (what & IDE_TIMING_REC8B)
		m->rec8b   = max(a->rec8b,   b->rec8b);
	if (what & IDE_TIMING_CYC8B)
		m->cyc8b   = max(a->cyc8b,   b->cyc8b);
	if (what & IDE_TIMING_ACTIVE)
		m->active  = max(a->active,  b->active);
	if (what & IDE_TIMING_RECOVER)
		m->recover = max(a->recover, b->recover);
	if (what & IDE_TIMING_CYCLE)
		m->cycle   = max(a->cycle,   b->cycle);
	if (what & IDE_TIMING_UDMA)
		m->udma    = max(a->udma,    b->udma);
}
EXPORT_SYMBOL_GPL(ide_timing_merge);

int ide_timing_compute(ide_drive_t *drive, u8 speed,
		       struct ide_timing *t, int T, int UT)
{
	u16 *id = drive->id;
	struct ide_timing *s, p;

	/*
	 * Find the mode.
	 */
	s = ide_timing_find_mode(speed);
	if (s == NULL)
		return -EINVAL;

	/*
	 * Copy the timing from the table.
	 */
	*t = *s;

	/*
	 * If the drive is an EIDE drive, it can tell us it needs extended
	 * PIO/MWDMA cycle timing.
	 */
	if (id[ATA_ID_FIELD_VALID] & 2) {	/* EIDE drive */
		memset(&p, 0, sizeof(p));

		if (speed <= XFER_PIO_2)
			p.cycle = p.cyc8b = id[ATA_ID_EIDE_PIO];
		else if (speed <= XFER_PIO_5)
			p.cycle = p.cyc8b = id[ATA_ID_EIDE_PIO_IORDY];
		else if (speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2)
			p.cycle = id[ATA_ID_EIDE_DMA_MIN];

		ide_timing_merge(&p, t, t, IDE_TIMING_CYCLE | IDE_TIMING_CYC8B);
	}

	/*
	 * Convert the timing to bus clock counts.
	 */
	ide_timing_quantize(t, t, T, UT);

	/*
	 * Even in DMA/UDMA modes we still use PIO access for IDENTIFY,
	 * S.M.A.R.T and some other commands. We have to ensure that the
	 * DMA cycle timing is slower/equal than the fastest PIO timing.
	 */
	if (speed >= XFER_SW_DMA_0) {
		u8 pio = ide_get_best_pio_mode(drive, 255, 5);
		ide_timing_compute(drive, XFER_PIO_0 + pio, &p, T, UT);
		ide_timing_merge(&p, t, t, IDE_TIMING_ALL);
	}

	/*
	 * Lengthen active & recovery time so that cycle time is correct.
	 */
	if (t->act8b + t->rec8b < t->cyc8b) {
		t->act8b += (t->cyc8b - (t->act8b + t->rec8b)) / 2;
		t->rec8b = t->cyc8b - t->act8b;
	}

	if (t->active + t->recover < t->cycle) {
		t->active += (t->cycle - (t->active + t->recover)) / 2;
		t->recover = t->cycle - t->active;
	}

	return 0;
}
EXPORT_SYMBOL_GPL(ide_timing_compute);
Commit	Line	Data
1da177e4	1	/*
1da177e4	2	* Copyright (c) 1999-2001 Vojtech Pavlik
c9d6c1a2	3	* Copyright (c) 2007-2008 Bartlomiej Zolnierkiewicz
2c139e7a	4	*
1da177e4 LT	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License as published by
	7	* the Free Software Foundation; either version 2 of the License, or
	8	* (at your option) any later version.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software
	17	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	*
	19	* Should you need to contact me, the author, you can do so either by
	20	* e-mail - mail your message to <vojtech@ucw.cz>, or by paper mail:
	21	* Vojtech Pavlik, Simunkova 1594, Prague 8, 182 00 Czech Republic
	22	*/
	23
2665b891	24	#include <linux/kernel.h>
f06ab340 BZ	25	#include <linux/ide.h>
f06ab340 BZ	26	#include <linux/module.h>
1da177e4	27
1da177e4 LT	28	/*
	29	* PIO 0-5, MWDMA 0-2 and UDMA 0-6 timings (in nanoseconds).
	30	* These were taken from ATA/ATAPI-6 standard, rev 0a, except
	31	* for PIO 5, which is a nonstandard extension and UDMA6, which
2c139e7a	32	* is currently supported only by Maxtor drives.
1da177e4 LT	33	*/
	34
	35	static struct ide_timing ide_timing[] = {
	36
	37	{ XFER_UDMA_6, 0, 0, 0, 0, 0, 0, 0, 15 },
	38	{ XFER_UDMA_5, 0, 0, 0, 0, 0, 0, 0, 20 },
	39	{ XFER_UDMA_4, 0, 0, 0, 0, 0, 0, 0, 30 },
	40	{ XFER_UDMA_3, 0, 0, 0, 0, 0, 0, 0, 45 },
	41
	42	{ XFER_UDMA_2, 0, 0, 0, 0, 0, 0, 0, 60 },
	43	{ XFER_UDMA_1, 0, 0, 0, 0, 0, 0, 0, 80 },
	44	{ XFER_UDMA_0, 0, 0, 0, 0, 0, 0, 0, 120 },
	45
1da177e4 LT	46	{ XFER_MW_DMA_2, 25, 0, 0, 0, 70, 25, 120, 0 },
	47	{ XFER_MW_DMA_1, 45, 0, 0, 0, 80, 50, 150, 0 },
	48	{ XFER_MW_DMA_0, 60, 0, 0, 0, 215, 215, 480, 0 },
f0ffc987	49
1da177e4 LT	50	{ XFER_SW_DMA_2, 60, 0, 0, 0, 120, 120, 240, 0 },
	51	{ XFER_SW_DMA_1, 90, 0, 0, 0, 240, 240, 480, 0 },
	52	{ XFER_SW_DMA_0, 120, 0, 0, 0, 480, 480, 960, 0 },
	53
	54	{ XFER_PIO_5, 20, 50, 30, 100, 50, 30, 100, 0 },
	55	{ XFER_PIO_4, 25, 70, 25, 120, 70, 25, 120, 0 },
	56	{ XFER_PIO_3, 30, 80, 70, 180, 80, 70, 180, 0 },
	57
	58	{ XFER_PIO_2, 30, 290, 40, 330, 100, 90, 240, 0 },
	59	{ XFER_PIO_1, 50, 290, 93, 383, 125, 100, 383, 0 },
	60	{ XFER_PIO_0, 70, 290, 240, 600, 165, 150, 600, 0 },
	61
	62	{ XFER_PIO_SLOW, 120, 290, 240, 960, 290, 240, 960, 0 },
	63
71d51614	64	{ 0xff }
1da177e4 LT	65	};
1da177e4 LT	66
f06ab340 BZ	67	struct ide_timing *ide_timing_find_mode(u8 speed)
	68	{
	69	struct ide_timing *t;
	70
	71	for (t = ide_timing; t->mode != speed; t++)
	72	if (t->mode == 0xff)
	73	return NULL;
	74	return t;
	75	}
	76	EXPORT_SYMBOL_GPL(ide_timing_find_mode);
	77
c9d6c1a2 BZ	78	u16 ide_pio_cycle_time(ide_drive_t *drive, u8 pio)
c9d6c1a2 BZ	79	{
4dde4492	80	u16 *id = drive->id;
c9d6c1a2 BZ	81	struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio);
	82	u16 cycle = 0;
	83
4dde4492	84	if (id[ATA_ID_FIELD_VALID] & 2) {
48fb2688	85	if (ata_id_has_iordy(drive->id))
4dde4492	86	cycle = id[ATA_ID_EIDE_PIO_IORDY];
c9d6c1a2	87	else
4dde4492	88	cycle = id[ATA_ID_EIDE_PIO];
c9d6c1a2 BZ	89
	90	/* conservative "downgrade" for all pre-ATA2 drives */
	91	if (pio < 3 && cycle < t->cycle)
	92	cycle = 0; /* use standard timing */
	93	}
	94
	95	return cycle ? cycle : t->cycle;
	96	}
	97	EXPORT_SYMBOL_GPL(ide_pio_cycle_time);
	98
2c139e7a BZ	99	#define ENOUGH(v, unit) (((v) - 1) / (unit) + 1)
2c139e7a BZ	100	#define EZ(v, unit) ((v) ? ENOUGH(v, unit) : 0)
1da177e4	101
2c139e7a BZ	102	static void ide_timing_quantize(struct ide_timing t, struct ide_timing q,
2c139e7a BZ	103	int T, int UT)
1da177e4 LT	104	{
	105	q->setup = EZ(t->setup * 1000, T);
	106	q->act8b = EZ(t->act8b * 1000, T);
	107	q->rec8b = EZ(t->rec8b * 1000, T);
	108	q->cyc8b = EZ(t->cyc8b * 1000, T);
	109	q->active = EZ(t->active * 1000, T);
	110	q->recover = EZ(t->recover * 1000, T);
	111	q->cycle = EZ(t->cycle * 1000, T);
	112	q->udma = EZ(t->udma * 1000, UT);
	113	}
	114
f06ab340 BZ	115	void ide_timing_merge(struct ide_timing a, struct ide_timing b,
f06ab340 BZ	116	struct ide_timing *m, unsigned int what)
1da177e4	117	{
2c139e7a BZ	118	if (what & IDE_TIMING_SETUP)
	119	m->setup = max(a->setup, b->setup);
	120	if (what & IDE_TIMING_ACT8B)
	121	m->act8b = max(a->act8b, b->act8b);
	122	if (what & IDE_TIMING_REC8B)
	123	m->rec8b = max(a->rec8b, b->rec8b);
	124	if (what & IDE_TIMING_CYC8B)
	125	m->cyc8b = max(a->cyc8b, b->cyc8b);
	126	if (what & IDE_TIMING_ACTIVE)
	127	m->active = max(a->active, b->active);
	128	if (what & IDE_TIMING_RECOVER)
	129	m->recover = max(a->recover, b->recover);
	130	if (what & IDE_TIMING_CYCLE)
	131	m->cycle = max(a->cycle, b->cycle);
	132	if (what & IDE_TIMING_UDMA)
	133	m->udma = max(a->udma, b->udma);
1da177e4	134	}
f06ab340	135	EXPORT_SYMBOL_GPL(ide_timing_merge);
1da177e4	136
f06ab340 BZ	137	int ide_timing_compute(ide_drive_t *drive, u8 speed,
f06ab340 BZ	138	struct ide_timing *t, int T, int UT)
1da177e4	139	{
4dde4492	140	u16 *id = drive->id;
1da177e4 LT	141	struct ide_timing *s, p;
1da177e4 LT	142
2c139e7a BZ	143	/*
	144	* Find the mode.
	145	*/
	146	s = ide_timing_find_mode(speed);
	147	if (s == NULL)
1da177e4 LT	148	return -EINVAL;
1da177e4 LT	149
2c139e7a BZ	150	/*
	151	* Copy the timing from the table.
	152	*/
17c1033d SS	153	t = s;
17c1033d SS	154
2c139e7a BZ	155	/*
	156	* If the drive is an EIDE drive, it can tell us it needs extended
	157	* PIO/MWDMA cycle timing.
	158	*/
4dde4492	159	if (id[ATA_ID_FIELD_VALID] & 2) { /* EIDE drive */
1da177e4 LT	160	memset(&p, 0, sizeof(p));
1da177e4 LT	161
bd887f72	162	if (speed <= XFER_PIO_2)
4dde4492	163	p.cycle = p.cyc8b = id[ATA_ID_EIDE_PIO];
bd887f72	164	else if (speed <= XFER_PIO_5)
4dde4492	165	p.cycle = p.cyc8b = id[ATA_ID_EIDE_PIO_IORDY];
bd887f72	166	else if (speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2)
4dde4492	167	p.cycle = id[ATA_ID_EIDE_DMA_MIN];
1da177e4 LT	168
	169	ide_timing_merge(&p, t, t, IDE_TIMING_CYCLE \| IDE_TIMING_CYC8B);
	170	}
	171
2c139e7a BZ	172	/*
	173	* Convert the timing to bus clock counts.
	174	*/
17c1033d	175	ide_timing_quantize(t, t, T, UT);
1da177e4	176
2c139e7a BZ	177	/*
	178	* Even in DMA/UDMA modes we still use PIO access for IDENTIFY,
	179	* S.M.A.R.T and some other commands. We have to ensure that the
	180	* DMA cycle timing is slower/equal than the fastest PIO timing.
	181	*/
bd887f72	182	if (speed >= XFER_SW_DMA_0) {
6a824c92 BZ	183	u8 pio = ide_get_best_pio_mode(drive, 255, 5);
6a824c92 BZ	184	ide_timing_compute(drive, XFER_PIO_0 + pio, &p, T, UT);
1da177e4 LT	185	ide_timing_merge(&p, t, t, IDE_TIMING_ALL);
	186	}
	187
2c139e7a BZ	188	/*
	189	* Lengthen active & recovery time so that cycle time is correct.
	190	*/
1da177e4 LT	191	if (t->act8b + t->rec8b < t->cyc8b) {
	192	t->act8b += (t->cyc8b - (t->act8b + t->rec8b)) / 2;
	193	t->rec8b = t->cyc8b - t->act8b;
	194	}
	195
	196	if (t->active + t->recover < t->cycle) {
	197	t->active += (t->cycle - (t->active + t->recover)) / 2;
	198	t->recover = t->cycle - t->active;
	199	}
	200
	201	return 0;
	202	}
f06ab340	203	EXPORT_SYMBOL_GPL(ide_timing_compute);