[linux-2.6-block.git] / drivers / ide / ide-dma-sff.c

// SPDX-License-Identifier: GPL-2.0-only
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/export.h>
#include <linux/ide.h>
#include <linux/scatterlist.h>
#include <linux/dma-mapping.h>
#include <linux/io.h>

/**
 *	config_drive_for_dma	-	attempt to activate IDE DMA
 *	@drive: the drive to place in DMA mode
 *
 *	If the drive supports at least mode 2 DMA or UDMA of any kind
 *	then attempt to place it into DMA mode. Drives that are known to
 *	support DMA but predate the DMA properties or that are known
 *	to have DMA handling bugs are also set up appropriately based
 *	on the good/bad drive lists.
 */

int config_drive_for_dma(ide_drive_t *drive)
{
	ide_hwif_t *hwif = drive->hwif;
	u16 *id = drive->id;

	if (drive->media != ide_disk) {
		if (hwif->host_flags & IDE_HFLAG_NO_ATAPI_DMA)
			return 0;
	}

	/*
	 * Enable DMA on any drive that has
	 * UltraDMA (mode 0/1/2/3/4/5/6) enabled
	 */
	if ((id[ATA_ID_FIELD_VALID] & 4) &&
	    ((id[ATA_ID_UDMA_MODES] >> 8) & 0x7f))
		return 1;

	/*
	 * Enable DMA on any drive that has mode2 DMA
	 * (multi or single) enabled
	 */
	if ((id[ATA_ID_MWDMA_MODES] & 0x404) == 0x404 ||
	    (id[ATA_ID_SWDMA_MODES] & 0x404) == 0x404)
		return 1;

	/* Consult the list of known "good" drives */
	if (ide_dma_good_drive(drive))
		return 1;

	return 0;
}

u8 ide_dma_sff_read_status(ide_hwif_t *hwif)
{
	unsigned long addr = hwif->dma_base + ATA_DMA_STATUS;

	if (hwif->host_flags & IDE_HFLAG_MMIO)
		return readb((void __iomem *)addr);
	else
		return inb(addr);
}
EXPORT_SYMBOL_GPL(ide_dma_sff_read_status);

static void ide_dma_sff_write_status(ide_hwif_t *hwif, u8 val)
{
	unsigned long addr = hwif->dma_base + ATA_DMA_STATUS;

	if (hwif->host_flags & IDE_HFLAG_MMIO)
		writeb(val, (void __iomem *)addr);
	else
		outb(val, addr);
}

/**
 *	ide_dma_host_set	-	Enable/disable DMA on a host
 *	@drive: drive to control
 *
 *	Enable/disable DMA on an IDE controller following generic
 *	bus-mastering IDE controller behaviour.
 */

void ide_dma_host_set(ide_drive_t *drive, int on)
{
	ide_hwif_t *hwif = drive->hwif;
	u8 unit = drive->dn & 1;
	u8 dma_stat = hwif->dma_ops->dma_sff_read_status(hwif);

	if (on)
		dma_stat |= (1 << (5 + unit));
	else
		dma_stat &= ~(1 << (5 + unit));

	ide_dma_sff_write_status(hwif, dma_stat);
}
EXPORT_SYMBOL_GPL(ide_dma_host_set);

/**
 *	ide_build_dmatable	-	build IDE DMA table
 *
 *	ide_build_dmatable() prepares a dma request. We map the command
 *	to get the pci bus addresses of the buffers and then build up
 *	the PRD table that the IDE layer wants to be fed.
 *
 *	Most chipsets correctly interpret a length of 0x0000 as 64KB,
 *	but at least one (e.g. CS5530) misinterprets it as zero (!).
 *	So we break the 64KB entry into two 32KB entries instead.
 *
 *	Returns the number of built PRD entries if all went okay,
 *	returns 0 otherwise.
 *
 *	May also be invoked from trm290.c
 */

int ide_build_dmatable(ide_drive_t *drive, struct ide_cmd *cmd)
{
	ide_hwif_t *hwif = drive->hwif;
	__le32 *table = (__le32 *)hwif->dmatable_cpu;
	unsigned int count = 0;
	int i;
	struct scatterlist *sg;
	u8 is_trm290 = !!(hwif->host_flags & IDE_HFLAG_TRM290);

	for_each_sg(hwif->sg_table, sg, cmd->sg_nents, i) {
		u32 cur_addr, cur_len, xcount, bcount;

		cur_addr = sg_dma_address(sg);
		cur_len = sg_dma_len(sg);

		/*
		 * Fill in the dma table, without crossing any 64kB boundaries.
		 * Most hardware requires 16-bit alignment of all blocks,
		 * but the trm290 requires 32-bit alignment.
		 */

		while (cur_len) {
			if (count++ >= PRD_ENTRIES)
				goto use_pio_instead;

			bcount = 0x10000 - (cur_addr & 0xffff);
			if (bcount > cur_len)
				bcount = cur_len;
			*table++ = cpu_to_le32(cur_addr);
			xcount = bcount & 0xffff;
			if (is_trm290)
				xcount = ((xcount >> 2) - 1) << 16;
			else if (xcount == 0x0000) {
				if (count++ >= PRD_ENTRIES)
					goto use_pio_instead;
				*table++ = cpu_to_le32(0x8000);
				*table++ = cpu_to_le32(cur_addr + 0x8000);
				xcount = 0x8000;
			}
			*table++ = cpu_to_le32(xcount);
			cur_addr += bcount;
			cur_len -= bcount;
		}
	}

	if (count) {
		if (!is_trm290)
			*--table |= cpu_to_le32(0x80000000);
		return count;
	}

use_pio_instead:
	printk(KERN_ERR "%s: %s\n", drive->name,
		count ? "DMA table too small" : "empty DMA table?");

	return 0; /* revert to PIO for this request */
}
EXPORT_SYMBOL_GPL(ide_build_dmatable);

/**
 *	ide_dma_setup	-	begin a DMA phase
 *	@drive: target device
 *	@cmd: command
 *
 *	Build an IDE DMA PRD (IDE speak for scatter gather table)
 *	and then set up the DMA transfer registers for a device
 *	that follows generic IDE PCI DMA behaviour. Controllers can
 *	override this function if they need to
 *
 *	Returns 0 on success. If a PIO fallback is required then 1
 *	is returned.
 */

int ide_dma_setup(ide_drive_t *drive, struct ide_cmd *cmd)
{
	ide_hwif_t *hwif = drive->hwif;
	u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0;
	u8 rw = (cmd->tf_flags & IDE_TFLAG_WRITE) ? 0 : ATA_DMA_WR;
	u8 dma_stat;

	/* fall back to pio! */
	if (ide_build_dmatable(drive, cmd) == 0) {
		ide_map_sg(drive, cmd);
		return 1;
	}

	/* PRD table */
	if (mmio)
		writel(hwif->dmatable_dma,
		       (void __iomem *)(hwif->dma_base + ATA_DMA_TABLE_OFS));
	else
		outl(hwif->dmatable_dma, hwif->dma_base + ATA_DMA_TABLE_OFS);

	/* specify r/w */
	if (mmio)
		writeb(rw, (void __iomem *)(hwif->dma_base + ATA_DMA_CMD));
	else
		outb(rw, hwif->dma_base + ATA_DMA_CMD);

	/* read DMA status for INTR & ERROR flags */
	dma_stat = hwif->dma_ops->dma_sff_read_status(hwif);

	/* clear INTR & ERROR flags */
	ide_dma_sff_write_status(hwif, dma_stat | ATA_DMA_ERR | ATA_DMA_INTR);

	return 0;
}
EXPORT_SYMBOL_GPL(ide_dma_setup);

/**
 *	ide_dma_sff_timer_expiry	-	handle a DMA timeout
 *	@drive: Drive that timed out
 *
 *	An IDE DMA transfer timed out. In the event of an error we ask
 *	the driver to resolve the problem, if a DMA transfer is still
 *	in progress we continue to wait (arguably we need to add a
 *	secondary 'I don't care what the drive thinks' timeout here)
 *	Finally if we have an interrupt we let it complete the I/O.
 *	But only one time - we clear expiry and if it's still not
 *	completed after WAIT_CMD, we error and retry in PIO.
 *	This can occur if an interrupt is lost or due to hang or bugs.
 */

int ide_dma_sff_timer_expiry(ide_drive_t *drive)
{
	ide_hwif_t *hwif = drive->hwif;
	u8 dma_stat = hwif->dma_ops->dma_sff_read_status(hwif);

	printk(KERN_WARNING "%s: %s: DMA status (0x%02x)\n",
		drive->name, __func__, dma_stat);

	if ((dma_stat & 0x18) == 0x18)	/* BUSY Stupid Early Timer !! */
		return WAIT_CMD;

	hwif->expiry = NULL;	/* one free ride for now */

	if (dma_stat & ATA_DMA_ERR)	/* ERROR */
		return -1;

	if (dma_stat & ATA_DMA_ACTIVE)	/* DMAing */
		return WAIT_CMD;

	if (dma_stat & ATA_DMA_INTR)	/* Got an Interrupt */
		return WAIT_CMD;

	return 0;	/* Status is unknown -- reset the bus */
}
EXPORT_SYMBOL_GPL(ide_dma_sff_timer_expiry);

void ide_dma_start(ide_drive_t *drive)
{
	ide_hwif_t *hwif = drive->hwif;
	u8 dma_cmd;

	/* Note that this is done *after* the cmd has
	 * been issued to the drive, as per the BM-IDE spec.
	 * The Promise Ultra33 doesn't work correctly when
	 * we do this part before issuing the drive cmd.
	 */
	if (hwif->host_flags & IDE_HFLAG_MMIO) {
		dma_cmd = readb((void __iomem *)(hwif->dma_base + ATA_DMA_CMD));
		writeb(dma_cmd | ATA_DMA_START,
		       (void __iomem *)(hwif->dma_base + ATA_DMA_CMD));
	} else {
		dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
		outb(dma_cmd | ATA_DMA_START, hwif->dma_base + ATA_DMA_CMD);
	}
}
EXPORT_SYMBOL_GPL(ide_dma_start);

/* returns 1 on error, 0 otherwise */
int ide_dma_end(ide_drive_t *drive)
{
	ide_hwif_t *hwif = drive->hwif;
	u8 dma_stat = 0, dma_cmd = 0;

	/* stop DMA */
	if (hwif->host_flags & IDE_HFLAG_MMIO) {
		dma_cmd = readb((void __iomem *)(hwif->dma_base + ATA_DMA_CMD));
		writeb(dma_cmd & ~ATA_DMA_START,
		       (void __iomem *)(hwif->dma_base + ATA_DMA_CMD));
	} else {
		dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
		outb(dma_cmd & ~ATA_DMA_START, hwif->dma_base + ATA_DMA_CMD);
	}

	/* get DMA status */
	dma_stat = hwif->dma_ops->dma_sff_read_status(hwif);

	/* clear INTR & ERROR bits */
	ide_dma_sff_write_status(hwif, dma_stat | ATA_DMA_ERR | ATA_DMA_INTR);

#define CHECK_DMA_MASK (ATA_DMA_ACTIVE | ATA_DMA_ERR | ATA_DMA_INTR)

	/* verify good DMA status */
	if ((dma_stat & CHECK_DMA_MASK) != ATA_DMA_INTR)
		return 0x10 | dma_stat;
	return 0;
}
EXPORT_SYMBOL_GPL(ide_dma_end);

/* returns 1 if dma irq issued, 0 otherwise */
int ide_dma_test_irq(ide_drive_t *drive)
{
	ide_hwif_t *hwif = drive->hwif;
	u8 dma_stat = hwif->dma_ops->dma_sff_read_status(hwif);

	return (dma_stat & ATA_DMA_INTR) ? 1 : 0;
}
EXPORT_SYMBOL_GPL(ide_dma_test_irq);

const struct ide_dma_ops sff_dma_ops = {
	.dma_host_set		= ide_dma_host_set,
	.dma_setup		= ide_dma_setup,
	.dma_start		= ide_dma_start,
	.dma_end		= ide_dma_end,
	.dma_test_irq		= ide_dma_test_irq,
	.dma_lost_irq		= ide_dma_lost_irq,
	.dma_timer_expiry	= ide_dma_sff_timer_expiry,
	.dma_sff_read_status	= ide_dma_sff_read_status,
};
EXPORT_SYMBOL_GPL(sff_dma_ops);
Commit	Line	Data
457c8996	1	// SPDX-License-Identifier: GPL-2.0-only
2dbe7e91 BZ	2	#include <linux/types.h>
2dbe7e91 BZ	3	#include <linux/kernel.h>
38789fda	4	#include <linux/export.h>
2dbe7e91 BZ	5	#include <linux/ide.h>
	6	#include <linux/scatterlist.h>
	7	#include <linux/dma-mapping.h>
	8	#include <linux/io.h>
	9
	10	/**
	11	* config_drive_for_dma - attempt to activate IDE DMA
	12	* @drive: the drive to place in DMA mode
	13	*
	14	* If the drive supports at least mode 2 DMA or UDMA of any kind
	15	* then attempt to place it into DMA mode. Drives that are known to
	16	* support DMA but predate the DMA properties or that are known
	17	* to have DMA handling bugs are also set up appropriately based
	18	* on the good/bad drive lists.
	19	*/
	20
	21	int config_drive_for_dma(ide_drive_t *drive)
	22	{
	23	ide_hwif_t *hwif = drive->hwif;
	24	u16 *id = drive->id;
	25
	26	if (drive->media != ide_disk) {
	27	if (hwif->host_flags & IDE_HFLAG_NO_ATAPI_DMA)
	28	return 0;
	29	}
	30
	31	/*
	32	* Enable DMA on any drive that has
	33	* UltraDMA (mode 0/1/2/3/4/5/6) enabled
	34	*/
	35	if ((id[ATA_ID_FIELD_VALID] & 4) &&
	36	((id[ATA_ID_UDMA_MODES] >> 8) & 0x7f))
	37	return 1;
	38
	39	/*
	40	* Enable DMA on any drive that has mode2 DMA
	41	* (multi or single) enabled
	42	*/
8d64fcd9 SS	43	if ((id[ATA_ID_MWDMA_MODES] & 0x404) == 0x404 \|\|
	44	(id[ATA_ID_SWDMA_MODES] & 0x404) == 0x404)
	45	return 1;
2dbe7e91 BZ	46
	47	/* Consult the list of known "good" drives */
	48	if (ide_dma_good_drive(drive))
	49	return 1;
	50
	51	return 0;
	52	}
	53
592b5315 SS	54	u8 ide_dma_sff_read_status(ide_hwif_t *hwif)
	55	{
	56	unsigned long addr = hwif->dma_base + ATA_DMA_STATUS;
	57
	58	if (hwif->host_flags & IDE_HFLAG_MMIO)
	59	return readb((void __iomem *)addr);
	60	else
	61	return inb(addr);
	62	}
	63	EXPORT_SYMBOL_GPL(ide_dma_sff_read_status);
	64
05789634 SS	65	static void ide_dma_sff_write_status(ide_hwif_t *hwif, u8 val)
	66	{
	67	unsigned long addr = hwif->dma_base + ATA_DMA_STATUS;
	68
	69	if (hwif->host_flags & IDE_HFLAG_MMIO)
	70	writeb(val, (void __iomem *)addr);
	71	else
	72	outb(val, addr);
	73	}
	74
2dbe7e91 BZ	75	/**
	76	* ide_dma_host_set - Enable/disable DMA on a host
	77	* @drive: drive to control
	78	*
	79	* Enable/disable DMA on an IDE controller following generic
	80	* bus-mastering IDE controller behaviour.
	81	*/
	82
	83	void ide_dma_host_set(ide_drive_t *drive, int on)
	84	{
	85	ide_hwif_t *hwif = drive->hwif;
	86	u8 unit = drive->dn & 1;
592b5315	87	u8 dma_stat = hwif->dma_ops->dma_sff_read_status(hwif);
2dbe7e91 BZ	88
	89	if (on)
	90	dma_stat \|= (1 << (5 + unit));
	91	else
	92	dma_stat &= ~(1 << (5 + unit));
	93
05789634	94	ide_dma_sff_write_status(hwif, dma_stat);
2dbe7e91 BZ	95	}
	96	EXPORT_SYMBOL_GPL(ide_dma_host_set);
	97
	98	/**
	99	* ide_build_dmatable - build IDE DMA table
	100	*
	101	* ide_build_dmatable() prepares a dma request. We map the command
	102	* to get the pci bus addresses of the buffers and then build up
	103	* the PRD table that the IDE layer wants to be fed.
	104	*
	105	* Most chipsets correctly interpret a length of 0x0000 as 64KB,
	106	* but at least one (e.g. CS5530) misinterprets it as zero (!).
	107	* So we break the 64KB entry into two 32KB entries instead.
	108	*
	109	* Returns the number of built PRD entries if all went okay,
	110	* returns 0 otherwise.
	111	*
	112	* May also be invoked from trm290.c
	113	*/
	114
22981694	115	int ide_build_dmatable(ide_drive_t drive, struct ide_cmd cmd)
2dbe7e91 BZ	116	{
	117	ide_hwif_t *hwif = drive->hwif;
	118	__le32 table = (__le32 )hwif->dmatable_cpu;
2dbe7e91 BZ	119	unsigned int count = 0;
	120	int i;
	121	struct scatterlist *sg;
1f66019b	122	u8 is_trm290 = !!(hwif->host_flags & IDE_HFLAG_TRM290);
2dbe7e91	123
22981694	124	for_each_sg(hwif->sg_table, sg, cmd->sg_nents, i) {
2dbe7e91 BZ	125	u32 cur_addr, cur_len, xcount, bcount;
	126
	127	cur_addr = sg_dma_address(sg);
	128	cur_len = sg_dma_len(sg);
	129
	130	/*
	131	* Fill in the dma table, without crossing any 64kB boundaries.
	132	* Most hardware requires 16-bit alignment of all blocks,
	133	* but the trm290 requires 32-bit alignment.
	134	*/
	135
	136	while (cur_len) {
	137	if (count++ >= PRD_ENTRIES)
	138	goto use_pio_instead;
	139
	140	bcount = 0x10000 - (cur_addr & 0xffff);
	141	if (bcount > cur_len)
	142	bcount = cur_len;
	143	*table++ = cpu_to_le32(cur_addr);
	144	xcount = bcount & 0xffff;
	145	if (is_trm290)
	146	xcount = ((xcount >> 2) - 1) << 16;
769b49ce	147	else if (xcount == 0x0000) {
2dbe7e91 BZ	148	if (count++ >= PRD_ENTRIES)
	149	goto use_pio_instead;
	150	*table++ = cpu_to_le32(0x8000);
	151	*table++ = cpu_to_le32(cur_addr + 0x8000);
	152	xcount = 0x8000;
	153	}
	154	*table++ = cpu_to_le32(xcount);
	155	cur_addr += bcount;
	156	cur_len -= bcount;
	157	}
	158	}
	159
	160	if (count) {
	161	if (!is_trm290)
	162	*--table \|= cpu_to_le32(0x80000000);
	163	return count;
	164	}
	165
	166	use_pio_instead:
	167	printk(KERN_ERR "%s: %s\n", drive->name,
	168	count ? "DMA table too small" : "empty DMA table?");
	169
2dbe7e91 BZ	170	return 0; /* revert to PIO for this request */
	171	}
	172	EXPORT_SYMBOL_GPL(ide_build_dmatable);
	173
	174	/**
	175	* ide_dma_setup - begin a DMA phase
	176	* @drive: target device
22981694	177	* @cmd: command
2dbe7e91 BZ	178	*
	179	* Build an IDE DMA PRD (IDE speak for scatter gather table)
	180	* and then set up the DMA transfer registers for a device
	181	* that follows generic IDE PCI DMA behaviour. Controllers can
	182	* override this function if they need to
	183	*
	184	* Returns 0 on success. If a PIO fallback is required then 1
	185	* is returned.
	186	*/
	187
22981694	188	int ide_dma_setup(ide_drive_t drive, struct ide_cmd cmd)
2dbe7e91 BZ	189	{
2dbe7e91 BZ	190	ide_hwif_t *hwif = drive->hwif;
2dbe7e91	191	u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0;
22981694	192	u8 rw = (cmd->tf_flags & IDE_TFLAG_WRITE) ? 0 : ATA_DMA_WR;
2dbe7e91 BZ	193	u8 dma_stat;
2dbe7e91 BZ	194
2dbe7e91	195	/* fall back to pio! */
22981694 BZ	196	if (ide_build_dmatable(drive, cmd) == 0) {
22981694 BZ	197	ide_map_sg(drive, cmd);
2dbe7e91 BZ	198	return 1;
	199	}
	200
	201	/* PRD table */
05789634	202	if (mmio)
2dbe7e91 BZ	203	writel(hwif->dmatable_dma,
	204	(void __iomem *)(hwif->dma_base + ATA_DMA_TABLE_OFS));
	205	else
	206	outl(hwif->dmatable_dma, hwif->dma_base + ATA_DMA_TABLE_OFS);
	207
	208	/* specify r/w */
	209	if (mmio)
22981694	210	writeb(rw, (void __iomem *)(hwif->dma_base + ATA_DMA_CMD));
2dbe7e91	211	else
22981694	212	outb(rw, hwif->dma_base + ATA_DMA_CMD);
2dbe7e91 BZ	213
2dbe7e91 BZ	214	/* read DMA status for INTR & ERROR flags */
592b5315	215	dma_stat = hwif->dma_ops->dma_sff_read_status(hwif);
2dbe7e91 BZ	216
2dbe7e91 BZ	217	/* clear INTR & ERROR flags */
05789634	218	ide_dma_sff_write_status(hwif, dma_stat \| ATA_DMA_ERR \| ATA_DMA_INTR);
2dbe7e91	219
2dbe7e91 BZ	220	return 0;
	221	}
	222	EXPORT_SYMBOL_GPL(ide_dma_setup);
	223
	224	/**
22117d6e	225	* ide_dma_sff_timer_expiry - handle a DMA timeout
2dbe7e91 BZ	226	* @drive: Drive that timed out
	227	*
	228	* An IDE DMA transfer timed out. In the event of an error we ask
	229	* the driver to resolve the problem, if a DMA transfer is still
	230	* in progress we continue to wait (arguably we need to add a
	231	* secondary 'I don't care what the drive thinks' timeout here)
	232	* Finally if we have an interrupt we let it complete the I/O.
	233	* But only one time - we clear expiry and if it's still not
	234	* completed after WAIT_CMD, we error and retry in PIO.
	235	* This can occur if an interrupt is lost or due to hang or bugs.
	236	*/
	237
22117d6e	238	int ide_dma_sff_timer_expiry(ide_drive_t *drive)
2dbe7e91 BZ	239	{
2dbe7e91 BZ	240	ide_hwif_t *hwif = drive->hwif;
592b5315	241	u8 dma_stat = hwif->dma_ops->dma_sff_read_status(hwif);
2dbe7e91 BZ	242
	243	printk(KERN_WARNING "%s: %s: DMA status (0x%02x)\n",
	244	drive->name, __func__, dma_stat);
	245
	246	if ((dma_stat & 0x18) == 0x18) /* BUSY Stupid Early Timer !! */
	247	return WAIT_CMD;
	248
b65fac32	249	hwif->expiry = NULL; /* one free ride for now */
2dbe7e91	250
1d35364a	251	if (dma_stat & ATA_DMA_ERR) /* ERROR */
2dbe7e91 BZ	252	return -1;
2dbe7e91 BZ	253
1d35364a	254	if (dma_stat & ATA_DMA_ACTIVE) /* DMAing */
2dbe7e91 BZ	255	return WAIT_CMD;
2dbe7e91 BZ	256
1d35364a	257	if (dma_stat & ATA_DMA_INTR) /* Got an Interrupt */
2dbe7e91 BZ	258	return WAIT_CMD;
	259
	260	return 0; /* Status is unknown -- reset the bus */
	261	}
22117d6e	262	EXPORT_SYMBOL_GPL(ide_dma_sff_timer_expiry);
2dbe7e91 BZ	263
	264	void ide_dma_start(ide_drive_t *drive)
	265	{
	266	ide_hwif_t *hwif = drive->hwif;
	267	u8 dma_cmd;
	268
	269	/* Note that this is done after the cmd has
	270	* been issued to the drive, as per the BM-IDE spec.
	271	* The Promise Ultra33 doesn't work correctly when
	272	* we do this part before issuing the drive cmd.
	273	*/
	274	if (hwif->host_flags & IDE_HFLAG_MMIO) {
	275	dma_cmd = readb((void __iomem *)(hwif->dma_base + ATA_DMA_CMD));
1d35364a	276	writeb(dma_cmd \| ATA_DMA_START,
2dbe7e91 BZ	277	(void __iomem *)(hwif->dma_base + ATA_DMA_CMD));
	278	} else {
	279	dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
1d35364a	280	outb(dma_cmd \| ATA_DMA_START, hwif->dma_base + ATA_DMA_CMD);
2dbe7e91	281	}
2dbe7e91 BZ	282	}
	283	EXPORT_SYMBOL_GPL(ide_dma_start);
	284
	285	/* returns 1 on error, 0 otherwise */
	286	int ide_dma_end(ide_drive_t *drive)
	287	{
	288	ide_hwif_t *hwif = drive->hwif;
edafcf73	289	u8 dma_stat = 0, dma_cmd = 0;
2dbe7e91	290
1d35364a	291	/* stop DMA */
05789634	292	if (hwif->host_flags & IDE_HFLAG_MMIO) {
2dbe7e91	293	dma_cmd = readb((void __iomem *)(hwif->dma_base + ATA_DMA_CMD));
1d35364a	294	writeb(dma_cmd & ~ATA_DMA_START,
2dbe7e91 BZ	295	(void __iomem *)(hwif->dma_base + ATA_DMA_CMD));
	296	} else {
	297	dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
1d35364a	298	outb(dma_cmd & ~ATA_DMA_START, hwif->dma_base + ATA_DMA_CMD);
2dbe7e91 BZ	299	}
	300
	301	/* get DMA status */
592b5315	302	dma_stat = hwif->dma_ops->dma_sff_read_status(hwif);
2dbe7e91	303
05789634 SS	304	/* clear INTR & ERROR bits */
05789634 SS	305	ide_dma_sff_write_status(hwif, dma_stat \| ATA_DMA_ERR \| ATA_DMA_INTR);
2dbe7e91	306
edafcf73	307	#define CHECK_DMA_MASK (ATA_DMA_ACTIVE \| ATA_DMA_ERR \| ATA_DMA_INTR)
1d35364a BZ	308
1d35364a BZ	309	/* verify good DMA status */
edafcf73	310	if ((dma_stat & CHECK_DMA_MASK) != ATA_DMA_INTR)
1d35364a BZ	311	return 0x10 \| dma_stat;
1d35364a BZ	312	return 0;
2dbe7e91 BZ	313	}
	314	EXPORT_SYMBOL_GPL(ide_dma_end);
	315
	316	/* returns 1 if dma irq issued, 0 otherwise */
	317	int ide_dma_test_irq(ide_drive_t *drive)
	318	{
	319	ide_hwif_t *hwif = drive->hwif;
592b5315	320	u8 dma_stat = hwif->dma_ops->dma_sff_read_status(hwif);
2dbe7e91	321
1d35364a	322	return (dma_stat & ATA_DMA_INTR) ? 1 : 0;
2dbe7e91 BZ	323	}
	324	EXPORT_SYMBOL_GPL(ide_dma_test_irq);
	325
	326	const struct ide_dma_ops sff_dma_ops = {
	327	.dma_host_set = ide_dma_host_set,
	328	.dma_setup = ide_dma_setup,
2dbe7e91 BZ	329	.dma_start = ide_dma_start,
	330	.dma_end = ide_dma_end,
	331	.dma_test_irq = ide_dma_test_irq,
2dbe7e91	332	.dma_lost_irq = ide_dma_lost_irq,
35c9b4da	333	.dma_timer_expiry = ide_dma_sff_timer_expiry,
592b5315	334	.dma_sff_read_status = ide_dma_sff_read_status,
2dbe7e91 BZ	335	};
2dbe7e91 BZ	336	EXPORT_SYMBOL_GPL(sff_dma_ops);