Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org> |
3 | * Portions Copyright (C) 2001 Sun Microsystems, Inc. | |
4 | * Portions Copyright (C) 2003 Red Hat Inc | |
fbf47840 | 5 | * Portions Copyright (C) 2007 Bartlomiej Zolnierkiewicz |
ea2ac5a3 | 6 | * Portions Copyright (C) 2005-2008 MontaVista Software, Inc. |
1da177e4 LT |
7 | * |
8 | * Thanks to HighPoint Technologies for their assistance, and hardware. | |
9 | * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his | |
10 | * donation of an ABit BP6 mainboard, processor, and memory acellerated | |
11 | * development and support. | |
12 | * | |
b39b01ff | 13 | * |
836c0063 SS |
14 | * HighPoint has its own drivers (open source except for the RAID part) |
15 | * available from http://www.highpoint-tech.com/BIOS%20+%20Driver/. | |
16 | * This may be useful to anyone wanting to work on this driver, however do not | |
17 | * trust them too much since the code tends to become less and less meaningful | |
18 | * as the time passes... :-/ | |
b39b01ff | 19 | * |
1da177e4 LT |
20 | * Note that final HPT370 support was done by force extraction of GPL. |
21 | * | |
22 | * - add function for getting/setting power status of drive | |
23 | * - the HPT370's state machine can get confused. reset it before each dma | |
24 | * xfer to prevent that from happening. | |
25 | * - reset state engine whenever we get an error. | |
26 | * - check for busmaster state at end of dma. | |
27 | * - use new highpoint timings. | |
28 | * - detect bus speed using highpoint register. | |
29 | * - use pll if we don't have a clock table. added a 66MHz table that's | |
30 | * just 2x the 33MHz table. | |
31 | * - removed turnaround. NOTE: we never want to switch between pll and | |
32 | * pci clocks as the chip can glitch in those cases. the highpoint | |
33 | * approved workaround slows everything down too much to be useful. in | |
34 | * addition, we would have to serialize access to each chip. | |
35 | * Adrian Sun <a.sun@sun.com> | |
36 | * | |
37 | * add drive timings for 66MHz PCI bus, | |
38 | * fix ATA Cable signal detection, fix incorrect /proc info | |
39 | * add /proc display for per-drive PIO/DMA/UDMA mode and | |
40 | * per-channel ATA-33/66 Cable detect. | |
41 | * Duncan Laurie <void@sun.com> | |
42 | * | |
43 | * fixup /proc output for multiple controllers | |
44 | * Tim Hockin <thockin@sun.com> | |
45 | * | |
46 | * On hpt366: | |
47 | * Reset the hpt366 on error, reset on dma | |
48 | * Fix disabling Fast Interrupt hpt366. | |
49 | * Mike Waychison <crlf@sun.com> | |
50 | * | |
51 | * Added support for 372N clocking and clock switching. The 372N needs | |
52 | * different clocks on read/write. This requires overloading rw_disk and | |
53 | * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for | |
54 | * keeping me sane. | |
ccd32e22 | 55 | * Alan Cox <alan@lxorguk.ukuu.org.uk> |
1da177e4 | 56 | * |
836c0063 SS |
57 | * - fix the clock turnaround code: it was writing to the wrong ports when |
58 | * called for the secondary channel, caching the current clock mode per- | |
59 | * channel caused the cached register value to get out of sync with the | |
60 | * actual one, the channels weren't serialized, the turnaround shouldn't | |
61 | * be done on 66 MHz PCI bus | |
7b73ee05 SS |
62 | * - disable UltraATA/100 for HPT370 by default as the 33 MHz clock being used |
63 | * does not allow for this speed anyway | |
64 | * - avoid touching disabled channels (e.g. HPT371/N are single channel chips, | |
65 | * their primary channel is kind of virtual, it isn't tied to any pins) | |
471a0bda SS |
66 | * - fix/remove bad/unused timing tables and use one set of tables for the whole |
67 | * HPT37x chip family; save space by introducing the separate transfer mode | |
68 | * table in which the mode lookup is done | |
26c068da | 69 | * - use f_CNT value saved by the HighPoint BIOS as reading it directly gives |
72931368 SS |
70 | * the wrong PCI frequency since DPLL has already been calibrated by BIOS; |
71 | * read it only from the function 0 of HPT374 chips | |
33b18a60 SS |
72 | * - fix the hotswap code: it caused RESET- to glitch when tristating the bus, |
73 | * and for HPT36x the obsolete HDIO_TRISTATE_HWIF handler was called instead | |
73d1dd93 SS |
74 | * - pass to init_chipset() handlers a copy of the IDE PCI device structure as |
75 | * they tamper with its fields | |
7b73ee05 SS |
76 | * - pass to the init_setup handlers a copy of the ide_pci_device_t structure |
77 | * since they may tamper with its fields | |
90778574 SS |
78 | * - prefix the driver startup messages with the real chip name |
79 | * - claim the extra 240 bytes of I/O space for all chips | |
2648e5d9 | 80 | * - optimize the UltraDMA filtering and the drive list lookup code |
b4586715 | 81 | * - use pci_get_slot() to get to the function 1 of HPT36x/374 |
7b73ee05 SS |
82 | * - cache offset of the channel's misc. control registers (MCRs) being used |
83 | * throughout the driver | |
84 | * - only touch the relevant MCR when detecting the cable type on HPT374's | |
85 | * function 1 | |
abc4ad4c | 86 | * - rename all the register related variables consistently |
7b73ee05 SS |
87 | * - move all the interrupt twiddling code from the speedproc handlers into |
88 | * init_hwif_hpt366(), also grouping all the DMA related code together there | |
866664d7 | 89 | * - merge HPT36x/HPT37x speedproc handlers, fix PIO timing register mask and |
7b73ee05 SS |
90 | * separate the UltraDMA and MWDMA masks there to avoid changing PIO timings |
91 | * when setting an UltraDMA mode | |
92 | * - fix hpt3xx_tune_drive() to set the PIO mode requested, not always select | |
93 | * the best possible one | |
4bf63de2 | 94 | * - clean up DMA timeout handling for HPT370 |
7b73ee05 SS |
95 | * - switch to using the enumeration type to differ between the numerous chip |
96 | * variants, matching PCI device/revision ID with the chip type early, at the | |
97 | * init_setup stage | |
98 | * - extend the hpt_info structure to hold the DPLL and PCI clock frequencies, | |
99 | * stop duplicating it for each channel by storing the pointer in the pci_dev | |
100 | * structure: first, at the init_setup stage, point it to a static "template" | |
101 | * with only the chip type and its specific base DPLL frequency, the highest | |
2648e5d9 SS |
102 | * UltraDMA mode, and the chip settings table pointer filled, then, at the |
103 | * init_chipset stage, allocate per-chip instance and fill it with the rest | |
104 | * of the necessary information | |
7b73ee05 SS |
105 | * - get rid of the constant thresholds in the HPT37x PCI clock detection code, |
106 | * switch to calculating PCI clock frequency based on the chip's base DPLL | |
107 | * frequency | |
108 | * - switch to using the DPLL clock and enable UltraATA/133 mode by default on | |
278978e9 SS |
109 | * anything newer than HPT370/A (except HPT374 that is not capable of this |
110 | * mode according to the manual) | |
6273d26a SS |
111 | * - fold PCI clock detection and DPLL setup code into init_chipset_hpt366(), |
112 | * also fixing the interchanged 25/40 MHz PCI clock cases for HPT36x chips; | |
7b73ee05 SS |
113 | * unify HPT36x/37x timing setup code and the speedproc handlers by joining |
114 | * the register setting lists into the table indexed by the clock selected | |
2648e5d9 | 115 | * - set the correct hwif->ultra_mask for each individual chip |
b4e44369 | 116 | * - add Ultra and MW DMA mode filtering for the HPT37[24] based SATA cards |
c018f1ee SS |
117 | * - stop resetting HPT370's state machine before each DMA transfer as that has |
118 | * caused more harm than good | |
7b73ee05 | 119 | * Sergei Shtylyov, <sshtylyov@ru.mvista.com> or <source@mvista.com> |
1da177e4 LT |
120 | */ |
121 | ||
1da177e4 LT |
122 | #include <linux/types.h> |
123 | #include <linux/module.h> | |
124 | #include <linux/kernel.h> | |
125 | #include <linux/delay.h> | |
1da177e4 | 126 | #include <linux/blkdev.h> |
1da177e4 LT |
127 | #include <linux/interrupt.h> |
128 | #include <linux/pci.h> | |
129 | #include <linux/init.h> | |
130 | #include <linux/ide.h> | |
131 | ||
132 | #include <asm/uaccess.h> | |
133 | #include <asm/io.h> | |
1da177e4 | 134 | |
ced3ec8a BZ |
135 | #define DRV_NAME "hpt366" |
136 | ||
1da177e4 | 137 | /* various tuning parameters */ |
c018f1ee | 138 | #undef HPT_RESET_STATE_ENGINE |
836c0063 | 139 | #undef HPT_DELAY_INTERRUPT |
1da177e4 LT |
140 | |
141 | static const char *quirk_drives[] = { | |
142 | "QUANTUM FIREBALLlct08 08", | |
143 | "QUANTUM FIREBALLP KA6.4", | |
144 | "QUANTUM FIREBALLP LM20.4", | |
145 | "QUANTUM FIREBALLP LM20.5", | |
146 | NULL | |
147 | }; | |
148 | ||
149 | static const char *bad_ata100_5[] = { | |
150 | "IBM-DTLA-307075", | |
151 | "IBM-DTLA-307060", | |
152 | "IBM-DTLA-307045", | |
153 | "IBM-DTLA-307030", | |
154 | "IBM-DTLA-307020", | |
155 | "IBM-DTLA-307015", | |
156 | "IBM-DTLA-305040", | |
157 | "IBM-DTLA-305030", | |
158 | "IBM-DTLA-305020", | |
159 | "IC35L010AVER07-0", | |
160 | "IC35L020AVER07-0", | |
161 | "IC35L030AVER07-0", | |
162 | "IC35L040AVER07-0", | |
163 | "IC35L060AVER07-0", | |
164 | "WDC AC310200R", | |
165 | NULL | |
166 | }; | |
167 | ||
168 | static const char *bad_ata66_4[] = { | |
169 | "IBM-DTLA-307075", | |
170 | "IBM-DTLA-307060", | |
171 | "IBM-DTLA-307045", | |
172 | "IBM-DTLA-307030", | |
173 | "IBM-DTLA-307020", | |
174 | "IBM-DTLA-307015", | |
175 | "IBM-DTLA-305040", | |
176 | "IBM-DTLA-305030", | |
177 | "IBM-DTLA-305020", | |
178 | "IC35L010AVER07-0", | |
179 | "IC35L020AVER07-0", | |
180 | "IC35L030AVER07-0", | |
181 | "IC35L040AVER07-0", | |
182 | "IC35L060AVER07-0", | |
183 | "WDC AC310200R", | |
783353b1 | 184 | "MAXTOR STM3320620A", |
1da177e4 LT |
185 | NULL |
186 | }; | |
187 | ||
188 | static const char *bad_ata66_3[] = { | |
189 | "WDC AC310200R", | |
190 | NULL | |
191 | }; | |
192 | ||
193 | static const char *bad_ata33[] = { | |
194 | "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2", | |
195 | "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2", | |
196 | "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4", | |
197 | "Maxtor 90510D4", | |
198 | "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2", | |
199 | "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4", | |
200 | "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2", | |
201 | NULL | |
202 | }; | |
203 | ||
471a0bda SS |
204 | static u8 xfer_speeds[] = { |
205 | XFER_UDMA_6, | |
206 | XFER_UDMA_5, | |
207 | XFER_UDMA_4, | |
208 | XFER_UDMA_3, | |
209 | XFER_UDMA_2, | |
210 | XFER_UDMA_1, | |
211 | XFER_UDMA_0, | |
212 | ||
213 | XFER_MW_DMA_2, | |
214 | XFER_MW_DMA_1, | |
215 | XFER_MW_DMA_0, | |
216 | ||
217 | XFER_PIO_4, | |
218 | XFER_PIO_3, | |
219 | XFER_PIO_2, | |
220 | XFER_PIO_1, | |
221 | XFER_PIO_0 | |
1da177e4 LT |
222 | }; |
223 | ||
471a0bda SS |
224 | /* Key for bus clock timings |
225 | * 36x 37x | |
226 | * bits bits | |
227 | * 0:3 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA. | |
228 | * cycles = value + 1 | |
229 | * 4:7 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA. | |
230 | * cycles = value + 1 | |
231 | * 8:11 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file | |
232 | * register access. | |
233 | * 12:15 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file | |
234 | * register access. | |
235 | * 16:18 18:20 udma_cycle_time. Clock cycles for UDMA xfer. | |
236 | * - 21 CLK frequency: 0=ATA clock, 1=dual ATA clock. | |
237 | * 19:21 22:24 pre_high_time. Time to initialize the 1st cycle for PIO and | |
238 | * MW DMA xfer. | |
239 | * 22:24 25:27 cmd_pre_high_time. Time to initialize the 1st PIO cycle for | |
240 | * task file register access. | |
241 | * 28 28 UDMA enable. | |
242 | * 29 29 DMA enable. | |
243 | * 30 30 PIO MST enable. If set, the chip is in bus master mode during | |
244 | * PIO xfer. | |
245 | * 31 31 FIFO enable. | |
1da177e4 | 246 | */ |
1da177e4 | 247 | |
471a0bda SS |
248 | static u32 forty_base_hpt36x[] = { |
249 | /* XFER_UDMA_6 */ 0x900fd943, | |
250 | /* XFER_UDMA_5 */ 0x900fd943, | |
251 | /* XFER_UDMA_4 */ 0x900fd943, | |
252 | /* XFER_UDMA_3 */ 0x900ad943, | |
253 | /* XFER_UDMA_2 */ 0x900bd943, | |
254 | /* XFER_UDMA_1 */ 0x9008d943, | |
255 | /* XFER_UDMA_0 */ 0x9008d943, | |
256 | ||
257 | /* XFER_MW_DMA_2 */ 0xa008d943, | |
258 | /* XFER_MW_DMA_1 */ 0xa010d955, | |
259 | /* XFER_MW_DMA_0 */ 0xa010d9fc, | |
260 | ||
261 | /* XFER_PIO_4 */ 0xc008d963, | |
262 | /* XFER_PIO_3 */ 0xc010d974, | |
263 | /* XFER_PIO_2 */ 0xc010d997, | |
264 | /* XFER_PIO_1 */ 0xc010d9c7, | |
265 | /* XFER_PIO_0 */ 0xc018d9d9 | |
1da177e4 LT |
266 | }; |
267 | ||
471a0bda SS |
268 | static u32 thirty_three_base_hpt36x[] = { |
269 | /* XFER_UDMA_6 */ 0x90c9a731, | |
270 | /* XFER_UDMA_5 */ 0x90c9a731, | |
271 | /* XFER_UDMA_4 */ 0x90c9a731, | |
272 | /* XFER_UDMA_3 */ 0x90cfa731, | |
273 | /* XFER_UDMA_2 */ 0x90caa731, | |
274 | /* XFER_UDMA_1 */ 0x90cba731, | |
275 | /* XFER_UDMA_0 */ 0x90c8a731, | |
276 | ||
277 | /* XFER_MW_DMA_2 */ 0xa0c8a731, | |
278 | /* XFER_MW_DMA_1 */ 0xa0c8a732, /* 0xa0c8a733 */ | |
279 | /* XFER_MW_DMA_0 */ 0xa0c8a797, | |
280 | ||
281 | /* XFER_PIO_4 */ 0xc0c8a731, | |
282 | /* XFER_PIO_3 */ 0xc0c8a742, | |
283 | /* XFER_PIO_2 */ 0xc0d0a753, | |
284 | /* XFER_PIO_1 */ 0xc0d0a7a3, /* 0xc0d0a793 */ | |
285 | /* XFER_PIO_0 */ 0xc0d0a7aa /* 0xc0d0a7a7 */ | |
1da177e4 LT |
286 | }; |
287 | ||
471a0bda SS |
288 | static u32 twenty_five_base_hpt36x[] = { |
289 | /* XFER_UDMA_6 */ 0x90c98521, | |
290 | /* XFER_UDMA_5 */ 0x90c98521, | |
291 | /* XFER_UDMA_4 */ 0x90c98521, | |
292 | /* XFER_UDMA_3 */ 0x90cf8521, | |
293 | /* XFER_UDMA_2 */ 0x90cf8521, | |
294 | /* XFER_UDMA_1 */ 0x90cb8521, | |
295 | /* XFER_UDMA_0 */ 0x90cb8521, | |
296 | ||
297 | /* XFER_MW_DMA_2 */ 0xa0ca8521, | |
298 | /* XFER_MW_DMA_1 */ 0xa0ca8532, | |
299 | /* XFER_MW_DMA_0 */ 0xa0ca8575, | |
300 | ||
301 | /* XFER_PIO_4 */ 0xc0ca8521, | |
302 | /* XFER_PIO_3 */ 0xc0ca8532, | |
303 | /* XFER_PIO_2 */ 0xc0ca8542, | |
304 | /* XFER_PIO_1 */ 0xc0d08572, | |
305 | /* XFER_PIO_0 */ 0xc0d08585 | |
1da177e4 LT |
306 | }; |
307 | ||
809b53c4 SS |
308 | #if 0 |
309 | /* These are the timing tables from the HighPoint open source drivers... */ | |
471a0bda SS |
310 | static u32 thirty_three_base_hpt37x[] = { |
311 | /* XFER_UDMA_6 */ 0x12446231, /* 0x12646231 ?? */ | |
312 | /* XFER_UDMA_5 */ 0x12446231, | |
313 | /* XFER_UDMA_4 */ 0x12446231, | |
314 | /* XFER_UDMA_3 */ 0x126c6231, | |
315 | /* XFER_UDMA_2 */ 0x12486231, | |
316 | /* XFER_UDMA_1 */ 0x124c6233, | |
317 | /* XFER_UDMA_0 */ 0x12506297, | |
318 | ||
319 | /* XFER_MW_DMA_2 */ 0x22406c31, | |
320 | /* XFER_MW_DMA_1 */ 0x22406c33, | |
321 | /* XFER_MW_DMA_0 */ 0x22406c97, | |
322 | ||
323 | /* XFER_PIO_4 */ 0x06414e31, | |
324 | /* XFER_PIO_3 */ 0x06414e42, | |
325 | /* XFER_PIO_2 */ 0x06414e53, | |
326 | /* XFER_PIO_1 */ 0x06814e93, | |
327 | /* XFER_PIO_0 */ 0x06814ea7 | |
1da177e4 LT |
328 | }; |
329 | ||
471a0bda SS |
330 | static u32 fifty_base_hpt37x[] = { |
331 | /* XFER_UDMA_6 */ 0x12848242, | |
332 | /* XFER_UDMA_5 */ 0x12848242, | |
333 | /* XFER_UDMA_4 */ 0x12ac8242, | |
334 | /* XFER_UDMA_3 */ 0x128c8242, | |
335 | /* XFER_UDMA_2 */ 0x120c8242, | |
336 | /* XFER_UDMA_1 */ 0x12148254, | |
337 | /* XFER_UDMA_0 */ 0x121882ea, | |
338 | ||
339 | /* XFER_MW_DMA_2 */ 0x22808242, | |
340 | /* XFER_MW_DMA_1 */ 0x22808254, | |
341 | /* XFER_MW_DMA_0 */ 0x228082ea, | |
342 | ||
343 | /* XFER_PIO_4 */ 0x0a81f442, | |
344 | /* XFER_PIO_3 */ 0x0a81f443, | |
345 | /* XFER_PIO_2 */ 0x0a81f454, | |
346 | /* XFER_PIO_1 */ 0x0ac1f465, | |
347 | /* XFER_PIO_0 */ 0x0ac1f48a | |
1da177e4 LT |
348 | }; |
349 | ||
471a0bda SS |
350 | static u32 sixty_six_base_hpt37x[] = { |
351 | /* XFER_UDMA_6 */ 0x1c869c62, | |
352 | /* XFER_UDMA_5 */ 0x1cae9c62, /* 0x1c8a9c62 */ | |
353 | /* XFER_UDMA_4 */ 0x1c8a9c62, | |
354 | /* XFER_UDMA_3 */ 0x1c8e9c62, | |
355 | /* XFER_UDMA_2 */ 0x1c929c62, | |
356 | /* XFER_UDMA_1 */ 0x1c9a9c62, | |
357 | /* XFER_UDMA_0 */ 0x1c829c62, | |
358 | ||
359 | /* XFER_MW_DMA_2 */ 0x2c829c62, | |
360 | /* XFER_MW_DMA_1 */ 0x2c829c66, | |
361 | /* XFER_MW_DMA_0 */ 0x2c829d2e, | |
362 | ||
363 | /* XFER_PIO_4 */ 0x0c829c62, | |
364 | /* XFER_PIO_3 */ 0x0c829c84, | |
365 | /* XFER_PIO_2 */ 0x0c829ca6, | |
366 | /* XFER_PIO_1 */ 0x0d029d26, | |
367 | /* XFER_PIO_0 */ 0x0d029d5e | |
1da177e4 | 368 | }; |
809b53c4 SS |
369 | #else |
370 | /* | |
371 | * The following are the new timing tables with PIO mode data/taskfile transfer | |
372 | * overclocking fixed... | |
373 | */ | |
374 | ||
375 | /* This table is taken from the HPT370 data manual rev. 1.02 */ | |
376 | static u32 thirty_three_base_hpt37x[] = { | |
377 | /* XFER_UDMA_6 */ 0x16455031, /* 0x16655031 ?? */ | |
378 | /* XFER_UDMA_5 */ 0x16455031, | |
379 | /* XFER_UDMA_4 */ 0x16455031, | |
380 | /* XFER_UDMA_3 */ 0x166d5031, | |
381 | /* XFER_UDMA_2 */ 0x16495031, | |
382 | /* XFER_UDMA_1 */ 0x164d5033, | |
383 | /* XFER_UDMA_0 */ 0x16515097, | |
384 | ||
385 | /* XFER_MW_DMA_2 */ 0x26515031, | |
386 | /* XFER_MW_DMA_1 */ 0x26515033, | |
387 | /* XFER_MW_DMA_0 */ 0x26515097, | |
388 | ||
389 | /* XFER_PIO_4 */ 0x06515021, | |
390 | /* XFER_PIO_3 */ 0x06515022, | |
391 | /* XFER_PIO_2 */ 0x06515033, | |
392 | /* XFER_PIO_1 */ 0x06915065, | |
393 | /* XFER_PIO_0 */ 0x06d1508a | |
394 | }; | |
395 | ||
396 | static u32 fifty_base_hpt37x[] = { | |
397 | /* XFER_UDMA_6 */ 0x1a861842, | |
398 | /* XFER_UDMA_5 */ 0x1a861842, | |
399 | /* XFER_UDMA_4 */ 0x1aae1842, | |
400 | /* XFER_UDMA_3 */ 0x1a8e1842, | |
401 | /* XFER_UDMA_2 */ 0x1a0e1842, | |
402 | /* XFER_UDMA_1 */ 0x1a161854, | |
403 | /* XFER_UDMA_0 */ 0x1a1a18ea, | |
404 | ||
405 | /* XFER_MW_DMA_2 */ 0x2a821842, | |
406 | /* XFER_MW_DMA_1 */ 0x2a821854, | |
407 | /* XFER_MW_DMA_0 */ 0x2a8218ea, | |
408 | ||
409 | /* XFER_PIO_4 */ 0x0a821842, | |
410 | /* XFER_PIO_3 */ 0x0a821843, | |
411 | /* XFER_PIO_2 */ 0x0a821855, | |
412 | /* XFER_PIO_1 */ 0x0ac218a8, | |
413 | /* XFER_PIO_0 */ 0x0b02190c | |
414 | }; | |
415 | ||
416 | static u32 sixty_six_base_hpt37x[] = { | |
417 | /* XFER_UDMA_6 */ 0x1c86fe62, | |
418 | /* XFER_UDMA_5 */ 0x1caefe62, /* 0x1c8afe62 */ | |
419 | /* XFER_UDMA_4 */ 0x1c8afe62, | |
420 | /* XFER_UDMA_3 */ 0x1c8efe62, | |
421 | /* XFER_UDMA_2 */ 0x1c92fe62, | |
422 | /* XFER_UDMA_1 */ 0x1c9afe62, | |
423 | /* XFER_UDMA_0 */ 0x1c82fe62, | |
424 | ||
425 | /* XFER_MW_DMA_2 */ 0x2c82fe62, | |
426 | /* XFER_MW_DMA_1 */ 0x2c82fe66, | |
427 | /* XFER_MW_DMA_0 */ 0x2c82ff2e, | |
428 | ||
429 | /* XFER_PIO_4 */ 0x0c82fe62, | |
430 | /* XFER_PIO_3 */ 0x0c82fe84, | |
431 | /* XFER_PIO_2 */ 0x0c82fea6, | |
432 | /* XFER_PIO_1 */ 0x0d02ff26, | |
433 | /* XFER_PIO_0 */ 0x0d42ff7f | |
434 | }; | |
435 | #endif | |
1da177e4 | 436 | |
1da177e4 | 437 | #define HPT366_DEBUG_DRIVE_INFO 0 |
7b73ee05 SS |
438 | #define HPT371_ALLOW_ATA133_6 1 |
439 | #define HPT302_ALLOW_ATA133_6 1 | |
440 | #define HPT372_ALLOW_ATA133_6 1 | |
e139b0b0 | 441 | #define HPT370_ALLOW_ATA100_5 0 |
1da177e4 LT |
442 | #define HPT366_ALLOW_ATA66_4 1 |
443 | #define HPT366_ALLOW_ATA66_3 1 | |
444 | #define HPT366_MAX_DEVS 8 | |
445 | ||
7b73ee05 SS |
446 | /* Supported ATA clock frequencies */ |
447 | enum ata_clock { | |
448 | ATA_CLOCK_25MHZ, | |
449 | ATA_CLOCK_33MHZ, | |
450 | ATA_CLOCK_40MHZ, | |
451 | ATA_CLOCK_50MHZ, | |
452 | ATA_CLOCK_66MHZ, | |
453 | NUM_ATA_CLOCKS | |
454 | }; | |
1da177e4 | 455 | |
866664d7 SS |
456 | struct hpt_timings { |
457 | u32 pio_mask; | |
458 | u32 dma_mask; | |
459 | u32 ultra_mask; | |
460 | u32 *clock_table[NUM_ATA_CLOCKS]; | |
461 | }; | |
462 | ||
b39b01ff | 463 | /* |
7b73ee05 | 464 | * Hold all the HighPoint chip information in one place. |
b39b01ff | 465 | */ |
1da177e4 | 466 | |
7b73ee05 | 467 | struct hpt_info { |
fbf47840 | 468 | char *chip_name; /* Chip name */ |
7b73ee05 | 469 | u8 chip_type; /* Chip type */ |
fbf47840 | 470 | u8 udma_mask; /* Allowed UltraDMA modes mask. */ |
7b73ee05 SS |
471 | u8 dpll_clk; /* DPLL clock in MHz */ |
472 | u8 pci_clk; /* PCI clock in MHz */ | |
866664d7 SS |
473 | struct hpt_timings *timings; /* Chipset timing data */ |
474 | u8 clock; /* ATA clock selected */ | |
b39b01ff AC |
475 | }; |
476 | ||
7b73ee05 SS |
477 | /* Supported HighPoint chips */ |
478 | enum { | |
479 | HPT36x, | |
480 | HPT370, | |
481 | HPT370A, | |
482 | HPT374, | |
483 | HPT372, | |
484 | HPT372A, | |
485 | HPT302, | |
486 | HPT371, | |
487 | HPT372N, | |
488 | HPT302N, | |
489 | HPT371N | |
490 | }; | |
b39b01ff | 491 | |
866664d7 SS |
492 | static struct hpt_timings hpt36x_timings = { |
493 | .pio_mask = 0xc1f8ffff, | |
494 | .dma_mask = 0x303800ff, | |
495 | .ultra_mask = 0x30070000, | |
496 | .clock_table = { | |
497 | [ATA_CLOCK_25MHZ] = twenty_five_base_hpt36x, | |
498 | [ATA_CLOCK_33MHZ] = thirty_three_base_hpt36x, | |
499 | [ATA_CLOCK_40MHZ] = forty_base_hpt36x, | |
500 | [ATA_CLOCK_50MHZ] = NULL, | |
501 | [ATA_CLOCK_66MHZ] = NULL | |
502 | } | |
7b73ee05 | 503 | }; |
e139b0b0 | 504 | |
866664d7 SS |
505 | static struct hpt_timings hpt37x_timings = { |
506 | .pio_mask = 0xcfc3ffff, | |
507 | .dma_mask = 0x31c001ff, | |
508 | .ultra_mask = 0x303c0000, | |
509 | .clock_table = { | |
510 | [ATA_CLOCK_25MHZ] = NULL, | |
511 | [ATA_CLOCK_33MHZ] = thirty_three_base_hpt37x, | |
512 | [ATA_CLOCK_40MHZ] = NULL, | |
513 | [ATA_CLOCK_50MHZ] = fifty_base_hpt37x, | |
514 | [ATA_CLOCK_66MHZ] = sixty_six_base_hpt37x | |
515 | } | |
7b73ee05 | 516 | }; |
1da177e4 | 517 | |
282037f1 | 518 | static const struct hpt_info hpt36x __devinitdata = { |
fbf47840 | 519 | .chip_name = "HPT36x", |
7b73ee05 | 520 | .chip_type = HPT36x, |
fbf47840 | 521 | .udma_mask = HPT366_ALLOW_ATA66_3 ? (HPT366_ALLOW_ATA66_4 ? ATA_UDMA4 : ATA_UDMA3) : ATA_UDMA2, |
7b73ee05 | 522 | .dpll_clk = 0, /* no DPLL */ |
866664d7 | 523 | .timings = &hpt36x_timings |
7b73ee05 SS |
524 | }; |
525 | ||
282037f1 | 526 | static const struct hpt_info hpt370 __devinitdata = { |
fbf47840 | 527 | .chip_name = "HPT370", |
7b73ee05 | 528 | .chip_type = HPT370, |
fbf47840 | 529 | .udma_mask = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4, |
7b73ee05 | 530 | .dpll_clk = 48, |
866664d7 | 531 | .timings = &hpt37x_timings |
7b73ee05 SS |
532 | }; |
533 | ||
282037f1 | 534 | static const struct hpt_info hpt370a __devinitdata = { |
fbf47840 | 535 | .chip_name = "HPT370A", |
7b73ee05 | 536 | .chip_type = HPT370A, |
fbf47840 | 537 | .udma_mask = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4, |
7b73ee05 | 538 | .dpll_clk = 48, |
866664d7 | 539 | .timings = &hpt37x_timings |
7b73ee05 SS |
540 | }; |
541 | ||
282037f1 | 542 | static const struct hpt_info hpt374 __devinitdata = { |
fbf47840 | 543 | .chip_name = "HPT374", |
7b73ee05 | 544 | .chip_type = HPT374, |
fbf47840 | 545 | .udma_mask = ATA_UDMA5, |
7b73ee05 | 546 | .dpll_clk = 48, |
866664d7 | 547 | .timings = &hpt37x_timings |
7b73ee05 SS |
548 | }; |
549 | ||
282037f1 | 550 | static const struct hpt_info hpt372 __devinitdata = { |
fbf47840 | 551 | .chip_name = "HPT372", |
7b73ee05 | 552 | .chip_type = HPT372, |
fbf47840 | 553 | .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5, |
7b73ee05 | 554 | .dpll_clk = 55, |
866664d7 | 555 | .timings = &hpt37x_timings |
7b73ee05 SS |
556 | }; |
557 | ||
282037f1 | 558 | static const struct hpt_info hpt372a __devinitdata = { |
fbf47840 | 559 | .chip_name = "HPT372A", |
7b73ee05 | 560 | .chip_type = HPT372A, |
fbf47840 | 561 | .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5, |
7b73ee05 | 562 | .dpll_clk = 66, |
866664d7 | 563 | .timings = &hpt37x_timings |
7b73ee05 SS |
564 | }; |
565 | ||
282037f1 | 566 | static const struct hpt_info hpt302 __devinitdata = { |
fbf47840 | 567 | .chip_name = "HPT302", |
7b73ee05 | 568 | .chip_type = HPT302, |
fbf47840 | 569 | .udma_mask = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5, |
7b73ee05 | 570 | .dpll_clk = 66, |
866664d7 | 571 | .timings = &hpt37x_timings |
7b73ee05 SS |
572 | }; |
573 | ||
282037f1 | 574 | static const struct hpt_info hpt371 __devinitdata = { |
fbf47840 | 575 | .chip_name = "HPT371", |
7b73ee05 | 576 | .chip_type = HPT371, |
fbf47840 | 577 | .udma_mask = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5, |
7b73ee05 | 578 | .dpll_clk = 66, |
866664d7 | 579 | .timings = &hpt37x_timings |
7b73ee05 SS |
580 | }; |
581 | ||
282037f1 | 582 | static const struct hpt_info hpt372n __devinitdata = { |
fbf47840 | 583 | .chip_name = "HPT372N", |
7b73ee05 | 584 | .chip_type = HPT372N, |
fbf47840 | 585 | .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5, |
7b73ee05 | 586 | .dpll_clk = 77, |
866664d7 | 587 | .timings = &hpt37x_timings |
7b73ee05 SS |
588 | }; |
589 | ||
282037f1 | 590 | static const struct hpt_info hpt302n __devinitdata = { |
fbf47840 | 591 | .chip_name = "HPT302N", |
7b73ee05 | 592 | .chip_type = HPT302N, |
fbf47840 | 593 | .udma_mask = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5, |
7b73ee05 | 594 | .dpll_clk = 77, |
866664d7 | 595 | .timings = &hpt37x_timings |
7b73ee05 SS |
596 | }; |
597 | ||
282037f1 | 598 | static const struct hpt_info hpt371n __devinitdata = { |
fbf47840 | 599 | .chip_name = "HPT371N", |
7b73ee05 | 600 | .chip_type = HPT371N, |
fbf47840 | 601 | .udma_mask = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5, |
7b73ee05 | 602 | .dpll_clk = 77, |
866664d7 | 603 | .timings = &hpt37x_timings |
7b73ee05 | 604 | }; |
1da177e4 | 605 | |
e139b0b0 SS |
606 | static int check_in_drive_list(ide_drive_t *drive, const char **list) |
607 | { | |
4dde4492 | 608 | char *m = (char *)&drive->id[ATA_ID_PROD]; |
e139b0b0 SS |
609 | |
610 | while (*list) | |
4dde4492 | 611 | if (!strcmp(*list++, m)) |
e139b0b0 SS |
612 | return 1; |
613 | return 0; | |
614 | } | |
1da177e4 | 615 | |
62ff2ecf MS |
616 | static struct hpt_info *hpt3xx_get_info(struct device *dev) |
617 | { | |
618 | struct ide_host *host = dev_get_drvdata(dev); | |
619 | struct hpt_info *info = (struct hpt_info *)host->host_priv; | |
620 | ||
621 | return dev == host->dev[1] ? info + 1 : info; | |
622 | } | |
623 | ||
1da177e4 | 624 | /* |
2808b0a9 SS |
625 | * The Marvell bridge chips used on the HighPoint SATA cards do not seem |
626 | * to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes... | |
1da177e4 | 627 | */ |
2d5eaa6d BZ |
628 | |
629 | static u8 hpt3xx_udma_filter(ide_drive_t *drive) | |
1da177e4 | 630 | { |
898ec223 | 631 | ide_hwif_t *hwif = drive->hwif; |
62ff2ecf | 632 | struct hpt_info *info = hpt3xx_get_info(hwif->dev); |
2808b0a9 | 633 | u8 mask = hwif->ultra_mask; |
1da177e4 | 634 | |
2648e5d9 | 635 | switch (info->chip_type) { |
2648e5d9 SS |
636 | case HPT36x: |
637 | if (!HPT366_ALLOW_ATA66_4 || | |
638 | check_in_drive_list(drive, bad_ata66_4)) | |
2808b0a9 | 639 | mask = ATA_UDMA3; |
7b73ee05 | 640 | |
2648e5d9 SS |
641 | if (!HPT366_ALLOW_ATA66_3 || |
642 | check_in_drive_list(drive, bad_ata66_3)) | |
2808b0a9 | 643 | mask = ATA_UDMA2; |
2648e5d9 | 644 | break; |
2808b0a9 SS |
645 | case HPT370: |
646 | if (!HPT370_ALLOW_ATA100_5 || | |
647 | check_in_drive_list(drive, bad_ata100_5)) | |
648 | mask = ATA_UDMA4; | |
649 | break; | |
650 | case HPT370A: | |
651 | if (!HPT370_ALLOW_ATA100_5 || | |
652 | check_in_drive_list(drive, bad_ata100_5)) | |
653 | return ATA_UDMA4; | |
654 | case HPT372 : | |
655 | case HPT372A: | |
656 | case HPT372N: | |
657 | case HPT374 : | |
367d7e78 | 658 | if (ata_id_is_sata(drive->id)) |
2808b0a9 SS |
659 | mask &= ~0x0e; |
660 | /* Fall thru */ | |
2648e5d9 | 661 | default: |
2808b0a9 | 662 | return mask; |
1da177e4 | 663 | } |
2648e5d9 SS |
664 | |
665 | return check_in_drive_list(drive, bad_ata33) ? 0x00 : mask; | |
1da177e4 LT |
666 | } |
667 | ||
b4e44369 SS |
668 | static u8 hpt3xx_mdma_filter(ide_drive_t *drive) |
669 | { | |
898ec223 | 670 | ide_hwif_t *hwif = drive->hwif; |
62ff2ecf | 671 | struct hpt_info *info = hpt3xx_get_info(hwif->dev); |
b4e44369 SS |
672 | |
673 | switch (info->chip_type) { | |
674 | case HPT372 : | |
675 | case HPT372A: | |
676 | case HPT372N: | |
677 | case HPT374 : | |
367d7e78 | 678 | if (ata_id_is_sata(drive->id)) |
b4e44369 SS |
679 | return 0x00; |
680 | /* Fall thru */ | |
681 | default: | |
682 | return 0x07; | |
683 | } | |
684 | } | |
685 | ||
7b73ee05 | 686 | static u32 get_speed_setting(u8 speed, struct hpt_info *info) |
1da177e4 | 687 | { |
471a0bda SS |
688 | int i; |
689 | ||
690 | /* | |
691 | * Lookup the transfer mode table to get the index into | |
692 | * the timing table. | |
693 | * | |
694 | * NOTE: For XFER_PIO_SLOW, PIO mode 0 timings will be used. | |
695 | */ | |
696 | for (i = 0; i < ARRAY_SIZE(xfer_speeds) - 1; i++) | |
697 | if (xfer_speeds[i] == speed) | |
698 | break; | |
866664d7 SS |
699 | |
700 | return info->timings->clock_table[info->clock][i]; | |
1da177e4 LT |
701 | } |
702 | ||
866664d7 | 703 | static void hpt3xx_set_mode(ide_drive_t *drive, const u8 speed) |
1da177e4 | 704 | { |
74811f35 BZ |
705 | ide_hwif_t *hwif = drive->hwif; |
706 | struct pci_dev *dev = to_pci_dev(hwif->dev); | |
62ff2ecf | 707 | struct hpt_info *info = hpt3xx_get_info(hwif->dev); |
866664d7 SS |
708 | struct hpt_timings *t = info->timings; |
709 | u8 itr_addr = 0x40 + (drive->dn * 4); | |
26ccb802 | 710 | u32 old_itr = 0; |
ceb1b2c5 | 711 | u32 new_itr = get_speed_setting(speed, info); |
866664d7 SS |
712 | u32 itr_mask = speed < XFER_MW_DMA_0 ? t->pio_mask : |
713 | (speed < XFER_UDMA_0 ? t->dma_mask : | |
714 | t->ultra_mask); | |
b39b01ff | 715 | |
ceb1b2c5 SS |
716 | pci_read_config_dword(dev, itr_addr, &old_itr); |
717 | new_itr = (old_itr & ~itr_mask) | (new_itr & itr_mask); | |
1da177e4 | 718 | /* |
abc4ad4c SS |
719 | * Disable on-chip PIO FIFO/buffer (and PIO MST mode as well) |
720 | * to avoid problems handling I/O errors later | |
1da177e4 | 721 | */ |
abc4ad4c | 722 | new_itr &= ~0xc0000000; |
1da177e4 | 723 | |
abc4ad4c | 724 | pci_write_config_dword(dev, itr_addr, new_itr); |
1da177e4 LT |
725 | } |
726 | ||
26bcb879 | 727 | static void hpt3xx_set_pio_mode(ide_drive_t *drive, const u8 pio) |
1da177e4 | 728 | { |
866664d7 | 729 | hpt3xx_set_mode(drive, XFER_PIO_0 + pio); |
1da177e4 LT |
730 | } |
731 | ||
f01393e4 | 732 | static void hpt3xx_quirkproc(ide_drive_t *drive) |
1da177e4 | 733 | { |
4dde4492 | 734 | char *m = (char *)&drive->id[ATA_ID_PROD]; |
e139b0b0 SS |
735 | const char **list = quirk_drives; |
736 | ||
737 | while (*list) | |
4dde4492 | 738 | if (strstr(m, *list++)) { |
f01393e4 BZ |
739 | drive->quirk_list = 1; |
740 | return; | |
741 | } | |
742 | ||
743 | drive->quirk_list = 0; | |
1da177e4 LT |
744 | } |
745 | ||
26ccb802 | 746 | static void hpt3xx_maskproc(ide_drive_t *drive, int mask) |
1da177e4 | 747 | { |
898ec223 | 748 | ide_hwif_t *hwif = drive->hwif; |
36501650 | 749 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
62ff2ecf | 750 | struct hpt_info *info = hpt3xx_get_info(hwif->dev); |
1da177e4 | 751 | |
ea2ac5a3 SS |
752 | if (drive->quirk_list == 0) |
753 | return; | |
754 | ||
755 | if (info->chip_type >= HPT370) { | |
756 | u8 scr1 = 0; | |
757 | ||
758 | pci_read_config_byte(dev, 0x5a, &scr1); | |
759 | if (((scr1 & 0x10) >> 4) != mask) { | |
abc4ad4c | 760 | if (mask) |
ea2ac5a3 | 761 | scr1 |= 0x10; |
abc4ad4c | 762 | else |
ea2ac5a3 SS |
763 | scr1 &= ~0x10; |
764 | pci_write_config_byte(dev, 0x5a, scr1); | |
1da177e4 | 765 | } |
ea2ac5a3 SS |
766 | } else if (mask) |
767 | disable_irq(hwif->irq); | |
768 | else | |
769 | enable_irq(hwif->irq); | |
1da177e4 LT |
770 | } |
771 | ||
1da177e4 | 772 | /* |
abc4ad4c | 773 | * This is specific to the HPT366 UDMA chipset |
1da177e4 LT |
774 | * by HighPoint|Triones Technologies, Inc. |
775 | */ | |
841d2a9b | 776 | static void hpt366_dma_lost_irq(ide_drive_t *drive) |
1da177e4 | 777 | { |
36501650 | 778 | struct pci_dev *dev = to_pci_dev(drive->hwif->dev); |
abc4ad4c SS |
779 | u8 mcr1 = 0, mcr3 = 0, scr1 = 0; |
780 | ||
781 | pci_read_config_byte(dev, 0x50, &mcr1); | |
782 | pci_read_config_byte(dev, 0x52, &mcr3); | |
783 | pci_read_config_byte(dev, 0x5a, &scr1); | |
784 | printk("%s: (%s) mcr1=0x%02x, mcr3=0x%02x, scr1=0x%02x\n", | |
eb63963a | 785 | drive->name, __func__, mcr1, mcr3, scr1); |
abc4ad4c SS |
786 | if (scr1 & 0x10) |
787 | pci_write_config_byte(dev, 0x5a, scr1 & ~0x10); | |
841d2a9b | 788 | ide_dma_lost_irq(drive); |
1da177e4 LT |
789 | } |
790 | ||
4bf63de2 | 791 | static void hpt370_clear_engine(ide_drive_t *drive) |
1da177e4 | 792 | { |
898ec223 | 793 | ide_hwif_t *hwif = drive->hwif; |
36501650 | 794 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
abc4ad4c | 795 | |
36501650 | 796 | pci_write_config_byte(dev, hwif->select_data, 0x37); |
1da177e4 LT |
797 | udelay(10); |
798 | } | |
799 | ||
4bf63de2 SS |
800 | static void hpt370_irq_timeout(ide_drive_t *drive) |
801 | { | |
898ec223 | 802 | ide_hwif_t *hwif = drive->hwif; |
36501650 | 803 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
4bf63de2 SS |
804 | u16 bfifo = 0; |
805 | u8 dma_cmd; | |
806 | ||
36501650 | 807 | pci_read_config_word(dev, hwif->select_data + 2, &bfifo); |
4bf63de2 SS |
808 | printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo & 0x1ff); |
809 | ||
810 | /* get DMA command mode */ | |
cab7f8ed | 811 | dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD); |
4bf63de2 | 812 | /* stop DMA */ |
cab7f8ed | 813 | outb(dma_cmd & ~0x1, hwif->dma_base + ATA_DMA_CMD); |
4bf63de2 SS |
814 | hpt370_clear_engine(drive); |
815 | } | |
816 | ||
5e37bdc0 | 817 | static void hpt370_dma_start(ide_drive_t *drive) |
1da177e4 LT |
818 | { |
819 | #ifdef HPT_RESET_STATE_ENGINE | |
820 | hpt370_clear_engine(drive); | |
821 | #endif | |
822 | ide_dma_start(drive); | |
823 | } | |
824 | ||
5e37bdc0 | 825 | static int hpt370_dma_end(ide_drive_t *drive) |
1da177e4 | 826 | { |
898ec223 | 827 | ide_hwif_t *hwif = drive->hwif; |
cab7f8ed | 828 | u8 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS); |
1da177e4 LT |
829 | |
830 | if (dma_stat & 0x01) { | |
831 | /* wait a little */ | |
832 | udelay(20); | |
cab7f8ed | 833 | dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS); |
4bf63de2 SS |
834 | if (dma_stat & 0x01) |
835 | hpt370_irq_timeout(drive); | |
1da177e4 | 836 | } |
653bcf52 | 837 | return ide_dma_end(drive); |
1da177e4 LT |
838 | } |
839 | ||
1da177e4 | 840 | /* returns 1 if DMA IRQ issued, 0 otherwise */ |
5e37bdc0 | 841 | static int hpt374_dma_test_irq(ide_drive_t *drive) |
1da177e4 | 842 | { |
898ec223 | 843 | ide_hwif_t *hwif = drive->hwif; |
36501650 | 844 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1da177e4 | 845 | u16 bfifo = 0; |
abc4ad4c | 846 | u8 dma_stat; |
1da177e4 | 847 | |
36501650 | 848 | pci_read_config_word(dev, hwif->select_data + 2, &bfifo); |
1da177e4 LT |
849 | if (bfifo & 0x1FF) { |
850 | // printk("%s: %d bytes in FIFO\n", drive->name, bfifo); | |
851 | return 0; | |
852 | } | |
853 | ||
cab7f8ed | 854 | dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS); |
1da177e4 | 855 | /* return 1 if INTR asserted */ |
abc4ad4c | 856 | if (dma_stat & 4) |
1da177e4 LT |
857 | return 1; |
858 | ||
1da177e4 LT |
859 | return 0; |
860 | } | |
861 | ||
5e37bdc0 | 862 | static int hpt374_dma_end(ide_drive_t *drive) |
1da177e4 | 863 | { |
898ec223 | 864 | ide_hwif_t *hwif = drive->hwif; |
36501650 | 865 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
abc4ad4c SS |
866 | u8 mcr = 0, mcr_addr = hwif->select_data; |
867 | u8 bwsr = 0, mask = hwif->channel ? 0x02 : 0x01; | |
868 | ||
869 | pci_read_config_byte(dev, 0x6a, &bwsr); | |
870 | pci_read_config_byte(dev, mcr_addr, &mcr); | |
871 | if (bwsr & mask) | |
872 | pci_write_config_byte(dev, mcr_addr, mcr | 0x30); | |
653bcf52 | 873 | return ide_dma_end(drive); |
1da177e4 LT |
874 | } |
875 | ||
876 | /** | |
836c0063 SS |
877 | * hpt3xxn_set_clock - perform clock switching dance |
878 | * @hwif: hwif to switch | |
879 | * @mode: clocking mode (0x21 for write, 0x23 otherwise) | |
1da177e4 | 880 | * |
836c0063 | 881 | * Switch the DPLL clock on the HPT3xxN devices. This is a right mess. |
1da177e4 | 882 | */ |
836c0063 SS |
883 | |
884 | static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode) | |
1da177e4 | 885 | { |
1c029fd6 BZ |
886 | unsigned long base = hwif->extra_base; |
887 | u8 scr2 = inb(base + 0x6b); | |
836c0063 SS |
888 | |
889 | if ((scr2 & 0x7f) == mode) | |
890 | return; | |
891 | ||
1da177e4 | 892 | /* Tristate the bus */ |
1c029fd6 BZ |
893 | outb(0x80, base + 0x63); |
894 | outb(0x80, base + 0x67); | |
836c0063 | 895 | |
1da177e4 | 896 | /* Switch clock and reset channels */ |
1c029fd6 BZ |
897 | outb(mode, base + 0x6b); |
898 | outb(0xc0, base + 0x69); | |
836c0063 | 899 | |
7b73ee05 SS |
900 | /* |
901 | * Reset the state machines. | |
902 | * NOTE: avoid accidentally enabling the disabled channels. | |
903 | */ | |
1c029fd6 BZ |
904 | outb(inb(base + 0x60) | 0x32, base + 0x60); |
905 | outb(inb(base + 0x64) | 0x32, base + 0x64); | |
836c0063 | 906 | |
1da177e4 | 907 | /* Complete reset */ |
1c029fd6 | 908 | outb(0x00, base + 0x69); |
836c0063 | 909 | |
1da177e4 | 910 | /* Reconnect channels to bus */ |
1c029fd6 BZ |
911 | outb(0x00, base + 0x63); |
912 | outb(0x00, base + 0x67); | |
1da177e4 LT |
913 | } |
914 | ||
915 | /** | |
836c0063 | 916 | * hpt3xxn_rw_disk - prepare for I/O |
1da177e4 LT |
917 | * @drive: drive for command |
918 | * @rq: block request structure | |
919 | * | |
836c0063 | 920 | * This is called when a disk I/O is issued to HPT3xxN. |
1da177e4 LT |
921 | * We need it because of the clock switching. |
922 | */ | |
923 | ||
836c0063 | 924 | static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq) |
1da177e4 | 925 | { |
898ec223 | 926 | hpt3xxn_set_clock(drive->hwif, rq_data_dir(rq) ? 0x23 : 0x21); |
1da177e4 LT |
927 | } |
928 | ||
7b73ee05 SS |
929 | /** |
930 | * hpt37x_calibrate_dpll - calibrate the DPLL | |
931 | * @dev: PCI device | |
932 | * | |
933 | * Perform a calibration cycle on the DPLL. | |
934 | * Returns 1 if this succeeds | |
935 | */ | |
feb22b7f | 936 | static int hpt37x_calibrate_dpll(struct pci_dev *dev, u16 f_low, u16 f_high) |
1da177e4 | 937 | { |
7b73ee05 SS |
938 | u32 dpll = (f_high << 16) | f_low | 0x100; |
939 | u8 scr2; | |
940 | int i; | |
b39b01ff | 941 | |
7b73ee05 | 942 | pci_write_config_dword(dev, 0x5c, dpll); |
b39b01ff | 943 | |
7b73ee05 SS |
944 | /* Wait for oscillator ready */ |
945 | for(i = 0; i < 0x5000; ++i) { | |
946 | udelay(50); | |
947 | pci_read_config_byte(dev, 0x5b, &scr2); | |
948 | if (scr2 & 0x80) | |
b39b01ff AC |
949 | break; |
950 | } | |
7b73ee05 SS |
951 | /* See if it stays ready (we'll just bail out if it's not yet) */ |
952 | for(i = 0; i < 0x1000; ++i) { | |
953 | pci_read_config_byte(dev, 0x5b, &scr2); | |
954 | /* DPLL destabilized? */ | |
955 | if(!(scr2 & 0x80)) | |
956 | return 0; | |
957 | } | |
958 | /* Turn off tuning, we have the DPLL set */ | |
959 | pci_read_config_dword (dev, 0x5c, &dpll); | |
960 | pci_write_config_dword(dev, 0x5c, (dpll & ~0x100)); | |
961 | return 1; | |
b39b01ff AC |
962 | } |
963 | ||
feb22b7f | 964 | static void hpt3xx_disable_fast_irq(struct pci_dev *dev, u8 mcr_addr) |
1785192b BZ |
965 | { |
966 | struct ide_host *host = pci_get_drvdata(dev); | |
967 | struct hpt_info *info = host->host_priv + (&dev->dev == host->dev[1]); | |
968 | u8 chip_type = info->chip_type; | |
969 | u8 new_mcr, old_mcr = 0; | |
970 | ||
971 | /* | |
972 | * Disable the "fast interrupt" prediction. Don't hold off | |
973 | * on interrupts. (== 0x01 despite what the docs say) | |
974 | */ | |
975 | pci_read_config_byte(dev, mcr_addr + 1, &old_mcr); | |
976 | ||
977 | if (chip_type >= HPT374) | |
978 | new_mcr = old_mcr & ~0x07; | |
979 | else if (chip_type >= HPT370) { | |
980 | new_mcr = old_mcr; | |
981 | new_mcr &= ~0x02; | |
982 | #ifdef HPT_DELAY_INTERRUPT | |
983 | new_mcr &= ~0x01; | |
984 | #else | |
985 | new_mcr |= 0x01; | |
986 | #endif | |
987 | } else /* HPT366 and HPT368 */ | |
988 | new_mcr = old_mcr & ~0x80; | |
989 | ||
990 | if (new_mcr != old_mcr) | |
991 | pci_write_config_byte(dev, mcr_addr + 1, new_mcr); | |
992 | } | |
993 | ||
2ed0ef54 | 994 | static int init_chipset_hpt366(struct pci_dev *dev) |
b39b01ff | 995 | { |
7b73ee05 | 996 | unsigned long io_base = pci_resource_start(dev, 4); |
62ff2ecf | 997 | struct hpt_info *info = hpt3xx_get_info(&dev->dev); |
a326b02b | 998 | const char *name = DRV_NAME; |
7b73ee05 | 999 | u8 pci_clk, dpll_clk = 0; /* PCI and DPLL clock in MHz */ |
72931368 | 1000 | u8 chip_type; |
7b73ee05 SS |
1001 | enum ata_clock clock; |
1002 | ||
72931368 | 1003 | chip_type = info->chip_type; |
1da177e4 | 1004 | |
7b73ee05 SS |
1005 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4)); |
1006 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78); | |
1007 | pci_write_config_byte(dev, PCI_MIN_GNT, 0x08); | |
1008 | pci_write_config_byte(dev, PCI_MAX_LAT, 0x08); | |
26c068da | 1009 | |
1da177e4 | 1010 | /* |
7b73ee05 | 1011 | * First, try to estimate the PCI clock frequency... |
1da177e4 | 1012 | */ |
72931368 | 1013 | if (chip_type >= HPT370) { |
7b73ee05 SS |
1014 | u8 scr1 = 0; |
1015 | u16 f_cnt = 0; | |
1016 | u32 temp = 0; | |
1017 | ||
1018 | /* Interrupt force enable. */ | |
1019 | pci_read_config_byte(dev, 0x5a, &scr1); | |
1020 | if (scr1 & 0x10) | |
1021 | pci_write_config_byte(dev, 0x5a, scr1 & ~0x10); | |
1022 | ||
1023 | /* | |
1024 | * HighPoint does this for HPT372A. | |
1025 | * NOTE: This register is only writeable via I/O space. | |
1026 | */ | |
72931368 | 1027 | if (chip_type == HPT372A) |
7b73ee05 SS |
1028 | outb(0x0e, io_base + 0x9c); |
1029 | ||
1030 | /* | |
1031 | * Default to PCI clock. Make sure MA15/16 are set to output | |
1032 | * to prevent drives having problems with 40-pin cables. | |
1033 | */ | |
1034 | pci_write_config_byte(dev, 0x5b, 0x23); | |
836c0063 | 1035 | |
7b73ee05 SS |
1036 | /* |
1037 | * We'll have to read f_CNT value in order to determine | |
1038 | * the PCI clock frequency according to the following ratio: | |
1039 | * | |
1040 | * f_CNT = Fpci * 192 / Fdpll | |
1041 | * | |
1042 | * First try reading the register in which the HighPoint BIOS | |
1043 | * saves f_CNT value before reprogramming the DPLL from its | |
1044 | * default setting (which differs for the various chips). | |
7b73ee05 | 1045 | * |
72931368 SS |
1046 | * NOTE: This register is only accessible via I/O space; |
1047 | * HPT374 BIOS only saves it for the function 0, so we have to | |
1048 | * always read it from there -- no need to check the result of | |
1049 | * pci_get_slot() for the function 0 as the whole device has | |
1050 | * been already "pinned" (via function 1) in init_setup_hpt374() | |
1051 | */ | |
1052 | if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) { | |
1053 | struct pci_dev *dev1 = pci_get_slot(dev->bus, | |
1054 | dev->devfn - 1); | |
1055 | unsigned long io_base = pci_resource_start(dev1, 4); | |
1056 | ||
1057 | temp = inl(io_base + 0x90); | |
1058 | pci_dev_put(dev1); | |
1059 | } else | |
1060 | temp = inl(io_base + 0x90); | |
1061 | ||
1062 | /* | |
1063 | * In case the signature check fails, we'll have to | |
1064 | * resort to reading the f_CNT register itself in hopes | |
1065 | * that nobody has touched the DPLL yet... | |
7b73ee05 | 1066 | */ |
7b73ee05 SS |
1067 | if ((temp & 0xFFFFF000) != 0xABCDE000) { |
1068 | int i; | |
1069 | ||
28cfd8af BZ |
1070 | printk(KERN_WARNING "%s %s: no clock data saved by " |
1071 | "BIOS\n", name, pci_name(dev)); | |
7b73ee05 SS |
1072 | |
1073 | /* Calculate the average value of f_CNT. */ | |
1074 | for (temp = i = 0; i < 128; i++) { | |
1075 | pci_read_config_word(dev, 0x78, &f_cnt); | |
1076 | temp += f_cnt & 0x1ff; | |
1077 | mdelay(1); | |
1078 | } | |
1079 | f_cnt = temp / 128; | |
1080 | } else | |
1081 | f_cnt = temp & 0x1ff; | |
1082 | ||
1083 | dpll_clk = info->dpll_clk; | |
1084 | pci_clk = (f_cnt * dpll_clk) / 192; | |
1085 | ||
1086 | /* Clamp PCI clock to bands. */ | |
1087 | if (pci_clk < 40) | |
1088 | pci_clk = 33; | |
1089 | else if(pci_clk < 45) | |
1090 | pci_clk = 40; | |
1091 | else if(pci_clk < 55) | |
1092 | pci_clk = 50; | |
1da177e4 | 1093 | else |
7b73ee05 | 1094 | pci_clk = 66; |
836c0063 | 1095 | |
28cfd8af BZ |
1096 | printk(KERN_INFO "%s %s: DPLL base: %d MHz, f_CNT: %d, " |
1097 | "assuming %d MHz PCI\n", name, pci_name(dev), | |
1098 | dpll_clk, f_cnt, pci_clk); | |
90778574 | 1099 | } else { |
7b73ee05 SS |
1100 | u32 itr1 = 0; |
1101 | ||
1102 | pci_read_config_dword(dev, 0x40, &itr1); | |
1103 | ||
1104 | /* Detect PCI clock by looking at cmd_high_time. */ | |
1105 | switch((itr1 >> 8) & 0x07) { | |
1106 | case 0x09: | |
1107 | pci_clk = 40; | |
6273d26a | 1108 | break; |
7b73ee05 SS |
1109 | case 0x05: |
1110 | pci_clk = 25; | |
6273d26a | 1111 | break; |
7b73ee05 SS |
1112 | case 0x07: |
1113 | default: | |
1114 | pci_clk = 33; | |
6273d26a | 1115 | break; |
1da177e4 LT |
1116 | } |
1117 | } | |
836c0063 | 1118 | |
7b73ee05 SS |
1119 | /* Let's assume we'll use PCI clock for the ATA clock... */ |
1120 | switch (pci_clk) { | |
1121 | case 25: | |
1122 | clock = ATA_CLOCK_25MHZ; | |
1123 | break; | |
1124 | case 33: | |
1125 | default: | |
1126 | clock = ATA_CLOCK_33MHZ; | |
1127 | break; | |
1128 | case 40: | |
1129 | clock = ATA_CLOCK_40MHZ; | |
1130 | break; | |
1131 | case 50: | |
1132 | clock = ATA_CLOCK_50MHZ; | |
1133 | break; | |
1134 | case 66: | |
1135 | clock = ATA_CLOCK_66MHZ; | |
1136 | break; | |
1137 | } | |
836c0063 | 1138 | |
1da177e4 | 1139 | /* |
7b73ee05 SS |
1140 | * Only try the DPLL if we don't have a table for the PCI clock that |
1141 | * we are running at for HPT370/A, always use it for anything newer... | |
b39b01ff | 1142 | * |
7b73ee05 SS |
1143 | * NOTE: Using the internal DPLL results in slow reads on 33 MHz PCI. |
1144 | * We also don't like using the DPLL because this causes glitches | |
1145 | * on PRST-/SRST- when the state engine gets reset... | |
1da177e4 | 1146 | */ |
866664d7 | 1147 | if (chip_type >= HPT374 || info->timings->clock_table[clock] == NULL) { |
7b73ee05 SS |
1148 | u16 f_low, delta = pci_clk < 50 ? 2 : 4; |
1149 | int adjust; | |
1150 | ||
1151 | /* | |
1152 | * Select 66 MHz DPLL clock only if UltraATA/133 mode is | |
1153 | * supported/enabled, use 50 MHz DPLL clock otherwise... | |
1154 | */ | |
fbf47840 | 1155 | if (info->udma_mask == ATA_UDMA6) { |
7b73ee05 SS |
1156 | dpll_clk = 66; |
1157 | clock = ATA_CLOCK_66MHZ; | |
1158 | } else if (dpll_clk) { /* HPT36x chips don't have DPLL */ | |
1159 | dpll_clk = 50; | |
1160 | clock = ATA_CLOCK_50MHZ; | |
1161 | } | |
b39b01ff | 1162 | |
866664d7 | 1163 | if (info->timings->clock_table[clock] == NULL) { |
28cfd8af BZ |
1164 | printk(KERN_ERR "%s %s: unknown bus timing!\n", |
1165 | name, pci_name(dev)); | |
7b73ee05 | 1166 | return -EIO; |
1da177e4 | 1167 | } |
1da177e4 | 1168 | |
7b73ee05 SS |
1169 | /* Select the DPLL clock. */ |
1170 | pci_write_config_byte(dev, 0x5b, 0x21); | |
1171 | ||
1172 | /* | |
1173 | * Adjust the DPLL based upon PCI clock, enable it, | |
1174 | * and wait for stabilization... | |
1175 | */ | |
1176 | f_low = (pci_clk * 48) / dpll_clk; | |
1177 | ||
1178 | for (adjust = 0; adjust < 8; adjust++) { | |
1179 | if(hpt37x_calibrate_dpll(dev, f_low, f_low + delta)) | |
1180 | break; | |
1181 | ||
1182 | /* | |
1183 | * See if it'll settle at a fractionally different clock | |
1184 | */ | |
1185 | if (adjust & 1) | |
1186 | f_low -= adjust >> 1; | |
1187 | else | |
1188 | f_low += adjust >> 1; | |
1189 | } | |
1190 | if (adjust == 8) { | |
28cfd8af BZ |
1191 | printk(KERN_ERR "%s %s: DPLL did not stabilize!\n", |
1192 | name, pci_name(dev)); | |
7b73ee05 SS |
1193 | return -EIO; |
1194 | } | |
1195 | ||
28cfd8af BZ |
1196 | printk(KERN_INFO "%s %s: using %d MHz DPLL clock\n", |
1197 | name, pci_name(dev), dpll_clk); | |
7b73ee05 SS |
1198 | } else { |
1199 | /* Mark the fact that we're not using the DPLL. */ | |
1200 | dpll_clk = 0; | |
1201 | ||
28cfd8af BZ |
1202 | printk(KERN_INFO "%s %s: using %d MHz PCI clock\n", |
1203 | name, pci_name(dev), pci_clk); | |
7b73ee05 | 1204 | } |
b39b01ff | 1205 | |
7b73ee05 SS |
1206 | /* Store the clock frequencies. */ |
1207 | info->dpll_clk = dpll_clk; | |
1208 | info->pci_clk = pci_clk; | |
866664d7 | 1209 | info->clock = clock; |
1da177e4 | 1210 | |
72931368 | 1211 | if (chip_type >= HPT370) { |
7b73ee05 SS |
1212 | u8 mcr1, mcr4; |
1213 | ||
1214 | /* | |
1215 | * Reset the state engines. | |
1216 | * NOTE: Avoid accidentally enabling the disabled channels. | |
1217 | */ | |
1218 | pci_read_config_byte (dev, 0x50, &mcr1); | |
1219 | pci_read_config_byte (dev, 0x54, &mcr4); | |
1220 | pci_write_config_byte(dev, 0x50, (mcr1 | 0x32)); | |
1221 | pci_write_config_byte(dev, 0x54, (mcr4 | 0x32)); | |
1222 | udelay(100); | |
26ccb802 | 1223 | } |
1da177e4 | 1224 | |
7b73ee05 SS |
1225 | /* |
1226 | * On HPT371N, if ATA clock is 66 MHz we must set bit 2 in | |
1227 | * the MISC. register to stretch the UltraDMA Tss timing. | |
1228 | * NOTE: This register is only writeable via I/O space. | |
1229 | */ | |
72931368 | 1230 | if (chip_type == HPT371N && clock == ATA_CLOCK_66MHZ) |
7b73ee05 SS |
1231 | outb(inb(io_base + 0x9c) | 0x04, io_base + 0x9c); |
1232 | ||
1785192b BZ |
1233 | hpt3xx_disable_fast_irq(dev, 0x50); |
1234 | hpt3xx_disable_fast_irq(dev, 0x54); | |
1235 | ||
2ed0ef54 | 1236 | return 0; |
1da177e4 LT |
1237 | } |
1238 | ||
f454cbe8 | 1239 | static u8 hpt3xx_cable_detect(ide_hwif_t *hwif) |
bfa14b42 BZ |
1240 | { |
1241 | struct pci_dev *dev = to_pci_dev(hwif->dev); | |
62ff2ecf | 1242 | struct hpt_info *info = hpt3xx_get_info(hwif->dev); |
bfa14b42 BZ |
1243 | u8 chip_type = info->chip_type; |
1244 | u8 scr1 = 0, ata66 = hwif->channel ? 0x01 : 0x02; | |
1245 | ||
1246 | /* | |
1247 | * The HPT37x uses the CBLID pins as outputs for MA15/MA16 | |
1248 | * address lines to access an external EEPROM. To read valid | |
1249 | * cable detect state the pins must be enabled as inputs. | |
1250 | */ | |
1251 | if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) { | |
1252 | /* | |
1253 | * HPT374 PCI function 1 | |
1254 | * - set bit 15 of reg 0x52 to enable TCBLID as input | |
1255 | * - set bit 15 of reg 0x56 to enable FCBLID as input | |
1256 | */ | |
1257 | u8 mcr_addr = hwif->select_data + 2; | |
1258 | u16 mcr; | |
1259 | ||
1260 | pci_read_config_word(dev, mcr_addr, &mcr); | |
1261 | pci_write_config_word(dev, mcr_addr, (mcr | 0x8000)); | |
1262 | /* now read cable id register */ | |
1263 | pci_read_config_byte(dev, 0x5a, &scr1); | |
1264 | pci_write_config_word(dev, mcr_addr, mcr); | |
1265 | } else if (chip_type >= HPT370) { | |
1266 | /* | |
1267 | * HPT370/372 and 374 pcifn 0 | |
1268 | * - clear bit 0 of reg 0x5b to enable P/SCBLID as inputs | |
1269 | */ | |
1270 | u8 scr2 = 0; | |
1271 | ||
1272 | pci_read_config_byte(dev, 0x5b, &scr2); | |
1273 | pci_write_config_byte(dev, 0x5b, (scr2 & ~1)); | |
1274 | /* now read cable id register */ | |
1275 | pci_read_config_byte(dev, 0x5a, &scr1); | |
1276 | pci_write_config_byte(dev, 0x5b, scr2); | |
1277 | } else | |
1278 | pci_read_config_byte(dev, 0x5a, &scr1); | |
1279 | ||
1280 | return (scr1 & ata66) ? ATA_CBL_PATA40 : ATA_CBL_PATA80; | |
1281 | } | |
1282 | ||
1da177e4 LT |
1283 | static void __devinit init_hwif_hpt366(ide_hwif_t *hwif) |
1284 | { | |
62ff2ecf | 1285 | struct hpt_info *info = hpt3xx_get_info(hwif->dev); |
2808b0a9 | 1286 | u8 chip_type = info->chip_type; |
abc4ad4c SS |
1287 | |
1288 | /* Cache the channel's MISC. control registers' offset */ | |
2808b0a9 | 1289 | hwif->select_data = hwif->channel ? 0x54 : 0x50; |
abc4ad4c | 1290 | |
836c0063 SS |
1291 | /* |
1292 | * HPT3xxN chips have some complications: | |
1293 | * | |
1294 | * - on 33 MHz PCI we must clock switch | |
1295 | * - on 66 MHz PCI we must NOT use the PCI clock | |
1296 | */ | |
7b73ee05 | 1297 | if (chip_type >= HPT372N && info->dpll_clk && info->pci_clk < 66) { |
836c0063 SS |
1298 | /* |
1299 | * Clock is shared between the channels, | |
1300 | * so we'll have to serialize them... :-( | |
1301 | */ | |
702c026b | 1302 | hwif->host->host_flags |= IDE_HFLAG_SERIALIZE; |
836c0063 SS |
1303 | hwif->rw_disk = &hpt3xxn_rw_disk; |
1304 | } | |
1da177e4 LT |
1305 | } |
1306 | ||
b123f56e BZ |
1307 | static int __devinit init_dma_hpt366(ide_hwif_t *hwif, |
1308 | const struct ide_port_info *d) | |
1da177e4 | 1309 | { |
36501650 | 1310 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
b123f56e BZ |
1311 | unsigned long flags, base = ide_pci_dma_base(hwif, d); |
1312 | u8 dma_old, dma_new, masterdma = 0, slavedma = 0; | |
1da177e4 | 1313 | |
ebb00fb5 BZ |
1314 | if (base == 0) |
1315 | return -1; | |
1316 | ||
1317 | hwif->dma_base = base; | |
1318 | ||
1319 | if (ide_pci_check_simplex(hwif, d) < 0) | |
1320 | return -1; | |
1321 | ||
1322 | if (ide_pci_set_master(dev, d->name) < 0) | |
b123f56e BZ |
1323 | return -1; |
1324 | ||
1325 | dma_old = inb(base + 2); | |
1da177e4 LT |
1326 | |
1327 | local_irq_save(flags); | |
1328 | ||
1329 | dma_new = dma_old; | |
abc4ad4c SS |
1330 | pci_read_config_byte(dev, hwif->channel ? 0x4b : 0x43, &masterdma); |
1331 | pci_read_config_byte(dev, hwif->channel ? 0x4f : 0x47, &slavedma); | |
1da177e4 LT |
1332 | |
1333 | if (masterdma & 0x30) dma_new |= 0x20; | |
abc4ad4c | 1334 | if ( slavedma & 0x30) dma_new |= 0x40; |
1da177e4 | 1335 | if (dma_new != dma_old) |
b123f56e | 1336 | outb(dma_new, base + 2); |
1da177e4 LT |
1337 | |
1338 | local_irq_restore(flags); | |
b123f56e BZ |
1339 | |
1340 | printk(KERN_INFO " %s: BM-DMA at 0x%04lx-0x%04lx\n", | |
1341 | hwif->name, base, base + 7); | |
1342 | ||
1343 | hwif->extra_base = base + (hwif->channel ? 8 : 16); | |
1344 | ||
1345 | if (ide_allocate_dma_engine(hwif)) | |
1346 | return -1; | |
1347 | ||
b123f56e | 1348 | return 0; |
1da177e4 LT |
1349 | } |
1350 | ||
fbf47840 | 1351 | static void __devinit hpt374_init(struct pci_dev *dev, struct pci_dev *dev2) |
1da177e4 | 1352 | { |
fbf47840 BZ |
1353 | if (dev2->irq != dev->irq) { |
1354 | /* FIXME: we need a core pci_set_interrupt() */ | |
1355 | dev2->irq = dev->irq; | |
ced3ec8a | 1356 | printk(KERN_INFO DRV_NAME " %s: PCI config space interrupt " |
28cfd8af | 1357 | "fixed\n", pci_name(dev2)); |
1da177e4 | 1358 | } |
1da177e4 LT |
1359 | } |
1360 | ||
fbf47840 | 1361 | static void __devinit hpt371_init(struct pci_dev *dev) |
836c0063 | 1362 | { |
44c10138 | 1363 | u8 mcr1 = 0; |
90778574 | 1364 | |
836c0063 SS |
1365 | /* |
1366 | * HPT371 chips physically have only one channel, the secondary one, | |
1367 | * but the primary channel registers do exist! Go figure... | |
1368 | * So, we manually disable the non-existing channel here | |
1369 | * (if the BIOS hasn't done this already). | |
1370 | */ | |
1371 | pci_read_config_byte(dev, 0x50, &mcr1); | |
1372 | if (mcr1 & 0x04) | |
90778574 | 1373 | pci_write_config_byte(dev, 0x50, mcr1 & ~0x04); |
90778574 SS |
1374 | } |
1375 | ||
fbf47840 | 1376 | static int __devinit hpt36x_init(struct pci_dev *dev, struct pci_dev *dev2) |
90778574 | 1377 | { |
fbf47840 | 1378 | u8 mcr1 = 0, pin1 = 0, pin2 = 0; |
7b73ee05 | 1379 | |
fbf47840 BZ |
1380 | /* |
1381 | * Now we'll have to force both channels enabled if | |
1382 | * at least one of them has been enabled by BIOS... | |
1383 | */ | |
1384 | pci_read_config_byte(dev, 0x50, &mcr1); | |
1385 | if (mcr1 & 0x30) | |
1386 | pci_write_config_byte(dev, 0x50, mcr1 | 0x30); | |
836c0063 | 1387 | |
fbf47840 BZ |
1388 | pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1); |
1389 | pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin2); | |
1da177e4 | 1390 | |
fbf47840 | 1391 | if (pin1 != pin2 && dev->irq == dev2->irq) { |
ced3ec8a | 1392 | printk(KERN_INFO DRV_NAME " %s: onboard version of chipset, " |
28cfd8af | 1393 | "pin1=%d pin2=%d\n", pci_name(dev), pin1, pin2); |
fbf47840 | 1394 | return 1; |
2648e5d9 SS |
1395 | } |
1396 | ||
fbf47840 | 1397 | return 0; |
1da177e4 LT |
1398 | } |
1399 | ||
4db90a14 BZ |
1400 | #define IDE_HFLAGS_HPT3XX \ |
1401 | (IDE_HFLAG_NO_ATAPI_DMA | \ | |
4db90a14 BZ |
1402 | IDE_HFLAG_OFF_BOARD) |
1403 | ||
ac95beed BZ |
1404 | static const struct ide_port_ops hpt3xx_port_ops = { |
1405 | .set_pio_mode = hpt3xx_set_pio_mode, | |
1406 | .set_dma_mode = hpt3xx_set_mode, | |
1407 | .quirkproc = hpt3xx_quirkproc, | |
1408 | .maskproc = hpt3xx_maskproc, | |
1409 | .mdma_filter = hpt3xx_mdma_filter, | |
1410 | .udma_filter = hpt3xx_udma_filter, | |
1411 | .cable_detect = hpt3xx_cable_detect, | |
1412 | }; | |
1413 | ||
f37afdac BZ |
1414 | static const struct ide_dma_ops hpt37x_dma_ops = { |
1415 | .dma_host_set = ide_dma_host_set, | |
1416 | .dma_setup = ide_dma_setup, | |
f37afdac | 1417 | .dma_start = ide_dma_start, |
5e37bdc0 BZ |
1418 | .dma_end = hpt374_dma_end, |
1419 | .dma_test_irq = hpt374_dma_test_irq, | |
f37afdac | 1420 | .dma_lost_irq = ide_dma_lost_irq, |
22117d6e | 1421 | .dma_timer_expiry = ide_dma_sff_timer_expiry, |
592b5315 | 1422 | .dma_sff_read_status = ide_dma_sff_read_status, |
5e37bdc0 BZ |
1423 | }; |
1424 | ||
f37afdac BZ |
1425 | static const struct ide_dma_ops hpt370_dma_ops = { |
1426 | .dma_host_set = ide_dma_host_set, | |
1427 | .dma_setup = ide_dma_setup, | |
5e37bdc0 BZ |
1428 | .dma_start = hpt370_dma_start, |
1429 | .dma_end = hpt370_dma_end, | |
f37afdac BZ |
1430 | .dma_test_irq = ide_dma_test_irq, |
1431 | .dma_lost_irq = ide_dma_lost_irq, | |
22117d6e | 1432 | .dma_timer_expiry = ide_dma_sff_timer_expiry, |
35c9b4da | 1433 | .dma_clear = hpt370_irq_timeout, |
592b5315 | 1434 | .dma_sff_read_status = ide_dma_sff_read_status, |
5e37bdc0 BZ |
1435 | }; |
1436 | ||
f37afdac BZ |
1437 | static const struct ide_dma_ops hpt36x_dma_ops = { |
1438 | .dma_host_set = ide_dma_host_set, | |
1439 | .dma_setup = ide_dma_setup, | |
f37afdac | 1440 | .dma_start = ide_dma_start, |
653bcf52 | 1441 | .dma_end = ide_dma_end, |
f37afdac | 1442 | .dma_test_irq = ide_dma_test_irq, |
5e37bdc0 | 1443 | .dma_lost_irq = hpt366_dma_lost_irq, |
22117d6e | 1444 | .dma_timer_expiry = ide_dma_sff_timer_expiry, |
592b5315 | 1445 | .dma_sff_read_status = ide_dma_sff_read_status, |
5e37bdc0 BZ |
1446 | }; |
1447 | ||
85620436 | 1448 | static const struct ide_port_info hpt366_chipsets[] __devinitdata = { |
ced3ec8a BZ |
1449 | { /* 0: HPT36x */ |
1450 | .name = DRV_NAME, | |
1da177e4 LT |
1451 | .init_chipset = init_chipset_hpt366, |
1452 | .init_hwif = init_hwif_hpt366, | |
1453 | .init_dma = init_dma_hpt366, | |
fbf47840 BZ |
1454 | /* |
1455 | * HPT36x chips have one channel per function and have | |
1456 | * both channel enable bits located differently and visible | |
1457 | * to both functions -- really stupid design decision... :-( | |
1458 | * Bit 4 is for the primary channel, bit 5 for the secondary. | |
1459 | */ | |
1460 | .enablebits = {{0x50,0x10,0x10}, {0x54,0x04,0x04}}, | |
ac95beed | 1461 | .port_ops = &hpt3xx_port_ops, |
5e37bdc0 | 1462 | .dma_ops = &hpt36x_dma_ops, |
4db90a14 | 1463 | .host_flags = IDE_HFLAGS_HPT3XX | IDE_HFLAG_SINGLE, |
4099d143 | 1464 | .pio_mask = ATA_PIO4, |
5f8b6c34 | 1465 | .mwdma_mask = ATA_MWDMA2, |
ced3ec8a BZ |
1466 | }, |
1467 | { /* 1: HPT3xx */ | |
1468 | .name = DRV_NAME, | |
1da177e4 LT |
1469 | .init_chipset = init_chipset_hpt366, |
1470 | .init_hwif = init_hwif_hpt366, | |
1471 | .init_dma = init_dma_hpt366, | |
7b73ee05 | 1472 | .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}}, |
ac95beed | 1473 | .port_ops = &hpt3xx_port_ops, |
5e37bdc0 | 1474 | .dma_ops = &hpt37x_dma_ops, |
4db90a14 | 1475 | .host_flags = IDE_HFLAGS_HPT3XX, |
4099d143 | 1476 | .pio_mask = ATA_PIO4, |
5f8b6c34 | 1477 | .mwdma_mask = ATA_MWDMA2, |
1da177e4 LT |
1478 | } |
1479 | }; | |
1480 | ||
1481 | /** | |
1482 | * hpt366_init_one - called when an HPT366 is found | |
1483 | * @dev: the hpt366 device | |
1484 | * @id: the matching pci id | |
1485 | * | |
1486 | * Called when the PCI registration layer (or the IDE initialization) | |
1487 | * finds a device matching our IDE device tables. | |
1488 | */ | |
1da177e4 LT |
1489 | static int __devinit hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id) |
1490 | { | |
282037f1 | 1491 | const struct hpt_info *info = NULL; |
74811f35 | 1492 | struct hpt_info *dyn_info; |
fbf47840 | 1493 | struct pci_dev *dev2 = NULL; |
039788e1 | 1494 | struct ide_port_info d; |
fbf47840 BZ |
1495 | u8 idx = id->driver_data; |
1496 | u8 rev = dev->revision; | |
74811f35 | 1497 | int ret; |
fbf47840 BZ |
1498 | |
1499 | if ((idx == 0 || idx == 4) && (PCI_FUNC(dev->devfn) & 1)) | |
1500 | return -ENODEV; | |
1501 | ||
1502 | switch (idx) { | |
1503 | case 0: | |
1504 | if (rev < 3) | |
1505 | info = &hpt36x; | |
1506 | else { | |
b66cae76 SR |
1507 | switch (min_t(u8, rev, 6)) { |
1508 | case 3: info = &hpt370; break; | |
1509 | case 4: info = &hpt370a; break; | |
1510 | case 5: info = &hpt372; break; | |
1511 | case 6: info = &hpt372n; break; | |
1512 | } | |
fbf47840 BZ |
1513 | idx++; |
1514 | } | |
1515 | break; | |
1516 | case 1: | |
1517 | info = (rev > 1) ? &hpt372n : &hpt372a; | |
1518 | break; | |
1519 | case 2: | |
1520 | info = (rev > 1) ? &hpt302n : &hpt302; | |
1521 | break; | |
1522 | case 3: | |
1523 | hpt371_init(dev); | |
1524 | info = (rev > 1) ? &hpt371n : &hpt371; | |
1525 | break; | |
1526 | case 4: | |
1527 | info = &hpt374; | |
1528 | break; | |
1529 | case 5: | |
1530 | info = &hpt372n; | |
1531 | break; | |
1532 | } | |
1533 | ||
ced3ec8a BZ |
1534 | printk(KERN_INFO DRV_NAME ": %s chipset detected\n", info->chip_name); |
1535 | ||
1536 | d = hpt366_chipsets[min_t(u8, idx, 1)]; | |
fbf47840 | 1537 | |
fbf47840 BZ |
1538 | d.udma_mask = info->udma_mask; |
1539 | ||
5e37bdc0 BZ |
1540 | /* fixup ->dma_ops for HPT370/HPT370A */ |
1541 | if (info == &hpt370 || info == &hpt370a) | |
1542 | d.dma_ops = &hpt370_dma_ops; | |
1543 | ||
fbf47840 BZ |
1544 | if (info == &hpt36x || info == &hpt374) |
1545 | dev2 = pci_get_slot(dev->bus, dev->devfn + 1); | |
1546 | ||
74811f35 BZ |
1547 | dyn_info = kzalloc(sizeof(*dyn_info) * (dev2 ? 2 : 1), GFP_KERNEL); |
1548 | if (dyn_info == NULL) { | |
28cfd8af BZ |
1549 | printk(KERN_ERR "%s %s: out of memory!\n", |
1550 | d.name, pci_name(dev)); | |
74811f35 BZ |
1551 | pci_dev_put(dev2); |
1552 | return -ENOMEM; | |
1553 | } | |
1554 | ||
1555 | /* | |
1556 | * Copy everything from a static "template" structure | |
1557 | * to just allocated per-chip hpt_info structure. | |
1558 | */ | |
1559 | memcpy(dyn_info, info, sizeof(*dyn_info)); | |
fbf47840 | 1560 | |
74811f35 BZ |
1561 | if (dev2) { |
1562 | memcpy(dyn_info + 1, info, sizeof(*dyn_info)); | |
fbf47840 BZ |
1563 | |
1564 | if (info == &hpt374) | |
1565 | hpt374_init(dev, dev2); | |
1566 | else { | |
1567 | if (hpt36x_init(dev, dev2)) | |
5e71d9c5 | 1568 | d.host_flags &= ~IDE_HFLAG_NON_BOOTABLE; |
fbf47840 BZ |
1569 | } |
1570 | ||
74811f35 BZ |
1571 | ret = ide_pci_init_two(dev, dev2, &d, dyn_info); |
1572 | if (ret < 0) { | |
fbf47840 | 1573 | pci_dev_put(dev2); |
74811f35 BZ |
1574 | kfree(dyn_info); |
1575 | } | |
fbf47840 BZ |
1576 | return ret; |
1577 | } | |
1da177e4 | 1578 | |
74811f35 BZ |
1579 | ret = ide_pci_init_one(dev, &d, dyn_info); |
1580 | if (ret < 0) | |
1581 | kfree(dyn_info); | |
1582 | ||
1583 | return ret; | |
1da177e4 LT |
1584 | } |
1585 | ||
a6c43a2b BZ |
1586 | static void __devexit hpt366_remove(struct pci_dev *dev) |
1587 | { | |
1588 | struct ide_host *host = pci_get_drvdata(dev); | |
1589 | struct ide_info *info = host->host_priv; | |
1590 | struct pci_dev *dev2 = host->dev[1] ? to_pci_dev(host->dev[1]) : NULL; | |
1591 | ||
1592 | ide_pci_remove(dev); | |
1593 | pci_dev_put(dev2); | |
1594 | kfree(info); | |
1595 | } | |
1596 | ||
b66cae76 | 1597 | static const struct pci_device_id hpt366_pci_tbl[] __devinitconst = { |
9cbcc5e3 BZ |
1598 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), 0 }, |
1599 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), 1 }, | |
1600 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), 2 }, | |
1601 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), 3 }, | |
1602 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374), 4 }, | |
1603 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372N), 5 }, | |
1da177e4 LT |
1604 | { 0, }, |
1605 | }; | |
1606 | MODULE_DEVICE_TABLE(pci, hpt366_pci_tbl); | |
1607 | ||
a9ab09e2 | 1608 | static struct pci_driver hpt366_pci_driver = { |
1da177e4 LT |
1609 | .name = "HPT366_IDE", |
1610 | .id_table = hpt366_pci_tbl, | |
1611 | .probe = hpt366_init_one, | |
a69999e2 | 1612 | .remove = __devexit_p(hpt366_remove), |
feb22b7f BZ |
1613 | .suspend = ide_pci_suspend, |
1614 | .resume = ide_pci_resume, | |
1da177e4 LT |
1615 | }; |
1616 | ||
82ab1eec | 1617 | static int __init hpt366_ide_init(void) |
1da177e4 | 1618 | { |
a9ab09e2 | 1619 | return ide_pci_register_driver(&hpt366_pci_driver); |
1da177e4 LT |
1620 | } |
1621 | ||
a6c43a2b BZ |
1622 | static void __exit hpt366_ide_exit(void) |
1623 | { | |
a9ab09e2 | 1624 | pci_unregister_driver(&hpt366_pci_driver); |
a6c43a2b BZ |
1625 | } |
1626 | ||
1da177e4 | 1627 | module_init(hpt366_ide_init); |
a6c43a2b | 1628 | module_exit(hpt366_ide_exit); |
1da177e4 LT |
1629 | |
1630 | MODULE_AUTHOR("Andre Hedrick"); | |
1631 | MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE"); | |
1632 | MODULE_LICENSE("GPL"); |