[linux-2.6-block.git] / drivers / ide / cs5535.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2004-2005 Advanced Micro Devices, Inc.
 * Copyright (C)      2007 Bartlomiej Zolnierkiewicz
 *
 * History:
 * 09/20/2005 - Jaya Kumar <jayakumar.ide@gmail.com>
 * - Reworked tuneproc, set_drive, misc mods to prep for mainline
 * - Work was sponsored by CIS (M) Sdn Bhd.
 * Ported to Kernel 2.6.11 on June 26, 2005 by
 *   Wolfgang Zuleger <wolfgang.zuleger@gmx.de>
 *   Alexander Kiausch <alex.kiausch@t-online.de>
 * Originally developed by AMD for 2.4/2.6
 *
 * Development of this chipset driver was funded
 * by the nice folks at National Semiconductor/AMD.
 *
 * Documentation:
 *  CS5535 documentation available from AMD
 */

#include <linux/module.h>
#include <linux/pci.h>
#include <linux/ide.h>

#define DRV_NAME "cs5535"

#define MSR_ATAC_BASE		0x51300000
#define ATAC_GLD_MSR_CAP	(MSR_ATAC_BASE+0)
#define ATAC_GLD_MSR_CONFIG	(MSR_ATAC_BASE+0x01)
#define ATAC_GLD_MSR_SMI	(MSR_ATAC_BASE+0x02)
#define ATAC_GLD_MSR_ERROR	(MSR_ATAC_BASE+0x03)
#define ATAC_GLD_MSR_PM		(MSR_ATAC_BASE+0x04)
#define ATAC_GLD_MSR_DIAG	(MSR_ATAC_BASE+0x05)
#define ATAC_IO_BAR		(MSR_ATAC_BASE+0x08)
#define ATAC_RESET		(MSR_ATAC_BASE+0x10)
#define ATAC_CH0D0_PIO		(MSR_ATAC_BASE+0x20)
#define ATAC_CH0D0_DMA		(MSR_ATAC_BASE+0x21)
#define ATAC_CH0D1_PIO		(MSR_ATAC_BASE+0x22)
#define ATAC_CH0D1_DMA		(MSR_ATAC_BASE+0x23)
#define ATAC_PCI_ABRTERR	(MSR_ATAC_BASE+0x24)
#define ATAC_BM0_CMD_PRIM	0x00
#define ATAC_BM0_STS_PRIM	0x02
#define ATAC_BM0_PRD		0x04
#define CS5535_CABLE_DETECT	0x48

/* Format I PIO settings. We separate out cmd and data for safer timings */

static unsigned int cs5535_pio_cmd_timings[5] =
{ 0xF7F4, 0x53F3, 0x13F1, 0x5131, 0x1131 };
static unsigned int cs5535_pio_dta_timings[5] =
{ 0xF7F4, 0xF173, 0x8141, 0x5131, 0x1131 };

static unsigned int cs5535_mwdma_timings[3] =
{ 0x7F0FFFF3, 0x7F035352, 0x7f024241 };

static unsigned int cs5535_udma_timings[5] =
{ 0x7F7436A1, 0x7F733481, 0x7F723261, 0x7F713161, 0x7F703061 };

/* Macros to check if the register is the reset value -  reset value is an
   invalid timing and indicates the register has not been set previously */

#define CS5535_BAD_PIO(timings) ( (timings&~0x80000000UL) == 0x00009172 )
#define CS5535_BAD_DMA(timings) ( (timings & 0x000FFFFF) == 0x00077771 )

/****
 *	cs5535_set_speed         -     Configure the chipset to the new speed
 *	@drive: Drive to set up
 *	@speed: desired speed
 *
 *	cs5535_set_speed() configures the chipset to a new speed.
 */
static void cs5535_set_speed(ide_drive_t *drive, const u8 speed)
{
	u32 reg = 0, dummy;
	u8 unit = drive->dn & 1;

	/* Set the PIO timings */
	if (speed < XFER_SW_DMA_0) {
		ide_drive_t *pair = ide_get_pair_dev(drive);
		u8 cmd, pioa;

		cmd = pioa = speed - XFER_PIO_0;

		if (pair) {
			u8 piob = pair->pio_mode - XFER_PIO_0;

			if (piob < cmd)
				cmd = piob;
		}

		/* Write the speed of the current drive */
		reg = (cs5535_pio_cmd_timings[cmd] << 16) |
			cs5535_pio_dta_timings[pioa];
		wrmsr(unit ? ATAC_CH0D1_PIO : ATAC_CH0D0_PIO, reg, 0);

		/* And if nessesary - change the speed of the other drive */
		rdmsr(unit ?  ATAC_CH0D0_PIO : ATAC_CH0D1_PIO, reg, dummy);

		if (((reg >> 16) & cs5535_pio_cmd_timings[cmd]) !=
			cs5535_pio_cmd_timings[cmd]) {
			reg &= 0x0000FFFF;
			reg |= cs5535_pio_cmd_timings[cmd] << 16;
			wrmsr(unit ? ATAC_CH0D0_PIO : ATAC_CH0D1_PIO, reg, 0);
		}

		/* Set bit 31 of the DMA register for PIO format 1 timings */
		rdmsr(unit ?  ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, dummy);
		wrmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA,
					reg | 0x80000000UL, 0);
	} else {
		rdmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, dummy);

		reg &= 0x80000000UL;  /* Preserve the PIO format bit */

		if (speed >= XFER_UDMA_0 && speed <= XFER_UDMA_4)
			reg |= cs5535_udma_timings[speed - XFER_UDMA_0];
		else if (speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2)
			reg |= cs5535_mwdma_timings[speed - XFER_MW_DMA_0];
		else
			return;

		wrmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, 0);
	}
}

/**
 *	cs5535_set_dma_mode	-	set host controller for DMA mode
 *	@hwif: port
 *	@drive: drive
 *
 *	Programs the chipset for DMA mode.
 */

static void cs5535_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
{
	cs5535_set_speed(drive, drive->dma_mode);
}

/**
 *	cs5535_set_pio_mode	-	set host controller for PIO mode
 *	@hwif: port
 *	@drive: drive
 *
 *	A callback from the upper layers for PIO-only tuning.
 */

static void cs5535_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
{
	cs5535_set_speed(drive, drive->pio_mode);
}

static u8 cs5535_cable_detect(ide_hwif_t *hwif)
{
	struct pci_dev *dev = to_pci_dev(hwif->dev);
	u8 bit;

	/* if a 80 wire cable was detected */
	pci_read_config_byte(dev, CS5535_CABLE_DETECT, &bit);

	return (bit & 1) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
}

static const struct ide_port_ops cs5535_port_ops = {
	.set_pio_mode		= cs5535_set_pio_mode,
	.set_dma_mode		= cs5535_set_dma_mode,
	.cable_detect		= cs5535_cable_detect,
};

static const struct ide_port_info cs5535_chipset = {
	.name		= DRV_NAME,
	.port_ops	= &cs5535_port_ops,
	.host_flags	= IDE_HFLAG_SINGLE | IDE_HFLAG_POST_SET_MODE,
	.pio_mask	= ATA_PIO4,
	.mwdma_mask	= ATA_MWDMA2,
	.udma_mask	= ATA_UDMA4,
};

static int cs5535_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	return ide_pci_init_one(dev, &cs5535_chipset, NULL);
}

static const struct pci_device_id cs5535_pci_tbl[] = {
	{ PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_CS5535_IDE), 0 },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5535_IDE), },
	{ 0, },
};

MODULE_DEVICE_TABLE(pci, cs5535_pci_tbl);

static struct pci_driver cs5535_pci_driver = {
	.name		= "CS5535_IDE",
	.id_table	= cs5535_pci_tbl,
	.probe		= cs5535_init_one,
	.remove		= ide_pci_remove,
	.suspend	= ide_pci_suspend,
	.resume		= ide_pci_resume,
};

static int __init cs5535_ide_init(void)
{
	return ide_pci_register_driver(&cs5535_pci_driver);
}

static void __exit cs5535_ide_exit(void)
{
	pci_unregister_driver(&cs5535_pci_driver);
}

module_init(cs5535_ide_init);
module_exit(cs5535_ide_exit);

MODULE_AUTHOR("AMD");
MODULE_DESCRIPTION("PCI driver module for AMD/NS CS5535 IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
f5b2d8b4	2	/*
f5b2d8b4	3	* Copyright (C) 2004-2005 Advanced Micro Devices, Inc.
bc0b0b5c	4	* Copyright (C) 2007 Bartlomiej Zolnierkiewicz
f5b2d8b4 JK	5	*
	6	* History:
	7	* 09/20/2005 - Jaya Kumar <jayakumar.ide@gmail.com>
	8	* - Reworked tuneproc, set_drive, misc mods to prep for mainline
	9	* - Work was sponsored by CIS (M) Sdn Bhd.
	10	* Ported to Kernel 2.6.11 on June 26, 2005 by
	11	* Wolfgang Zuleger <wolfgang.zuleger@gmx.de>
	12	* Alexander Kiausch <alex.kiausch@t-online.de>
	13	* Originally developed by AMD for 2.4/2.6
	14	*
	15	* Development of this chipset driver was funded
	16	* by the nice folks at National Semiconductor/AMD.
	17	*
f5b2d8b4 JK	18	* Documentation:
	19	* CS5535 documentation available from AMD
	20	*/
	21
f5b2d8b4 JK	22	#include <linux/module.h>
	23	#include <linux/pci.h>
	24	#include <linux/ide.h>
	25
ced3ec8a BZ	26	#define DRV_NAME "cs5535"
ced3ec8a BZ	27
f5b2d8b4 JK	28	#define MSR_ATAC_BASE 0x51300000
	29	#define ATAC_GLD_MSR_CAP (MSR_ATAC_BASE+0)
	30	#define ATAC_GLD_MSR_CONFIG (MSR_ATAC_BASE+0x01)
	31	#define ATAC_GLD_MSR_SMI (MSR_ATAC_BASE+0x02)
	32	#define ATAC_GLD_MSR_ERROR (MSR_ATAC_BASE+0x03)
	33	#define ATAC_GLD_MSR_PM (MSR_ATAC_BASE+0x04)
	34	#define ATAC_GLD_MSR_DIAG (MSR_ATAC_BASE+0x05)
	35	#define ATAC_IO_BAR (MSR_ATAC_BASE+0x08)
	36	#define ATAC_RESET (MSR_ATAC_BASE+0x10)
	37	#define ATAC_CH0D0_PIO (MSR_ATAC_BASE+0x20)
	38	#define ATAC_CH0D0_DMA (MSR_ATAC_BASE+0x21)
	39	#define ATAC_CH0D1_PIO (MSR_ATAC_BASE+0x22)
	40	#define ATAC_CH0D1_DMA (MSR_ATAC_BASE+0x23)
	41	#define ATAC_PCI_ABRTERR (MSR_ATAC_BASE+0x24)
	42	#define ATAC_BM0_CMD_PRIM 0x00
	43	#define ATAC_BM0_STS_PRIM 0x02
	44	#define ATAC_BM0_PRD 0x04
	45	#define CS5535_CABLE_DETECT 0x48
	46
a1c6d28c	47	/* Format I PIO settings. We separate out cmd and data for safer timings */
f5b2d8b4 JK	48
	49	static unsigned int cs5535_pio_cmd_timings[5] =
	50	{ 0xF7F4, 0x53F3, 0x13F1, 0x5131, 0x1131 };
	51	static unsigned int cs5535_pio_dta_timings[5] =
	52	{ 0xF7F4, 0xF173, 0x8141, 0x5131, 0x1131 };
	53
	54	static unsigned int cs5535_mwdma_timings[3] =
	55	{ 0x7F0FFFF3, 0x7F035352, 0x7f024241 };
	56
	57	static unsigned int cs5535_udma_timings[5] =
	58	{ 0x7F7436A1, 0x7F733481, 0x7F723261, 0x7F713161, 0x7F703061 };
	59
	60	/* Macros to check if the register is the reset value - reset value is an
	61	invalid timing and indicates the register has not been set previously */
	62
	63	#define CS5535_BAD_PIO(timings) ( (timings&~0x80000000UL) == 0x00009172 )
	64	#define CS5535_BAD_DMA(timings) ( (timings & 0x000FFFFF) == 0x00077771 )
	65
	66	/****
	67	* cs5535_set_speed - Configure the chipset to the new speed
	68	* @drive: Drive to set up
	69	* @speed: desired speed
	70	*
	71	* cs5535_set_speed() configures the chipset to a new speed.
	72	*/
f212ff28	73	static void cs5535_set_speed(ide_drive_t *drive, const u8 speed)
f5b2d8b4	74	{
f5b2d8b4	75	u32 reg = 0, dummy;
123995b9	76	u8 unit = drive->dn & 1;
f5b2d8b4	77
f5b2d8b4	78	/* Set the PIO timings */
bd887f72	79	if (speed < XFER_SW_DMA_0) {
7e59ea21	80	ide_drive_t *pair = ide_get_pair_dev(drive);
bc0b0b5c	81	u8 cmd, pioa;
f5b2d8b4	82
bc0b0b5c BZ	83	cmd = pioa = speed - XFER_PIO_0;
bc0b0b5c BZ	84
7e59ea21	85	if (pair) {
a298dc02	86	u8 piob = pair->pio_mode - XFER_PIO_0;
bc0b0b5c BZ	87
	88	if (piob < cmd)
	89	cmd = piob;
	90	}
f5b2d8b4 JK	91
	92	/* Write the speed of the current drive */
	93	reg = (cs5535_pio_cmd_timings[cmd] << 16) \|
	94	cs5535_pio_dta_timings[pioa];
	95	wrmsr(unit ? ATAC_CH0D1_PIO : ATAC_CH0D0_PIO, reg, 0);
	96
	97	/* And if nessesary - change the speed of the other drive */
	98	rdmsr(unit ? ATAC_CH0D0_PIO : ATAC_CH0D1_PIO, reg, dummy);
	99
	100	if (((reg >> 16) & cs5535_pio_cmd_timings[cmd]) !=
	101	cs5535_pio_cmd_timings[cmd]) {
	102	reg &= 0x0000FFFF;
	103	reg \|= cs5535_pio_cmd_timings[cmd] << 16;
	104	wrmsr(unit ? ATAC_CH0D0_PIO : ATAC_CH0D1_PIO, reg, 0);
	105	}
	106
	107	/* Set bit 31 of the DMA register for PIO format 1 timings */
	108	rdmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, dummy);
	109	wrmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA,
	110	reg \| 0x80000000UL, 0);
	111	} else {
	112	rdmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, dummy);
	113
	114	reg &= 0x80000000UL; /* Preserve the PIO format bit */
	115
32a70a81	116	if (speed >= XFER_UDMA_0 && speed <= XFER_UDMA_4)
f5b2d8b4 JK	117	reg \|= cs5535_udma_timings[speed - XFER_UDMA_0];
	118	else if (speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2)
	119	reg \|= cs5535_mwdma_timings[speed - XFER_MW_DMA_0];
	120	else
	121	return;
	122
	123	wrmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, 0);
	124	}
	125	}
	126
88b2b32b BZ	127	/**
88b2b32b BZ	128	* cs5535_set_dma_mode - set host controller for DMA mode
8776168c	129	* @hwif: port
88b2b32b	130	* @drive: drive
f5b2d8b4	131	*
88b2b32b	132	* Programs the chipset for DMA mode.
f5b2d8b4	133	*/
249aa4ff	134
8776168c	135	static void cs5535_set_dma_mode(ide_hwif_t hwif, ide_drive_t drive)
88b2b32b	136	{
8776168c	137	cs5535_set_speed(drive, drive->dma_mode);
f5b2d8b4 JK	138	}
f5b2d8b4 JK	139
26bcb879	140	/**
88b2b32b	141	* cs5535_set_pio_mode - set host controller for PIO mode
e085b3ca	142	* @hwif: port
26bcb879	143	* @drive: drive
f5b2d8b4 JK	144	*
	145	* A callback from the upper layers for PIO-only tuning.
	146	*/
26bcb879	147
e085b3ca	148	static void cs5535_set_pio_mode(ide_hwif_t hwif, ide_drive_t drive)
f5b2d8b4	149	{
e085b3ca	150	cs5535_set_speed(drive, drive->pio_mode);
f5b2d8b4 JK	151	}
f5b2d8b4 JK	152
f454cbe8	153	static u8 cs5535_cable_detect(ide_hwif_t *hwif)
f5b2d8b4	154	{
b4d1c73d	155	struct pci_dev *dev = to_pci_dev(hwif->dev);
f5b2d8b4 JK	156	u8 bit;
	157
	158	/* if a 80 wire cable was detected */
	159	pci_read_config_byte(dev, CS5535_CABLE_DETECT, &bit);
49521f97 BZ	160
49521f97 BZ	161	return (bit & 1) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
f5b2d8b4 JK	162	}
f5b2d8b4 JK	163
ac95beed BZ	164	static const struct ide_port_ops cs5535_port_ops = {
	165	.set_pio_mode = cs5535_set_pio_mode,
	166	.set_dma_mode = cs5535_set_dma_mode,
	167	.cable_detect = cs5535_cable_detect,
	168	};
f5b2d8b4	169
fe31edc8	170	static const struct ide_port_info cs5535_chipset = {
ced3ec8a	171	.name = DRV_NAME,
ac95beed	172	.port_ops = &cs5535_port_ops,
3b2a5c71	173	.host_flags = IDE_HFLAG_SINGLE \| IDE_HFLAG_POST_SET_MODE,
4099d143	174	.pio_mask = ATA_PIO4,
5f8b6c34 BZ	175	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	176	.udma_mask = ATA_UDMA4,
f5b2d8b4 JK	177	};
f5b2d8b4 JK	178
fe31edc8	179	static int cs5535_init_one(struct pci_dev dev, const struct pci_device_id id)
f5b2d8b4	180	{
6cdf6eb3	181	return ide_pci_init_one(dev, &cs5535_chipset, NULL);
f5b2d8b4 JK	182	}
f5b2d8b4 JK	183
9cbcc5e3 BZ	184	static const struct pci_device_id cs5535_pci_tbl[] = {
9cbcc5e3 BZ	185	{ PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_CS5535_IDE), 0 },
10ca3028	186	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5535_IDE), },
f5b2d8b4 JK	187	{ 0, },
	188	};
	189
	190	MODULE_DEVICE_TABLE(pci, cs5535_pci_tbl);
	191
a9ab09e2	192	static struct pci_driver cs5535_pci_driver = {
feb22b7f BZ	193	.name = "CS5535_IDE",
	194	.id_table = cs5535_pci_tbl,
	195	.probe = cs5535_init_one,
	196	.remove = ide_pci_remove,
	197	.suspend = ide_pci_suspend,
	198	.resume = ide_pci_resume,
f5b2d8b4 JK	199	};
	200
	201	static int __init cs5535_ide_init(void)
	202	{
a9ab09e2	203	return ide_pci_register_driver(&cs5535_pci_driver);
f5b2d8b4 JK	204	}
f5b2d8b4 JK	205
40c8a7f6 BZ	206	static void __exit cs5535_ide_exit(void)
40c8a7f6 BZ	207	{
a9ab09e2	208	pci_unregister_driver(&cs5535_pci_driver);
40c8a7f6 BZ	209	}
40c8a7f6 BZ	210
f5b2d8b4	211	module_init(cs5535_ide_init);
40c8a7f6	212	module_exit(cs5535_ide_exit);
f5b2d8b4 JK	213
	214	MODULE_AUTHOR("AMD");
	215	MODULE_DESCRIPTION("PCI driver module for AMD/NS CS5535 IDE");
	216	MODULE_LICENSE("GPL");