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[PATCH] CRIS IDE driver
[linux-block.git] / drivers / ide / cris / ide-cris.c
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e63b68de
MS		 1/* $Id: cris-ide-driver.patch,v 1.1 2005/06/29 21:39:07 akpm Exp $
2 *
3 * Etrax specific IDE functions, like init and PIO-mode setting etc.
4 * Almost the entire ide.c is used for the rest of the Etrax ATA driver.
5 * Copyright (c) 2000-2005 Axis Communications AB
6 *
7 * Authors: Bjorn Wesen (initial version)
8 * Mikael Starvik (crisv32 port)
9 */
10
11/* Regarding DMA:
12 *
13 * There are two forms of DMA - "DMA handshaking" between the interface and the drive,
14 * and DMA between the memory and the interface. We can ALWAYS use the latter, since it's
15 * something built-in in the Etrax. However only some drives support the DMA-mode handshaking
16 * on the ATA-bus. The normal PC driver and Triton interface disables memory-if DMA when the
17 * device can't do DMA handshaking for some stupid reason. We don't need to do that.
18 */
19
20#undef REALLY_SLOW_IO /* most systems can safely undef this */
21
22#include <linux/config.h>
23#include <linux/types.h>
24#include <linux/kernel.h>
25#include <linux/timer.h>
26#include <linux/mm.h>
27#include <linux/interrupt.h>
28#include <linux/delay.h>
29#include <linux/blkdev.h>
30#include <linux/hdreg.h>
31#include <linux/ide.h>
32#include <linux/init.h>
33
34#include <asm/io.h>
35#include <asm/dma.h>
36
37/* number of DMA descriptors */
38#define MAX_DMA_DESCRS 64
39
40/* number of times to retry busy-flags when reading/writing IDE-registers
41 * this can't be too high because a hung harddisk might cause the watchdog
42 * to trigger (sometimes INB and OUTB are called with irq's disabled)
43 */
44
45#define IDE_REGISTER_TIMEOUT 300
46
47#define LOWDB(x)
48#define D(x)
49
50enum /* Transfer types */
51{
52 TYPE_PIO,
53 TYPE_DMA,
54 TYPE_UDMA
55};
56
57/* CRISv32 specifics */
58#ifdef CONFIG_ETRAX_ARCH_V32
59#include <asm/arch/hwregs/ata_defs.h>
60#include <asm/arch/hwregs/dma_defs.h>
61#include <asm/arch/hwregs/dma.h>
62#include <asm/arch/pinmux.h>
63
64#define ATA_UDMA2_CYC 2
65#define ATA_UDMA2_DVS 3
66#define ATA_UDMA1_CYC 2
67#define ATA_UDMA1_DVS 4
68#define ATA_UDMA0_CYC 4
69#define ATA_UDMA0_DVS 6
70#define ATA_DMA2_STROBE 7
71#define ATA_DMA2_HOLD 1
72#define ATA_DMA1_STROBE 8
73#define ATA_DMA1_HOLD 3
74#define ATA_DMA0_STROBE 25
75#define ATA_DMA0_HOLD 19
76#define ATA_PIO4_SETUP 3
77#define ATA_PIO4_STROBE 7
78#define ATA_PIO4_HOLD 1
79#define ATA_PIO3_SETUP 3
80#define ATA_PIO3_STROBE 9
81#define ATA_PIO3_HOLD 3
82#define ATA_PIO2_SETUP 3
83#define ATA_PIO2_STROBE 13
84#define ATA_PIO2_HOLD 5
85#define ATA_PIO1_SETUP 5
86#define ATA_PIO1_STROBE 23
87#define ATA_PIO1_HOLD 9
88#define ATA_PIO0_SETUP 9
89#define ATA_PIO0_STROBE 39
90#define ATA_PIO0_HOLD 9
91
92int
93cris_ide_ack_intr(ide_hwif_t* hwif)
94{
95 reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2,
96 int, hwif->io_ports[0]);
97 REG_WR_INT(ata, regi_ata, rw_ack_intr, 1 << ctrl2.sel);
98 return 1;
99}
100
101static inline int
102cris_ide_busy(void)
103{
104 reg_ata_rs_stat_data stat_data;
105 stat_data = REG_RD(ata, regi_ata, rs_stat_data);
106 return stat_data.busy;
107}
108
109static inline int
110cris_ide_ready(void)
111{
112 return !cris_ide_busy();
113}
114
115static inline int
116cris_ide_data_available(unsigned short* data)
117{
118 reg_ata_rs_stat_data stat_data;
119 stat_data = REG_RD(ata, regi_ata, rs_stat_data);
120 *data = stat_data.data;
121 return stat_data.dav;
122}
123
124static void
125cris_ide_write_command(unsigned long command)
126{
127 REG_WR_INT(ata, regi_ata, rw_ctrl2, command); /* write data to the drive's register */
128}
129
130static void
131cris_ide_set_speed(int type, int setup, int strobe, int hold)
132{
133 reg_ata_rw_ctrl0 ctrl0 = REG_RD(ata, regi_ata, rw_ctrl0);
134 reg_ata_rw_ctrl1 ctrl1 = REG_RD(ata, regi_ata, rw_ctrl1);
135
136 if (type == TYPE_PIO) {
137 ctrl0.pio_setup = setup;
138 ctrl0.pio_strb = strobe;
139 ctrl0.pio_hold = hold;
140 } else if (type == TYPE_DMA) {
141 ctrl0.dma_strb = strobe;
142 ctrl0.dma_hold = hold;
143 } else if (type == TYPE_UDMA) {
144 ctrl1.udma_tcyc = setup;
145 ctrl1.udma_tdvs = strobe;
146 }
147 REG_WR(ata, regi_ata, rw_ctrl0, ctrl0);
148 REG_WR(ata, regi_ata, rw_ctrl1, ctrl1);
149}
150
151static unsigned long
152cris_ide_base_address(int bus)
153{
154 reg_ata_rw_ctrl2 ctrl2 = {0};
155 ctrl2.sel = bus;
156 return REG_TYPE_CONV(int, reg_ata_rw_ctrl2, ctrl2);
157}
158
159static unsigned long
160cris_ide_reg_addr(unsigned long addr, int cs0, int cs1)
161{
162 reg_ata_rw_ctrl2 ctrl2 = {0};
163 ctrl2.addr = addr;
164 ctrl2.cs1 = cs1;
165 ctrl2.cs0 = cs0;
166 return REG_TYPE_CONV(int, reg_ata_rw_ctrl2, ctrl2);
167}
168
169static __init void
170cris_ide_reset(unsigned val)
171{
172 reg_ata_rw_ctrl0 ctrl0 = {0};
173 ctrl0.rst = val ? regk_ata_active : regk_ata_inactive;
174 REG_WR(ata, regi_ata, rw_ctrl0, ctrl0);
175}
176
177static __init void
178cris_ide_init(void)
179{
180 reg_ata_rw_ctrl0 ctrl0 = {0};
181 reg_ata_rw_intr_mask intr_mask = {0};
182
183 ctrl0.en = regk_ata_yes;
184 REG_WR(ata, regi_ata, rw_ctrl0, ctrl0);
185
186 intr_mask.bus0 = regk_ata_yes;
187 intr_mask.bus1 = regk_ata_yes;
188 intr_mask.bus2 = regk_ata_yes;
189 intr_mask.bus3 = regk_ata_yes;
190
191 REG_WR(ata, regi_ata, rw_intr_mask, intr_mask);
192
193 crisv32_request_dma(2, "ETRAX FS built-in ATA", DMA_VERBOSE_ON_ERROR, 0, dma_ata);
194 crisv32_request_dma(3, "ETRAX FS built-in ATA", DMA_VERBOSE_ON_ERROR, 0, dma_ata);
195
196 crisv32_pinmux_alloc_fixed(pinmux_ata);
197 crisv32_pinmux_alloc_fixed(pinmux_ata0);
198 crisv32_pinmux_alloc_fixed(pinmux_ata1);
199 crisv32_pinmux_alloc_fixed(pinmux_ata2);
200 crisv32_pinmux_alloc_fixed(pinmux_ata3);
201
202 DMA_RESET(regi_dma2);
203 DMA_ENABLE(regi_dma2);
204 DMA_RESET(regi_dma3);
205 DMA_ENABLE(regi_dma3);
206
207 DMA_WR_CMD (regi_dma2, regk_dma_set_w_size2);
208 DMA_WR_CMD (regi_dma3, regk_dma_set_w_size2);
209}
210
211static dma_descr_context mycontext __attribute__ ((__aligned__(32)));
212
213#define cris_dma_descr_type dma_descr_data
214#define cris_pio_read regk_ata_rd
215#define cris_ultra_mask 0x7
216#define MAX_DESCR_SIZE 0xffffffffUL
217
218static unsigned long
219cris_ide_get_reg(unsigned long reg)
220{
221 return (reg & 0x0e000000) >> 25;
222}
223
224static void
225cris_ide_fill_descriptor(cris_dma_descr_type *d, void* buf, unsigned int len, int last)
226{
227 d->buf = (char*)virt_to_phys(buf);
228 d->after = d->buf + len;
229 d->eol = last;
230}
231
232static void
233cris_ide_start_dma(ide_drive_t *drive, cris_dma_descr_type *d, int dir,int type,int len)
234{
235 reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2, int, IDE_DATA_REG);
236 reg_ata_rw_trf_cnt trf_cnt = {0};
237
238 mycontext.saved_data = (dma_descr_data*)virt_to_phys(d);
239 mycontext.saved_data_buf = d->buf;
240 /* start the dma channel */
241 DMA_START_CONTEXT(dir ? regi_dma3 : regi_dma2, virt_to_phys(&mycontext));
242
243 /* initiate a multi word dma read using PIO handshaking */
244 trf_cnt.cnt = len >> 1;
245 /* Due to a "feature" the transfer count has to be one extra word for UDMA. */
246 if (type == TYPE_UDMA)
247 trf_cnt.cnt++;
248 REG_WR(ata, regi_ata, rw_trf_cnt, trf_cnt);
249
250 ctrl2.rw = dir ? regk_ata_rd : regk_ata_wr;
251 ctrl2.trf_mode = regk_ata_dma;
252 ctrl2.hsh = type == TYPE_PIO ? regk_ata_pio :
253 type == TYPE_DMA ? regk_ata_dma : regk_ata_udma;
254 ctrl2.multi = regk_ata_yes;
255 ctrl2.dma_size = regk_ata_word;
256 REG_WR(ata, regi_ata, rw_ctrl2, ctrl2);
257}
258
259static void
260cris_ide_wait_dma(int dir)
261{
262 reg_dma_rw_stat status;
263 do
264 {
265 status = REG_RD(dma, dir ? regi_dma3 : regi_dma2, rw_stat);
266 } while(status.list_state != regk_dma_data_at_eol);
267}
268
269static int cris_dma_test_irq(ide_drive_t *drive)
270{
271 int intr = REG_RD_INT(ata, regi_ata, r_intr);
272 reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2, int, IDE_DATA_REG);
273 return intr & (1 << ctrl2.sel) ? 1 : 0;
274}
275
276static void cris_ide_initialize_dma(int dir)
277{
278}
279
280#else
281/* CRISv10 specifics */
282#include <asm/arch/svinto.h>
283#include <asm/arch/io_interface_mux.h>
284
285/* PIO timing (in R_ATA_CONFIG)
286 *
287 * _____________________________
288 * ADDRESS : ________/
289 *
290 * _______________
291 * DIOR : ____________/ \__________
292 *
293 * _______________
294 * DATA : XXXXXXXXXXXXXXXX_______________XXXXXXXX
295 *
296 *
297 * DIOR is unbuffered while address and data is buffered.
298 * This creates two problems:
299 * 1. The DIOR pulse is to early (because it is unbuffered)
300 * 2. The rise time of DIOR is long
301 *
302 * There are at least three different plausible solutions
303 * 1. Use a pad capable of larger currents in Etrax
304 * 2. Use an external buffer
305 * 3. Make the strobe pulse longer
306 *
307 * Some of the strobe timings below are modified to compensate
308 * for this. This implies a slight performance decrease.
309 *
310 * THIS SHOULD NEVER BE CHANGED!
311 *
312 * TODO: Is this true for the latest LX boards still ?
313 */
314
315#define ATA_UDMA2_CYC 0 /* No UDMA supported, just to make it compile. */
316#define ATA_UDMA2_DVS 0
317#define ATA_UDMA1_CYC 0
318#define ATA_UDMA1_DVS 0
319#define ATA_UDMA0_CYC 0
320#define ATA_UDMA0_DVS 0
321#define ATA_DMA2_STROBE 4
322#define ATA_DMA2_HOLD 0
323#define ATA_DMA1_STROBE 4
324#define ATA_DMA1_HOLD 1
325#define ATA_DMA0_STROBE 12
326#define ATA_DMA0_HOLD 9
327#define ATA_PIO4_SETUP 1
328#define ATA_PIO4_STROBE 5
329#define ATA_PIO4_HOLD 0
330#define ATA_PIO3_SETUP 1
331#define ATA_PIO3_STROBE 5
332#define ATA_PIO3_HOLD 1
333#define ATA_PIO2_SETUP 1
334#define ATA_PIO2_STROBE 6
335#define ATA_PIO2_HOLD 2
336#define ATA_PIO1_SETUP 2
337#define ATA_PIO1_STROBE 11
338#define ATA_PIO1_HOLD 4
339#define ATA_PIO0_SETUP 4
340#define ATA_PIO0_STROBE 19
341#define ATA_PIO0_HOLD 4
342
343int
344cris_ide_ack_intr(ide_hwif_t* hwif)
345{
346 return 1;
347}
348
349static inline int
350cris_ide_busy(void)
351{
352 return *R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy) ;
353}
354
355static inline int
356cris_ide_ready(void)
357{
358 return *R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, tr_rdy) ;
359}
360
361static inline int
362cris_ide_data_available(unsigned short* data)
363{
364 unsigned long status = *R_ATA_STATUS_DATA;
365 *data = (unsigned short)status;
366 return status & IO_MASK(R_ATA_STATUS_DATA, dav);
367}
368
369static void
370cris_ide_write_command(unsigned long command)
371{
372 *R_ATA_CTRL_DATA = command;
373}
374
375static void
376cris_ide_set_speed(int type, int setup, int strobe, int hold)
377{
378 static int pio_setup = ATA_PIO4_SETUP;
379 static int pio_strobe = ATA_PIO4_STROBE;
380 static int pio_hold = ATA_PIO4_HOLD;
381 static int dma_strobe = ATA_DMA2_STROBE;
382 static int dma_hold = ATA_DMA2_HOLD;
383
384 if (type == TYPE_PIO) {
385 pio_setup = setup;
386 pio_strobe = strobe;
387 pio_hold = hold;
388 } else if (type == TYPE_DMA) {
389 dma_strobe = strobe;
390 dma_hold = hold;
391 }
392 *R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable, 1 ) |
393 IO_FIELD( R_ATA_CONFIG, dma_strobe, dma_strobe ) |
394 IO_FIELD( R_ATA_CONFIG, dma_hold, dma_hold ) |
395 IO_FIELD( R_ATA_CONFIG, pio_setup, pio_setup ) |
396 IO_FIELD( R_ATA_CONFIG, pio_strobe, pio_strobe ) |
397 IO_FIELD( R_ATA_CONFIG, pio_hold, pio_hold ) );
398}
399
400static unsigned long
401cris_ide_base_address(int bus)
402{
403 return IO_FIELD(R_ATA_CTRL_DATA, sel, bus);
404}
405
406static unsigned long
407cris_ide_reg_addr(unsigned long addr, int cs0, int cs1)
408{
409 return IO_FIELD(R_ATA_CTRL_DATA, addr, addr) |
410 IO_FIELD(R_ATA_CTRL_DATA, cs0, cs0) |
411 IO_FIELD(R_ATA_CTRL_DATA, cs1, cs1);
412}
413
414static __init void
415cris_ide_reset(unsigned val)
416{
417#ifdef CONFIG_ETRAX_IDE_G27_RESET
418 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow, 27, val);
419#endif
420#ifdef CONFIG_ETRAX_IDE_CSE1_16_RESET
421 REG_SHADOW_SET(port_cse1_addr, port_cse1_shadow, 16, val);
422#endif
423#ifdef CONFIG_ETRAX_IDE_CSP0_8_RESET
424 REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, 8, val);
425#endif
426#ifdef CONFIG_ETRAX_IDE_PB7_RESET
427 port_pb_dir_shadow = port_pb_dir_shadow |
428 IO_STATE(R_PORT_PB_DIR, dir7, output);
429 *R_PORT_PB_DIR = port_pb_dir_shadow;
430 REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, 7, val);
431#endif
432}
433
434static __init void
435cris_ide_init(void)
436{
437 volatile unsigned int dummy;
438
439 *R_ATA_CTRL_DATA = 0;
440 *R_ATA_TRANSFER_CNT = 0;
441 *R_ATA_CONFIG = 0;
442
443 if (cris_request_io_interface(if_ata, "ETRAX100LX IDE")) {
444 printk(KERN_CRIT "ide: Failed to get IO interface\n");
445 return;
446 } else if (cris_request_dma(ATA_TX_DMA_NBR,
447 "ETRAX100LX IDE TX",
448 DMA_VERBOSE_ON_ERROR,
449 dma_ata)) {
450 cris_free_io_interface(if_ata);
451 printk(KERN_CRIT "ide: Failed to get Tx DMA channel\n");
452 return;
453 } else if (cris_request_dma(ATA_RX_DMA_NBR,
454 "ETRAX100LX IDE RX",
455 DMA_VERBOSE_ON_ERROR,
456 dma_ata)) {
457 cris_free_dma(ATA_TX_DMA_NBR, "ETRAX100LX IDE Tx");
458 cris_free_io_interface(if_ata);
459 printk(KERN_CRIT "ide: Failed to get Rx DMA channel\n");
460 return;
461 }
462
463 /* make a dummy read to set the ata controller in a proper state */
464 dummy = *R_ATA_STATUS_DATA;
465
466 *R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable, 1 ));
467 *R_ATA_CTRL_DATA = ( IO_STATE( R_ATA_CTRL_DATA, rw, read) |
468 IO_FIELD( R_ATA_CTRL_DATA, addr, 1 ) );
469
470 while(*R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy)); /* wait for busy flag*/
471
472 *R_IRQ_MASK0_SET = ( IO_STATE( R_IRQ_MASK0_SET, ata_irq0, set ) |
473 IO_STATE( R_IRQ_MASK0_SET, ata_irq1, set ) |
474 IO_STATE( R_IRQ_MASK0_SET, ata_irq2, set ) |
475 IO_STATE( R_IRQ_MASK0_SET, ata_irq3, set ) );
476
477 /* reset the dma channels we will use */
478
479 RESET_DMA(ATA_TX_DMA_NBR);
480 RESET_DMA(ATA_RX_DMA_NBR);
481 WAIT_DMA(ATA_TX_DMA_NBR);
482 WAIT_DMA(ATA_RX_DMA_NBR);
483}
484
485#define cris_dma_descr_type etrax_dma_descr
486#define cris_pio_read IO_STATE(R_ATA_CTRL_DATA, rw, read)
487#define cris_ultra_mask 0x0
488#define MAX_DESCR_SIZE 0x10000UL
489
490static unsigned long
491cris_ide_get_reg(unsigned long reg)
492{
493 return (reg & 0x0e000000) >> 25;
494}
495
496static void
497cris_ide_fill_descriptor(cris_dma_descr_type *d, void* buf, unsigned int len, int last)
498{
499 d->buf = virt_to_phys(buf);
500 d->sw_len = len == MAX_DESCR_SIZE ? 0 : len;
501 if (last)
502 d->ctrl |= d_eol;
503}
504
505static void cris_ide_start_dma(ide_drive_t *drive, cris_dma_descr_type *d, int dir, int type, int len)
506{
507 unsigned long cmd;
508
509 if (dir) {
510 /* need to do this before RX DMA due to a chip bug
511 * it is enough to just flush the part of the cache that
512 * corresponds to the buffers we start, but since HD transfers
513 * usually are more than 8 kB, it is easier to optimize for the
514 * normal case and just flush the entire cache. its the only
515 * way to be sure! (OB movie quote)
516 */
517 flush_etrax_cache();
518 *R_DMA_CH3_FIRST = virt_to_phys(d);
519 *R_DMA_CH3_CMD = IO_STATE(R_DMA_CH3_CMD, cmd, start);
520
521 } else {
522 *R_DMA_CH2_FIRST = virt_to_phys(d);
523 *R_DMA_CH2_CMD = IO_STATE(R_DMA_CH2_CMD, cmd, start);
524 }
525
526 /* initiate a multi word dma read using DMA handshaking */
527
528 *R_ATA_TRANSFER_CNT =
529 IO_FIELD(R_ATA_TRANSFER_CNT, count, len >> 1);
530
531 cmd = dir ? IO_STATE(R_ATA_CTRL_DATA, rw, read) : IO_STATE(R_ATA_CTRL_DATA, rw, write);
532 cmd |= type == TYPE_PIO ? IO_STATE(R_ATA_CTRL_DATA, handsh, pio) :
533 IO_STATE(R_ATA_CTRL_DATA, handsh, dma);
534 *R_ATA_CTRL_DATA =
535 cmd |
536 IO_FIELD(R_ATA_CTRL_DATA, data, IDE_DATA_REG) |
537 IO_STATE(R_ATA_CTRL_DATA, src_dst, dma) |
538 IO_STATE(R_ATA_CTRL_DATA, multi, on) |
539 IO_STATE(R_ATA_CTRL_DATA, dma_size, word);
540}
541
542static void
543cris_ide_wait_dma(int dir)
544{
545 if (dir)
546 WAIT_DMA(ATA_RX_DMA_NBR);
547 else
548 WAIT_DMA(ATA_TX_DMA_NBR);
549}
550
551static int cris_dma_test_irq(ide_drive_t *drive)
552{
553 int intr = *R_IRQ_MASK0_RD;
554 int bus = IO_EXTRACT(R_ATA_CTRL_DATA, sel, IDE_DATA_REG);
555 return intr & (1 << (bus + IO_BITNR(R_IRQ_MASK0_RD, ata_irq0))) ? 1 : 0;
556}
557
558
559static void cris_ide_initialize_dma(int dir)
560{
561 if (dir)
562 {
563 RESET_DMA(ATA_RX_DMA_NBR); /* sometimes the DMA channel get stuck so we need to do this */
564 WAIT_DMA(ATA_RX_DMA_NBR);
565 }
566 else
567 {
568 RESET_DMA(ATA_TX_DMA_NBR); /* sometimes the DMA channel get stuck so we need to do this */
569 WAIT_DMA(ATA_TX_DMA_NBR);
570 }
571}
572
573#endif
574
575void
576cris_ide_outw(unsigned short data, unsigned long reg) {
577 int timeleft;
578
579 LOWDB(printk("ow: data 0x%x, reg 0x%x\n", data, reg));
580
581 /* note the lack of handling any timeouts. we stop waiting, but we don't
582 * really notify anybody.
583 */
584
585 timeleft = IDE_REGISTER_TIMEOUT;
586 /* wait for busy flag */
587 do {
588 timeleft--;
589 } while(timeleft && cris_ide_busy());
590
591 /*
592 * Fall through at a timeout, so the ongoing command will be
593 * aborted by the write below, which is expected to be a dummy
594 * command to the command register. This happens when a faulty
595 * drive times out on a command. See comment on timeout in
596 * INB.
597 */
598 if(!timeleft)
599 printk("ATA timeout reg 0x%lx := 0x%x\n", reg, data);
600
601 cris_ide_write_command(reg|data); /* write data to the drive's register */
602
603 timeleft = IDE_REGISTER_TIMEOUT;
604 /* wait for transmitter ready */
605 do {
606 timeleft--;
607 } while(timeleft && !cris_ide_ready());
608}
609
610void
611cris_ide_outb(unsigned char data, unsigned long reg)
612{
613 cris_ide_outw(data, reg);
614}
615
616void
617cris_ide_outbsync(ide_drive_t *drive, u8 addr, unsigned long port)
618{
619 cris_ide_outw(addr, port);
620}
621
622unsigned short
623cris_ide_inw(unsigned long reg) {
624 int timeleft;
625 unsigned short val;
626
627 timeleft = IDE_REGISTER_TIMEOUT;
628 /* wait for busy flag */
629 do {
630 timeleft--;
631 } while(timeleft && cris_ide_busy());
632
633 if(!timeleft) {
634 /*
635 * If we're asked to read the status register, like for
636 * example when a command does not complete for an
637 * extended time, but the ATA interface is stuck in a
638 * busy state at the *ETRAX* ATA interface level (as has
639 * happened repeatedly with at least one bad disk), then
640 * the best thing to do is to pretend that we read
641 * "busy" in the status register, so the IDE driver will
642 * time-out, abort the ongoing command and perform a
643 * reset sequence. Note that the subsequent OUT_BYTE
644 * call will also timeout on busy, but as long as the
645 * write is still performed, everything will be fine.
646 */
647 if (cris_ide_get_reg(reg) == IDE_STATUS_OFFSET)
648 return BUSY_STAT;
649 else
650 /* For other rare cases we assume 0 is good enough. */
651 return 0;
652 }
653
654 cris_ide_write_command(reg | cris_pio_read);
655
656 timeleft = IDE_REGISTER_TIMEOUT;
657 /* wait for available */
658 do {
659 timeleft--;
660 } while(timeleft && !cris_ide_data_available(&val));
661
662 if(!timeleft)
663 return 0;
664
665 LOWDB(printk("inb: 0x%x from reg 0x%x\n", val & 0xff, reg));
666
667 return val;
668}
669
670unsigned char
671cris_ide_inb(unsigned long reg)
672{
673 return (unsigned char)cris_ide_inw(reg);
674}
675
676static int cris_dma_check (ide_drive_t *drive);
677static int cris_dma_end (ide_drive_t *drive);
678static int cris_dma_setup (ide_drive_t *drive);
679static void cris_dma_exec_cmd (ide_drive_t *drive, u8 command);
680static int cris_dma_test_irq(ide_drive_t *drive);
681static void cris_dma_start(ide_drive_t *drive);
682static void cris_ide_input_data (ide_drive_t *drive, void *, unsigned int);
683static void cris_ide_output_data (ide_drive_t *drive, void *, unsigned int);
684static void cris_atapi_input_bytes(ide_drive_t *drive, void *, unsigned int);
685static void cris_atapi_output_bytes(ide_drive_t *drive, void *, unsigned int);
686static int cris_dma_off (ide_drive_t *drive);
687static int cris_dma_on (ide_drive_t *drive);
688
689static void tune_cris_ide(ide_drive_t *drive, u8 pio)
690{
691 int setup, strobe, hold;
692
693 switch(pio)
694 {
695 case 0:
696 setup = ATA_PIO0_SETUP;
697 strobe = ATA_PIO0_STROBE;
698 hold = ATA_PIO0_HOLD;
699 break;
700 case 1:
701 setup = ATA_PIO1_SETUP;
702 strobe = ATA_PIO1_STROBE;
703 hold = ATA_PIO1_HOLD;
704 break;
705 case 2:
706 setup = ATA_PIO2_SETUP;
707 strobe = ATA_PIO2_STROBE;
708 hold = ATA_PIO2_HOLD;
709 break;
710 case 3:
711 setup = ATA_PIO3_SETUP;
712 strobe = ATA_PIO3_STROBE;
713 hold = ATA_PIO3_HOLD;
714 break;
715 case 4:
716 setup = ATA_PIO4_SETUP;
717 strobe = ATA_PIO4_STROBE;
718 hold = ATA_PIO4_HOLD;
719 break;
720 default:
721 return;
722 }
723
724 cris_ide_set_speed(TYPE_PIO, setup, strobe, hold);
725}
726
727static int speed_cris_ide(ide_drive_t *drive, u8 speed)
728{
729 int cyc = 0, dvs = 0, strobe = 0, hold = 0;
730
731 if (speed >= XFER_PIO_0 && speed <= XFER_PIO_4) {
732 tune_cris_ide(drive, speed - XFER_PIO_0);
733 return 0;
734 }
735
736 switch(speed)
737 {
738 case XFER_UDMA_0:
739 cyc = ATA_UDMA0_CYC;
740 dvs = ATA_UDMA0_DVS;
741 break;
742 case XFER_UDMA_1:
743 cyc = ATA_UDMA1_CYC;
744 dvs = ATA_UDMA1_DVS;
745 break;
746 case XFER_UDMA_2:
747 cyc = ATA_UDMA2_CYC;
748 dvs = ATA_UDMA2_DVS;
749 break;
750 case XFER_MW_DMA_0:
751 strobe = ATA_DMA0_STROBE;
752 hold = ATA_DMA0_HOLD;
753 break;
754 case XFER_MW_DMA_1:
755 strobe = ATA_DMA1_STROBE;
756 hold = ATA_DMA1_HOLD;
757 break;
758 case XFER_MW_DMA_2:
759 strobe = ATA_DMA2_STROBE;
760 hold = ATA_DMA2_HOLD;
761 break;
762 default:
763 return 0;
764 }
765
766 if (speed >= XFER_UDMA_0)
767 cris_ide_set_speed(TYPE_UDMA, cyc, dvs, 0);
768 else
769 cris_ide_set_speed(TYPE_DMA, 0, strobe, hold);
770
771 return 0;
772}
773
774void __init
775init_e100_ide (void)
776{
777 hw_regs_t hw;
778 int ide_offsets[IDE_NR_PORTS];
779 int h;
780 int i;
781
782 printk("ide: ETRAX FS built-in ATA DMA controller\n");
783
784 for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++)
785 ide_offsets[i] = cris_ide_reg_addr(i, 0, 1);
786
787 /* the IDE control register is at ATA address 6, with CS1 active instead of CS0 */
788 ide_offsets[IDE_CONTROL_OFFSET] = cris_ide_reg_addr(6, 1, 0);
789
790 /* first fill in some stuff in the ide_hwifs fields */
791
792 for(h = 0; h < MAX_HWIFS; h++) {
793 ide_hwif_t *hwif = &ide_hwifs[h];
794 ide_setup_ports(&hw, cris_ide_base_address(h),
795 ide_offsets,
796 0, 0, cris_ide_ack_intr,
797 ide_default_irq(0));
798 ide_register_hw(&hw, &hwif);
799 hwif->mmio = 2;
800 hwif->chipset = ide_etrax100;
801 hwif->tuneproc = &tune_cris_ide;
802 hwif->speedproc = &speed_cris_ide;
803 hwif->ata_input_data = &cris_ide_input_data;
804 hwif->ata_output_data = &cris_ide_output_data;
805 hwif->atapi_input_bytes = &cris_atapi_input_bytes;
806 hwif->atapi_output_bytes = &cris_atapi_output_bytes;
807 hwif->ide_dma_check = &cris_dma_check;
808 hwif->ide_dma_end = &cris_dma_end;
809 hwif->dma_setup = &cris_dma_setup;
810 hwif->dma_exec_cmd = &cris_dma_exec_cmd;
811 hwif->ide_dma_test_irq = &cris_dma_test_irq;
812 hwif->dma_start = &cris_dma_start;
813 hwif->OUTB = &cris_ide_outb;
814 hwif->OUTW = &cris_ide_outw;
815 hwif->OUTBSYNC = &cris_ide_outbsync;
816 hwif->INB = &cris_ide_inb;
817 hwif->INW = &cris_ide_inw;
818 hwif->ide_dma_host_off = &cris_dma_off;
819 hwif->ide_dma_host_on = &cris_dma_on;
820 hwif->ide_dma_off_quietly = &cris_dma_off;
821 hwif->udma_four = 0;
822 hwif->ultra_mask = cris_ultra_mask;
823 hwif->mwdma_mask = 0x07; /* Multiword DMA 0-2 */
824 hwif->swdma_mask = 0x07; /* Singleword DMA 0-2 */
825 }
826
827 /* Reset pulse */
828 cris_ide_reset(0);
829 udelay(25);
830 cris_ide_reset(1);
831
832 cris_ide_init();
833
834 cris_ide_set_speed(TYPE_PIO, ATA_PIO4_SETUP, ATA_PIO4_STROBE, ATA_PIO4_HOLD);
835 cris_ide_set_speed(TYPE_DMA, 0, ATA_DMA2_STROBE, ATA_DMA2_HOLD);
836 cris_ide_set_speed(TYPE_UDMA, ATA_UDMA2_CYC, ATA_UDMA2_DVS, 0);
837}
838
839static int cris_dma_off (ide_drive_t *drive)
840{
841 return 0;
842}
843
844static int cris_dma_on (ide_drive_t *drive)
845{
846 return 0;
847}
848
849
850static cris_dma_descr_type mydescr __attribute__ ((__aligned__(16)));
851
852/*
853 * The following routines are mainly used by the ATAPI drivers.
854 *
855 * These routines will round up any request for an odd number of bytes,
856 * so if an odd bytecount is specified, be sure that there's at least one
857 * extra byte allocated for the buffer.
858 */
859static void
860cris_atapi_input_bytes (ide_drive_t *drive, void *buffer, unsigned int bytecount)
861{
862 D(printk("atapi_input_bytes, buffer 0x%x, count %d\n",
863 buffer, bytecount));
864
865 if(bytecount & 1) {
866 printk("warning, odd bytecount in cdrom_in_bytes = %d.\n", bytecount);
867 bytecount++; /* to round off */
868 }
869
870 /* setup DMA and start transfer */
871
872 cris_ide_fill_descriptor(&mydescr, buffer, bytecount, 1);
873 cris_ide_start_dma(drive, &mydescr, 1, TYPE_PIO, bytecount);
874
875 /* wait for completion */
876 LED_DISK_READ(1);
877 cris_ide_wait_dma(1);
878 LED_DISK_READ(0);
879}
880
881static void
882cris_atapi_output_bytes (ide_drive_t *drive, void *buffer, unsigned int bytecount)
883{
884 D(printk("atapi_output_bytes, buffer 0x%x, count %d\n",
885 buffer, bytecount));
886
887 if(bytecount & 1) {
888 printk("odd bytecount %d in atapi_out_bytes!\n", bytecount);
889 bytecount++;
890 }
891
892 cris_ide_fill_descriptor(&mydescr, buffer, bytecount, 1);
893 cris_ide_start_dma(drive, &mydescr, 0, TYPE_PIO, bytecount);
894
895 /* wait for completion */
896
897 LED_DISK_WRITE(1);
898 LED_DISK_READ(1);
899 cris_ide_wait_dma(0);
900 LED_DISK_WRITE(0);
901}
902
903/*
904 * This is used for most PIO data transfers *from* the IDE interface
905 */
906static void
907cris_ide_input_data (ide_drive_t *drive, void *buffer, unsigned int wcount)
908{
909 cris_atapi_input_bytes(drive, buffer, wcount << 2);
910}
911
912/*
913 * This is used for most PIO data transfers *to* the IDE interface
914 */
915static void
916cris_ide_output_data (ide_drive_t *drive, void *buffer, unsigned int wcount)
917{
918 cris_atapi_output_bytes(drive, buffer, wcount << 2);
919}
920
921/* we only have one DMA channel on the chip for ATA, so we can keep these statically */
922static cris_dma_descr_type ata_descrs[MAX_DMA_DESCRS] __attribute__ ((__aligned__(16)));
923static unsigned int ata_tot_size;
924
925/*
926 * cris_ide_build_dmatable() prepares a dma request.
927 * Returns 0 if all went okay, returns 1 otherwise.
928 */
929static int cris_ide_build_dmatable (ide_drive_t *drive)
930{
931 ide_hwif_t *hwif = drive->hwif;
932 struct scatterlist* sg;
933 struct request *rq = drive->hwif->hwgroup->rq;
934 unsigned long size, addr;
935 unsigned int count = 0;
936 int i = 0;
937
938 sg = hwif->sg_table;
939
940 ata_tot_size = 0;
941
942 ide_map_sg(drive, rq);
943 i = hwif->sg_nents;
944
945 while(i) {
946 /*
947 * Determine addr and size of next buffer area. We assume that
948 * individual virtual buffers are always composed linearly in
949 * physical memory. For example, we assume that any 8kB buffer
950 * is always composed of two adjacent physical 4kB pages rather
951 * than two possibly non-adjacent physical 4kB pages.
952 */
953 /* group sequential buffers into one large buffer */
954 addr = page_to_phys(sg->page) + sg->offset;
955 size = sg_dma_len(sg);
956 while (sg++, --i) {
957 if ((addr + size) != page_to_phys(sg->page) + sg->offset)
958 break;
959 size += sg_dma_len(sg);
960 }
961
962 /* did we run out of descriptors? */
963
964 if(count >= MAX_DMA_DESCRS) {
965 printk("%s: too few DMA descriptors\n", drive->name);
966 return 1;
967 }
968
969 /* however, this case is more difficult - rw_trf_cnt cannot be more
970 than 65536 words per transfer, so in that case we need to either
971 1) use a DMA interrupt to re-trigger rw_trf_cnt and continue with
972 the descriptors, or
973 2) simply do the request here, and get dma_intr to only ide_end_request on
974 those blocks that were actually set-up for transfer.
975 */
976
977 if(ata_tot_size + size > 131072) {
978 printk("too large total ATA DMA request, %d + %d!\n", ata_tot_size, (int)size);
979 return 1;
980 }
981
982 /* If size > MAX_DESCR_SIZE it has to be splitted into new descriptors. Since we
983 don't handle size > 131072 only one split is necessary */
984
985 if(size > MAX_DESCR_SIZE) {
986 cris_ide_fill_descriptor(&ata_descrs[count], (void*)addr, MAX_DESCR_SIZE, 0);
987 count++;
988 ata_tot_size += MAX_DESCR_SIZE;
989 size -= MAX_DESCR_SIZE;
990 addr += MAX_DESCR_SIZE;
991 }
992
993 cris_ide_fill_descriptor(&ata_descrs[count], (void*)addr, size,i ? 0 : 1);
994 count++;
995 ata_tot_size += size;
996 }
997
998 if (count) {
999 /* return and say all is ok */
1000 return 0;
1001 }
1002
1003 printk("%s: empty DMA table?\n", drive->name);
1004 return 1; /* let the PIO routines handle this weirdness */
1005}
1006
1007static int cris_config_drive_for_dma (ide_drive_t *drive)
1008{
1009 u8 speed = ide_dma_speed(drive, 1);
1010
1011 if (!speed)
1012 return 0;
1013
1014 speed_cris_ide(drive, speed);
1015 ide_config_drive_speed(drive, speed);
1016
1017 return ide_dma_enable(drive);
1018}
1019
1020/*
1021 * cris_dma_intr() is the handler for disk read/write DMA interrupts
1022 */
1023static ide_startstop_t cris_dma_intr (ide_drive_t *drive)
1024{
1025 LED_DISK_READ(0);
1026 LED_DISK_WRITE(0);
1027
1028 return ide_dma_intr(drive);
1029}
1030
1031/*
1032 * Functions below initiates/aborts DMA read/write operations on a drive.
1033 *
1034 * The caller is assumed to have selected the drive and programmed the drive's
1035 * sector address using CHS or LBA. All that remains is to prepare for DMA
1036 * and then issue the actual read/write DMA/PIO command to the drive.
1037 *
1038 * For ATAPI devices, we just prepare for DMA and return. The caller should
1039 * then issue the packet command to the drive and call us again with
1040 * cris_dma_start afterwards.
1041 *
1042 * Returns 0 if all went well.
1043 * Returns 1 if DMA read/write could not be started, in which case
1044 * the caller should revert to PIO for the current request.
1045 */
1046
1047static int cris_dma_check(ide_drive_t *drive)
1048{
1049 ide_hwif_t *hwif = drive->hwif;
1050 struct hd_driveid* id = drive->id;
1051
1052 if (id && (id->capability & 1)) {
1053 if (ide_use_dma(drive)) {
1054 if (cris_config_drive_for_dma(drive))
1055 return hwif->ide_dma_on(drive);
1056 }
1057 }
1058
1059 return hwif->ide_dma_off_quietly(drive);
1060}
1061
1062static int cris_dma_end(ide_drive_t *drive)
1063{
1064 drive->waiting_for_dma = 0;
1065 return 0;
1066}
1067
1068static int cris_dma_setup(ide_drive_t *drive)
1069{
1070 struct request *rq = drive->hwif->hwgroup->rq;
1071
1072 cris_ide_initialize_dma(!rq_data_dir(rq));
1073 if (cris_ide_build_dmatable (drive)) {
1074 ide_map_sg(drive, rq);
1075 return 1;
1076 }
1077
1078 drive->waiting_for_dma = 1;
1079 return 0;
1080}
1081
1082static void cris_dma_exec_cmd(ide_drive_t *drive, u8 command)
1083{
1084 /* set the irq handler which will finish the request when DMA is done */
1085 ide_set_handler(drive, &cris_dma_intr, WAIT_CMD, NULL);
1086
1087 /* issue cmd to drive */
1088 cris_ide_outb(command, IDE_COMMAND_REG);
1089}
1090
1091static void cris_dma_start(ide_drive_t *drive)
1092{
1093 struct request *rq = drive->hwif->hwgroup->rq;
1094 int writing = rq_data_dir(rq);
1095 int type = TYPE_DMA;
1096
1097 if (drive->current_speed >= XFER_UDMA_0)
1098 type = TYPE_UDMA;
1099
1100 cris_ide_start_dma(drive, &ata_descrs[0], writing ? 0 : 1, type, ata_tot_size);
1101
1102 if (writing) {
1103 LED_DISK_WRITE(1);
1104 } else {
1105 LED_DISK_READ(1);
1106 }
1107}
Linux 6.x block layer and io_uring tree(s)