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ide: add short cables support
[linux-2.6-block.git] / drivers / ide / cris / ide-cris.c
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e63b68de
MS		 1/* $Id: cris-ide-driver.patch,v 1.1 2005/06/29 21:39:07 akpm Exp $
2 *
3 * Etrax specific IDE functions, like init and PIO-mode setting etc.
4 * Almost the entire ide.c is used for the rest of the Etrax ATA driver.
5 * Copyright (c) 2000-2005 Axis Communications AB
6 *
7 * Authors: Bjorn Wesen (initial version)
8 * Mikael Starvik (crisv32 port)
9 */
10
11/* Regarding DMA:
12 *
13 * There are two forms of DMA - "DMA handshaking" between the interface and the drive,
14 * and DMA between the memory and the interface. We can ALWAYS use the latter, since it's
15 * something built-in in the Etrax. However only some drives support the DMA-mode handshaking
16 * on the ATA-bus. The normal PC driver and Triton interface disables memory-if DMA when the
17 * device can't do DMA handshaking for some stupid reason. We don't need to do that.
18 */
19
e63b68de
MS		 20#include <linux/types.h>
21#include <linux/kernel.h>
22#include <linux/timer.h>
23#include <linux/mm.h>
24#include <linux/interrupt.h>
25#include <linux/delay.h>
26#include <linux/blkdev.h>
27#include <linux/hdreg.h>
28#include <linux/ide.h>
29#include <linux/init.h>
30
31#include <asm/io.h>
32#include <asm/dma.h>
33
34/* number of DMA descriptors */
35#define MAX_DMA_DESCRS 64
36
37/* number of times to retry busy-flags when reading/writing IDE-registers
38 * this can't be too high because a hung harddisk might cause the watchdog
39 * to trigger (sometimes INB and OUTB are called with irq's disabled)
40 */
41
42#define IDE_REGISTER_TIMEOUT 300
43
44#define LOWDB(x)
45#define D(x)
46
47enum /* Transfer types */
48{
49 TYPE_PIO,
50 TYPE_DMA,
51 TYPE_UDMA
52};
53
54/* CRISv32 specifics */
55#ifdef CONFIG_ETRAX_ARCH_V32
56#include <asm/arch/hwregs/ata_defs.h>
57#include <asm/arch/hwregs/dma_defs.h>
58#include <asm/arch/hwregs/dma.h>
59#include <asm/arch/pinmux.h>
60
61#define ATA_UDMA2_CYC 2
62#define ATA_UDMA2_DVS 3
63#define ATA_UDMA1_CYC 2
64#define ATA_UDMA1_DVS 4
65#define ATA_UDMA0_CYC 4
66#define ATA_UDMA0_DVS 6
67#define ATA_DMA2_STROBE 7
68#define ATA_DMA2_HOLD 1
69#define ATA_DMA1_STROBE 8
70#define ATA_DMA1_HOLD 3
71#define ATA_DMA0_STROBE 25
72#define ATA_DMA0_HOLD 19
73#define ATA_PIO4_SETUP 3
74#define ATA_PIO4_STROBE 7
75#define ATA_PIO4_HOLD 1
76#define ATA_PIO3_SETUP 3
77#define ATA_PIO3_STROBE 9
78#define ATA_PIO3_HOLD 3
79#define ATA_PIO2_SETUP 3
80#define ATA_PIO2_STROBE 13
81#define ATA_PIO2_HOLD 5
82#define ATA_PIO1_SETUP 5
83#define ATA_PIO1_STROBE 23
84#define ATA_PIO1_HOLD 9
85#define ATA_PIO0_SETUP 9
86#define ATA_PIO0_STROBE 39
87#define ATA_PIO0_HOLD 9
88
89int
90cris_ide_ack_intr(ide_hwif_t* hwif)
91{
92 reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2,
93 int, hwif->io_ports[0]);
94 REG_WR_INT(ata, regi_ata, rw_ack_intr, 1 << ctrl2.sel);
95 return 1;
96}
97
98static inline int
99cris_ide_busy(void)
100{
101 reg_ata_rs_stat_data stat_data;
102 stat_data = REG_RD(ata, regi_ata, rs_stat_data);
103 return stat_data.busy;
104}
105
106static inline int
107cris_ide_ready(void)
108{
109 return !cris_ide_busy();
110}
111
112static inline int
113cris_ide_data_available(unsigned short* data)
114{
115 reg_ata_rs_stat_data stat_data;
116 stat_data = REG_RD(ata, regi_ata, rs_stat_data);
117 *data = stat_data.data;
118 return stat_data.dav;
119}
120
121static void
122cris_ide_write_command(unsigned long command)
123{
124 REG_WR_INT(ata, regi_ata, rw_ctrl2, command); /* write data to the drive's register */
125}
126
127static void
128cris_ide_set_speed(int type, int setup, int strobe, int hold)
129{
130 reg_ata_rw_ctrl0 ctrl0 = REG_RD(ata, regi_ata, rw_ctrl0);
131 reg_ata_rw_ctrl1 ctrl1 = REG_RD(ata, regi_ata, rw_ctrl1);
132
133 if (type == TYPE_PIO) {
134 ctrl0.pio_setup = setup;
135 ctrl0.pio_strb = strobe;
136 ctrl0.pio_hold = hold;
137 } else if (type == TYPE_DMA) {
138 ctrl0.dma_strb = strobe;
139 ctrl0.dma_hold = hold;
140 } else if (type == TYPE_UDMA) {
141 ctrl1.udma_tcyc = setup;
142 ctrl1.udma_tdvs = strobe;
143 }
144 REG_WR(ata, regi_ata, rw_ctrl0, ctrl0);
145 REG_WR(ata, regi_ata, rw_ctrl1, ctrl1);
146}
147
148static unsigned long
149cris_ide_base_address(int bus)
150{
151 reg_ata_rw_ctrl2 ctrl2 = {0};
152 ctrl2.sel = bus;
153 return REG_TYPE_CONV(int, reg_ata_rw_ctrl2, ctrl2);
154}
155
156static unsigned long
157cris_ide_reg_addr(unsigned long addr, int cs0, int cs1)
158{
159 reg_ata_rw_ctrl2 ctrl2 = {0};
160 ctrl2.addr = addr;
161 ctrl2.cs1 = cs1;
162 ctrl2.cs0 = cs0;
163 return REG_TYPE_CONV(int, reg_ata_rw_ctrl2, ctrl2);
164}
165
166static __init void
167cris_ide_reset(unsigned val)
168{
169 reg_ata_rw_ctrl0 ctrl0 = {0};
170 ctrl0.rst = val ? regk_ata_active : regk_ata_inactive;
171 REG_WR(ata, regi_ata, rw_ctrl0, ctrl0);
172}
173
174static __init void
175cris_ide_init(void)
176{
177 reg_ata_rw_ctrl0 ctrl0 = {0};
178 reg_ata_rw_intr_mask intr_mask = {0};
179
180 ctrl0.en = regk_ata_yes;
181 REG_WR(ata, regi_ata, rw_ctrl0, ctrl0);
182
183 intr_mask.bus0 = regk_ata_yes;
184 intr_mask.bus1 = regk_ata_yes;
185 intr_mask.bus2 = regk_ata_yes;
186 intr_mask.bus3 = regk_ata_yes;
187
188 REG_WR(ata, regi_ata, rw_intr_mask, intr_mask);
189
190 crisv32_request_dma(2, "ETRAX FS built-in ATA", DMA_VERBOSE_ON_ERROR, 0, dma_ata);
191 crisv32_request_dma(3, "ETRAX FS built-in ATA", DMA_VERBOSE_ON_ERROR, 0, dma_ata);
192
193 crisv32_pinmux_alloc_fixed(pinmux_ata);
194 crisv32_pinmux_alloc_fixed(pinmux_ata0);
195 crisv32_pinmux_alloc_fixed(pinmux_ata1);
196 crisv32_pinmux_alloc_fixed(pinmux_ata2);
197 crisv32_pinmux_alloc_fixed(pinmux_ata3);
198
199 DMA_RESET(regi_dma2);
200 DMA_ENABLE(regi_dma2);
201 DMA_RESET(regi_dma3);
202 DMA_ENABLE(regi_dma3);
203
204 DMA_WR_CMD (regi_dma2, regk_dma_set_w_size2);
205 DMA_WR_CMD (regi_dma3, regk_dma_set_w_size2);
206}
207
208static dma_descr_context mycontext __attribute__ ((__aligned__(32)));
209
210#define cris_dma_descr_type dma_descr_data
211#define cris_pio_read regk_ata_rd
212#define cris_ultra_mask 0x7
213#define MAX_DESCR_SIZE 0xffffffffUL
214
215static unsigned long
216cris_ide_get_reg(unsigned long reg)
217{
218 return (reg & 0x0e000000) >> 25;
219}
220
221static void
222cris_ide_fill_descriptor(cris_dma_descr_type *d, void* buf, unsigned int len, int last)
223{
224 d->buf = (char*)virt_to_phys(buf);
225 d->after = d->buf + len;
226 d->eol = last;
227}
228
229static void
230cris_ide_start_dma(ide_drive_t *drive, cris_dma_descr_type *d, int dir,int type,int len)
231{
232 reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2, int, IDE_DATA_REG);
233 reg_ata_rw_trf_cnt trf_cnt = {0};
234
235 mycontext.saved_data = (dma_descr_data*)virt_to_phys(d);
236 mycontext.saved_data_buf = d->buf;
237 /* start the dma channel */
238 DMA_START_CONTEXT(dir ? regi_dma3 : regi_dma2, virt_to_phys(&mycontext));
239
240 /* initiate a multi word dma read using PIO handshaking */
241 trf_cnt.cnt = len >> 1;
242 /* Due to a "feature" the transfer count has to be one extra word for UDMA. */
243 if (type == TYPE_UDMA)
244 trf_cnt.cnt++;
245 REG_WR(ata, regi_ata, rw_trf_cnt, trf_cnt);
246
247 ctrl2.rw = dir ? regk_ata_rd : regk_ata_wr;
248 ctrl2.trf_mode = regk_ata_dma;
249 ctrl2.hsh = type == TYPE_PIO ? regk_ata_pio :
250 type == TYPE_DMA ? regk_ata_dma : regk_ata_udma;
251 ctrl2.multi = regk_ata_yes;
252 ctrl2.dma_size = regk_ata_word;
253 REG_WR(ata, regi_ata, rw_ctrl2, ctrl2);
254}
255
256static void
257cris_ide_wait_dma(int dir)
258{
259 reg_dma_rw_stat status;
260 do
261 {
262 status = REG_RD(dma, dir ? regi_dma3 : regi_dma2, rw_stat);
263 } while(status.list_state != regk_dma_data_at_eol);
264}
265
266static int cris_dma_test_irq(ide_drive_t *drive)
267{
268 int intr = REG_RD_INT(ata, regi_ata, r_intr);
269 reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2, int, IDE_DATA_REG);
270 return intr & (1 << ctrl2.sel) ? 1 : 0;
271}
272
273static void cris_ide_initialize_dma(int dir)
274{
275}
276
277#else
278/* CRISv10 specifics */
279#include <asm/arch/svinto.h>
280#include <asm/arch/io_interface_mux.h>
281
282/* PIO timing (in R_ATA_CONFIG)
283 *
284 * _____________________________
285 * ADDRESS : ________/
286 *
287 * _______________
288 * DIOR : ____________/ \__________
289 *
290 * _______________
291 * DATA : XXXXXXXXXXXXXXXX_______________XXXXXXXX
292 *
293 *
294 * DIOR is unbuffered while address and data is buffered.
295 * This creates two problems:
296 * 1. The DIOR pulse is to early (because it is unbuffered)
297 * 2. The rise time of DIOR is long
298 *
299 * There are at least three different plausible solutions
300 * 1. Use a pad capable of larger currents in Etrax
301 * 2. Use an external buffer
302 * 3. Make the strobe pulse longer
303 *
304 * Some of the strobe timings below are modified to compensate
305 * for this. This implies a slight performance decrease.
306 *
307 * THIS SHOULD NEVER BE CHANGED!
308 *
309 * TODO: Is this true for the latest LX boards still ?
310 */
311
312#define ATA_UDMA2_CYC 0 /* No UDMA supported, just to make it compile. */
313#define ATA_UDMA2_DVS 0
314#define ATA_UDMA1_CYC 0
315#define ATA_UDMA1_DVS 0
316#define ATA_UDMA0_CYC 0
317#define ATA_UDMA0_DVS 0
318#define ATA_DMA2_STROBE 4
319#define ATA_DMA2_HOLD 0
320#define ATA_DMA1_STROBE 4
321#define ATA_DMA1_HOLD 1
322#define ATA_DMA0_STROBE 12
323#define ATA_DMA0_HOLD 9
324#define ATA_PIO4_SETUP 1
325#define ATA_PIO4_STROBE 5
326#define ATA_PIO4_HOLD 0
327#define ATA_PIO3_SETUP 1
328#define ATA_PIO3_STROBE 5
329#define ATA_PIO3_HOLD 1
330#define ATA_PIO2_SETUP 1
331#define ATA_PIO2_STROBE 6
332#define ATA_PIO2_HOLD 2
333#define ATA_PIO1_SETUP 2
334#define ATA_PIO1_STROBE 11
335#define ATA_PIO1_HOLD 4
336#define ATA_PIO0_SETUP 4
337#define ATA_PIO0_STROBE 19
338#define ATA_PIO0_HOLD 4
339
340int
341cris_ide_ack_intr(ide_hwif_t* hwif)
342{
343 return 1;
344}
345
346static inline int
347cris_ide_busy(void)
348{
349 return *R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy) ;
350}
351
352static inline int
353cris_ide_ready(void)
354{
355 return *R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, tr_rdy) ;
356}
357
358static inline int
359cris_ide_data_available(unsigned short* data)
360{
361 unsigned long status = *R_ATA_STATUS_DATA;
362 *data = (unsigned short)status;
363 return status & IO_MASK(R_ATA_STATUS_DATA, dav);
364}
365
366static void
367cris_ide_write_command(unsigned long command)
368{
369 *R_ATA_CTRL_DATA = command;
370}
371
372static void
373cris_ide_set_speed(int type, int setup, int strobe, int hold)
374{
375 static int pio_setup = ATA_PIO4_SETUP;
376 static int pio_strobe = ATA_PIO4_STROBE;
377 static int pio_hold = ATA_PIO4_HOLD;
378 static int dma_strobe = ATA_DMA2_STROBE;
379 static int dma_hold = ATA_DMA2_HOLD;
380
381 if (type == TYPE_PIO) {
382 pio_setup = setup;
383 pio_strobe = strobe;
384 pio_hold = hold;
385 } else if (type == TYPE_DMA) {
386 dma_strobe = strobe;
387 dma_hold = hold;
388 }
389 *R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable, 1 ) |
390 IO_FIELD( R_ATA_CONFIG, dma_strobe, dma_strobe ) |
391 IO_FIELD( R_ATA_CONFIG, dma_hold, dma_hold ) |
392 IO_FIELD( R_ATA_CONFIG, pio_setup, pio_setup ) |
393 IO_FIELD( R_ATA_CONFIG, pio_strobe, pio_strobe ) |
394 IO_FIELD( R_ATA_CONFIG, pio_hold, pio_hold ) );
395}
396
397static unsigned long
398cris_ide_base_address(int bus)
399{
400 return IO_FIELD(R_ATA_CTRL_DATA, sel, bus);
401}
402
403static unsigned long
404cris_ide_reg_addr(unsigned long addr, int cs0, int cs1)
405{
406 return IO_FIELD(R_ATA_CTRL_DATA, addr, addr) |
407 IO_FIELD(R_ATA_CTRL_DATA, cs0, cs0) |
408 IO_FIELD(R_ATA_CTRL_DATA, cs1, cs1);
409}
410
411static __init void
412cris_ide_reset(unsigned val)
413{
414#ifdef CONFIG_ETRAX_IDE_G27_RESET
415 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow, 27, val);
416#endif
417#ifdef CONFIG_ETRAX_IDE_CSE1_16_RESET
418 REG_SHADOW_SET(port_cse1_addr, port_cse1_shadow, 16, val);
419#endif
420#ifdef CONFIG_ETRAX_IDE_CSP0_8_RESET
421 REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, 8, val);
422#endif
423#ifdef CONFIG_ETRAX_IDE_PB7_RESET
424 port_pb_dir_shadow = port_pb_dir_shadow |
425 IO_STATE(R_PORT_PB_DIR, dir7, output);
426 *R_PORT_PB_DIR = port_pb_dir_shadow;
427 REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, 7, val);
428#endif
429}
430
431static __init void
432cris_ide_init(void)
433{
434 volatile unsigned int dummy;
435
436 *R_ATA_CTRL_DATA = 0;
437 *R_ATA_TRANSFER_CNT = 0;
438 *R_ATA_CONFIG = 0;
439
440 if (cris_request_io_interface(if_ata, "ETRAX100LX IDE")) {
441 printk(KERN_CRIT "ide: Failed to get IO interface\n");
442 return;
443 } else if (cris_request_dma(ATA_TX_DMA_NBR,
444 "ETRAX100LX IDE TX",
445 DMA_VERBOSE_ON_ERROR,
446 dma_ata)) {
447 cris_free_io_interface(if_ata);
448 printk(KERN_CRIT "ide: Failed to get Tx DMA channel\n");
449 return;
450 } else if (cris_request_dma(ATA_RX_DMA_NBR,
451 "ETRAX100LX IDE RX",
452 DMA_VERBOSE_ON_ERROR,
453 dma_ata)) {
454 cris_free_dma(ATA_TX_DMA_NBR, "ETRAX100LX IDE Tx");
455 cris_free_io_interface(if_ata);
456 printk(KERN_CRIT "ide: Failed to get Rx DMA channel\n");
457 return;
458 }
459
460 /* make a dummy read to set the ata controller in a proper state */
461 dummy = *R_ATA_STATUS_DATA;
462
463 *R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable, 1 ));
464 *R_ATA_CTRL_DATA = ( IO_STATE( R_ATA_CTRL_DATA, rw, read) |
465 IO_FIELD( R_ATA_CTRL_DATA, addr, 1 ) );
466
467 while(*R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy)); /* wait for busy flag*/
468
469 *R_IRQ_MASK0_SET = ( IO_STATE( R_IRQ_MASK0_SET, ata_irq0, set ) |
470 IO_STATE( R_IRQ_MASK0_SET, ata_irq1, set ) |
471 IO_STATE( R_IRQ_MASK0_SET, ata_irq2, set ) |
472 IO_STATE( R_IRQ_MASK0_SET, ata_irq3, set ) );
473
474 /* reset the dma channels we will use */
475
476 RESET_DMA(ATA_TX_DMA_NBR);
477 RESET_DMA(ATA_RX_DMA_NBR);
478 WAIT_DMA(ATA_TX_DMA_NBR);
479 WAIT_DMA(ATA_RX_DMA_NBR);
480}
481
482#define cris_dma_descr_type etrax_dma_descr
483#define cris_pio_read IO_STATE(R_ATA_CTRL_DATA, rw, read)
484#define cris_ultra_mask 0x0
485#define MAX_DESCR_SIZE 0x10000UL
486
487static unsigned long
488cris_ide_get_reg(unsigned long reg)
489{
490 return (reg & 0x0e000000) >> 25;
491}
492
493static void
494cris_ide_fill_descriptor(cris_dma_descr_type *d, void* buf, unsigned int len, int last)
495{
496 d->buf = virt_to_phys(buf);
497 d->sw_len = len == MAX_DESCR_SIZE ? 0 : len;
498 if (last)
499 d->ctrl |= d_eol;
500}
501
502static void cris_ide_start_dma(ide_drive_t *drive, cris_dma_descr_type *d, int dir, int type, int len)
503{
504 unsigned long cmd;
505
506 if (dir) {
507 /* need to do this before RX DMA due to a chip bug
508 * it is enough to just flush the part of the cache that
509 * corresponds to the buffers we start, but since HD transfers
510 * usually are more than 8 kB, it is easier to optimize for the
511 * normal case and just flush the entire cache. its the only
512 * way to be sure! (OB movie quote)
513 */
514 flush_etrax_cache();
515 *R_DMA_CH3_FIRST = virt_to_phys(d);
516 *R_DMA_CH3_CMD = IO_STATE(R_DMA_CH3_CMD, cmd, start);
517
518 } else {
519 *R_DMA_CH2_FIRST = virt_to_phys(d);
520 *R_DMA_CH2_CMD = IO_STATE(R_DMA_CH2_CMD, cmd, start);
521 }
522
523 /* initiate a multi word dma read using DMA handshaking */
524
525 *R_ATA_TRANSFER_CNT =
526 IO_FIELD(R_ATA_TRANSFER_CNT, count, len >> 1);
527
528 cmd = dir ? IO_STATE(R_ATA_CTRL_DATA, rw, read) : IO_STATE(R_ATA_CTRL_DATA, rw, write);
529 cmd |= type == TYPE_PIO ? IO_STATE(R_ATA_CTRL_DATA, handsh, pio) :
530 IO_STATE(R_ATA_CTRL_DATA, handsh, dma);
531 *R_ATA_CTRL_DATA =
532 cmd |
533 IO_FIELD(R_ATA_CTRL_DATA, data, IDE_DATA_REG) |
534 IO_STATE(R_ATA_CTRL_DATA, src_dst, dma) |
535 IO_STATE(R_ATA_CTRL_DATA, multi, on) |
536 IO_STATE(R_ATA_CTRL_DATA, dma_size, word);
537}
538
539static void
540cris_ide_wait_dma(int dir)
541{
542 if (dir)
543 WAIT_DMA(ATA_RX_DMA_NBR);
544 else
545 WAIT_DMA(ATA_TX_DMA_NBR);
546}
547
548static int cris_dma_test_irq(ide_drive_t *drive)
549{
550 int intr = *R_IRQ_MASK0_RD;
551 int bus = IO_EXTRACT(R_ATA_CTRL_DATA, sel, IDE_DATA_REG);
552 return intr & (1 << (bus + IO_BITNR(R_IRQ_MASK0_RD, ata_irq0))) ? 1 : 0;
553}
554
555
556static void cris_ide_initialize_dma(int dir)
557{
558 if (dir)
559 {
560 RESET_DMA(ATA_RX_DMA_NBR); /* sometimes the DMA channel get stuck so we need to do this */
561 WAIT_DMA(ATA_RX_DMA_NBR);
562 }
563 else
564 {
565 RESET_DMA(ATA_TX_DMA_NBR); /* sometimes the DMA channel get stuck so we need to do this */
566 WAIT_DMA(ATA_TX_DMA_NBR);
567 }
568}
569
570#endif
571
572void
573cris_ide_outw(unsigned short data, unsigned long reg) {
574 int timeleft;
575
576 LOWDB(printk("ow: data 0x%x, reg 0x%x\n", data, reg));
577
578 /* note the lack of handling any timeouts. we stop waiting, but we don't
579 * really notify anybody.
580 */
581
582 timeleft = IDE_REGISTER_TIMEOUT;
583 /* wait for busy flag */
584 do {
585 timeleft--;
586 } while(timeleft && cris_ide_busy());
587
588 /*
589 * Fall through at a timeout, so the ongoing command will be
590 * aborted by the write below, which is expected to be a dummy
591 * command to the command register. This happens when a faulty
592 * drive times out on a command. See comment on timeout in
593 * INB.
594 */
595 if(!timeleft)
596 printk("ATA timeout reg 0x%lx := 0x%x\n", reg, data);
597
598 cris_ide_write_command(reg|data); /* write data to the drive's register */
599
600 timeleft = IDE_REGISTER_TIMEOUT;
601 /* wait for transmitter ready */
602 do {
603 timeleft--;
604 } while(timeleft && !cris_ide_ready());
605}
606
607void
608cris_ide_outb(unsigned char data, unsigned long reg)
609{
610 cris_ide_outw(data, reg);
611}
612
613void
614cris_ide_outbsync(ide_drive_t *drive, u8 addr, unsigned long port)
615{
616 cris_ide_outw(addr, port);
617}
618
619unsigned short
620cris_ide_inw(unsigned long reg) {
621 int timeleft;
622 unsigned short val;
623
624 timeleft = IDE_REGISTER_TIMEOUT;
625 /* wait for busy flag */
626 do {
627 timeleft--;
628 } while(timeleft && cris_ide_busy());
629
630 if(!timeleft) {
631 /*
632 * If we're asked to read the status register, like for
633 * example when a command does not complete for an
634 * extended time, but the ATA interface is stuck in a
635 * busy state at the *ETRAX* ATA interface level (as has
636 * happened repeatedly with at least one bad disk), then
637 * the best thing to do is to pretend that we read
638 * "busy" in the status register, so the IDE driver will
639 * time-out, abort the ongoing command and perform a
640 * reset sequence. Note that the subsequent OUT_BYTE
641 * call will also timeout on busy, but as long as the
642 * write is still performed, everything will be fine.
643 */
644 if (cris_ide_get_reg(reg) == IDE_STATUS_OFFSET)
645 return BUSY_STAT;
646 else
647 /* For other rare cases we assume 0 is good enough. */
648 return 0;
649 }
650
651 cris_ide_write_command(reg | cris_pio_read);
652
653 timeleft = IDE_REGISTER_TIMEOUT;
654 /* wait for available */
655 do {
656 timeleft--;
657 } while(timeleft && !cris_ide_data_available(&val));
658
659 if(!timeleft)
660 return 0;
661
662 LOWDB(printk("inb: 0x%x from reg 0x%x\n", val & 0xff, reg));
663
664 return val;
665}
666
667unsigned char
668cris_ide_inb(unsigned long reg)
669{
670 return (unsigned char)cris_ide_inw(reg);
671}
672
673static int cris_dma_check (ide_drive_t *drive);
674static int cris_dma_end (ide_drive_t *drive);
675static int cris_dma_setup (ide_drive_t *drive);
676static void cris_dma_exec_cmd (ide_drive_t *drive, u8 command);
677static int cris_dma_test_irq(ide_drive_t *drive);
678static void cris_dma_start(ide_drive_t *drive);
679static void cris_ide_input_data (ide_drive_t *drive, void *, unsigned int);
680static void cris_ide_output_data (ide_drive_t *drive, void *, unsigned int);
681static void cris_atapi_input_bytes(ide_drive_t *drive, void *, unsigned int);
682static void cris_atapi_output_bytes(ide_drive_t *drive, void *, unsigned int);
e63b68de
MS		 683static int cris_dma_on (ide_drive_t *drive);
684
7469aaf6
BZ		 685static void cris_dma_off(ide_drive_t *drive)
686{
687}
688
e63b68de
MS		 689static void tune_cris_ide(ide_drive_t *drive, u8 pio)
690{
691 int setup, strobe, hold;
692
693 switch(pio)
694 {
695 case 0:
696 setup = ATA_PIO0_SETUP;
697 strobe = ATA_PIO0_STROBE;
698 hold = ATA_PIO0_HOLD;
699 break;
700 case 1:
701 setup = ATA_PIO1_SETUP;
702 strobe = ATA_PIO1_STROBE;
703 hold = ATA_PIO1_HOLD;
704 break;
705 case 2:
706 setup = ATA_PIO2_SETUP;
707 strobe = ATA_PIO2_STROBE;
708 hold = ATA_PIO2_HOLD;
709 break;
710 case 3:
711 setup = ATA_PIO3_SETUP;
712 strobe = ATA_PIO3_STROBE;
713 hold = ATA_PIO3_HOLD;
714 break;
715 case 4:
716 setup = ATA_PIO4_SETUP;
717 strobe = ATA_PIO4_STROBE;
718 hold = ATA_PIO4_HOLD;
719 break;
720 default:
721 return;
722 }
723
724 cris_ide_set_speed(TYPE_PIO, setup, strobe, hold);
725}
726
727static int speed_cris_ide(ide_drive_t *drive, u8 speed)
728{
729 int cyc = 0, dvs = 0, strobe = 0, hold = 0;
730
731 if (speed >= XFER_PIO_0 && speed <= XFER_PIO_4) {
732 tune_cris_ide(drive, speed - XFER_PIO_0);
55e4dee3 733 return ide_config_drive_speed(drive, speed);
e63b68de
MS		 734 }
735
736 switch(speed)
737 {
738 case XFER_UDMA_0:
739 cyc = ATA_UDMA0_CYC;
740 dvs = ATA_UDMA0_DVS;
741 break;
742 case XFER_UDMA_1:
743 cyc = ATA_UDMA1_CYC;
744 dvs = ATA_UDMA1_DVS;
745 break;
746 case XFER_UDMA_2:
747 cyc = ATA_UDMA2_CYC;
748 dvs = ATA_UDMA2_DVS;
749 break;
750 case XFER_MW_DMA_0:
751 strobe = ATA_DMA0_STROBE;
752 hold = ATA_DMA0_HOLD;
753 break;
754 case XFER_MW_DMA_1:
755 strobe = ATA_DMA1_STROBE;
756 hold = ATA_DMA1_HOLD;
757 break;
758 case XFER_MW_DMA_2:
759 strobe = ATA_DMA2_STROBE;
760 hold = ATA_DMA2_HOLD;
761 break;
762 default:
55e4dee3
BZ		 763 BUG();
764 break;
e63b68de
MS		 765 }
766
767 if (speed >= XFER_UDMA_0)
768 cris_ide_set_speed(TYPE_UDMA, cyc, dvs, 0);
769 else
770 cris_ide_set_speed(TYPE_DMA, 0, strobe, hold);
771
55e4dee3 772 return ide_config_drive_speed(drive, speed);
e63b68de
MS		 773}
774
775void __init
776init_e100_ide (void)
777{
778 hw_regs_t hw;
779 int ide_offsets[IDE_NR_PORTS];
780 int h;
781 int i;
782
783 printk("ide: ETRAX FS built-in ATA DMA controller\n");
784
785 for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++)
786 ide_offsets[i] = cris_ide_reg_addr(i, 0, 1);
787
788 /* the IDE control register is at ATA address 6, with CS1 active instead of CS0 */
789 ide_offsets[IDE_CONTROL_OFFSET] = cris_ide_reg_addr(6, 1, 0);
790
791 /* first fill in some stuff in the ide_hwifs fields */
792
793 for(h = 0; h < MAX_HWIFS; h++) {
794 ide_hwif_t *hwif = &ide_hwifs[h];
795 ide_setup_ports(&hw, cris_ide_base_address(h),
796 ide_offsets,
797 0, 0, cris_ide_ack_intr,
798 ide_default_irq(0));
869c56ee 799 ide_register_hw(&hw, 1, &hwif);
2ad1e558 800 hwif->mmio = 1;
e63b68de
MS		 801 hwif->chipset = ide_etrax100;
802 hwif->tuneproc = &tune_cris_ide;
803 hwif->speedproc = &speed_cris_ide;
804 hwif->ata_input_data = &cris_ide_input_data;
805 hwif->ata_output_data = &cris_ide_output_data;
806 hwif->atapi_input_bytes = &cris_atapi_input_bytes;
807 hwif->atapi_output_bytes = &cris_atapi_output_bytes;
808 hwif->ide_dma_check = &cris_dma_check;
809 hwif->ide_dma_end = &cris_dma_end;
810 hwif->dma_setup = &cris_dma_setup;
811 hwif->dma_exec_cmd = &cris_dma_exec_cmd;
812 hwif->ide_dma_test_irq = &cris_dma_test_irq;
813 hwif->dma_start = &cris_dma_start;
814 hwif->OUTB = &cris_ide_outb;
815 hwif->OUTW = &cris_ide_outw;
816 hwif->OUTBSYNC = &cris_ide_outbsync;
817 hwif->INB = &cris_ide_inb;
818 hwif->INW = &cris_ide_inw;
7469aaf6 819 hwif->dma_host_off = &cris_dma_off;
ccf35289 820 hwif->dma_host_on = &cris_dma_on;
7469aaf6 821 hwif->dma_off_quietly = &cris_dma_off;
49521f97 822 hwif->cbl = ATA_CBL_PATA40;
e63b68de
MS		 823 hwif->ultra_mask = cris_ultra_mask;
824 hwif->mwdma_mask = 0x07; /* Multiword DMA 0-2 */
7569e8dc
BZ		 825 hwif->autodma = 1;
826 hwif->drives[0].autodma = 1;
827 hwif->drives[1].autodma = 1;
e63b68de
MS		 828 }
829
830 /* Reset pulse */
831 cris_ide_reset(0);
832 udelay(25);
833 cris_ide_reset(1);
834
835 cris_ide_init();
836
837 cris_ide_set_speed(TYPE_PIO, ATA_PIO4_SETUP, ATA_PIO4_STROBE, ATA_PIO4_HOLD);
838 cris_ide_set_speed(TYPE_DMA, 0, ATA_DMA2_STROBE, ATA_DMA2_HOLD);
839 cris_ide_set_speed(TYPE_UDMA, ATA_UDMA2_CYC, ATA_UDMA2_DVS, 0);
840}
841
e63b68de
MS		 842static int cris_dma_on (ide_drive_t *drive)
843{
844 return 0;
845}
846
847
848static cris_dma_descr_type mydescr __attribute__ ((__aligned__(16)));
849
850/*
851 * The following routines are mainly used by the ATAPI drivers.
852 *
853 * These routines will round up any request for an odd number of bytes,
854 * so if an odd bytecount is specified, be sure that there's at least one
855 * extra byte allocated for the buffer.
856 */
857static void
858cris_atapi_input_bytes (ide_drive_t *drive, void *buffer, unsigned int bytecount)
859{
860 D(printk("atapi_input_bytes, buffer 0x%x, count %d\n",
861 buffer, bytecount));
862
863 if(bytecount & 1) {
864 printk("warning, odd bytecount in cdrom_in_bytes = %d.\n", bytecount);
865 bytecount++; /* to round off */
866 }
867
868 /* setup DMA and start transfer */
869
870 cris_ide_fill_descriptor(&mydescr, buffer, bytecount, 1);
871 cris_ide_start_dma(drive, &mydescr, 1, TYPE_PIO, bytecount);
872
873 /* wait for completion */
874 LED_DISK_READ(1);
875 cris_ide_wait_dma(1);
876 LED_DISK_READ(0);
877}
878
879static void
880cris_atapi_output_bytes (ide_drive_t *drive, void *buffer, unsigned int bytecount)
881{
882 D(printk("atapi_output_bytes, buffer 0x%x, count %d\n",
883 buffer, bytecount));
884
885 if(bytecount & 1) {
886 printk("odd bytecount %d in atapi_out_bytes!\n", bytecount);
887 bytecount++;
888 }
889
890 cris_ide_fill_descriptor(&mydescr, buffer, bytecount, 1);
891 cris_ide_start_dma(drive, &mydescr, 0, TYPE_PIO, bytecount);
892
893 /* wait for completion */
894
895 LED_DISK_WRITE(1);
896 LED_DISK_READ(1);
897 cris_ide_wait_dma(0);
898 LED_DISK_WRITE(0);
899}
900
901/*
902 * This is used for most PIO data transfers *from* the IDE interface
903 */
904static void
905cris_ide_input_data (ide_drive_t *drive, void *buffer, unsigned int wcount)
906{
907 cris_atapi_input_bytes(drive, buffer, wcount << 2);
908}
909
910/*
911 * This is used for most PIO data transfers *to* the IDE interface
912 */
913static void
914cris_ide_output_data (ide_drive_t *drive, void *buffer, unsigned int wcount)
915{
916 cris_atapi_output_bytes(drive, buffer, wcount << 2);
917}
918
919/* we only have one DMA channel on the chip for ATA, so we can keep these statically */
920static cris_dma_descr_type ata_descrs[MAX_DMA_DESCRS] __attribute__ ((__aligned__(16)));
921static unsigned int ata_tot_size;
922
923/*
924 * cris_ide_build_dmatable() prepares a dma request.
925 * Returns 0 if all went okay, returns 1 otherwise.
926 */
927static int cris_ide_build_dmatable (ide_drive_t *drive)
928{
929 ide_hwif_t *hwif = drive->hwif;
930 struct scatterlist* sg;
931 struct request *rq = drive->hwif->hwgroup->rq;
932 unsigned long size, addr;
933 unsigned int count = 0;
934 int i = 0;
935
936 sg = hwif->sg_table;
937
938 ata_tot_size = 0;
939
940 ide_map_sg(drive, rq);
941 i = hwif->sg_nents;
942
943 while(i) {
944 /*
945 * Determine addr and size of next buffer area. We assume that
946 * individual virtual buffers are always composed linearly in
947 * physical memory. For example, we assume that any 8kB buffer
948 * is always composed of two adjacent physical 4kB pages rather
949 * than two possibly non-adjacent physical 4kB pages.
950 */
951 /* group sequential buffers into one large buffer */
952 addr = page_to_phys(sg->page) + sg->offset;
953 size = sg_dma_len(sg);
954 while (sg++, --i) {
955 if ((addr + size) != page_to_phys(sg->page) + sg->offset)
956 break;
957 size += sg_dma_len(sg);
958 }
959
960 /* did we run out of descriptors? */
961
962 if(count >= MAX_DMA_DESCRS) {
963 printk("%s: too few DMA descriptors\n", drive->name);
964 return 1;
965 }
966
967 /* however, this case is more difficult - rw_trf_cnt cannot be more
968 than 65536 words per transfer, so in that case we need to either
969 1) use a DMA interrupt to re-trigger rw_trf_cnt and continue with
970 the descriptors, or
971 2) simply do the request here, and get dma_intr to only ide_end_request on
972 those blocks that were actually set-up for transfer.
973 */
974
975 if(ata_tot_size + size > 131072) {
976 printk("too large total ATA DMA request, %d + %d!\n", ata_tot_size, (int)size);
977 return 1;
978 }
979
980 /* If size > MAX_DESCR_SIZE it has to be splitted into new descriptors. Since we
981 don't handle size > 131072 only one split is necessary */
982
983 if(size > MAX_DESCR_SIZE) {
984 cris_ide_fill_descriptor(&ata_descrs[count], (void*)addr, MAX_DESCR_SIZE, 0);
985 count++;
986 ata_tot_size += MAX_DESCR_SIZE;
987 size -= MAX_DESCR_SIZE;
988 addr += MAX_DESCR_SIZE;
989 }
990
991 cris_ide_fill_descriptor(&ata_descrs[count], (void*)addr, size,i ? 0 : 1);
992 count++;
993 ata_tot_size += size;
994 }
995
996 if (count) {
997 /* return and say all is ok */
998 return 0;
999 }
1000
1001 printk("%s: empty DMA table?\n", drive->name);
1002 return 1; /* let the PIO routines handle this weirdness */
1003}
1004
e63b68de
MS		 1005/*
1006 * cris_dma_intr() is the handler for disk read/write DMA interrupts
1007 */
1008static ide_startstop_t cris_dma_intr (ide_drive_t *drive)
1009{
1010 LED_DISK_READ(0);
1011 LED_DISK_WRITE(0);
1012
1013 return ide_dma_intr(drive);
1014}
1015
1016/*
1017 * Functions below initiates/aborts DMA read/write operations on a drive.
1018 *
1019 * The caller is assumed to have selected the drive and programmed the drive's
1020 * sector address using CHS or LBA. All that remains is to prepare for DMA
1021 * and then issue the actual read/write DMA/PIO command to the drive.
1022 *
1023 * For ATAPI devices, we just prepare for DMA and return. The caller should
1024 * then issue the packet command to the drive and call us again with
1025 * cris_dma_start afterwards.
1026 *
1027 * Returns 0 if all went well.
1028 * Returns 1 if DMA read/write could not be started, in which case
1029 * the caller should revert to PIO for the current request.
1030 */
1031
1032static int cris_dma_check(ide_drive_t *drive)
1033{
bd203b57 1034 if (ide_tune_dma(drive))
3608b5d7 1035 return 0;
e63b68de 1036
3608b5d7 1037 return -1;
e63b68de
MS		 1038}
1039
1040static int cris_dma_end(ide_drive_t *drive)
1041{
1042 drive->waiting_for_dma = 0;
1043 return 0;
1044}
1045
1046static int cris_dma_setup(ide_drive_t *drive)
1047{
1048 struct request *rq = drive->hwif->hwgroup->rq;
1049
1050 cris_ide_initialize_dma(!rq_data_dir(rq));
1051 if (cris_ide_build_dmatable (drive)) {
1052 ide_map_sg(drive, rq);
1053 return 1;
1054 }
1055
1056 drive->waiting_for_dma = 1;
1057 return 0;
1058}
1059
1060static void cris_dma_exec_cmd(ide_drive_t *drive, u8 command)
1061{
1062 /* set the irq handler which will finish the request when DMA is done */
1063 ide_set_handler(drive, &cris_dma_intr, WAIT_CMD, NULL);
1064
1065 /* issue cmd to drive */
1066 cris_ide_outb(command, IDE_COMMAND_REG);
1067}
1068
1069static void cris_dma_start(ide_drive_t *drive)
1070{
1071 struct request *rq = drive->hwif->hwgroup->rq;
1072 int writing = rq_data_dir(rq);
1073 int type = TYPE_DMA;
1074
1075 if (drive->current_speed >= XFER_UDMA_0)
1076 type = TYPE_UDMA;
1077
1078 cris_ide_start_dma(drive, &ata_descrs[0], writing ? 0 : 1, type, ata_tot_size);
1079
1080 if (writing) {
1081 LED_DISK_WRITE(1);
1082 } else {
1083 LED_DISK_READ(1);
1084 }
1085}
Linux 6.x block layer and io_uring tree(s)