[linux-2.6-block.git] / drivers / ide / cmd64x.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
 *           Due to massive hardware bugs, UltraDMA is only supported
 *           on the 646U2 and not on the 646U.
 *
 * Copyright (C) 1998		Eddie C. Dost  (ecd@skynet.be)
 * Copyright (C) 1998		David S. Miller (davem@redhat.com)
 *
 * Copyright (C) 1999-2002	Andre Hedrick <andre@linux-ide.org>
 * Copyright (C) 2007-2010	Bartlomiej Zolnierkiewicz
 * Copyright (C) 2007,2009	MontaVista Software, Inc. <source@mvista.com>
 */

#include <linux/module.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/ide.h>
#include <linux/init.h>

#include <asm/io.h>

#define DRV_NAME "cmd64x"

/*
 * CMD64x specific registers definition.
 */
#define CFR		0x50
#define   CFR_INTR_CH0		0x04

#define	CMDTIM		0x52
#define	ARTTIM0		0x53
#define	DRWTIM0		0x54
#define ARTTIM1 	0x55
#define DRWTIM1		0x56
#define ARTTIM23	0x57
#define   ARTTIM23_DIS_RA2	0x04
#define   ARTTIM23_DIS_RA3	0x08
#define   ARTTIM23_INTR_CH1	0x10
#define DRWTIM2		0x58
#define BRST		0x59
#define DRWTIM3		0x5b

#define BMIDECR0	0x70
#define MRDMODE		0x71
#define   MRDMODE_INTR_CH0	0x04
#define   MRDMODE_INTR_CH1	0x08
#define UDIDETCR0	0x73
#define DTPR0		0x74
#define BMIDECR1	0x78
#define BMIDECSR	0x79
#define UDIDETCR1	0x7B
#define DTPR1		0x7C

static void cmd64x_program_timings(ide_drive_t *drive, u8 mode)
{
	ide_hwif_t *hwif = drive->hwif;
	struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
	int bus_speed = ide_pci_clk ? ide_pci_clk : 33;
	const unsigned long T = 1000000 / bus_speed;
	static const u8 recovery_values[] =
		{15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0};
	static const u8 setup_values[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0};
	static const u8 arttim_regs[4] = {ARTTIM0, ARTTIM1, ARTTIM23, ARTTIM23};
	static const u8 drwtim_regs[4] = {DRWTIM0, DRWTIM1, DRWTIM2, DRWTIM3};
	struct ide_timing t;
	u8 arttim = 0;

	ide_timing_compute(drive, mode, &t, T, 0);

	/*
	 * In case we've got too long recovery phase, try to lengthen
	 * the active phase
	 */
	if (t.recover > 16) {
		t.active += t.recover - 16;
		t.recover = 16;
	}
	if (t.active > 16)		/* shouldn't actually happen... */
		t.active = 16;

	/*
	 * Convert values to internal chipset representation
	 */
	t.recover = recovery_values[t.recover];
	t.active &= 0x0f;

	/* Program the active/recovery counts into the DRWTIM register */
	pci_write_config_byte(dev, drwtim_regs[drive->dn],
			      (t.active << 4) | t.recover);

	/*
	 * The primary channel has individual address setup timing registers
	 * for each drive and the hardware selects the slowest timing itself.
	 * The secondary channel has one common register and we have to select
	 * the slowest address setup timing ourselves.
	 */
	if (hwif->channel) {
		ide_drive_t *pair = ide_get_pair_dev(drive);

		if (pair) {
			struct ide_timing tp;

			ide_timing_compute(pair, pair->pio_mode, &tp, T, 0);
			ide_timing_merge(&t, &tp, &t, IDE_TIMING_SETUP);
			if (pair->dma_mode) {
				ide_timing_compute(pair, pair->dma_mode,
						&tp, T, 0);
				ide_timing_merge(&tp, &t, &t, IDE_TIMING_SETUP);
			}
		}
	}

	if (t.setup > 5)		/* shouldn't actually happen... */
		t.setup = 5;

	/*
	 * Program the address setup clocks into the ARTTIM registers.
	 * Avoid clearing the secondary channel's interrupt bit.
	 */
	(void) pci_read_config_byte (dev, arttim_regs[drive->dn], &arttim);
	if (hwif->channel)
		arttim &= ~ARTTIM23_INTR_CH1;
	arttim &= ~0xc0;
	arttim |= setup_values[t.setup];
	(void) pci_write_config_byte(dev, arttim_regs[drive->dn], arttim);
}

/*
 * Attempts to set drive's PIO mode.
 * Special cases are 8: prefetch off, 9: prefetch on (both never worked)
 */

static void cmd64x_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
{
	const u8 pio = drive->pio_mode - XFER_PIO_0;

	/*
	 * Filter out the prefetch control values
	 * to prevent PIO5 from being programmed
	 */
	if (pio == 8 || pio == 9)
		return;

	cmd64x_program_timings(drive, XFER_PIO_0 + pio);
}

static void cmd64x_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
{
	struct pci_dev *dev	= to_pci_dev(hwif->dev);
	u8 unit			= drive->dn & 0x01;
	u8 regU = 0, pciU	= hwif->channel ? UDIDETCR1 : UDIDETCR0;
	const u8 speed		= drive->dma_mode;

	pci_read_config_byte(dev, pciU, &regU);
	regU &= ~(unit ? 0xCA : 0x35);

	switch(speed) {
	case XFER_UDMA_5:
		regU |= unit ? 0x0A : 0x05;
		break;
	case XFER_UDMA_4:
		regU |= unit ? 0x4A : 0x15;
		break;
	case XFER_UDMA_3:
		regU |= unit ? 0x8A : 0x25;
		break;
	case XFER_UDMA_2:
		regU |= unit ? 0x42 : 0x11;
		break;
	case XFER_UDMA_1:
		regU |= unit ? 0x82 : 0x21;
		break;
	case XFER_UDMA_0:
		regU |= unit ? 0xC2 : 0x31;
		break;
	case XFER_MW_DMA_2:
	case XFER_MW_DMA_1:
	case XFER_MW_DMA_0:
		cmd64x_program_timings(drive, speed);
		break;
	}

	pci_write_config_byte(dev, pciU, regU);
}

static void cmd648_clear_irq(ide_drive_t *drive)
{
	ide_hwif_t *hwif	= drive->hwif;
	struct pci_dev *dev	= to_pci_dev(hwif->dev);
	unsigned long base	= pci_resource_start(dev, 4);
	u8  irq_mask		= hwif->channel ? MRDMODE_INTR_CH1 :
						  MRDMODE_INTR_CH0;
	u8  mrdmode		= inb(base + 1);

	/* clear the interrupt bit */
	outb((mrdmode & ~(MRDMODE_INTR_CH0 | MRDMODE_INTR_CH1)) | irq_mask,
	     base + 1);
}

static void cmd64x_clear_irq(ide_drive_t *drive)
{
	ide_hwif_t *hwif	= drive->hwif;
	struct pci_dev *dev	= to_pci_dev(hwif->dev);
	int irq_reg		= hwif->channel ? ARTTIM23 : CFR;
	u8  irq_mask		= hwif->channel ? ARTTIM23_INTR_CH1 :
						  CFR_INTR_CH0;
	u8  irq_stat		= 0;

	(void) pci_read_config_byte(dev, irq_reg, &irq_stat);
	/* clear the interrupt bit */
	(void) pci_write_config_byte(dev, irq_reg, irq_stat | irq_mask);
}

static int cmd648_test_irq(ide_hwif_t *hwif)
{
	struct pci_dev *dev	= to_pci_dev(hwif->dev);
	unsigned long base	= pci_resource_start(dev, 4);
	u8 irq_mask		= hwif->channel ? MRDMODE_INTR_CH1 :
						  MRDMODE_INTR_CH0;
	u8 mrdmode		= inb(base + 1);

	pr_debug("%s: mrdmode: 0x%02x irq_mask: 0x%02x\n",
		 hwif->name, mrdmode, irq_mask);

	return (mrdmode & irq_mask) ? 1 : 0;
}

static int cmd64x_test_irq(ide_hwif_t *hwif)
{
	struct pci_dev *dev	= to_pci_dev(hwif->dev);
	int irq_reg		= hwif->channel ? ARTTIM23 : CFR;
	u8  irq_mask		= hwif->channel ? ARTTIM23_INTR_CH1 :
						  CFR_INTR_CH0;
	u8  irq_stat		= 0;

	(void) pci_read_config_byte(dev, irq_reg, &irq_stat);

	pr_debug("%s: irq_stat: 0x%02x irq_mask: 0x%02x\n",
		 hwif->name, irq_stat, irq_mask);

	return (irq_stat & irq_mask) ? 1 : 0;
}

/*
 * ASUS P55T2P4D with CMD646 chipset revision 0x01 requires the old
 * event order for DMA transfers.
 */

static int cmd646_1_dma_end(ide_drive_t *drive)
{
	ide_hwif_t *hwif = drive->hwif;
	u8 dma_stat = 0, dma_cmd = 0;

	/* get DMA status */
	dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
	/* read DMA command state */
	dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
	/* stop DMA */
	outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD);
	/* clear the INTR & ERROR bits */
	outb(dma_stat | 6, hwif->dma_base + ATA_DMA_STATUS);
	/* verify good DMA status */
	return (dma_stat & 7) != 4;
}

static int init_chipset_cmd64x(struct pci_dev *dev)
{
	u8 mrdmode = 0;

	/* Set a good latency timer and cache line size value. */
	(void) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
	/* FIXME: pci_set_master() to ensure a good latency timer value */

	/*
	 * Enable interrupts, select MEMORY READ LINE for reads.
	 *
	 * NOTE: although not mentioned in the PCI0646U specs,
	 * bits 0-1 are write only and won't be read back as
	 * set or not -- PCI0646U2 specs clarify this point.
	 */
	(void) pci_read_config_byte (dev, MRDMODE, &mrdmode);
	mrdmode &= ~0x30;
	(void) pci_write_config_byte(dev, MRDMODE, (mrdmode | 0x02));

	return 0;
}

static u8 cmd64x_cable_detect(ide_hwif_t *hwif)
{
	struct pci_dev  *dev	= to_pci_dev(hwif->dev);
	u8 bmidecsr = 0, mask	= hwif->channel ? 0x02 : 0x01;

	switch (dev->device) {
	case PCI_DEVICE_ID_CMD_648:
	case PCI_DEVICE_ID_CMD_649:
 		pci_read_config_byte(dev, BMIDECSR, &bmidecsr);
		return (bmidecsr & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
	default:
		return ATA_CBL_PATA40;
	}
}

static const struct ide_port_ops cmd64x_port_ops = {
	.set_pio_mode		= cmd64x_set_pio_mode,
	.set_dma_mode		= cmd64x_set_dma_mode,
	.clear_irq		= cmd64x_clear_irq,
	.test_irq		= cmd64x_test_irq,
	.cable_detect		= cmd64x_cable_detect,
};

static const struct ide_port_ops cmd648_port_ops = {
	.set_pio_mode		= cmd64x_set_pio_mode,
	.set_dma_mode		= cmd64x_set_dma_mode,
	.clear_irq		= cmd648_clear_irq,
	.test_irq		= cmd648_test_irq,
	.cable_detect		= cmd64x_cable_detect,
};

static const struct ide_dma_ops cmd646_rev1_dma_ops = {
	.dma_host_set		= ide_dma_host_set,
	.dma_setup		= ide_dma_setup,
	.dma_start		= ide_dma_start,
	.dma_end		= cmd646_1_dma_end,
	.dma_test_irq		= ide_dma_test_irq,
	.dma_lost_irq		= ide_dma_lost_irq,
	.dma_timer_expiry	= ide_dma_sff_timer_expiry,
	.dma_sff_read_status	= ide_dma_sff_read_status,
};

static const struct ide_port_info cmd64x_chipsets[] = {
	{	/* 0: CMD643 */
		.name		= DRV_NAME,
		.init_chipset	= init_chipset_cmd64x,
		.enablebits	= {{0x00,0x00,0x00}, {0x51,0x08,0x08}},
		.port_ops	= &cmd64x_port_ops,
		.host_flags	= IDE_HFLAG_CLEAR_SIMPLEX |
				  IDE_HFLAG_ABUSE_PREFETCH |
				  IDE_HFLAG_SERIALIZE,
		.pio_mask	= ATA_PIO5,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= 0x00, /* no udma */
	},
	{	/* 1: CMD646 */
		.name		= DRV_NAME,
		.init_chipset	= init_chipset_cmd64x,
		.enablebits	= {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
		.port_ops	= &cmd648_port_ops,
		.host_flags	= IDE_HFLAG_ABUSE_PREFETCH |
				  IDE_HFLAG_SERIALIZE,
		.pio_mask	= ATA_PIO5,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA2,
	},
	{	/* 2: CMD648 */
		.name		= DRV_NAME,
		.init_chipset	= init_chipset_cmd64x,
		.enablebits	= {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
		.port_ops	= &cmd648_port_ops,
		.host_flags	= IDE_HFLAG_ABUSE_PREFETCH,
		.pio_mask	= ATA_PIO5,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA4,
	},
	{	/* 3: CMD649 */
		.name		= DRV_NAME,
		.init_chipset	= init_chipset_cmd64x,
		.enablebits	= {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
		.port_ops	= &cmd648_port_ops,
		.host_flags	= IDE_HFLAG_ABUSE_PREFETCH,
		.pio_mask	= ATA_PIO5,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA5,
	}
};

static int cmd64x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	struct ide_port_info d;
	u8 idx = id->driver_data;

	d = cmd64x_chipsets[idx];

	if (idx == 1) {
		/*
		 * UltraDMA only supported on PCI646U and PCI646U2, which
		 * correspond to revisions 0x03, 0x05 and 0x07 respectively.
		 * Actually, although the CMD tech support people won't
		 * tell me the details, the 0x03 revision cannot support
		 * UDMA correctly without hardware modifications, and even
		 * then it only works with Quantum disks due to some
		 * hold time assumptions in the 646U part which are fixed
		 * in the 646U2.
		 *
		 * So we only do UltraDMA on revision 0x05 and 0x07 chipsets.
		 */
		if (dev->revision < 5) {
			d.udma_mask = 0x00;
			/*
			 * The original PCI0646 didn't have the primary
			 * channel enable bit, it appeared starting with
			 * PCI0646U (i.e. revision ID 3).
			 */
			if (dev->revision < 3) {
				d.enablebits[0].reg = 0;
				d.port_ops = &cmd64x_port_ops;
				if (dev->revision == 1)
					d.dma_ops = &cmd646_rev1_dma_ops;
			}
		}
	}

	return ide_pci_init_one(dev, &d, NULL);
}

static const struct pci_device_id cmd64x_pci_tbl[] = {
	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 },
	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 },
	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 2 },
	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 3 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, cmd64x_pci_tbl);

static struct pci_driver cmd64x_pci_driver = {
	.name		= "CMD64x_IDE",
	.id_table	= cmd64x_pci_tbl,
	.probe		= cmd64x_init_one,
	.remove		= ide_pci_remove,
	.suspend	= ide_pci_suspend,
	.resume		= ide_pci_resume,
};

static int __init cmd64x_ide_init(void)
{
	return ide_pci_register_driver(&cmd64x_pci_driver);
}

static void __exit cmd64x_ide_exit(void)
{
	pci_unregister_driver(&cmd64x_pci_driver);
}

module_init(cmd64x_ide_init);
module_exit(cmd64x_ide_exit);

MODULE_AUTHOR("Eddie Dost, David Miller, Andre Hedrick, Bartlomiej Zolnierkiewicz");
MODULE_DESCRIPTION("PCI driver module for CMD64x IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
09c434b8	1	// SPDX-License-Identifier: GPL-2.0-only
60e7a82f	2	/*
1da177e4	3	* cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
1da177e4 LT	4	* Due to massive hardware bugs, UltraDMA is only supported
	5	* on the 646U2 and not on the 646U.
	6	*
	7	* Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
	8	* Copyright (C) 1998 David S. Miller (davem@redhat.com)
	9	*
	10	* Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
60349ab9	11	* Copyright (C) 2007-2010 Bartlomiej Zolnierkiewicz
30e5ffc3	12	* Copyright (C) 2007,2009 MontaVista Software, Inc. <source@mvista.com>
1da177e4 LT	13	*/
1da177e4 LT	14
1da177e4 LT	15	#include <linux/module.h>
	16	#include <linux/types.h>
	17	#include <linux/pci.h>
1da177e4 LT	18	#include <linux/ide.h>
	19	#include <linux/init.h>
	20
	21	#include <asm/io.h>
	22
ced3ec8a BZ	23	#define DRV_NAME "cmd64x"
ced3ec8a BZ	24
1da177e4 LT	25	/*
	26	* CMD64x specific registers definition.
	27	*/
	28	#define CFR 0x50
e51e2528	29	#define CFR_INTR_CH0 0x04
1da177e4 LT	30
	31	#define CMDTIM 0x52
	32	#define ARTTIM0 0x53
	33	#define DRWTIM0 0x54
	34	#define ARTTIM1 0x55
	35	#define DRWTIM1 0x56
	36	#define ARTTIM23 0x57
	37	#define ARTTIM23_DIS_RA2 0x04
	38	#define ARTTIM23_DIS_RA3 0x08
	39	#define ARTTIM23_INTR_CH1 0x10
1da177e4 LT	40	#define DRWTIM2 0x58
	41	#define BRST 0x59
	42	#define DRWTIM3 0x5b
	43
	44	#define BMIDECR0 0x70
	45	#define MRDMODE 0x71
	46	#define MRDMODE_INTR_CH0 0x04
	47	#define MRDMODE_INTR_CH1 0x08
1da177e4 LT	48	#define UDIDETCR0 0x73
	49	#define DTPR0 0x74
	50	#define BMIDECR1 0x78
	51	#define BMIDECSR 0x79
1da177e4 LT	52	#define UDIDETCR1 0x7B
	53	#define DTPR1 0x7C
	54
60349ab9	55	static void cmd64x_program_timings(ide_drive_t *drive, u8 mode)
1da177e4	56	{
60349ab9	57	ide_hwif_t *hwif = drive->hwif;
ebae41a5	58	struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
60349ab9 BZ	59	int bus_speed = ide_pci_clk ? ide_pci_clk : 33;
60349ab9 BZ	60	const unsigned long T = 1000000 / bus_speed;
60e7a82f	61	static const u8 recovery_values[] =
1da177e4	62	{15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0};
60349ab9 BZ	63	static const u8 setup_values[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0};
60349ab9 BZ	64	static const u8 arttim_regs[4] = {ARTTIM0, ARTTIM1, ARTTIM23, ARTTIM23};
60e7a82f	65	static const u8 drwtim_regs[4] = {DRWTIM0, DRWTIM1, DRWTIM2, DRWTIM3};
60349ab9 BZ	66	struct ide_timing t;
60349ab9 BZ	67	u8 arttim = 0;
60e7a82f	68
60349ab9	69	ide_timing_compute(drive, mode, &t, T, 0);
60e7a82f	70
1da177e4	71	/*
60e7a82f SS	72	* In case we've got too long recovery phase, try to lengthen
60e7a82f SS	73	* the active phase
1da177e4	74	*/
60349ab9 BZ	75	if (t.recover > 16) {
	76	t.active += t.recover - 16;
	77	t.recover = 16;
1da177e4	78	}
60349ab9 BZ	79	if (t.active > 16) /* shouldn't actually happen... */
60349ab9 BZ	80	t.active = 16;
60e7a82f	81
1da177e4 LT	82	/*
	83	* Convert values to internal chipset representation
	84	*/
60349ab9 BZ	85	t.recover = recovery_values[t.recover];
60349ab9 BZ	86	t.active &= 0x0f;
1da177e4	87
60e7a82f	88	/* Program the active/recovery counts into the DRWTIM register */
60349ab9 BZ	89	pci_write_config_byte(dev, drwtim_regs[drive->dn],
60349ab9 BZ	90	(t.active << 4) \| t.recover);
1da177e4	91
60e7a82f SS	92	/*
	93	* The primary channel has individual address setup timing registers
	94	* for each drive and the hardware selects the slowest timing itself.
	95	* The secondary channel has one common register and we have to select
	96	* the slowest address setup timing ourselves.
	97	*/
	98	if (hwif->channel) {
5d44a150	99	ide_drive_t *pair = ide_get_pair_dev(drive);
60e7a82f	100
23d87405 BZ	101	if (pair) {
	102	struct ide_timing tp;
	103
	104	ide_timing_compute(pair, pair->pio_mode, &tp, T, 0);
	105	ide_timing_merge(&t, &tp, &t, IDE_TIMING_SETUP);
	106	if (pair->dma_mode) {
	107	ide_timing_compute(pair, pair->dma_mode,
	108	&tp, T, 0);
	109	ide_timing_merge(&tp, &t, &t, IDE_TIMING_SETUP);
	110	}
	111	}
1da177e4	112	}
1da177e4	113
60349ab9 BZ	114	if (t.setup > 5) /* shouldn't actually happen... */
60349ab9 BZ	115	t.setup = 5;
1da177e4	116
60e7a82f SS	117	/*
	118	* Program the address setup clocks into the ARTTIM registers.
	119	* Avoid clearing the secondary channel's interrupt bit.
	120	*/
	121	(void) pci_read_config_byte (dev, arttim_regs[drive->dn], &arttim);
	122	if (hwif->channel)
	123	arttim &= ~ARTTIM23_INTR_CH1;
	124	arttim &= ~0xc0;
60349ab9	125	arttim \|= setup_values[t.setup];
60e7a82f	126	(void) pci_write_config_byte(dev, arttim_regs[drive->dn], arttim);
f92d50e6 SS	127	}
	128
	129	/*
	130	* Attempts to set drive's PIO mode.
26bcb879	131	* Special cases are 8: prefetch off, 9: prefetch on (both never worked)
f92d50e6	132	*/
26bcb879	133
e085b3ca	134	static void cmd64x_set_pio_mode(ide_hwif_t hwif, ide_drive_t drive)
f92d50e6	135	{
e085b3ca BZ	136	const u8 pio = drive->pio_mode - XFER_PIO_0;
e085b3ca BZ	137
f92d50e6 SS	138	/*
	139	* Filter out the prefetch control values
	140	* to prevent PIO5 from being programmed
	141	*/
	142	if (pio == 8 \|\| pio == 9)
	143	return;
	144
60349ab9	145	cmd64x_program_timings(drive, XFER_PIO_0 + pio);
1da177e4 LT	146	}
1da177e4 LT	147
8776168c	148	static void cmd64x_set_dma_mode(ide_hwif_t hwif, ide_drive_t drive)
1da177e4	149	{
36501650	150	struct pci_dev *dev = to_pci_dev(hwif->dev);
60e7a82f SS	151	u8 unit = drive->dn & 0x01;
60e7a82f SS	152	u8 regU = 0, pciU = hwif->channel ? UDIDETCR1 : UDIDETCR0;
8776168c	153	const u8 speed = drive->dma_mode;
1da177e4	154
22cabc26 BZ	155	pci_read_config_byte(dev, pciU, &regU);
22cabc26 BZ	156	regU &= ~(unit ? 0xCA : 0x35);
1da177e4 LT	157
1da177e4 LT	158	switch(speed) {
60e7a82f SS	159	case XFER_UDMA_5:
	160	regU \|= unit ? 0x0A : 0x05;
	161	break;
	162	case XFER_UDMA_4:
	163	regU \|= unit ? 0x4A : 0x15;
	164	break;
	165	case XFER_UDMA_3:
	166	regU \|= unit ? 0x8A : 0x25;
	167	break;
	168	case XFER_UDMA_2:
	169	regU \|= unit ? 0x42 : 0x11;
	170	break;
	171	case XFER_UDMA_1:
	172	regU \|= unit ? 0x82 : 0x21;
	173	break;
	174	case XFER_UDMA_0:
	175	regU \|= unit ? 0xC2 : 0x31;
	176	break;
	177	case XFER_MW_DMA_2:
60e7a82f	178	case XFER_MW_DMA_1:
60e7a82f	179	case XFER_MW_DMA_0:
60349ab9	180	cmd64x_program_timings(drive, speed);
60e7a82f	181	break;
1da177e4 LT	182	}
1da177e4 LT	183
22cabc26	184	pci_write_config_byte(dev, pciU, regU);
1da177e4 LT	185	}
1da177e4 LT	186
30e5ffc3	187	static void cmd648_clear_irq(ide_drive_t *drive)
1da177e4	188	{
898ec223	189	ide_hwif_t *hwif = drive->hwif;
30e5ffc3 SS	190	struct pci_dev *dev = to_pci_dev(hwif->dev);
30e5ffc3 SS	191	unsigned long base = pci_resource_start(dev, 4);
66602c83 SS	192	u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 :
66602c83 SS	193	MRDMODE_INTR_CH0;
1c029fd6	194	u8 mrdmode = inb(base + 1);
66602c83 SS	195
66602c83 SS	196	/* clear the interrupt bit */
6183289c	197	outb((mrdmode & ~(MRDMODE_INTR_CH0 \| MRDMODE_INTR_CH1)) \| irq_mask,
1c029fd6	198	base + 1);
1da177e4 LT	199	}
1da177e4 LT	200
30e5ffc3	201	static void cmd64x_clear_irq(ide_drive_t *drive)
1da177e4	202	{
898ec223	203	ide_hwif_t *hwif = drive->hwif;
36501650	204	struct pci_dev *dev = to_pci_dev(hwif->dev);
66602c83 SS	205	int irq_reg = hwif->channel ? ARTTIM23 : CFR;
	206	u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 :
	207	CFR_INTR_CH0;
	208	u8 irq_stat = 0;
1da177e4	209
66602c83 SS	210	(void) pci_read_config_byte(dev, irq_reg, &irq_stat);
	211	/* clear the interrupt bit */
	212	(void) pci_write_config_byte(dev, irq_reg, irq_stat \| irq_mask);
66602c83 SS	213	}
66602c83 SS	214
628df2f3	215	static int cmd648_test_irq(ide_hwif_t *hwif)
66602c83	216	{
628df2f3 SS	217	struct pci_dev *dev = to_pci_dev(hwif->dev);
628df2f3 SS	218	unsigned long base = pci_resource_start(dev, 4);
66602c83 SS	219	u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 :
66602c83 SS	220	MRDMODE_INTR_CH0;
1c029fd6	221	u8 mrdmode = inb(base + 1);
66602c83	222
628df2f3 SS	223	pr_debug("%s: mrdmode: 0x%02x irq_mask: 0x%02x\n",
628df2f3 SS	224	hwif->name, mrdmode, irq_mask);
66602c83	225
628df2f3	226	return (mrdmode & irq_mask) ? 1 : 0;
1da177e4 LT	227	}
1da177e4 LT	228
628df2f3	229	static int cmd64x_test_irq(ide_hwif_t *hwif)
1da177e4	230	{
36501650	231	struct pci_dev *dev = to_pci_dev(hwif->dev);
66602c83 SS	232	int irq_reg = hwif->channel ? ARTTIM23 : CFR;
	233	u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 :
	234	CFR_INTR_CH0;
66602c83	235	u8 irq_stat = 0;
e51e2528 SS	236
e51e2528 SS	237	(void) pci_read_config_byte(dev, irq_reg, &irq_stat);
1da177e4	238
628df2f3 SS	239	pr_debug("%s: irq_stat: 0x%02x irq_mask: 0x%02x\n",
628df2f3 SS	240	hwif->name, irq_stat, irq_mask);
1da177e4	241
628df2f3	242	return (irq_stat & irq_mask) ? 1 : 0;
1da177e4 LT	243	}
	244
	245	/*
	246	* ASUS P55T2P4D with CMD646 chipset revision 0x01 requires the old
	247	* event order for DMA transfers.
	248	*/
	249
5e37bdc0	250	static int cmd646_1_dma_end(ide_drive_t *drive)
1da177e4	251	{
898ec223	252	ide_hwif_t *hwif = drive->hwif;
1da177e4 LT	253	u8 dma_stat = 0, dma_cmd = 0;
1da177e4 LT	254
1da177e4	255	/* get DMA status */
cab7f8ed	256	dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
1da177e4	257	/* read DMA command state */
cab7f8ed	258	dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
1da177e4	259	/* stop DMA */
cab7f8ed	260	outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD);
1da177e4	261	/* clear the INTR & ERROR bits */
cab7f8ed	262	outb(dma_stat \| 6, hwif->dma_base + ATA_DMA_STATUS);
1da177e4 LT	263	/* verify good DMA status */
	264	return (dma_stat & 7) != 4;
	265	}
	266
2ed0ef54	267	static int init_chipset_cmd64x(struct pci_dev *dev)
1da177e4	268	{
1da177e4 LT	269	u8 mrdmode = 0;
1da177e4 LT	270
1da177e4 LT	271	/* Set a good latency timer and cache line size value. */
	272	(void) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
	273	/* FIXME: pci_set_master() to ensure a good latency timer value */
	274
83a6d4ab SS	275	/*
	276	* Enable interrupts, select MEMORY READ LINE for reads.
	277	*
	278	* NOTE: although not mentioned in the PCI0646U specs,
	279	* bits 0-1 are write only and won't be read back as
	280	* set or not -- PCI0646U2 specs clarify this point.
1da177e4	281	*/
83a6d4ab SS	282	(void) pci_read_config_byte (dev, MRDMODE, &mrdmode);
	283	mrdmode &= ~0x30;
	284	(void) pci_write_config_byte(dev, MRDMODE, (mrdmode \| 0x02));
1da177e4	285
1da177e4 LT	286	return 0;
	287	}
	288
f454cbe8	289	static u8 cmd64x_cable_detect(ide_hwif_t *hwif)
1da177e4	290	{
36501650	291	struct pci_dev *dev = to_pci_dev(hwif->dev);
83a6d4ab	292	u8 bmidecsr = 0, mask = hwif->channel ? 0x02 : 0x01;
1da177e4	293
83a6d4ab SS	294	switch (dev->device) {
	295	case PCI_DEVICE_ID_CMD_648:
	296	case PCI_DEVICE_ID_CMD_649:
	297	pci_read_config_byte(dev, BMIDECSR, &bmidecsr);
49521f97	298	return (bmidecsr & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
83a6d4ab	299	default:
49521f97	300	return ATA_CBL_PATA40;
1da177e4	301	}
1da177e4 LT	302	}
1da177e4 LT	303
ac95beed BZ	304	static const struct ide_port_ops cmd64x_port_ops = {
	305	.set_pio_mode = cmd64x_set_pio_mode,
	306	.set_dma_mode = cmd64x_set_dma_mode,
30e5ffc3	307	.clear_irq = cmd64x_clear_irq,
628df2f3	308	.test_irq = cmd64x_test_irq,
30e5ffc3 SS	309	.cable_detect = cmd64x_cable_detect,
	310	};
	311
	312	static const struct ide_port_ops cmd648_port_ops = {
	313	.set_pio_mode = cmd64x_set_pio_mode,
	314	.set_dma_mode = cmd64x_set_dma_mode,
	315	.clear_irq = cmd648_clear_irq,
628df2f3	316	.test_irq = cmd648_test_irq,
ac95beed BZ	317	.cable_detect = cmd64x_cable_detect,
	318	};
	319
f37afdac BZ	320	static const struct ide_dma_ops cmd646_rev1_dma_ops = {
	321	.dma_host_set = ide_dma_host_set,
	322	.dma_setup = ide_dma_setup,
f37afdac	323	.dma_start = ide_dma_start,
5e37bdc0	324	.dma_end = cmd646_1_dma_end,
f37afdac BZ	325	.dma_test_irq = ide_dma_test_irq,
f37afdac BZ	326	.dma_lost_irq = ide_dma_lost_irq,
22117d6e	327	.dma_timer_expiry = ide_dma_sff_timer_expiry,
592b5315	328	.dma_sff_read_status = ide_dma_sff_read_status,
5e37bdc0 BZ	329	};
5e37bdc0 BZ	330
fe31edc8	331	static const struct ide_port_info cmd64x_chipsets[] = {
ced3ec8a BZ	332	{ /* 0: CMD643 */
ced3ec8a BZ	333	.name = DRV_NAME,
1da177e4	334	.init_chipset = init_chipset_cmd64x,
7accbffd	335	.enablebits = {{0x00,0x00,0x00}, {0x51,0x08,0x08}},
ac95beed	336	.port_ops = &cmd64x_port_ops,
8ac2b42a	337	.host_flags = IDE_HFLAG_CLEAR_SIMPLEX \|
9bd7496f MP	338	IDE_HFLAG_ABUSE_PREFETCH \|
9bd7496f MP	339	IDE_HFLAG_SERIALIZE,
4099d143	340	.pio_mask = ATA_PIO5,
5f8b6c34	341	.mwdma_mask = ATA_MWDMA2,
18137207	342	.udma_mask = 0x00, /* no udma */
ced3ec8a BZ	343	},
	344	{ /* 1: CMD646 */
	345	.name = DRV_NAME,
1da177e4	346	.init_chipset = init_chipset_cmd64x,
7accbffd	347	.enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
30e5ffc3	348	.port_ops = &cmd648_port_ops,
9bd7496f MP	349	.host_flags = IDE_HFLAG_ABUSE_PREFETCH \|
9bd7496f MP	350	IDE_HFLAG_SERIALIZE,
4099d143	351	.pio_mask = ATA_PIO5,
5f8b6c34 BZ	352	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	353	.udma_mask = ATA_UDMA2,
ced3ec8a BZ	354	},
	355	{ /* 2: CMD648 */
	356	.name = DRV_NAME,
1da177e4	357	.init_chipset = init_chipset_cmd64x,
7accbffd	358	.enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
30e5ffc3	359	.port_ops = &cmd648_port_ops,
5e71d9c5	360	.host_flags = IDE_HFLAG_ABUSE_PREFETCH,
4099d143	361	.pio_mask = ATA_PIO5,
5f8b6c34 BZ	362	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	363	.udma_mask = ATA_UDMA4,
ced3ec8a BZ	364	},
	365	{ /* 3: CMD649 */
	366	.name = DRV_NAME,
1da177e4	367	.init_chipset = init_chipset_cmd64x,
7accbffd	368	.enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
30e5ffc3	369	.port_ops = &cmd648_port_ops,
5e71d9c5	370	.host_flags = IDE_HFLAG_ABUSE_PREFETCH,
4099d143	371	.pio_mask = ATA_PIO5,
5f8b6c34 BZ	372	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	373	.udma_mask = ATA_UDMA5,
1da177e4 LT	374	}
	375	};
	376
fe31edc8	377	static int cmd64x_init_one(struct pci_dev dev, const struct pci_device_id id)
1da177e4	378	{
039788e1	379	struct ide_port_info d;
bfd314a3 BZ	380	u8 idx = id->driver_data;
	381
	382	d = cmd64x_chipsets[idx];
	383
5e37bdc0 BZ	384	if (idx == 1) {
	385	/*
	386	* UltraDMA only supported on PCI646U and PCI646U2, which
	387	* correspond to revisions 0x03, 0x05 and 0x07 respectively.
	388	* Actually, although the CMD tech support people won't
	389	* tell me the details, the 0x03 revision cannot support
	390	* UDMA correctly without hardware modifications, and even
	391	* then it only works with Quantum disks due to some
	392	* hold time assumptions in the 646U part which are fixed
	393	* in the 646U2.
	394	*
	395	* So we only do UltraDMA on revision 0x05 and 0x07 chipsets.
	396	*/
	397	if (dev->revision < 5) {
	398	d.udma_mask = 0x00;
	399	/*
	400	* The original PCI0646 didn't have the primary
	401	* channel enable bit, it appeared starting with
	402	* PCI0646U (i.e. revision ID 3).
	403	*/
	404	if (dev->revision < 3) {
	405	d.enablebits[0].reg = 0;
30e5ffc3	406	d.port_ops = &cmd64x_port_ops;
5e37bdc0 BZ	407	if (dev->revision == 1)
5e37bdc0 BZ	408	d.dma_ops = &cmd646_rev1_dma_ops;
5e37bdc0 BZ	409	}
	410	}
	411	}
7accbffd	412
6cdf6eb3	413	return ide_pci_init_one(dev, &d, NULL);
1da177e4 LT	414	}
1da177e4 LT	415
9cbcc5e3 BZ	416	static const struct pci_device_id cmd64x_pci_tbl[] = {
	417	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 },
	418	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 },
	419	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 2 },
	420	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 3 },
1da177e4 LT	421	{ 0, },
	422	};
	423	MODULE_DEVICE_TABLE(pci, cmd64x_pci_tbl);
	424
a9ab09e2	425	static struct pci_driver cmd64x_pci_driver = {
1da177e4 LT	426	.name = "CMD64x_IDE",
	427	.id_table = cmd64x_pci_tbl,
	428	.probe = cmd64x_init_one,
e2b15b47	429	.remove = ide_pci_remove,
feb22b7f BZ	430	.suspend = ide_pci_suspend,
feb22b7f BZ	431	.resume = ide_pci_resume,
1da177e4 LT	432	};
1da177e4 LT	433
82ab1eec	434	static int __init cmd64x_ide_init(void)
1da177e4	435	{
a9ab09e2	436	return ide_pci_register_driver(&cmd64x_pci_driver);
1da177e4 LT	437	}
1da177e4 LT	438
e2b15b47 BZ	439	static void __exit cmd64x_ide_exit(void)
e2b15b47 BZ	440	{
a9ab09e2	441	pci_unregister_driver(&cmd64x_pci_driver);
e2b15b47 BZ	442	}
e2b15b47 BZ	443
1da177e4	444	module_init(cmd64x_ide_init);
e2b15b47	445	module_exit(cmd64x_ide_exit);
1da177e4	446
60349ab9	447	MODULE_AUTHOR("Eddie Dost, David Miller, Andre Hedrick, Bartlomiej Zolnierkiewicz");
1da177e4 LT	448	MODULE_DESCRIPTION("PCI driver module for CMD64x IDE");
1da177e4 LT	449	MODULE_LICENSE("GPL");