[linux-2.6-block.git] / drivers / ide / atiixp.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 *  Copyright (C) 2003 ATI Inc. <hyu@ati.com>
 *  Copyright (C) 2004,2007 Bartlomiej Zolnierkiewicz
 */

#include <linux/types.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/ide.h>
#include <linux/init.h>

#define DRV_NAME "atiixp"

#define ATIIXP_IDE_PIO_TIMING		0x40
#define ATIIXP_IDE_MDMA_TIMING		0x44
#define ATIIXP_IDE_PIO_CONTROL		0x48
#define ATIIXP_IDE_PIO_MODE		0x4a
#define ATIIXP_IDE_UDMA_CONTROL		0x54
#define ATIIXP_IDE_UDMA_MODE		0x56

struct atiixp_ide_timing {
	u8 command_width;
	u8 recover_width;
};

static struct atiixp_ide_timing pio_timing[] = {
	{ 0x05, 0x0d },
	{ 0x04, 0x07 },
	{ 0x03, 0x04 },
	{ 0x02, 0x02 },
	{ 0x02, 0x00 },
};

static struct atiixp_ide_timing mdma_timing[] = {
	{ 0x07, 0x07 },
	{ 0x02, 0x01 },
	{ 0x02, 0x00 },
};

static DEFINE_SPINLOCK(atiixp_lock);

/**
 *	atiixp_set_pio_mode	-	set host controller for PIO mode
 *	@hwif: port
 *	@drive: drive
 *
 *	Set the interface PIO mode.
 */

static void atiixp_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
{
	struct pci_dev *dev = to_pci_dev(hwif->dev);
	unsigned long flags;
	int timing_shift = (drive->dn ^ 1) * 8;
	u32 pio_timing_data;
	u16 pio_mode_data;
	const u8 pio = drive->pio_mode - XFER_PIO_0;

	spin_lock_irqsave(&atiixp_lock, flags);

	pci_read_config_word(dev, ATIIXP_IDE_PIO_MODE, &pio_mode_data);
	pio_mode_data &= ~(0x07 << (drive->dn * 4));
	pio_mode_data |= (pio << (drive->dn * 4));
	pci_write_config_word(dev, ATIIXP_IDE_PIO_MODE, pio_mode_data);

	pci_read_config_dword(dev, ATIIXP_IDE_PIO_TIMING, &pio_timing_data);
	pio_timing_data &= ~(0xff << timing_shift);
	pio_timing_data |= (pio_timing[pio].recover_width << timing_shift) |
		 (pio_timing[pio].command_width << (timing_shift + 4));
	pci_write_config_dword(dev, ATIIXP_IDE_PIO_TIMING, pio_timing_data);

	spin_unlock_irqrestore(&atiixp_lock, flags);
}

/**
 *	atiixp_set_dma_mode	-	set host controller for DMA mode
 *	@hwif: port
 *	@drive: drive
 *
 *	Set a ATIIXP host controller to the desired DMA mode.  This involves
 *	programming the right timing data into the PCI configuration space.
 */

static void atiixp_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
{
	struct pci_dev *dev = to_pci_dev(hwif->dev);
	unsigned long flags;
	int timing_shift = (drive->dn ^ 1) * 8;
	u32 tmp32;
	u16 tmp16;
	u16 udma_ctl = 0;
	const u8 speed = drive->dma_mode;

	spin_lock_irqsave(&atiixp_lock, flags);

	pci_read_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, &udma_ctl);

	if (speed >= XFER_UDMA_0) {
		pci_read_config_word(dev, ATIIXP_IDE_UDMA_MODE, &tmp16);
		tmp16 &= ~(0x07 << (drive->dn * 4));
		tmp16 |= ((speed & 0x07) << (drive->dn * 4));
		pci_write_config_word(dev, ATIIXP_IDE_UDMA_MODE, tmp16);

		udma_ctl |= (1 << drive->dn);
	} else if (speed >= XFER_MW_DMA_0) {
		u8 i = speed & 0x03;

		pci_read_config_dword(dev, ATIIXP_IDE_MDMA_TIMING, &tmp32);
		tmp32 &= ~(0xff << timing_shift);
		tmp32 |= (mdma_timing[i].recover_width << timing_shift) |
			 (mdma_timing[i].command_width << (timing_shift + 4));
		pci_write_config_dword(dev, ATIIXP_IDE_MDMA_TIMING, tmp32);

		udma_ctl &= ~(1 << drive->dn);
	}

	pci_write_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, udma_ctl);

	spin_unlock_irqrestore(&atiixp_lock, flags);
}

static u8 atiixp_cable_detect(ide_hwif_t *hwif)
{
	struct pci_dev *pdev = to_pci_dev(hwif->dev);
	u8 udma_mode = 0, ch = hwif->channel;

	pci_read_config_byte(pdev, ATIIXP_IDE_UDMA_MODE + ch, &udma_mode);

	if ((udma_mode & 0x07) >= 0x04 || (udma_mode & 0x70) >= 0x40)
		return ATA_CBL_PATA80;
	else
		return ATA_CBL_PATA40;
}

static const struct ide_port_ops atiixp_port_ops = {
	.set_pio_mode		= atiixp_set_pio_mode,
	.set_dma_mode		= atiixp_set_dma_mode,
	.cable_detect		= atiixp_cable_detect,
};

static const struct ide_port_info atiixp_pci_info[] = {
	{	/* 0: IXP200/300/400/700 */
		.name		= DRV_NAME,
		.enablebits	= {{0x48,0x01,0x00}, {0x48,0x08,0x00}},
		.port_ops	= &atiixp_port_ops,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA5,
	},
	{	/* 1: IXP600 */
		.name		= DRV_NAME,
		.enablebits	= {{0x48,0x01,0x00}, {0x00,0x00,0x00}},
		.port_ops	= &atiixp_port_ops,
		.host_flags	= IDE_HFLAG_SINGLE,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA5,
 	},
};

/**
 *	atiixp_init_one	-	called when a ATIIXP is found
 *	@dev: the atiixp device
 *	@id: the matching pci id
 *
 *	Called when the PCI registration layer (or the IDE initialization)
 *	finds a device matching our IDE device tables.
 */

static int atiixp_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	return ide_pci_init_one(dev, &atiixp_pci_info[id->driver_data], NULL);
}

static const struct pci_device_id atiixp_pci_tbl[] = {
	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP200_IDE), 0 },
	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP300_IDE), 0 },
	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP400_IDE), 0 },
	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP600_IDE), 1 },
	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP700_IDE), 0 },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_HUDSON2_IDE), 0 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, atiixp_pci_tbl);

static struct pci_driver atiixp_pci_driver = {
	.name		= "ATIIXP_IDE",
	.id_table	= atiixp_pci_tbl,
	.probe		= atiixp_init_one,
	.remove		= ide_pci_remove,
	.suspend	= ide_pci_suspend,
	.resume		= ide_pci_resume,
};

static int __init atiixp_ide_init(void)
{
	return ide_pci_register_driver(&atiixp_pci_driver);
}

static void __exit atiixp_ide_exit(void)
{
	pci_unregister_driver(&atiixp_pci_driver);
}

module_init(atiixp_ide_init);
module_exit(atiixp_ide_exit);

MODULE_AUTHOR("HUI YU");
MODULE_DESCRIPTION("PCI driver module for ATI IXP IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
09c434b8	1	// SPDX-License-Identifier: GPL-2.0-only
1da177e4	2	/*
1da177e4	3	* Copyright (C) 2003 ATI Inc. <hyu@ati.com>
485efc6c	4	* Copyright (C) 2004,2007 Bartlomiej Zolnierkiewicz
1da177e4 LT	5	*/
1da177e4 LT	6
1da177e4 LT	7	#include <linux/types.h>
	8	#include <linux/module.h>
	9	#include <linux/kernel.h>
1da177e4	10	#include <linux/pci.h>
1da177e4	11	#include <linux/ide.h>
1da177e4 LT	12	#include <linux/init.h>
1da177e4 LT	13
ced3ec8a BZ	14	#define DRV_NAME "atiixp"
ced3ec8a BZ	15
1da177e4 LT	16	#define ATIIXP_IDE_PIO_TIMING 0x40
	17	#define ATIIXP_IDE_MDMA_TIMING 0x44
	18	#define ATIIXP_IDE_PIO_CONTROL 0x48
	19	#define ATIIXP_IDE_PIO_MODE 0x4a
	20	#define ATIIXP_IDE_UDMA_CONTROL 0x54
	21	#define ATIIXP_IDE_UDMA_MODE 0x56
	22
7546e52b	23	struct atiixp_ide_timing {
1da177e4 LT	24	u8 command_width;
1da177e4 LT	25	u8 recover_width;
7546e52b	26	};
1da177e4	27
7546e52b	28	static struct atiixp_ide_timing pio_timing[] = {
1da177e4 LT	29	{ 0x05, 0x0d },
	30	{ 0x04, 0x07 },
	31	{ 0x03, 0x04 },
	32	{ 0x02, 0x02 },
	33	{ 0x02, 0x00 },
	34	};
	35
7546e52b	36	static struct atiixp_ide_timing mdma_timing[] = {
1da177e4 LT	37	{ 0x07, 0x07 },
	38	{ 0x02, 0x01 },
	39	{ 0x02, 0x00 },
	40	};
	41
6c5f8cc3 A	42	static DEFINE_SPINLOCK(atiixp_lock);
6c5f8cc3 A	43
1da177e4	44	/**
88b2b32b	45	* atiixp_set_pio_mode - set host controller for PIO mode
e085b3ca	46	* @hwif: port
88b2b32b	47	* @drive: drive
1da177e4 LT	48	*
	49	* Set the interface PIO mode.
	50	*/
	51
e085b3ca	52	static void atiixp_set_pio_mode(ide_hwif_t hwif, ide_drive_t drive)
1da177e4	53	{
e085b3ca	54	struct pci_dev *dev = to_pci_dev(hwif->dev);
1da177e4	55	unsigned long flags;
f76bee16	56	int timing_shift = (drive->dn ^ 1) * 8;
1da177e4 LT	57	u32 pio_timing_data;
1da177e4 LT	58	u16 pio_mode_data;
e085b3ca	59	const u8 pio = drive->pio_mode - XFER_PIO_0;
1da177e4	60
6c5f8cc3	61	spin_lock_irqsave(&atiixp_lock, flags);
1da177e4 LT	62
	63	pci_read_config_word(dev, ATIIXP_IDE_PIO_MODE, &pio_mode_data);
	64	pio_mode_data &= ~(0x07 << (drive->dn * 4));
	65	pio_mode_data \|= (pio << (drive->dn * 4));
	66	pci_write_config_word(dev, ATIIXP_IDE_PIO_MODE, pio_mode_data);
	67
	68	pci_read_config_dword(dev, ATIIXP_IDE_PIO_TIMING, &pio_timing_data);
	69	pio_timing_data &= ~(0xff << timing_shift);
	70	pio_timing_data \|= (pio_timing[pio].recover_width << timing_shift) \|
	71	(pio_timing[pio].command_width << (timing_shift + 4));
	72	pci_write_config_dword(dev, ATIIXP_IDE_PIO_TIMING, pio_timing_data);
	73
6c5f8cc3	74	spin_unlock_irqrestore(&atiixp_lock, flags);
1da177e4 LT	75	}
	76
	77	/**
88b2b32b	78	* atiixp_set_dma_mode - set host controller for DMA mode
8776168c	79	* @hwif: port
88b2b32b	80	* @drive: drive
1da177e4	81	*
88b2b32b BZ	82	* Set a ATIIXP host controller to the desired DMA mode. This involves
88b2b32b BZ	83	* programming the right timing data into the PCI configuration space.
1da177e4 LT	84	*/
1da177e4 LT	85
8776168c	86	static void atiixp_set_dma_mode(ide_hwif_t hwif, ide_drive_t drive)
1da177e4	87	{
8776168c	88	struct pci_dev *dev = to_pci_dev(hwif->dev);
1da177e4	89	unsigned long flags;
f76bee16	90	int timing_shift = (drive->dn ^ 1) * 8;
1da177e4 LT	91	u32 tmp32;
1da177e4 LT	92	u16 tmp16;
8ae60e34	93	u16 udma_ctl = 0;
8776168c	94	const u8 speed = drive->dma_mode;
94c7fa0f	95
6c5f8cc3	96	spin_lock_irqsave(&atiixp_lock, flags);
1da177e4	97
8ae60e34 BZ	98	pci_read_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, &udma_ctl);
8ae60e34 BZ	99
1da177e4 LT	100	if (speed >= XFER_UDMA_0) {
	101	pci_read_config_word(dev, ATIIXP_IDE_UDMA_MODE, &tmp16);
	102	tmp16 &= ~(0x07 << (drive->dn * 4));
	103	tmp16 \|= ((speed & 0x07) << (drive->dn * 4));
	104	pci_write_config_word(dev, ATIIXP_IDE_UDMA_MODE, tmp16);
8ae60e34 BZ	105
	106	udma_ctl \|= (1 << drive->dn);
	107	} else if (speed >= XFER_MW_DMA_0) {
	108	u8 i = speed & 0x03;
	109
	110	pci_read_config_dword(dev, ATIIXP_IDE_MDMA_TIMING, &tmp32);
	111	tmp32 &= ~(0xff << timing_shift);
	112	tmp32 \|= (mdma_timing[i].recover_width << timing_shift) \|
	113	(mdma_timing[i].command_width << (timing_shift + 4));
	114	pci_write_config_dword(dev, ATIIXP_IDE_MDMA_TIMING, tmp32);
	115
	116	udma_ctl &= ~(1 << drive->dn);
1da177e4 LT	117	}
1da177e4 LT	118
8ae60e34 BZ	119	pci_write_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, udma_ctl);
8ae60e34 BZ	120
6c5f8cc3	121	spin_unlock_irqrestore(&atiixp_lock, flags);
1da177e4 LT	122	}
1da177e4 LT	123
f454cbe8	124	static u8 atiixp_cable_detect(ide_hwif_t *hwif)
b4d1c73d BZ	125	{
	126	struct pci_dev *pdev = to_pci_dev(hwif->dev);
	127	u8 udma_mode = 0, ch = hwif->channel;
	128
	129	pci_read_config_byte(pdev, ATIIXP_IDE_UDMA_MODE + ch, &udma_mode);
	130
	131	if ((udma_mode & 0x07) >= 0x04 \|\| (udma_mode & 0x70) >= 0x40)
	132	return ATA_CBL_PATA80;
	133	else
	134	return ATA_CBL_PATA40;
	135	}
	136
ac95beed BZ	137	static const struct ide_port_ops atiixp_port_ops = {
	138	.set_pio_mode = atiixp_set_pio_mode,
	139	.set_dma_mode = atiixp_set_dma_mode,
	140	.cable_detect = atiixp_cable_detect,
	141	};
1da177e4	142
fe31edc8	143	static const struct ide_port_info atiixp_pci_info[] = {
ced3ec8a BZ	144	{ /* 0: IXP200/300/400/700 */
ced3ec8a BZ	145	.name = DRV_NAME,
1da177e4	146	.enablebits = {{0x48,0x01,0x00}, {0x48,0x08,0x00}},
ac95beed	147	.port_ops = &atiixp_port_ops,
4099d143	148	.pio_mask = ATA_PIO4,
5f8b6c34 BZ	149	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	150	.udma_mask = ATA_UDMA5,
ced3ec8a BZ	151	},
	152	{ /* 1: IXP600 */
	153	.name = DRV_NAME,
b25168df	154	.enablebits = {{0x48,0x01,0x00}, {0x00,0x00,0x00}},
ac95beed	155	.port_ops = &atiixp_port_ops,
2467922a	156	.host_flags = IDE_HFLAG_SINGLE,
4099d143	157	.pio_mask = ATA_PIO4,
5f8b6c34 BZ	158	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	159	.udma_mask = ATA_UDMA5,
b25168df	160	},
1da177e4 LT	161	};
	162
	163	/**
	164	* atiixp_init_one - called when a ATIIXP is found
	165	* @dev: the atiixp device
	166	* @id: the matching pci id
	167	*
	168	* Called when the PCI registration layer (or the IDE initialization)
	169	* finds a device matching our IDE device tables.
	170	*/
	171
fe31edc8	172	static int atiixp_init_one(struct pci_dev dev, const struct pci_device_id id)
1da177e4	173	{
6cdf6eb3	174	return ide_pci_init_one(dev, &atiixp_pci_info[id->driver_data], NULL);
1da177e4 LT	175	}
1da177e4 LT	176
9cbcc5e3 BZ	177	static const struct pci_device_id atiixp_pci_tbl[] = {
	178	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP200_IDE), 0 },
	179	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP300_IDE), 0 },
	180	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP400_IDE), 0 },
	181	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP600_IDE), 1 },
	182	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP700_IDE), 0 },
5deab536	183	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_HUDSON2_IDE), 0 },
1da177e4 LT	184	{ 0, },
	185	};
	186	MODULE_DEVICE_TABLE(pci, atiixp_pci_tbl);
	187
a9ab09e2	188	static struct pci_driver atiixp_pci_driver = {
1da177e4 LT	189	.name = "ATIIXP_IDE",
	190	.id_table = atiixp_pci_tbl,
	191	.probe = atiixp_init_one,
f354fbc4	192	.remove = ide_pci_remove,
feb22b7f BZ	193	.suspend = ide_pci_suspend,
feb22b7f BZ	194	.resume = ide_pci_resume,
1da177e4 LT	195	};
1da177e4 LT	196
82ab1eec	197	static int __init atiixp_ide_init(void)
1da177e4	198	{
a9ab09e2	199	return ide_pci_register_driver(&atiixp_pci_driver);
1da177e4 LT	200	}
1da177e4 LT	201
f354fbc4 BZ	202	static void __exit atiixp_ide_exit(void)
f354fbc4 BZ	203	{
a9ab09e2	204	pci_unregister_driver(&atiixp_pci_driver);
f354fbc4 BZ	205	}
f354fbc4 BZ	206
1da177e4	207	module_init(atiixp_ide_init);
f354fbc4	208	module_exit(atiixp_ide_exit);
1da177e4 LT	209
	210	MODULE_AUTHOR("HUI YU");
	211	MODULE_DESCRIPTION("PCI driver module for ATI IXP IDE");
	212	MODULE_LICENSE("GPL");