[linux-2.6-block.git] / drivers / ide / aec62xx.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 1999-2002	Andre Hedrick <andre@linux-ide.org>
 * Copyright (C) 2007		MontaVista Software, Inc. <source@mvista.com>
 *
 */

#include <linux/module.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/ide.h>
#include <linux/init.h>

#include <asm/io.h>

#define DRV_NAME "aec62xx"

struct chipset_bus_clock_list_entry {
	u8 xfer_speed;
	u8 chipset_settings;
	u8 ultra_settings;
};

static const struct chipset_bus_clock_list_entry aec6xxx_33_base [] = {
	{	XFER_UDMA_6,	0x31,	0x07	},
	{	XFER_UDMA_5,	0x31,	0x06	},
	{	XFER_UDMA_4,	0x31,	0x05	},
	{	XFER_UDMA_3,	0x31,	0x04	},
	{	XFER_UDMA_2,	0x31,	0x03	},
	{	XFER_UDMA_1,	0x31,	0x02	},
	{	XFER_UDMA_0,	0x31,	0x01	},

	{	XFER_MW_DMA_2,	0x31,	0x00	},
	{	XFER_MW_DMA_1,	0x31,	0x00	},
	{	XFER_MW_DMA_0,	0x0a,	0x00	},
	{	XFER_PIO_4,	0x31,	0x00	},
	{	XFER_PIO_3,	0x33,	0x00	},
	{	XFER_PIO_2,	0x08,	0x00	},
	{	XFER_PIO_1,	0x0a,	0x00	},
	{	XFER_PIO_0,	0x00,	0x00	},
	{	0,		0x00,	0x00	}
};

static const struct chipset_bus_clock_list_entry aec6xxx_34_base [] = {
	{	XFER_UDMA_6,	0x41,	0x06	},
	{	XFER_UDMA_5,	0x41,	0x05	},
	{	XFER_UDMA_4,	0x41,	0x04	},
	{	XFER_UDMA_3,	0x41,	0x03	},
	{	XFER_UDMA_2,	0x41,	0x02	},
	{	XFER_UDMA_1,	0x41,	0x01	},
	{	XFER_UDMA_0,	0x41,	0x01	},

	{	XFER_MW_DMA_2,	0x41,	0x00	},
	{	XFER_MW_DMA_1,	0x42,	0x00	},
	{	XFER_MW_DMA_0,	0x7a,	0x00	},
	{	XFER_PIO_4,	0x41,	0x00	},
	{	XFER_PIO_3,	0x43,	0x00	},
	{	XFER_PIO_2,	0x78,	0x00	},
	{	XFER_PIO_1,	0x7a,	0x00	},
	{	XFER_PIO_0,	0x70,	0x00	},
	{	0,		0x00,	0x00	}
};

/*
 * TO DO: active tuning and correction of cards without a bios.
 */
static u8 pci_bus_clock_list (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
{
	for ( ; chipset_table->xfer_speed ; chipset_table++)
		if (chipset_table->xfer_speed == speed) {
			return chipset_table->chipset_settings;
		}
	return chipset_table->chipset_settings;
}

static u8 pci_bus_clock_list_ultra (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
{
	for ( ; chipset_table->xfer_speed ; chipset_table++)
		if (chipset_table->xfer_speed == speed) {
			return chipset_table->ultra_settings;
		}
	return chipset_table->ultra_settings;
}

static void aec6210_set_mode(ide_hwif_t *hwif, ide_drive_t *drive)
{
	struct pci_dev *dev	= to_pci_dev(hwif->dev);
	struct ide_host *host	= pci_get_drvdata(dev);
	struct chipset_bus_clock_list_entry *bus_clock = host->host_priv;
	u16 d_conf		= 0;
	u8 ultra = 0, ultra_conf = 0;
	u8 tmp0 = 0, tmp1 = 0, tmp2 = 0;
	const u8 speed = drive->dma_mode;
	unsigned long flags;

	local_irq_save(flags);
	/* 0x40|(2*drive->dn): Active, 0x41|(2*drive->dn): Recovery */
	pci_read_config_word(dev, 0x40|(2*drive->dn), &d_conf);
	tmp0 = pci_bus_clock_list(speed, bus_clock);
	d_conf = ((tmp0 & 0xf0) << 4) | (tmp0 & 0xf);
	pci_write_config_word(dev, 0x40|(2*drive->dn), d_conf);

	tmp1 = 0x00;
	tmp2 = 0x00;
	pci_read_config_byte(dev, 0x54, &ultra);
	tmp1 = ((0x00 << (2*drive->dn)) | (ultra & ~(3 << (2*drive->dn))));
	ultra_conf = pci_bus_clock_list_ultra(speed, bus_clock);
	tmp2 = ((ultra_conf << (2*drive->dn)) | (tmp1 & ~(3 << (2*drive->dn))));
	pci_write_config_byte(dev, 0x54, tmp2);
	local_irq_restore(flags);
}

static void aec6260_set_mode(ide_hwif_t *hwif, ide_drive_t *drive)
{
	struct pci_dev *dev	= to_pci_dev(hwif->dev);
	struct ide_host *host	= pci_get_drvdata(dev);
	struct chipset_bus_clock_list_entry *bus_clock = host->host_priv;
	u8 unit			= drive->dn & 1;
	u8 tmp1 = 0, tmp2 = 0;
	u8 ultra = 0, drive_conf = 0, ultra_conf = 0;
	const u8 speed = drive->dma_mode;
	unsigned long flags;

	local_irq_save(flags);
	/* high 4-bits: Active, low 4-bits: Recovery */
	pci_read_config_byte(dev, 0x40|drive->dn, &drive_conf);
	drive_conf = pci_bus_clock_list(speed, bus_clock);
	pci_write_config_byte(dev, 0x40|drive->dn, drive_conf);

	pci_read_config_byte(dev, (0x44|hwif->channel), &ultra);
	tmp1 = ((0x00 << (4*unit)) | (ultra & ~(7 << (4*unit))));
	ultra_conf = pci_bus_clock_list_ultra(speed, bus_clock);
	tmp2 = ((ultra_conf << (4*unit)) | (tmp1 & ~(7 << (4*unit))));
	pci_write_config_byte(dev, (0x44|hwif->channel), tmp2);
	local_irq_restore(flags);
}

static void aec_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
{
	drive->dma_mode = drive->pio_mode;
	hwif->port_ops->set_dma_mode(hwif, drive);
}

static int init_chipset_aec62xx(struct pci_dev *dev)
{
	/* These are necessary to get AEC6280 Macintosh cards to work */
	if ((dev->device == PCI_DEVICE_ID_ARTOP_ATP865) ||
	    (dev->device == PCI_DEVICE_ID_ARTOP_ATP865R)) {
		u8 reg49h = 0, reg4ah = 0;
		/* Clear reset and test bits.  */
		pci_read_config_byte(dev, 0x49, &reg49h);
		pci_write_config_byte(dev, 0x49, reg49h & ~0x30);
		/* Enable chip interrupt output.  */
		pci_read_config_byte(dev, 0x4a, &reg4ah);
		pci_write_config_byte(dev, 0x4a, reg4ah & ~0x01);
		/* Enable burst mode. */
		pci_read_config_byte(dev, 0x4a, &reg4ah);
		pci_write_config_byte(dev, 0x4a, reg4ah | 0x80);
	}

	return 0;
}

static u8 atp86x_cable_detect(ide_hwif_t *hwif)
{
	struct pci_dev *dev = to_pci_dev(hwif->dev);
	u8 ata66 = 0, mask = hwif->channel ? 0x02 : 0x01;

	pci_read_config_byte(dev, 0x49, &ata66);

	return (ata66 & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
}

static const struct ide_port_ops atp850_port_ops = {
	.set_pio_mode		= aec_set_pio_mode,
	.set_dma_mode		= aec6210_set_mode,
};

static const struct ide_port_ops atp86x_port_ops = {
	.set_pio_mode		= aec_set_pio_mode,
	.set_dma_mode		= aec6260_set_mode,
	.cable_detect		= atp86x_cable_detect,
};

static const struct ide_port_info aec62xx_chipsets[] = {
	{	/* 0: AEC6210 */
		.name		= DRV_NAME,
		.init_chipset	= init_chipset_aec62xx,
		.enablebits	= {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
		.port_ops	= &atp850_port_ops,
		.host_flags	= IDE_HFLAG_SERIALIZE |
				  IDE_HFLAG_NO_ATAPI_DMA |
				  IDE_HFLAG_NO_DSC |
				  IDE_HFLAG_OFF_BOARD,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA2,
	},
	{	/* 1: AEC6260 */
		.name		= DRV_NAME,
		.init_chipset	= init_chipset_aec62xx,
		.port_ops	= &atp86x_port_ops,
		.host_flags	= IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_NO_AUTODMA |
				  IDE_HFLAG_OFF_BOARD,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA4,
	},
	{	/* 2: AEC6260R */
		.name		= DRV_NAME,
		.init_chipset	= init_chipset_aec62xx,
		.enablebits	= {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
		.port_ops	= &atp86x_port_ops,
		.host_flags	= IDE_HFLAG_NO_ATAPI_DMA |
				  IDE_HFLAG_NON_BOOTABLE,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA4,
	},
	{	/* 3: AEC6280 */
		.name		= DRV_NAME,
		.init_chipset	= init_chipset_aec62xx,
		.port_ops	= &atp86x_port_ops,
		.host_flags	= IDE_HFLAG_NO_ATAPI_DMA |
				  IDE_HFLAG_OFF_BOARD,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA5,
	},
	{	/* 4: AEC6280R */
		.name		= DRV_NAME,
		.init_chipset	= init_chipset_aec62xx,
		.enablebits	= {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
		.port_ops	= &atp86x_port_ops,
		.host_flags	= IDE_HFLAG_NO_ATAPI_DMA |
				  IDE_HFLAG_OFF_BOARD,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA5,
	}
};

/**
 *	aec62xx_init_one	-	called when a AEC is found
 *	@dev: the aec62xx device
 *	@id: the matching pci id
 *
 *	Called when the PCI registration layer (or the IDE initialization)
 *	finds a device matching our IDE device tables.
 *
 *	NOTE: since we're going to modify the 'name' field for AEC-6[26]80[R]
 *	chips, pass a local copy of 'struct ide_port_info' down the call chain.
 */

static int aec62xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	const struct chipset_bus_clock_list_entry *bus_clock;
	struct ide_port_info d;
	u8 idx = id->driver_data;
	int bus_speed = ide_pci_clk ? ide_pci_clk : 33;
	int err;

	if (bus_speed <= 33)
		bus_clock = aec6xxx_33_base;
	else
		bus_clock = aec6xxx_34_base;

	err = pci_enable_device(dev);
	if (err)
		return err;

	d = aec62xx_chipsets[idx];

	if (idx == 3 || idx == 4) {
		unsigned long dma_base = pci_resource_start(dev, 4);

		if (inb(dma_base + 2) & 0x10) {
			printk(KERN_INFO DRV_NAME " %s: AEC6880%s card detected"
				"\n", pci_name(dev), (idx == 4) ? "R" : "");
			d.udma_mask = ATA_UDMA6;
		}
	}

	err = ide_pci_init_one(dev, &d, (void *)bus_clock);
	if (err)
		pci_disable_device(dev);

	return err;
}

static void aec62xx_remove(struct pci_dev *dev)
{
	ide_pci_remove(dev);
	pci_disable_device(dev);
}

static const struct pci_device_id aec62xx_pci_tbl[] = {
	{ PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP850UF), 0 },
	{ PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP860),   1 },
	{ PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP860R),  2 },
	{ PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP865),   3 },
	{ PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP865R),  4 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, aec62xx_pci_tbl);

static struct pci_driver aec62xx_pci_driver = {
	.name		= "AEC62xx_IDE",
	.id_table	= aec62xx_pci_tbl,
	.probe		= aec62xx_init_one,
	.remove		= aec62xx_remove,
	.suspend	= ide_pci_suspend,
	.resume		= ide_pci_resume,
};

static int __init aec62xx_ide_init(void)
{
	return ide_pci_register_driver(&aec62xx_pci_driver);
}

static void __exit aec62xx_ide_exit(void)
{
	pci_unregister_driver(&aec62xx_pci_driver);
}

module_init(aec62xx_ide_init);
module_exit(aec62xx_ide_exit);

MODULE_AUTHOR("Andre Hedrick");
MODULE_DESCRIPTION("PCI driver module for ARTOP AEC62xx IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
09c434b8	1	// SPDX-License-Identifier: GPL-2.0-only
1da177e4	2	/*
1da177e4	3	* Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
826a1b65	4	* Copyright (C) 2007 MontaVista Software, Inc. <source@mvista.com>
1da177e4 LT	5	*
	6	*/
	7
	8	#include <linux/module.h>
1da177e4 LT	9	#include <linux/types.h>
1da177e4 LT	10	#include <linux/pci.h>
1da177e4 LT	11	#include <linux/ide.h>
	12	#include <linux/init.h>
	13
	14	#include <asm/io.h>
	15
ced3ec8a BZ	16	#define DRV_NAME "aec62xx"
ced3ec8a BZ	17
1da177e4 LT	18	struct chipset_bus_clock_list_entry {
	19	u8 xfer_speed;
	20	u8 chipset_settings;
	21	u8 ultra_settings;
	22	};
	23
f201f504	24	static const struct chipset_bus_clock_list_entry aec6xxx_33_base [] = {
1da177e4 LT	25	{ XFER_UDMA_6, 0x31, 0x07 },
	26	{ XFER_UDMA_5, 0x31, 0x06 },
	27	{ XFER_UDMA_4, 0x31, 0x05 },
	28	{ XFER_UDMA_3, 0x31, 0x04 },
	29	{ XFER_UDMA_2, 0x31, 0x03 },
	30	{ XFER_UDMA_1, 0x31, 0x02 },
	31	{ XFER_UDMA_0, 0x31, 0x01 },
	32
	33	{ XFER_MW_DMA_2, 0x31, 0x00 },
	34	{ XFER_MW_DMA_1, 0x31, 0x00 },
	35	{ XFER_MW_DMA_0, 0x0a, 0x00 },
	36	{ XFER_PIO_4, 0x31, 0x00 },
	37	{ XFER_PIO_3, 0x33, 0x00 },
	38	{ XFER_PIO_2, 0x08, 0x00 },
	39	{ XFER_PIO_1, 0x0a, 0x00 },
	40	{ XFER_PIO_0, 0x00, 0x00 },
	41	{ 0, 0x00, 0x00 }
	42	};
	43
f201f504	44	static const struct chipset_bus_clock_list_entry aec6xxx_34_base [] = {
1da177e4 LT	45	{ XFER_UDMA_6, 0x41, 0x06 },
	46	{ XFER_UDMA_5, 0x41, 0x05 },
	47	{ XFER_UDMA_4, 0x41, 0x04 },
	48	{ XFER_UDMA_3, 0x41, 0x03 },
	49	{ XFER_UDMA_2, 0x41, 0x02 },
	50	{ XFER_UDMA_1, 0x41, 0x01 },
	51	{ XFER_UDMA_0, 0x41, 0x01 },
	52
	53	{ XFER_MW_DMA_2, 0x41, 0x00 },
	54	{ XFER_MW_DMA_1, 0x42, 0x00 },
	55	{ XFER_MW_DMA_0, 0x7a, 0x00 },
	56	{ XFER_PIO_4, 0x41, 0x00 },
	57	{ XFER_PIO_3, 0x43, 0x00 },
	58	{ XFER_PIO_2, 0x78, 0x00 },
	59	{ XFER_PIO_1, 0x7a, 0x00 },
	60	{ XFER_PIO_0, 0x70, 0x00 },
	61	{ 0, 0x00, 0x00 }
	62	};
	63
1da177e4 LT	64	/*
	65	* TO DO: active tuning and correction of cards without a bios.
	66	*/
	67	static u8 pci_bus_clock_list (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
	68	{
	69	for ( ; chipset_table->xfer_speed ; chipset_table++)
	70	if (chipset_table->xfer_speed == speed) {
	71	return chipset_table->chipset_settings;
	72	}
	73	return chipset_table->chipset_settings;
	74	}
	75
	76	static u8 pci_bus_clock_list_ultra (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
	77	{
	78	for ( ; chipset_table->xfer_speed ; chipset_table++)
	79	if (chipset_table->xfer_speed == speed) {
	80	return chipset_table->ultra_settings;
	81	}
	82	return chipset_table->ultra_settings;
	83	}
	84
8776168c	85	static void aec6210_set_mode(ide_hwif_t hwif, ide_drive_t drive)
1da177e4	86	{
36501650	87	struct pci_dev *dev = to_pci_dev(hwif->dev);
60e57ed7 BZ	88	struct ide_host *host = pci_get_drvdata(dev);
60e57ed7 BZ	89	struct chipset_bus_clock_list_entry *bus_clock = host->host_priv;
1da177e4	90	u16 d_conf = 0;
1da177e4 LT	91	u8 ultra = 0, ultra_conf = 0;
1da177e4 LT	92	u8 tmp0 = 0, tmp1 = 0, tmp2 = 0;
8776168c	93	const u8 speed = drive->dma_mode;
1da177e4 LT	94	unsigned long flags;
	95
	96	local_irq_save(flags);
	97	/* 0x40\|(2drive->dn): Active, 0x41\|(2drive->dn): Recovery */
	98	pci_read_config_word(dev, 0x40\|(2*drive->dn), &d_conf);
60e57ed7	99	tmp0 = pci_bus_clock_list(speed, bus_clock);
1da177e4 LT	100	d_conf = ((tmp0 & 0xf0) << 4) \| (tmp0 & 0xf);
	101	pci_write_config_word(dev, 0x40\|(2*drive->dn), d_conf);
	102
	103	tmp1 = 0x00;
	104	tmp2 = 0x00;
	105	pci_read_config_byte(dev, 0x54, &ultra);
	106	tmp1 = ((0x00 << (2drive->dn)) \| (ultra & ~(3 << (2drive->dn))));
60e57ed7	107	ultra_conf = pci_bus_clock_list_ultra(speed, bus_clock);
1da177e4 LT	108	tmp2 = ((ultra_conf << (2drive->dn)) \| (tmp1 & ~(3 << (2drive->dn))));
	109	pci_write_config_byte(dev, 0x54, tmp2);
	110	local_irq_restore(flags);
1da177e4 LT	111	}
1da177e4 LT	112
8776168c	113	static void aec6260_set_mode(ide_hwif_t hwif, ide_drive_t drive)
1da177e4	114	{
36501650	115	struct pci_dev *dev = to_pci_dev(hwif->dev);
60e57ed7 BZ	116	struct ide_host *host = pci_get_drvdata(dev);
60e57ed7 BZ	117	struct chipset_bus_clock_list_entry *bus_clock = host->host_priv;
123995b9	118	u8 unit = drive->dn & 1;
1da177e4 LT	119	u8 tmp1 = 0, tmp2 = 0;
1da177e4 LT	120	u8 ultra = 0, drive_conf = 0, ultra_conf = 0;
8776168c	121	const u8 speed = drive->dma_mode;
1da177e4 LT	122	unsigned long flags;
	123
	124	local_irq_save(flags);
	125	/* high 4-bits: Active, low 4-bits: Recovery */
	126	pci_read_config_byte(dev, 0x40\|drive->dn, &drive_conf);
60e57ed7	127	drive_conf = pci_bus_clock_list(speed, bus_clock);
1da177e4 LT	128	pci_write_config_byte(dev, 0x40\|drive->dn, drive_conf);
	129
	130	pci_read_config_byte(dev, (0x44\|hwif->channel), &ultra);
	131	tmp1 = ((0x00 << (4unit)) \| (ultra & ~(7 << (4unit))));
60e57ed7	132	ultra_conf = pci_bus_clock_list_ultra(speed, bus_clock);
1da177e4 LT	133	tmp2 = ((ultra_conf << (4unit)) \| (tmp1 & ~(7 << (4unit))));
	134	pci_write_config_byte(dev, (0x44\|hwif->channel), tmp2);
	135	local_irq_restore(flags);
1da177e4 LT	136	}
1da177e4 LT	137
e085b3ca	138	static void aec_set_pio_mode(ide_hwif_t hwif, ide_drive_t drive)
1da177e4	139	{
e085b3ca	140	drive->dma_mode = drive->pio_mode;
8776168c	141	hwif->port_ops->set_dma_mode(hwif, drive);
1da177e4 LT	142	}
1da177e4 LT	143
2ed0ef54	144	static int init_chipset_aec62xx(struct pci_dev *dev)
1da177e4	145	{
d237bf49 TV	146	/* These are necessary to get AEC6280 Macintosh cards to work */
	147	if ((dev->device == PCI_DEVICE_ID_ARTOP_ATP865) \|\|
	148	(dev->device == PCI_DEVICE_ID_ARTOP_ATP865R)) {
	149	u8 reg49h = 0, reg4ah = 0;
	150	/* Clear reset and test bits. */
	151	pci_read_config_byte(dev, 0x49, &reg49h);
	152	pci_write_config_byte(dev, 0x49, reg49h & ~0x30);
	153	/* Enable chip interrupt output. */
	154	pci_read_config_byte(dev, 0x4a, &reg4ah);
	155	pci_write_config_byte(dev, 0x4a, reg4ah & ~0x01);
	156	/* Enable burst mode. */
	157	pci_read_config_byte(dev, 0x4a, &reg4ah);
	158	pci_write_config_byte(dev, 0x4a, reg4ah \| 0x80);
	159	}
	160
2ed0ef54	161	return 0;
1da177e4 LT	162	}
1da177e4 LT	163
f454cbe8	164	static u8 atp86x_cable_detect(ide_hwif_t *hwif)
bfa14b42 BZ	165	{
	166	struct pci_dev *dev = to_pci_dev(hwif->dev);
	167	u8 ata66 = 0, mask = hwif->channel ? 0x02 : 0x01;
	168
	169	pci_read_config_byte(dev, 0x49, &ata66);
	170
	171	return (ata66 & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
	172	}
	173
ac95beed BZ	174	static const struct ide_port_ops atp850_port_ops = {
	175	.set_pio_mode = aec_set_pio_mode,
	176	.set_dma_mode = aec6210_set_mode,
	177	};
1da177e4	178
ac95beed BZ	179	static const struct ide_port_ops atp86x_port_ops = {
	180	.set_pio_mode = aec_set_pio_mode,
	181	.set_dma_mode = aec6260_set_mode,
	182	.cable_detect = atp86x_cable_detect,
	183	};
1da177e4	184
fe31edc8	185	static const struct ide_port_info aec62xx_chipsets[] = {
ced3ec8a BZ	186	{ /* 0: AEC6210 */
ced3ec8a BZ	187	.name = DRV_NAME,
1da177e4	188	.init_chipset = init_chipset_aec62xx,
1da177e4	189	.enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
ac95beed	190	.port_ops = &atp850_port_ops,
1c51361a BZ	191	.host_flags = IDE_HFLAG_SERIALIZE \|
1c51361a BZ	192	IDE_HFLAG_NO_ATAPI_DMA \|
4166c199	193	IDE_HFLAG_NO_DSC \|
1c51361a	194	IDE_HFLAG_OFF_BOARD,
4099d143	195	.pio_mask = ATA_PIO4,
5f8b6c34 BZ	196	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	197	.udma_mask = ATA_UDMA2,
ced3ec8a BZ	198	},
	199	{ /* 1: AEC6260 */
	200	.name = DRV_NAME,
1da177e4	201	.init_chipset = init_chipset_aec62xx,
ac95beed	202	.port_ops = &atp86x_port_ops,
47b68788 BZ	203	.host_flags = IDE_HFLAG_NO_ATAPI_DMA \| IDE_HFLAG_NO_AUTODMA \|
47b68788 BZ	204	IDE_HFLAG_OFF_BOARD,
4099d143	205	.pio_mask = ATA_PIO4,
5f8b6c34 BZ	206	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	207	.udma_mask = ATA_UDMA4,
ced3ec8a BZ	208	},
	209	{ /* 2: AEC6260R */
	210	.name = DRV_NAME,
1da177e4	211	.init_chipset = init_chipset_aec62xx,
1da177e4	212	.enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
ac95beed	213	.port_ops = &atp86x_port_ops,
4db90a14	214	.host_flags = IDE_HFLAG_NO_ATAPI_DMA \|
5e71d9c5	215	IDE_HFLAG_NON_BOOTABLE,
4099d143	216	.pio_mask = ATA_PIO4,
5f8b6c34 BZ	217	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	218	.udma_mask = ATA_UDMA4,
ced3ec8a BZ	219	},
	220	{ /* 3: AEC6280 */
	221	.name = DRV_NAME,
1da177e4	222	.init_chipset = init_chipset_aec62xx,
ac95beed	223	.port_ops = &atp86x_port_ops,
4db90a14	224	.host_flags = IDE_HFLAG_NO_ATAPI_DMA \|
4db90a14	225	IDE_HFLAG_OFF_BOARD,
4099d143	226	.pio_mask = ATA_PIO4,
5f8b6c34 BZ	227	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	228	.udma_mask = ATA_UDMA5,
ced3ec8a BZ	229	},
	230	{ /* 4: AEC6280R */
	231	.name = DRV_NAME,
1da177e4	232	.init_chipset = init_chipset_aec62xx,
1da177e4	233	.enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
ac95beed	234	.port_ops = &atp86x_port_ops,
4db90a14	235	.host_flags = IDE_HFLAG_NO_ATAPI_DMA \|
4db90a14	236	IDE_HFLAG_OFF_BOARD,
4099d143	237	.pio_mask = ATA_PIO4,
5f8b6c34 BZ	238	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	239	.udma_mask = ATA_UDMA5,
1da177e4 LT	240	}
	241	};
	242
	243	/**
	244	* aec62xx_init_one - called when a AEC is found
	245	* @dev: the aec62xx device
	246	* @id: the matching pci id
	247	*
	248	* Called when the PCI registration layer (or the IDE initialization)
	249	* finds a device matching our IDE device tables.
b1d19db4 SS	250	*
b1d19db4 SS	251	* NOTE: since we're going to modify the 'name' field for AEC-6[26]80[R]
039788e1	252	* chips, pass a local copy of 'struct ide_port_info' down the call chain.
1da177e4	253	*/
039788e1	254
fe31edc8	255	static int aec62xx_init_one(struct pci_dev dev, const struct pci_device_id id)
1da177e4	256	{
60e57ed7	257	const struct chipset_bus_clock_list_entry *bus_clock;
039788e1	258	struct ide_port_info d;
df95f5ab	259	u8 idx = id->driver_data;
60e57ed7	260	int bus_speed = ide_pci_clk ? ide_pci_clk : 33;
b48d0817 AR	261	int err;
b48d0817 AR	262
60e57ed7 BZ	263	if (bus_speed <= 33)
	264	bus_clock = aec6xxx_33_base;
	265	else
	266	bus_clock = aec6xxx_34_base;
	267
b48d0817 AR	268	err = pci_enable_device(dev);
	269	if (err)
	270	return err;
df95f5ab BZ	271
	272	d = aec62xx_chipsets[idx];
	273
	274	if (idx == 3 \|\| idx == 4) {
	275	unsigned long dma_base = pci_resource_start(dev, 4);
	276
	277	if (inb(dma_base + 2) & 0x10) {
ced3ec8a BZ	278	printk(KERN_INFO DRV_NAME " %s: AEC6880%s card detected"
ced3ec8a BZ	279	"\n", pci_name(dev), (idx == 4) ? "R" : "");
df95f5ab BZ	280	d.udma_mask = ATA_UDMA6;
	281	}
	282	}
1da177e4	283
60e57ed7	284	err = ide_pci_init_one(dev, &d, (void *)bus_clock);
b48d0817 AR	285	if (err)
	286	pci_disable_device(dev);
	287
	288	return err;
1da177e4 LT	289	}
1da177e4 LT	290
fe31edc8	291	static void aec62xx_remove(struct pci_dev *dev)
eb7cb98b BZ	292	{
	293	ide_pci_remove(dev);
	294	pci_disable_device(dev);
	295	}
	296
9cbcc5e3 BZ	297	static const struct pci_device_id aec62xx_pci_tbl[] = {
	298	{ PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP850UF), 0 },
	299	{ PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP860), 1 },
	300	{ PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP860R), 2 },
	301	{ PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP865), 3 },
	302	{ PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP865R), 4 },
1da177e4 LT	303	{ 0, },
	304	};
	305	MODULE_DEVICE_TABLE(pci, aec62xx_pci_tbl);
	306
a9ab09e2	307	static struct pci_driver aec62xx_pci_driver = {
1da177e4 LT	308	.name = "AEC62xx_IDE",
	309	.id_table = aec62xx_pci_tbl,
	310	.probe = aec62xx_init_one,
fe31edc8	311	.remove = aec62xx_remove,
feb22b7f BZ	312	.suspend = ide_pci_suspend,
feb22b7f BZ	313	.resume = ide_pci_resume,
1da177e4 LT	314	};
1da177e4 LT	315
82ab1eec	316	static int __init aec62xx_ide_init(void)
1da177e4	317	{
a9ab09e2	318	return ide_pci_register_driver(&aec62xx_pci_driver);
1da177e4 LT	319	}
1da177e4 LT	320
eb7cb98b BZ	321	static void __exit aec62xx_ide_exit(void)
eb7cb98b BZ	322	{
a9ab09e2	323	pci_unregister_driver(&aec62xx_pci_driver);
eb7cb98b BZ	324	}
eb7cb98b BZ	325
1da177e4	326	module_init(aec62xx_ide_init);
eb7cb98b	327	module_exit(aec62xx_ide_exit);
1da177e4 LT	328
	329	MODULE_AUTHOR("Andre Hedrick");
	330	MODULE_DESCRIPTION("PCI driver module for ARTOP AEC62xx IDE");
	331	MODULE_LICENSE("GPL");