Commit | Line | Data |
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401c3434 GR |
1 | /* |
2 | * Copyright 2011, Netlogic Microsystems Inc. | |
3 | * Copyright 2004, Matt Porter <mporter@kernel.crashing.org> | |
4 | * | |
5 | * This file is licensed under the terms of the GNU General Public | |
6 | * License version 2. This program is licensed "as is" without any | |
7 | * warranty of any kind, whether express or implied. | |
8 | */ | |
9 | ||
84dbf809 | 10 | #include <linux/err.h> |
401c3434 GR |
11 | #include <linux/kernel.h> |
12 | #include <linux/module.h> | |
13 | #include <linux/slab.h> | |
401c3434 GR |
14 | #include <linux/ioport.h> |
15 | #include <linux/delay.h> | |
16 | #include <linux/errno.h> | |
17 | #include <linux/i2c.h> | |
18 | #include <linux/io.h> | |
19 | #include <linux/platform_device.h> | |
75d31c23 MR |
20 | #include <linux/of_device.h> |
21 | #include <linux/clk.h> | |
5398b7ef MR |
22 | #include <linux/interrupt.h> |
23 | #include <linux/wait.h> | |
401c3434 GR |
24 | |
25 | /* XLR I2C REGISTERS */ | |
26 | #define XLR_I2C_CFG 0x00 | |
27 | #define XLR_I2C_CLKDIV 0x01 | |
28 | #define XLR_I2C_DEVADDR 0x02 | |
29 | #define XLR_I2C_ADDR 0x03 | |
30 | #define XLR_I2C_DATAOUT 0x04 | |
31 | #define XLR_I2C_DATAIN 0x05 | |
32 | #define XLR_I2C_STATUS 0x06 | |
33 | #define XLR_I2C_STARTXFR 0x07 | |
34 | #define XLR_I2C_BYTECNT 0x08 | |
35 | #define XLR_I2C_HDSTATIM 0x09 | |
36 | ||
5398b7ef MR |
37 | /* Sigma Designs additional registers */ |
38 | #define XLR_I2C_INT_EN 0x09 | |
39 | #define XLR_I2C_INT_STAT 0x0a | |
40 | ||
401c3434 GR |
41 | /* XLR I2C REGISTERS FLAGS */ |
42 | #define XLR_I2C_BUS_BUSY 0x01 | |
43 | #define XLR_I2C_SDOEMPTY 0x02 | |
44 | #define XLR_I2C_RXRDY 0x04 | |
45 | #define XLR_I2C_ACK_ERR 0x08 | |
46 | #define XLR_I2C_ARB_STARTERR 0x30 | |
47 | ||
48 | /* Register Values */ | |
49 | #define XLR_I2C_CFG_ADDR 0xF8 | |
50 | #define XLR_I2C_CFG_NOADDR 0xFA | |
51 | #define XLR_I2C_STARTXFR_ND 0x02 /* No Data */ | |
52 | #define XLR_I2C_STARTXFR_RD 0x01 /* Read */ | |
53 | #define XLR_I2C_STARTXFR_WR 0x00 /* Write */ | |
54 | ||
55 | #define XLR_I2C_TIMEOUT 10 /* timeout per byte in msec */ | |
56 | ||
57 | /* | |
58 | * On XLR/XLS, we need to use __raw_ IO to read the I2C registers | |
59 | * because they are in the big-endian MMIO area on the SoC. | |
60 | * | |
61 | * The readl/writel implementation on XLR/XLS byteswaps, because | |
62 | * those are for its little-endian PCI space (see arch/mips/Kconfig). | |
63 | */ | |
64 | static inline void xlr_i2c_wreg(u32 __iomem *base, unsigned int reg, u32 val) | |
65 | { | |
66 | __raw_writel(val, base + reg); | |
67 | } | |
68 | ||
69 | static inline u32 xlr_i2c_rdreg(u32 __iomem *base, unsigned int reg) | |
70 | { | |
71 | return __raw_readl(base + reg); | |
72 | } | |
73 | ||
5398b7ef MR |
74 | #define XLR_I2C_FLAG_IRQ 1 |
75 | ||
75d31c23 | 76 | struct xlr_i2c_config { |
5398b7ef | 77 | u32 flags; /* optional feature support */ |
75d31c23 MR |
78 | u32 status_busy; /* value of STATUS[0] when busy */ |
79 | u32 cfg_extra; /* extra CFG bits to set */ | |
80 | }; | |
81 | ||
401c3434 GR |
82 | struct xlr_i2c_private { |
83 | struct i2c_adapter adap; | |
84 | u32 __iomem *iobase; | |
5398b7ef MR |
85 | int irq; |
86 | int pos; | |
87 | struct i2c_msg *msg; | |
75d31c23 | 88 | const struct xlr_i2c_config *cfg; |
5398b7ef | 89 | wait_queue_head_t wait; |
75d31c23 | 90 | struct clk *clk; |
401c3434 GR |
91 | }; |
92 | ||
75d31c23 MR |
93 | static int xlr_i2c_busy(struct xlr_i2c_private *priv, u32 status) |
94 | { | |
95 | return (status & XLR_I2C_BUS_BUSY) == priv->cfg->status_busy; | |
96 | } | |
97 | ||
5398b7ef MR |
98 | static int xlr_i2c_idle(struct xlr_i2c_private *priv) |
99 | { | |
100 | return !xlr_i2c_busy(priv, xlr_i2c_rdreg(priv->iobase, XLR_I2C_STATUS)); | |
101 | } | |
102 | ||
103 | static int xlr_i2c_wait(struct xlr_i2c_private *priv, unsigned long timeout) | |
104 | { | |
105 | int status; | |
106 | int t; | |
107 | ||
108 | t = wait_event_timeout(priv->wait, xlr_i2c_idle(priv), | |
109 | msecs_to_jiffies(timeout)); | |
110 | if (!t) | |
111 | return -ETIMEDOUT; | |
112 | ||
113 | status = xlr_i2c_rdreg(priv->iobase, XLR_I2C_STATUS); | |
114 | ||
115 | return status & XLR_I2C_ACK_ERR ? -EIO : 0; | |
116 | } | |
117 | ||
118 | static void xlr_i2c_tx_irq(struct xlr_i2c_private *priv, u32 status) | |
119 | { | |
120 | struct i2c_msg *msg = priv->msg; | |
121 | ||
122 | if (status & XLR_I2C_SDOEMPTY) | |
123 | xlr_i2c_wreg(priv->iobase, XLR_I2C_DATAOUT, | |
124 | msg->buf[priv->pos++]); | |
125 | } | |
126 | ||
127 | static void xlr_i2c_rx_irq(struct xlr_i2c_private *priv, u32 status) | |
128 | { | |
129 | struct i2c_msg *msg = priv->msg; | |
130 | ||
131 | if (status & XLR_I2C_RXRDY) | |
132 | msg->buf[priv->pos++] = | |
133 | xlr_i2c_rdreg(priv->iobase, XLR_I2C_DATAIN); | |
134 | } | |
135 | ||
136 | static irqreturn_t xlr_i2c_irq(int irq, void *dev_id) | |
137 | { | |
138 | struct xlr_i2c_private *priv = dev_id; | |
139 | struct i2c_msg *msg = priv->msg; | |
140 | u32 int_stat, status; | |
141 | ||
142 | int_stat = xlr_i2c_rdreg(priv->iobase, XLR_I2C_INT_STAT); | |
143 | if (!int_stat) | |
144 | return IRQ_NONE; | |
145 | ||
146 | xlr_i2c_wreg(priv->iobase, XLR_I2C_INT_STAT, int_stat); | |
147 | ||
148 | if (!msg) | |
149 | return IRQ_HANDLED; | |
150 | ||
151 | status = xlr_i2c_rdreg(priv->iobase, XLR_I2C_STATUS); | |
152 | ||
153 | if (priv->pos < msg->len) { | |
154 | if (msg->flags & I2C_M_RD) | |
155 | xlr_i2c_rx_irq(priv, status); | |
156 | else | |
157 | xlr_i2c_tx_irq(priv, status); | |
158 | } | |
159 | ||
160 | if (!xlr_i2c_busy(priv, status)) | |
161 | wake_up(&priv->wait); | |
162 | ||
163 | return IRQ_HANDLED; | |
164 | } | |
165 | ||
401c3434 GR |
166 | static int xlr_i2c_tx(struct xlr_i2c_private *priv, u16 len, |
167 | u8 *buf, u16 addr) | |
168 | { | |
169 | struct i2c_adapter *adap = &priv->adap; | |
170 | unsigned long timeout, stoptime, checktime; | |
171 | u32 i2c_status; | |
172 | int pos, timedout; | |
a45af72a MR |
173 | u8 offset; |
174 | u32 xfer; | |
175 | ||
176 | if (!len) | |
177 | return -EOPNOTSUPP; | |
401c3434 GR |
178 | |
179 | offset = buf[0]; | |
180 | xlr_i2c_wreg(priv->iobase, XLR_I2C_ADDR, offset); | |
181 | xlr_i2c_wreg(priv->iobase, XLR_I2C_DEVADDR, addr); | |
75d31c23 MR |
182 | xlr_i2c_wreg(priv->iobase, XLR_I2C_CFG, |
183 | XLR_I2C_CFG_ADDR | priv->cfg->cfg_extra); | |
401c3434 GR |
184 | |
185 | timeout = msecs_to_jiffies(XLR_I2C_TIMEOUT); | |
186 | stoptime = jiffies + timeout; | |
187 | timedout = 0; | |
a45af72a | 188 | |
401c3434 | 189 | if (len == 1) { |
a45af72a MR |
190 | xlr_i2c_wreg(priv->iobase, XLR_I2C_BYTECNT, len - 1); |
191 | xfer = XLR_I2C_STARTXFR_ND; | |
192 | pos = 1; | |
401c3434 | 193 | } else { |
a45af72a MR |
194 | xlr_i2c_wreg(priv->iobase, XLR_I2C_BYTECNT, len - 2); |
195 | xlr_i2c_wreg(priv->iobase, XLR_I2C_DATAOUT, buf[1]); | |
196 | xfer = XLR_I2C_STARTXFR_WR; | |
197 | pos = 2; | |
401c3434 GR |
198 | } |
199 | ||
5398b7ef MR |
200 | priv->pos = pos; |
201 | ||
a45af72a MR |
202 | retry: |
203 | /* retry can only happen on the first byte */ | |
204 | xlr_i2c_wreg(priv->iobase, XLR_I2C_STARTXFR, xfer); | |
205 | ||
5398b7ef MR |
206 | if (priv->irq > 0) |
207 | return xlr_i2c_wait(priv, XLR_I2C_TIMEOUT * len); | |
208 | ||
401c3434 GR |
209 | while (!timedout) { |
210 | checktime = jiffies; | |
211 | i2c_status = xlr_i2c_rdreg(priv->iobase, XLR_I2C_STATUS); | |
212 | ||
a45af72a MR |
213 | if ((i2c_status & XLR_I2C_SDOEMPTY) && pos < len) { |
214 | xlr_i2c_wreg(priv->iobase, XLR_I2C_DATAOUT, buf[pos++]); | |
401c3434 GR |
215 | |
216 | /* reset timeout on successful xmit */ | |
217 | stoptime = jiffies + timeout; | |
218 | } | |
219 | timedout = time_after(checktime, stoptime); | |
220 | ||
221 | if (i2c_status & XLR_I2C_ARB_STARTERR) { | |
222 | if (timedout) | |
223 | break; | |
224 | goto retry; | |
225 | } | |
226 | ||
227 | if (i2c_status & XLR_I2C_ACK_ERR) | |
228 | return -EIO; | |
229 | ||
75d31c23 | 230 | if (!xlr_i2c_busy(priv, i2c_status) && pos >= len) |
401c3434 GR |
231 | return 0; |
232 | } | |
233 | dev_err(&adap->dev, "I2C transmit timeout\n"); | |
234 | return -ETIMEDOUT; | |
235 | } | |
236 | ||
237 | static int xlr_i2c_rx(struct xlr_i2c_private *priv, u16 len, u8 *buf, u16 addr) | |
238 | { | |
239 | struct i2c_adapter *adap = &priv->adap; | |
240 | u32 i2c_status; | |
241 | unsigned long timeout, stoptime, checktime; | |
242 | int nbytes, timedout; | |
a45af72a MR |
243 | |
244 | if (!len) | |
245 | return -EOPNOTSUPP; | |
401c3434 | 246 | |
75d31c23 MR |
247 | xlr_i2c_wreg(priv->iobase, XLR_I2C_CFG, |
248 | XLR_I2C_CFG_NOADDR | priv->cfg->cfg_extra); | |
a45af72a | 249 | xlr_i2c_wreg(priv->iobase, XLR_I2C_BYTECNT, len - 1); |
401c3434 GR |
250 | xlr_i2c_wreg(priv->iobase, XLR_I2C_DEVADDR, addr); |
251 | ||
5398b7ef MR |
252 | priv->pos = 0; |
253 | ||
401c3434 GR |
254 | timeout = msecs_to_jiffies(XLR_I2C_TIMEOUT); |
255 | stoptime = jiffies + timeout; | |
256 | timedout = 0; | |
257 | nbytes = 0; | |
258 | retry: | |
259 | xlr_i2c_wreg(priv->iobase, XLR_I2C_STARTXFR, XLR_I2C_STARTXFR_RD); | |
260 | ||
5398b7ef MR |
261 | if (priv->irq > 0) |
262 | return xlr_i2c_wait(priv, XLR_I2C_TIMEOUT * len); | |
263 | ||
401c3434 GR |
264 | while (!timedout) { |
265 | checktime = jiffies; | |
266 | i2c_status = xlr_i2c_rdreg(priv->iobase, XLR_I2C_STATUS); | |
267 | if (i2c_status & XLR_I2C_RXRDY) { | |
a45af72a | 268 | if (nbytes >= len) |
401c3434 GR |
269 | return -EIO; /* should not happen */ |
270 | ||
a45af72a MR |
271 | buf[nbytes++] = |
272 | xlr_i2c_rdreg(priv->iobase, XLR_I2C_DATAIN); | |
401c3434 GR |
273 | |
274 | /* reset timeout on successful read */ | |
275 | stoptime = jiffies + timeout; | |
276 | } | |
277 | ||
278 | timedout = time_after(checktime, stoptime); | |
279 | if (i2c_status & XLR_I2C_ARB_STARTERR) { | |
280 | if (timedout) | |
281 | break; | |
282 | goto retry; | |
283 | } | |
284 | ||
285 | if (i2c_status & XLR_I2C_ACK_ERR) | |
286 | return -EIO; | |
287 | ||
75d31c23 | 288 | if (!xlr_i2c_busy(priv, i2c_status)) |
401c3434 GR |
289 | return 0; |
290 | } | |
291 | ||
292 | dev_err(&adap->dev, "I2C receive timeout\n"); | |
293 | return -ETIMEDOUT; | |
294 | } | |
295 | ||
296 | static int xlr_i2c_xfer(struct i2c_adapter *adap, | |
297 | struct i2c_msg *msgs, int num) | |
298 | { | |
299 | struct i2c_msg *msg; | |
300 | int i; | |
301 | int ret = 0; | |
302 | struct xlr_i2c_private *priv = i2c_get_adapdata(adap); | |
303 | ||
75d31c23 MR |
304 | ret = clk_enable(priv->clk); |
305 | if (ret) | |
306 | return ret; | |
307 | ||
5398b7ef MR |
308 | if (priv->irq) |
309 | xlr_i2c_wreg(priv->iobase, XLR_I2C_INT_EN, 0xf); | |
310 | ||
311 | ||
401c3434 GR |
312 | for (i = 0; ret == 0 && i < num; i++) { |
313 | msg = &msgs[i]; | |
5398b7ef | 314 | priv->msg = msg; |
401c3434 GR |
315 | if (msg->flags & I2C_M_RD) |
316 | ret = xlr_i2c_rx(priv, msg->len, &msg->buf[0], | |
317 | msg->addr); | |
318 | else | |
319 | ret = xlr_i2c_tx(priv, msg->len, &msg->buf[0], | |
320 | msg->addr); | |
321 | } | |
322 | ||
5398b7ef MR |
323 | if (priv->irq) |
324 | xlr_i2c_wreg(priv->iobase, XLR_I2C_INT_EN, 0); | |
325 | ||
75d31c23 | 326 | clk_disable(priv->clk); |
5398b7ef | 327 | priv->msg = NULL; |
75d31c23 | 328 | |
401c3434 GR |
329 | return (ret != 0) ? ret : num; |
330 | } | |
331 | ||
332 | static u32 xlr_func(struct i2c_adapter *adap) | |
333 | { | |
334 | /* Emulate SMBUS over I2C */ | |
a45af72a | 335 | return (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) | I2C_FUNC_I2C; |
401c3434 GR |
336 | } |
337 | ||
92d9d0df | 338 | static const struct i2c_algorithm xlr_i2c_algo = { |
401c3434 GR |
339 | .master_xfer = xlr_i2c_xfer, |
340 | .functionality = xlr_func, | |
341 | }; | |
342 | ||
75d31c23 MR |
343 | static const struct xlr_i2c_config xlr_i2c_config_default = { |
344 | .status_busy = XLR_I2C_BUS_BUSY, | |
345 | .cfg_extra = 0, | |
346 | }; | |
347 | ||
348 | static const struct xlr_i2c_config xlr_i2c_config_tangox = { | |
5398b7ef | 349 | .flags = XLR_I2C_FLAG_IRQ, |
75d31c23 MR |
350 | .status_busy = 0, |
351 | .cfg_extra = 1 << 8, | |
352 | }; | |
353 | ||
354 | static const struct of_device_id xlr_i2c_dt_ids[] = { | |
355 | { | |
356 | .compatible = "sigma,smp8642-i2c", | |
357 | .data = &xlr_i2c_config_tangox, | |
358 | }, | |
359 | { } | |
360 | }; | |
2cb496db | 361 | MODULE_DEVICE_TABLE(of, xlr_i2c_dt_ids); |
75d31c23 | 362 | |
0b255e92 | 363 | static int xlr_i2c_probe(struct platform_device *pdev) |
401c3434 | 364 | { |
75d31c23 | 365 | const struct of_device_id *match; |
401c3434 GR |
366 | struct xlr_i2c_private *priv; |
367 | struct resource *res; | |
75d31c23 MR |
368 | struct clk *clk; |
369 | unsigned long clk_rate; | |
370 | unsigned long clk_div; | |
371 | u32 busfreq; | |
5398b7ef | 372 | int irq; |
401c3434 GR |
373 | int ret; |
374 | ||
375 | priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); | |
376 | if (!priv) | |
377 | return -ENOMEM; | |
378 | ||
75d31c23 MR |
379 | match = of_match_device(xlr_i2c_dt_ids, &pdev->dev); |
380 | if (match) | |
381 | priv->cfg = match->data; | |
382 | else | |
383 | priv->cfg = &xlr_i2c_config_default; | |
384 | ||
401c3434 | 385 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
84dbf809 TR |
386 | priv->iobase = devm_ioremap_resource(&pdev->dev, res); |
387 | if (IS_ERR(priv->iobase)) | |
388 | return PTR_ERR(priv->iobase); | |
401c3434 | 389 | |
5398b7ef MR |
390 | irq = platform_get_irq(pdev, 0); |
391 | ||
392 | if (irq > 0 && (priv->cfg->flags & XLR_I2C_FLAG_IRQ)) { | |
393 | priv->irq = irq; | |
394 | ||
395 | xlr_i2c_wreg(priv->iobase, XLR_I2C_INT_EN, 0); | |
396 | xlr_i2c_wreg(priv->iobase, XLR_I2C_INT_STAT, 0xf); | |
397 | ||
398 | ret = devm_request_irq(&pdev->dev, priv->irq, xlr_i2c_irq, | |
399 | IRQF_SHARED, dev_name(&pdev->dev), | |
400 | priv); | |
401 | if (ret) | |
402 | return ret; | |
403 | ||
404 | init_waitqueue_head(&priv->wait); | |
405 | } | |
406 | ||
75d31c23 MR |
407 | if (of_property_read_u32(pdev->dev.of_node, "clock-frequency", |
408 | &busfreq)) | |
409 | busfreq = 100000; | |
410 | ||
411 | clk = devm_clk_get(&pdev->dev, NULL); | |
412 | if (!IS_ERR(clk)) { | |
413 | ret = clk_prepare_enable(clk); | |
414 | if (ret) | |
415 | return ret; | |
416 | ||
417 | clk_rate = clk_get_rate(clk); | |
418 | clk_div = DIV_ROUND_UP(clk_rate, 2 * busfreq); | |
419 | xlr_i2c_wreg(priv->iobase, XLR_I2C_CLKDIV, clk_div); | |
420 | ||
421 | clk_disable(clk); | |
422 | priv->clk = clk; | |
423 | } | |
424 | ||
401c3434 | 425 | priv->adap.dev.parent = &pdev->dev; |
75d31c23 | 426 | priv->adap.dev.of_node = pdev->dev.of_node; |
401c3434 GR |
427 | priv->adap.owner = THIS_MODULE; |
428 | priv->adap.algo_data = priv; | |
429 | priv->adap.algo = &xlr_i2c_algo; | |
430 | priv->adap.nr = pdev->id; | |
431 | priv->adap.class = I2C_CLASS_HWMON; | |
432 | snprintf(priv->adap.name, sizeof(priv->adap.name), "xlr-i2c"); | |
433 | ||
434 | i2c_set_adapdata(&priv->adap, priv); | |
435 | ret = i2c_add_numbered_adapter(&priv->adap); | |
ea734404 | 436 | if (ret < 0) |
401c3434 | 437 | return ret; |
401c3434 GR |
438 | |
439 | platform_set_drvdata(pdev, priv); | |
440 | dev_info(&priv->adap.dev, "Added I2C Bus.\n"); | |
441 | return 0; | |
442 | } | |
443 | ||
0b255e92 | 444 | static int xlr_i2c_remove(struct platform_device *pdev) |
401c3434 GR |
445 | { |
446 | struct xlr_i2c_private *priv; | |
447 | ||
448 | priv = platform_get_drvdata(pdev); | |
449 | i2c_del_adapter(&priv->adap); | |
75d31c23 MR |
450 | clk_unprepare(priv->clk); |
451 | ||
401c3434 GR |
452 | return 0; |
453 | } | |
454 | ||
455 | static struct platform_driver xlr_i2c_driver = { | |
456 | .probe = xlr_i2c_probe, | |
0b255e92 | 457 | .remove = xlr_i2c_remove, |
401c3434 GR |
458 | .driver = { |
459 | .name = "xlr-i2cbus", | |
75d31c23 | 460 | .of_match_table = xlr_i2c_dt_ids, |
401c3434 GR |
461 | }, |
462 | }; | |
463 | ||
464 | module_platform_driver(xlr_i2c_driver); | |
465 | ||
466 | MODULE_AUTHOR("Ganesan Ramalingam <ganesanr@netlogicmicro.com>"); | |
467 | MODULE_DESCRIPTION("XLR/XLS SoC I2C Controller driver"); | |
468 | MODULE_LICENSE("GPL v2"); | |
469 | MODULE_ALIAS("platform:xlr-i2cbus"); |