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Merge tag 'v4.4-rockchip-dts32-fixes1' of git://git.kernel.org/pub/scm/linux/kernel...
[linux-2.6-block.git] / drivers / i2c / busses / i2c-xiic.c
CommitLineData
e1d5b659
RR		 1/*
2 * i2c-xiic.c
3 * Copyright (c) 2002-2007 Xilinx Inc.
4 * Copyright (c) 2009-2010 Intel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
e1d5b659
RR		 15 *
16 * This code was implemented by Mocean Laboratories AB when porting linux
17 * to the automotive development board Russellville. The copyright holder
18 * as seen in the header is Intel corporation.
19 * Mocean Laboratories forked off the GNU/Linux platform work into a
25985edc 20 * separate company called Pelagicore AB, which committed the code to the
e1d5b659
RR		 21 * kernel.
22 */
23
24/* Supports:
25 * Xilinx IIC
26 */
27#include <linux/kernel.h>
28#include <linux/module.h>
e1d5b659 29#include <linux/errno.h>
168e722d 30#include <linux/err.h>
02ca6c40 31#include <linux/delay.h>
e1d5b659
RR		 32#include <linux/platform_device.h>
33#include <linux/i2c.h>
34#include <linux/interrupt.h>
35#include <linux/wait.h>
36#include <linux/i2c-xiic.h>
37#include <linux/io.h>
5a0e3ad6 38#include <linux/slab.h>
4edd65e6 39#include <linux/of.h>
e1d5b659
RR		 40
41#define DRIVER_NAME "xiic-i2c"
42
43enum xilinx_i2c_state {
44 STATE_DONE,
45 STATE_ERROR,
46 STATE_START
47};
48
48ef3ca9
TG		 49enum xiic_endian {
50 LITTLE,
51 BIG
52};
53
e1d5b659
RR		 54/**
55 * struct xiic_i2c - Internal representation of the XIIC I2C bus
56 * @base: Memory base of the HW registers
57 * @wait: Wait queue for callers
58 * @adap: Kernel adapter representation
59 * @tx_msg: Messages from above to be sent
60 * @lock: Mutual exclusion
61 * @tx_pos: Current pos in TX message
62 * @nmsgs: Number of messages in tx_msg
63 * @state: See STATE_
64 * @rx_msg: Current RX message
65 * @rx_pos: Position within current RX message
bea6ff02 66 * @endianness: big/little-endian byte order
e1d5b659
RR		 67 */
68struct xiic_i2c {
69 void __iomem *base;
70 wait_queue_head_t wait;
71 struct i2c_adapter adap;
72 struct i2c_msg *tx_msg;
73 spinlock_t lock;
f1e9f89a 74 unsigned int tx_pos;
e1d5b659
RR		 75 unsigned int nmsgs;
76 enum xilinx_i2c_state state;
77 struct i2c_msg *rx_msg;
78 int rx_pos;
48ef3ca9 79 enum xiic_endian endianness;
e1d5b659
RR		 80};
81
82
83#define XIIC_MSB_OFFSET 0
84#define XIIC_REG_OFFSET (0x100+XIIC_MSB_OFFSET)
85
86/*
87 * Register offsets in bytes from RegisterBase. Three is added to the
88 * base offset to access LSB (IBM style) of the word
89 */
90#define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET) /* Control Register */
91#define XIIC_SR_REG_OFFSET (0x04+XIIC_REG_OFFSET) /* Status Register */
92#define XIIC_DTR_REG_OFFSET (0x08+XIIC_REG_OFFSET) /* Data Tx Register */
93#define XIIC_DRR_REG_OFFSET (0x0C+XIIC_REG_OFFSET) /* Data Rx Register */
94#define XIIC_ADR_REG_OFFSET (0x10+XIIC_REG_OFFSET) /* Address Register */
95#define XIIC_TFO_REG_OFFSET (0x14+XIIC_REG_OFFSET) /* Tx FIFO Occupancy */
96#define XIIC_RFO_REG_OFFSET (0x18+XIIC_REG_OFFSET) /* Rx FIFO Occupancy */
97#define XIIC_TBA_REG_OFFSET (0x1C+XIIC_REG_OFFSET) /* 10 Bit Address reg */
98#define XIIC_RFD_REG_OFFSET (0x20+XIIC_REG_OFFSET) /* Rx FIFO Depth reg */
99#define XIIC_GPO_REG_OFFSET (0x24+XIIC_REG_OFFSET) /* Output Register */
100
101/* Control Register masks */
102#define XIIC_CR_ENABLE_DEVICE_MASK 0x01 /* Device enable = 1 */
103#define XIIC_CR_TX_FIFO_RESET_MASK 0x02 /* Transmit FIFO reset=1 */
104#define XIIC_CR_MSMS_MASK 0x04 /* Master starts Txing=1 */
105#define XIIC_CR_DIR_IS_TX_MASK 0x08 /* Dir of tx. Txing=1 */
106#define XIIC_CR_NO_ACK_MASK 0x10 /* Tx Ack. NO ack = 1 */
107#define XIIC_CR_REPEATED_START_MASK 0x20 /* Repeated start = 1 */
108#define XIIC_CR_GENERAL_CALL_MASK 0x40 /* Gen Call enabled = 1 */
109
110/* Status Register masks */
111#define XIIC_SR_GEN_CALL_MASK 0x01 /* 1=a mstr issued a GC */
112#define XIIC_SR_ADDR_AS_SLAVE_MASK 0x02 /* 1=when addr as slave */
113#define XIIC_SR_BUS_BUSY_MASK 0x04 /* 1 = bus is busy */
114#define XIIC_SR_MSTR_RDING_SLAVE_MASK 0x08 /* 1=Dir: mstr <-- slave */
115#define XIIC_SR_TX_FIFO_FULL_MASK 0x10 /* 1 = Tx FIFO full */
116#define XIIC_SR_RX_FIFO_FULL_MASK 0x20 /* 1 = Rx FIFO full */
117#define XIIC_SR_RX_FIFO_EMPTY_MASK 0x40 /* 1 = Rx FIFO empty */
118#define XIIC_SR_TX_FIFO_EMPTY_MASK 0x80 /* 1 = Tx FIFO empty */
119
120/* Interrupt Status Register masks Interrupt occurs when... */
121#define XIIC_INTR_ARB_LOST_MASK 0x01 /* 1 = arbitration lost */
122#define XIIC_INTR_TX_ERROR_MASK 0x02 /* 1=Tx error/msg complete */
123#define XIIC_INTR_TX_EMPTY_MASK 0x04 /* 1 = Tx FIFO/reg empty */
124#define XIIC_INTR_RX_FULL_MASK 0x08 /* 1=Rx FIFO/reg=OCY level */
125#define XIIC_INTR_BNB_MASK 0x10 /* 1 = Bus not busy */
126#define XIIC_INTR_AAS_MASK 0x20 /* 1 = when addr as slave */
127#define XIIC_INTR_NAAS_MASK 0x40 /* 1 = not addr as slave */
128#define XIIC_INTR_TX_HALF_MASK 0x80 /* 1 = TX FIFO half empty */
129
130/* The following constants specify the depth of the FIFOs */
131#define IIC_RX_FIFO_DEPTH 16 /* Rx fifo capacity */
132#define IIC_TX_FIFO_DEPTH 16 /* Tx fifo capacity */
133
134/* The following constants specify groups of interrupts that are typically
135 * enabled or disables at the same time
136 */
137#define XIIC_TX_INTERRUPTS \
138(XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)
139
140#define XIIC_TX_RX_INTERRUPTS (XIIC_INTR_RX_FULL_MASK | XIIC_TX_INTERRUPTS)
141
142/* The following constants are used with the following macros to specify the
143 * operation, a read or write operation.
144 */
145#define XIIC_READ_OPERATION 1
146#define XIIC_WRITE_OPERATION 0
147
148/*
149 * Tx Fifo upper bit masks.
150 */
151#define XIIC_TX_DYN_START_MASK 0x0100 /* 1 = Set dynamic start */
152#define XIIC_TX_DYN_STOP_MASK 0x0200 /* 1 = Set dynamic stop */
153
154/*
155 * The following constants define the register offsets for the Interrupt
156 * registers. There are some holes in the memory map for reserved addresses
157 * to allow other registers to be added and still match the memory map of the
158 * interrupt controller registers
159 */
160#define XIIC_DGIER_OFFSET 0x1C /* Device Global Interrupt Enable Register */
161#define XIIC_IISR_OFFSET 0x20 /* Interrupt Status Register */
162#define XIIC_IIER_OFFSET 0x28 /* Interrupt Enable Register */
163#define XIIC_RESETR_OFFSET 0x40 /* Reset Register */
164
165#define XIIC_RESET_MASK 0xAUL
166
167/*
168 * The following constant is used for the device global interrupt enable
169 * register, to enable all interrupts for the device, this is the only bit
170 * in the register
171 */
172#define XIIC_GINTR_ENABLE_MASK 0x80000000UL
173
174#define xiic_tx_space(i2c) ((i2c)->tx_msg->len - (i2c)->tx_pos)
175#define xiic_rx_space(i2c) ((i2c)->rx_msg->len - (i2c)->rx_pos)
176
177static void xiic_start_xfer(struct xiic_i2c *i2c);
178static void __xiic_start_xfer(struct xiic_i2c *i2c);
179
48ef3ca9
TG		 180/*
181 * For the register read and write functions, a little-endian and big-endian
182 * version are necessary. Endianness is detected during the probe function.
183 * Only the least significant byte [doublet] of the register are ever
184 * accessed. This requires an offset of 3 [2] from the base address for
185 * big-endian systems.
186 */
187
e1d5b659
RR		 188static inline void xiic_setreg8(struct xiic_i2c *i2c, int reg, u8 value)
189{
48ef3ca9
TG		 190 if (i2c->endianness == LITTLE)
191 iowrite8(value, i2c->base + reg);
192 else
193 iowrite8(value, i2c->base + reg + 3);
e1d5b659
RR		 194}
195
196static inline u8 xiic_getreg8(struct xiic_i2c *i2c, int reg)
197{
48ef3ca9
TG		 198 u8 ret;
199
200 if (i2c->endianness == LITTLE)
201 ret = ioread8(i2c->base + reg);
202 else
203 ret = ioread8(i2c->base + reg + 3);
204 return ret;
e1d5b659
RR		 205}
206
207static inline void xiic_setreg16(struct xiic_i2c *i2c, int reg, u16 value)
208{
48ef3ca9
TG		 209 if (i2c->endianness == LITTLE)
210 iowrite16(value, i2c->base + reg);
211 else
212 iowrite16be(value, i2c->base + reg + 2);
e1d5b659
RR		 213}
214
215static inline void xiic_setreg32(struct xiic_i2c *i2c, int reg, int value)
216{
48ef3ca9
TG		 217 if (i2c->endianness == LITTLE)
218 iowrite32(value, i2c->base + reg);
219 else
220 iowrite32be(value, i2c->base + reg);
e1d5b659
RR		 221}
222
223static inline int xiic_getreg32(struct xiic_i2c *i2c, int reg)
224{
48ef3ca9
TG		 225 u32 ret;
226
227 if (i2c->endianness == LITTLE)
228 ret = ioread32(i2c->base + reg);
229 else
230 ret = ioread32be(i2c->base + reg);
231 return ret;
e1d5b659
RR		 232}
233
234static inline void xiic_irq_dis(struct xiic_i2c *i2c, u32 mask)
235{
236 u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
237 xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier & ~mask);
238}
239
240static inline void xiic_irq_en(struct xiic_i2c *i2c, u32 mask)
241{
242 u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
243 xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier | mask);
244}
245
246static inline void xiic_irq_clr(struct xiic_i2c *i2c, u32 mask)
247{
248 u32 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
249 xiic_setreg32(i2c, XIIC_IISR_OFFSET, isr & mask);
250}
251
252static inline void xiic_irq_clr_en(struct xiic_i2c *i2c, u32 mask)
253{
254 xiic_irq_clr(i2c, mask);
255 xiic_irq_en(i2c, mask);
256}
257
258static void xiic_clear_rx_fifo(struct xiic_i2c *i2c)
259{
260 u8 sr;
261 for (sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET);
262 !(sr & XIIC_SR_RX_FIFO_EMPTY_MASK);
263 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET))
264 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET);
265}
266
267static void xiic_reinit(struct xiic_i2c *i2c)
268{
269 xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK);
270
271 /* Set receive Fifo depth to maximum (zero based). */
272 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, IIC_RX_FIFO_DEPTH - 1);
273
274 /* Reset Tx Fifo. */
275 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK);
276
277 /* Enable IIC Device, remove Tx Fifo reset & disable general call. */
278 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_ENABLE_DEVICE_MASK);
279
280 /* make sure RX fifo is empty */
281 xiic_clear_rx_fifo(i2c);
282
283 /* Enable interrupts */
284 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);
285
542e2a9b 286 xiic_irq_clr_en(i2c, XIIC_INTR_ARB_LOST_MASK);
e1d5b659
RR		 287}
288
289static void xiic_deinit(struct xiic_i2c *i2c)
290{
291 u8 cr;
292
293 xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK);
294
295 /* Disable IIC Device. */
296 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
297 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & ~XIIC_CR_ENABLE_DEVICE_MASK);
298}
299
300static void xiic_read_rx(struct xiic_i2c *i2c)
301{
302 u8 bytes_in_fifo;
303 int i;
304
305 bytes_in_fifo = xiic_getreg8(i2c, XIIC_RFO_REG_OFFSET) + 1;
306
f1e9f89a
KA		 307 dev_dbg(i2c->adap.dev.parent,
308 "%s entry, bytes in fifo: %d, msg: %d, SR: 0x%x, CR: 0x%x\n",
e1d5b659
RR		 309 __func__, bytes_in_fifo, xiic_rx_space(i2c),
310 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET),
311 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
312
313 if (bytes_in_fifo > xiic_rx_space(i2c))
314 bytes_in_fifo = xiic_rx_space(i2c);
315
316 for (i = 0; i < bytes_in_fifo; i++)
317 i2c->rx_msg->buf[i2c->rx_pos++] =
318 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET);
319
320 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET,
321 (xiic_rx_space(i2c) > IIC_RX_FIFO_DEPTH) ?
322 IIC_RX_FIFO_DEPTH - 1 : xiic_rx_space(i2c) - 1);
323}
324
325static int xiic_tx_fifo_space(struct xiic_i2c *i2c)
326{
327 /* return the actual space left in the FIFO */
328 return IIC_TX_FIFO_DEPTH - xiic_getreg8(i2c, XIIC_TFO_REG_OFFSET) - 1;
329}
330
331static void xiic_fill_tx_fifo(struct xiic_i2c *i2c)
332{
333 u8 fifo_space = xiic_tx_fifo_space(i2c);
334 int len = xiic_tx_space(i2c);
335
336 len = (len > fifo_space) ? fifo_space : len;
337
338 dev_dbg(i2c->adap.dev.parent, "%s entry, len: %d, fifo space: %d\n",
339 __func__, len, fifo_space);
340
341 while (len--) {
342 u16 data = i2c->tx_msg->buf[i2c->tx_pos++];
343 if ((xiic_tx_space(i2c) == 0) && (i2c->nmsgs == 1)) {
344 /* last message in transfer -> STOP */
345 data |= XIIC_TX_DYN_STOP_MASK;
346 dev_dbg(i2c->adap.dev.parent, "%s TX STOP\n", __func__);
c39e8e43
SF		 347 }
348 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data);
e1d5b659
RR		 349 }
350}
351
352static void xiic_wakeup(struct xiic_i2c *i2c, int code)
353{
354 i2c->tx_msg = NULL;
355 i2c->rx_msg = NULL;
356 i2c->nmsgs = 0;
357 i2c->state = code;
358 wake_up(&i2c->wait);
359}
360
fcc2fac6 361static irqreturn_t xiic_process(int irq, void *dev_id)
e1d5b659 362{
fcc2fac6 363 struct xiic_i2c *i2c = dev_id;
e1d5b659
RR		 364 u32 pend, isr, ier;
365 u32 clr = 0;
366
367 /* Get the interrupt Status from the IPIF. There is no clearing of
368 * interrupts in the IPIF. Interrupts must be cleared at the source.
369 * To find which interrupts are pending; AND interrupts pending with
370 * interrupts masked.
371 */
fcc2fac6 372 spin_lock(&i2c->lock);
e1d5b659
RR		 373 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
374 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
375 pend = isr & ier;
376
f1e9f89a
KA		 377 dev_dbg(i2c->adap.dev.parent, "%s: IER: 0x%x, ISR: 0x%x, pend: 0x%x\n",
378 __func__, ier, isr, pend);
379 dev_dbg(i2c->adap.dev.parent, "%s: SR: 0x%x, msg: %p, nmsgs: %d\n",
380 __func__, xiic_getreg8(i2c, XIIC_SR_REG_OFFSET),
e1d5b659
RR		 381 i2c->tx_msg, i2c->nmsgs);
382
e1d5b659
RR		 383
384 /* Service requesting interrupt */
385 if ((pend & XIIC_INTR_ARB_LOST_MASK) ||
386 ((pend & XIIC_INTR_TX_ERROR_MASK) &&
387 !(pend & XIIC_INTR_RX_FULL_MASK))) {
388 /* bus arbritration lost, or...
389 * Transmit error _OR_ RX completed
390 * if this happens when RX_FULL is not set
391 * this is probably a TX error
392 */
393
394 dev_dbg(i2c->adap.dev.parent, "%s error\n", __func__);
395
396 /* dynamic mode seem to suffer from problems if we just flushes
397 * fifos and the next message is a TX with len 0 (only addr)
398 * reset the IP instead of just flush fifos
399 */
400 xiic_reinit(i2c);
401
6b0c8dc3
SD		 402 if (i2c->rx_msg)
403 xiic_wakeup(i2c, STATE_ERROR);
e1d5b659
RR		 404 if (i2c->tx_msg)
405 xiic_wakeup(i2c, STATE_ERROR);
7f9906bd
SD		 406 }
407 if (pend & XIIC_INTR_RX_FULL_MASK) {
e1d5b659
RR		 408 /* Receive register/FIFO is full */
409
7f9906bd 410 clr |= XIIC_INTR_RX_FULL_MASK;
e1d5b659
RR		 411 if (!i2c->rx_msg) {
412 dev_dbg(i2c->adap.dev.parent,
413 "%s unexpexted RX IRQ\n", __func__);
414 xiic_clear_rx_fifo(i2c);
415 goto out;
416 }
417
418 xiic_read_rx(i2c);
419 if (xiic_rx_space(i2c) == 0) {
420 /* this is the last part of the message */
421 i2c->rx_msg = NULL;
422
423 /* also clear TX error if there (RX complete) */
424 clr |= (isr & XIIC_INTR_TX_ERROR_MASK);
425
426 dev_dbg(i2c->adap.dev.parent,
427 "%s end of message, nmsgs: %d\n",
428 __func__, i2c->nmsgs);
429
430 /* send next message if this wasn't the last,
431 * otherwise the transfer will be finialise when
432 * receiving the bus not busy interrupt
433 */
434 if (i2c->nmsgs > 1) {
435 i2c->nmsgs--;
436 i2c->tx_msg++;
437 dev_dbg(i2c->adap.dev.parent,
438 "%s will start next...\n", __func__);
439
440 __xiic_start_xfer(i2c);
441 }
442 }
7f9906bd
SD		 443 }
444 if (pend & XIIC_INTR_BNB_MASK) {
e1d5b659 445 /* IIC bus has transitioned to not busy */
7f9906bd 446 clr |= XIIC_INTR_BNB_MASK;
e1d5b659
RR		 447
448 /* The bus is not busy, disable BusNotBusy interrupt */
449 xiic_irq_dis(i2c, XIIC_INTR_BNB_MASK);
450
451 if (!i2c->tx_msg)
452 goto out;
453
454 if ((i2c->nmsgs == 1) && !i2c->rx_msg &&
455 xiic_tx_space(i2c) == 0)
456 xiic_wakeup(i2c, STATE_DONE);
457 else
458 xiic_wakeup(i2c, STATE_ERROR);
7f9906bd
SD		 459 }
460 if (pend & (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)) {
d36b6910 461 /* Transmit register/FIFO is empty or ½ empty */
e1d5b659 462
7f9906bd
SD		 463 clr |= (pend &
464 (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK));
e1d5b659
RR		 465
466 if (!i2c->tx_msg) {
467 dev_dbg(i2c->adap.dev.parent,
468 "%s unexpexted TX IRQ\n", __func__);
469 goto out;
470 }
471
472 xiic_fill_tx_fifo(i2c);
473
474 /* current message sent and there is space in the fifo */
475 if (!xiic_tx_space(i2c) && xiic_tx_fifo_space(i2c) >= 2) {
476 dev_dbg(i2c->adap.dev.parent,
477 "%s end of message sent, nmsgs: %d\n",
478 __func__, i2c->nmsgs);
479 if (i2c->nmsgs > 1) {
480 i2c->nmsgs--;
481 i2c->tx_msg++;
482 __xiic_start_xfer(i2c);
483 } else {
484 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK);
485
486 dev_dbg(i2c->adap.dev.parent,
487 "%s Got TX IRQ but no more to do...\n",
488 __func__);
489 }
490 } else if (!xiic_tx_space(i2c) && (i2c->nmsgs == 1))
491 /* current frame is sent and is last,
492 * make sure to disable tx half
493 */
494 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK);
e1d5b659
RR		 495 }
496out:
497 dev_dbg(i2c->adap.dev.parent, "%s clr: 0x%x\n", __func__, clr);
498
499 xiic_setreg32(i2c, XIIC_IISR_OFFSET, clr);
fcc2fac6
SD		 500 spin_unlock(&i2c->lock);
501 return IRQ_HANDLED;
e1d5b659
RR		 502}
503
504static int xiic_bus_busy(struct xiic_i2c *i2c)
505{
506 u8 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET);
507
508 return (sr & XIIC_SR_BUS_BUSY_MASK) ? -EBUSY : 0;
509}
510
511static int xiic_busy(struct xiic_i2c *i2c)
512{
513 int tries = 3;
514 int err;
515
516 if (i2c->tx_msg)
517 return -EBUSY;
518
519 /* for instance if previous transfer was terminated due to TX error
520 * it might be that the bus is on it's way to become available
521 * give it at most 3 ms to wake
522 */
523 err = xiic_bus_busy(i2c);
524 while (err && tries--) {
b33aa252 525 msleep(1);
e1d5b659
RR		 526 err = xiic_bus_busy(i2c);
527 }
528
529 return err;
530}
531
532static void xiic_start_recv(struct xiic_i2c *i2c)
533{
534 u8 rx_watermark;
535 struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg;
536
537 /* Clear and enable Rx full interrupt. */
538 xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK | XIIC_INTR_TX_ERROR_MASK);
539
540 /* we want to get all but last byte, because the TX_ERROR IRQ is used
541 * to inidicate error ACK on the address, and negative ack on the last
542 * received byte, so to not mix them receive all but last.
543 * In the case where there is only one byte to receive
544 * we can check if ERROR and RX full is set at the same time
545 */
546 rx_watermark = msg->len;
547 if (rx_watermark > IIC_RX_FIFO_DEPTH)
548 rx_watermark = IIC_RX_FIFO_DEPTH;
549 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rx_watermark - 1);
550
551 if (!(msg->flags & I2C_M_NOSTART))
552 /* write the address */
553 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET,
554 (msg->addr << 1) | XIIC_READ_OPERATION |
555 XIIC_TX_DYN_START_MASK);
556
557 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK);
558
559 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET,
560 msg->len | ((i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0));
561 if (i2c->nmsgs == 1)
562 /* very last, enable bus not busy as well */
563 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK);
564
565 /* the message is tx:ed */
566 i2c->tx_pos = msg->len;
567}
568
569static void xiic_start_send(struct xiic_i2c *i2c)
570{
571 struct i2c_msg *msg = i2c->tx_msg;
572
573 xiic_irq_clr(i2c, XIIC_INTR_TX_ERROR_MASK);
574
f1e9f89a
KA		 575 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, len: %d",
576 __func__, msg, msg->len);
577 dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n",
578 __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET),
e1d5b659
RR		 579 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
580
581 if (!(msg->flags & I2C_M_NOSTART)) {
582 /* write the address */
583 u16 data = ((msg->addr << 1) & 0xfe) | XIIC_WRITE_OPERATION |
584 XIIC_TX_DYN_START_MASK;
585 if ((i2c->nmsgs == 1) && msg->len == 0)
586 /* no data and last message -> add STOP */
587 data |= XIIC_TX_DYN_STOP_MASK;
588
589 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data);
590 }
591
592 xiic_fill_tx_fifo(i2c);
593
594 /* Clear any pending Tx empty, Tx Error and then enable them. */
595 xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_ERROR_MASK |
596 XIIC_INTR_BNB_MASK);
597}
598
599static irqreturn_t xiic_isr(int irq, void *dev_id)
600{
601 struct xiic_i2c *i2c = dev_id;
fcc2fac6
SD		 602 u32 pend, isr, ier;
603 irqreturn_t ret = IRQ_NONE;
604 /* Do not processes a devices interrupts if the device has no
605 * interrupts pending
606 */
e1d5b659
RR		 607
608 dev_dbg(i2c->adap.dev.parent, "%s entry\n", __func__);
609
fcc2fac6
SD		 610 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
611 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
612 pend = isr & ier;
613 if (pend)
614 ret = IRQ_WAKE_THREAD;
e1d5b659 615
fcc2fac6 616 return ret;
e1d5b659
RR		 617}
618
619static void __xiic_start_xfer(struct xiic_i2c *i2c)
620{
621 int first = 1;
622 int fifo_space = xiic_tx_fifo_space(i2c);
623 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, fifos space: %d\n",
624 __func__, i2c->tx_msg, fifo_space);
625
626 if (!i2c->tx_msg)
627 return;
628
629 i2c->rx_pos = 0;
630 i2c->tx_pos = 0;
631 i2c->state = STATE_START;
632 while ((fifo_space >= 2) && (first || (i2c->nmsgs > 1))) {
633 if (!first) {
634 i2c->nmsgs--;
635 i2c->tx_msg++;
636 i2c->tx_pos = 0;
637 } else
638 first = 0;
639
640 if (i2c->tx_msg->flags & I2C_M_RD) {
641 /* we dont date putting several reads in the FIFO */
642 xiic_start_recv(i2c);
643 return;
644 } else {
645 xiic_start_send(i2c);
646 if (xiic_tx_space(i2c) != 0) {
647 /* the message could not be completely sent */
648 break;
649 }
650 }
651
652 fifo_space = xiic_tx_fifo_space(i2c);
653 }
654
655 /* there are more messages or the current one could not be completely
656 * put into the FIFO, also enable the half empty interrupt
657 */
658 if (i2c->nmsgs > 1 || xiic_tx_space(i2c))
659 xiic_irq_clr_en(i2c, XIIC_INTR_TX_HALF_MASK);
660
661}
662
663static void xiic_start_xfer(struct xiic_i2c *i2c)
664{
9656eeeb
LPC		 665 spin_lock(&i2c->lock);
666 xiic_reinit(i2c);
e1d5b659 667 __xiic_start_xfer(i2c);
d0fe5258 668 spin_unlock(&i2c->lock);
e1d5b659
RR		 669}
670
671static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
672{
673 struct xiic_i2c *i2c = i2c_get_adapdata(adap);
674 int err;
675
676 dev_dbg(adap->dev.parent, "%s entry SR: 0x%x\n", __func__,
677 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET));
678
679 err = xiic_busy(i2c);
680 if (err)
681 return err;
682
683 i2c->tx_msg = msgs;
684 i2c->nmsgs = num;
685
686 xiic_start_xfer(i2c);
687
688 if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) ||
689 (i2c->state == STATE_DONE), HZ))
690 return (i2c->state == STATE_DONE) ? num : -EIO;
691 else {
692 i2c->tx_msg = NULL;
693 i2c->rx_msg = NULL;
694 i2c->nmsgs = 0;
695 return -ETIMEDOUT;
696 }
697}
698
699static u32 xiic_func(struct i2c_adapter *adap)
700{
701 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
702}
703
704static const struct i2c_algorithm xiic_algorithm = {
4db5beed
WS		 705 .master_xfer = xiic_xfer,
706 .functionality = xiic_func,
e1d5b659
RR		 707};
708
709static struct i2c_adapter xiic_adapter = {
4db5beed
WS		 710 .owner = THIS_MODULE,
711 .name = DRIVER_NAME,
712 .class = I2C_CLASS_DEPRECATED,
713 .algo = &xiic_algorithm,
e1d5b659
RR		 714};
715
716
0b255e92 717static int xiic_i2c_probe(struct platform_device *pdev)
e1d5b659
RR		 718{
719 struct xiic_i2c *i2c;
720 struct xiic_i2c_platform_data *pdata;
721 struct resource *res;
722 int ret, irq;
723 u8 i;
48ef3ca9 724 u32 sr;
e1d5b659 725
168e722d
KA		 726 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
727 if (!i2c)
728 return -ENOMEM;
729
e1d5b659 730 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
168e722d
KA		 731 i2c->base = devm_ioremap_resource(&pdev->dev, res);
732 if (IS_ERR(i2c->base))
733 return PTR_ERR(i2c->base);
e1d5b659
RR		 734
735 irq = platform_get_irq(pdev, 0);
736 if (irq < 0)
168e722d 737 return irq;
e1d5b659 738
ab0dc7a8 739 pdata = dev_get_platdata(&pdev->dev);
e1d5b659 740
e1d5b659
RR		 741 /* hook up driver to tree */
742 platform_set_drvdata(pdev, i2c);
743 i2c->adap = xiic_adapter;
744 i2c_set_adapdata(&i2c->adap, i2c);
745 i2c->adap.dev.parent = &pdev->dev;
3ac0b337 746 i2c->adap.dev.of_node = pdev->dev.of_node;
e1d5b659 747
e1d5b659
RR		 748 spin_lock_init(&i2c->lock);
749 init_waitqueue_head(&i2c->wait);
168e722d 750
fcc2fac6
SD		 751 ret = devm_request_threaded_irq(&pdev->dev, irq, xiic_isr,
752 xiic_process, IRQF_ONESHOT,
753 pdev->name, i2c);
754
168e722d 755 if (ret < 0) {
e1d5b659 756 dev_err(&pdev->dev, "Cannot claim IRQ\n");
168e722d 757 return ret;
e1d5b659
RR		 758 }
759
48ef3ca9
TG		 760 /*
761 * Detect endianness
762 * Try to reset the TX FIFO. Then check the EMPTY flag. If it is not
763 * set, assume that the endianness was wrong and swap.
764 */
765 i2c->endianness = LITTLE;
766 xiic_setreg32(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK);
767 /* Reset is cleared in xiic_reinit */
768 sr = xiic_getreg32(i2c, XIIC_SR_REG_OFFSET);
769 if (!(sr & XIIC_SR_TX_FIFO_EMPTY_MASK))
770 i2c->endianness = BIG;
771
617bdcbc
MS		 772 xiic_reinit(i2c);
773
e1d5b659
RR		 774 /* add i2c adapter to i2c tree */
775 ret = i2c_add_adapter(&i2c->adap);
776 if (ret) {
777 dev_err(&pdev->dev, "Failed to add adapter\n");
168e722d
KA		 778 xiic_deinit(i2c);
779 return ret;
e1d5b659
RR		 780 }
781
3ac0b337
LPC		 782 if (pdata) {
783 /* add in known devices to the bus */
784 for (i = 0; i < pdata->num_devices; i++)
785 i2c_new_device(&i2c->adap, pdata->devices + i);
786 }
787
e1d5b659 788 return 0;
e1d5b659
RR		 789}
790
0b255e92 791static int xiic_i2c_remove(struct platform_device *pdev)
e1d5b659
RR		 792{
793 struct xiic_i2c *i2c = platform_get_drvdata(pdev);
e1d5b659
RR		 794
795 /* remove adapter & data */
796 i2c_del_adapter(&i2c->adap);
797
798 xiic_deinit(i2c);
799
e1d5b659
RR		 800 return 0;
801}
802
3ac0b337 803#if defined(CONFIG_OF)
0b255e92 804static const struct of_device_id xiic_of_match[] = {
3ac0b337
LPC		 805 { .compatible = "xlnx,xps-iic-2.00.a", },
806 {},
807};
808MODULE_DEVICE_TABLE(of, xiic_of_match);
809#endif
810
e1d5b659
RR		 811static struct platform_driver xiic_i2c_driver = {
812 .probe = xiic_i2c_probe,
0b255e92 813 .remove = xiic_i2c_remove,
e1d5b659 814 .driver = {
e1d5b659 815 .name = DRIVER_NAME,
3ac0b337 816 .of_match_table = of_match_ptr(xiic_of_match),
e1d5b659
RR		 817 },
818};
819
a3664b51 820module_platform_driver(xiic_i2c_driver);
e1d5b659
RR		 821
822MODULE_AUTHOR("info@mocean-labs.com");
823MODULE_DESCRIPTION("Xilinx I2C bus driver");
824MODULE_LICENSE("GPL v2");
a3664b51 825MODULE_ALIAS("platform:"DRIVER_NAME);
Linux 6.x block layer and io_uring tree(s)