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Merge tag 'please-pull-root_bus_hotplug' of git://git.kernel.org/pub/scm/linux/kernel...
[linux-2.6-block.git] / drivers / i2c / busses / i2c-stu300.c
CommitLineData
18904c0e 1/*
6f535b94 2 * Copyright (C) 2007-2012 ST-Ericsson AB
18904c0e
LW		 3 * License terms: GNU General Public License (GPL) version 2
4 * ST DDC I2C master mode driver, used in e.g. U300 series platforms.
5 * Author: Linus Walleij <linus.walleij@stericsson.com>
6 * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
7 */
8#include <linux/init.h>
9#include <linux/module.h>
10#include <linux/platform_device.h>
11#include <linux/delay.h>
12#include <linux/i2c.h>
13#include <linux/spinlock.h>
14#include <linux/completion.h>
15#include <linux/err.h>
16#include <linux/interrupt.h>
17#include <linux/clk.h>
18#include <linux/io.h>
5a0e3ad6 19#include <linux/slab.h>
8c58d891 20#include <linux/of_i2c.h>
18904c0e
LW		 21
22/* the name of this kernel module */
23#define NAME "stu300"
24
25/* CR (Control Register) 8bit (R/W) */
26#define I2C_CR (0x00000000)
27#define I2C_CR_RESET_VALUE (0x00)
28#define I2C_CR_RESET_UMASK (0x00)
29#define I2C_CR_DDC1_ENABLE (0x80)
30#define I2C_CR_TRANS_ENABLE (0x40)
31#define I2C_CR_PERIPHERAL_ENABLE (0x20)
32#define I2C_CR_DDC2B_ENABLE (0x10)
33#define I2C_CR_START_ENABLE (0x08)
34#define I2C_CR_ACK_ENABLE (0x04)
35#define I2C_CR_STOP_ENABLE (0x02)
36#define I2C_CR_INTERRUPT_ENABLE (0x01)
37/* SR1 (Status Register 1) 8bit (R/-) */
38#define I2C_SR1 (0x00000004)
39#define I2C_SR1_RESET_VALUE (0x00)
40#define I2C_SR1_RESET_UMASK (0x00)
41#define I2C_SR1_EVF_IND (0x80)
42#define I2C_SR1_ADD10_IND (0x40)
43#define I2C_SR1_TRA_IND (0x20)
44#define I2C_SR1_BUSY_IND (0x10)
45#define I2C_SR1_BTF_IND (0x08)
46#define I2C_SR1_ADSL_IND (0x04)
47#define I2C_SR1_MSL_IND (0x02)
48#define I2C_SR1_SB_IND (0x01)
49/* SR2 (Status Register 2) 8bit (R/-) */
50#define I2C_SR2 (0x00000008)
51#define I2C_SR2_RESET_VALUE (0x00)
52#define I2C_SR2_RESET_UMASK (0x40)
53#define I2C_SR2_MASK (0xBF)
54#define I2C_SR2_SCLFAL_IND (0x80)
55#define I2C_SR2_ENDAD_IND (0x20)
56#define I2C_SR2_AF_IND (0x10)
57#define I2C_SR2_STOPF_IND (0x08)
58#define I2C_SR2_ARLO_IND (0x04)
59#define I2C_SR2_BERR_IND (0x02)
60#define I2C_SR2_DDC2BF_IND (0x01)
61/* CCR (Clock Control Register) 8bit (R/W) */
62#define I2C_CCR (0x0000000C)
63#define I2C_CCR_RESET_VALUE (0x00)
64#define I2C_CCR_RESET_UMASK (0x00)
65#define I2C_CCR_MASK (0xFF)
66#define I2C_CCR_FMSM (0x80)
67#define I2C_CCR_CC_MASK (0x7F)
68/* OAR1 (Own Address Register 1) 8bit (R/W) */
69#define I2C_OAR1 (0x00000010)
70#define I2C_OAR1_RESET_VALUE (0x00)
71#define I2C_OAR1_RESET_UMASK (0x00)
72#define I2C_OAR1_ADD_MASK (0xFF)
73/* OAR2 (Own Address Register 2) 8bit (R/W) */
74#define I2C_OAR2 (0x00000014)
75#define I2C_OAR2_RESET_VALUE (0x40)
76#define I2C_OAR2_RESET_UMASK (0x19)
77#define I2C_OAR2_MASK (0xE6)
78#define I2C_OAR2_FR_25_10MHZ (0x00)
79#define I2C_OAR2_FR_10_1667MHZ (0x20)
80#define I2C_OAR2_FR_1667_2667MHZ (0x40)
81#define I2C_OAR2_FR_2667_40MHZ (0x60)
82#define I2C_OAR2_FR_40_5333MHZ (0x80)
83#define I2C_OAR2_FR_5333_66MHZ (0xA0)
84#define I2C_OAR2_FR_66_80MHZ (0xC0)
85#define I2C_OAR2_FR_80_100MHZ (0xE0)
86#define I2C_OAR2_FR_MASK (0xE0)
87#define I2C_OAR2_ADD_MASK (0x06)
88/* DR (Data Register) 8bit (R/W) */
89#define I2C_DR (0x00000018)
90#define I2C_DR_RESET_VALUE (0x00)
91#define I2C_DR_RESET_UMASK (0xFF)
92#define I2C_DR_D_MASK (0xFF)
93/* ECCR (Extended Clock Control Register) 8bit (R/W) */
94#define I2C_ECCR (0x0000001C)
95#define I2C_ECCR_RESET_VALUE (0x00)
96#define I2C_ECCR_RESET_UMASK (0xE0)
97#define I2C_ECCR_MASK (0x1F)
98#define I2C_ECCR_CC_MASK (0x1F)
99
100/*
101 * These events are more or less responses to commands
102 * sent into the hardware, presumably reflecting the state
103 * of an internal state machine.
104 */
105enum stu300_event {
106 STU300_EVENT_NONE = 0,
107 STU300_EVENT_1,
108 STU300_EVENT_2,
109 STU300_EVENT_3,
110 STU300_EVENT_4,
111 STU300_EVENT_5,
112 STU300_EVENT_6,
113 STU300_EVENT_7,
114 STU300_EVENT_8,
115 STU300_EVENT_9
116};
117
118enum stu300_error {
119 STU300_ERROR_NONE = 0,
120 STU300_ERROR_ACKNOWLEDGE_FAILURE,
121 STU300_ERROR_BUS_ERROR,
c37faafa
LW		 122 STU300_ERROR_ARBITRATION_LOST,
123 STU300_ERROR_UNKNOWN
18904c0e
LW		 124};
125
126/* timeout waiting for the controller to respond */
127#define STU300_TIMEOUT (msecs_to_jiffies(1000))
128
129/*
130 * The number of address send athemps tried before giving up.
131 * If the first one failes it seems like 5 to 8 attempts are required.
132 */
c37faafa 133#define NUM_ADDR_RESEND_ATTEMPTS 12
18904c0e
LW		 134
135/* I2C clock speed, in Hz 0-400kHz*/
136static unsigned int scl_frequency = 100000;
137module_param(scl_frequency, uint, 0644);
138
139/**
140 * struct stu300_dev - the stu300 driver state holder
141 * @pdev: parent platform device
142 * @adapter: corresponding I2C adapter
18904c0e
LW		 143 * @clk: hardware block clock
144 * @irq: assigned interrupt line
145 * @cmd_issue_lock: this locks the following cmd_ variables
146 * @cmd_complete: acknowledge completion for an I2C command
147 * @cmd_event: expected event coming in as a response to a command
148 * @cmd_err: error code as response to a command
149 * @speed: current bus speed in Hz
150 * @msg_index: index of current message
151 * @msg_len: length of current message
152 */
c37faafa 153
18904c0e
LW		 154struct stu300_dev {
155 struct platform_device *pdev;
156 struct i2c_adapter adapter;
18904c0e
LW		 157 void __iomem *virtbase;
158 struct clk *clk;
159 int irq;
160 spinlock_t cmd_issue_lock;
161 struct completion cmd_complete;
162 enum stu300_event cmd_event;
163 enum stu300_error cmd_err;
164 unsigned int speed;
165 int msg_index;
166 int msg_len;
167};
168
169/* Local forward function declarations */
170static int stu300_init_hw(struct stu300_dev *dev);
171
172/*
173 * The block needs writes in both MSW and LSW in order
174 * for all data lines to reach their destination.
175 */
176static inline void stu300_wr8(u32 value, void __iomem *address)
177{
178 writel((value << 16) | value, address);
179}
180
181/*
182 * This merely masks off the duplicates which appear
183 * in bytes 1-3. You _MUST_ use 32-bit bus access on this
184 * device, else it will not work.
185 */
186static inline u32 stu300_r8(void __iomem *address)
187{
188 return readl(address) & 0x000000FFU;
189}
190
c37faafa
LW		 191static void stu300_irq_enable(struct stu300_dev *dev)
192{
193 u32 val;
194 val = stu300_r8(dev->virtbase + I2C_CR);
195 val |= I2C_CR_INTERRUPT_ENABLE;
196 /* Twice paranoia (possible HW glitch) */
197 stu300_wr8(val, dev->virtbase + I2C_CR);
198 stu300_wr8(val, dev->virtbase + I2C_CR);
199}
200
201static void stu300_irq_disable(struct stu300_dev *dev)
202{
203 u32 val;
204 val = stu300_r8(dev->virtbase + I2C_CR);
205 val &= ~I2C_CR_INTERRUPT_ENABLE;
206 /* Twice paranoia (possible HW glitch) */
207 stu300_wr8(val, dev->virtbase + I2C_CR);
208 stu300_wr8(val, dev->virtbase + I2C_CR);
209}
210
211
18904c0e
LW		 212/*
213 * Tells whether a certain event or events occurred in
214 * response to a command. The events represent states in
215 * the internal state machine of the hardware. The events
216 * are not very well described in the hardware
217 * documentation and can only be treated as abstract state
218 * machine states.
219 *
c37faafa
LW		 220 * @ret 0 = event has not occurred or unknown error, any
221 * other value means the correct event occurred or an error.
18904c0e 222 */
c37faafa 223
18904c0e
LW		 224static int stu300_event_occurred(struct stu300_dev *dev,
225 enum stu300_event mr_event) {
226 u32 status1;
227 u32 status2;
228
229 /* What event happened? */
230 status1 = stu300_r8(dev->virtbase + I2C_SR1);
c37faafa 231
18904c0e
LW		 232 if (!(status1 & I2C_SR1_EVF_IND))
233 /* No event at all */
234 return 0;
c37faafa 235
18904c0e
LW		 236 status2 = stu300_r8(dev->virtbase + I2C_SR2);
237
c37faafa
LW		 238 /* Block any multiple interrupts */
239 stu300_irq_disable(dev);
240
241 /* Check for errors first */
242 if (status2 & I2C_SR2_AF_IND) {
243 dev->cmd_err = STU300_ERROR_ACKNOWLEDGE_FAILURE;
244 return 1;
245 } else if (status2 & I2C_SR2_BERR_IND) {
246 dev->cmd_err = STU300_ERROR_BUS_ERROR;
247 return 1;
248 } else if (status2 & I2C_SR2_ARLO_IND) {
249 dev->cmd_err = STU300_ERROR_ARBITRATION_LOST;
250 return 1;
251 }
252
18904c0e
LW		 253 switch (mr_event) {
254 case STU300_EVENT_1:
255 if (status1 & I2C_SR1_ADSL_IND)
256 return 1;
257 break;
258 case STU300_EVENT_2:
259 case STU300_EVENT_3:
260 case STU300_EVENT_7:
261 case STU300_EVENT_8:
262 if (status1 & I2C_SR1_BTF_IND) {
18904c0e
LW		 263 return 1;
264 }
265 break;
266 case STU300_EVENT_4:
267 if (status2 & I2C_SR2_STOPF_IND)
268 return 1;
269 break;
270 case STU300_EVENT_5:
271 if (status1 & I2C_SR1_SB_IND)
272 /* Clear start bit */
273 return 1;
274 break;
275 case STU300_EVENT_6:
276 if (status2 & I2C_SR2_ENDAD_IND) {
277 /* First check for any errors */
18904c0e
LW		 278 return 1;
279 }
280 break;
281 case STU300_EVENT_9:
282 if (status1 & I2C_SR1_ADD10_IND)
283 return 1;
284 break;
285 default:
286 break;
287 }
c37faafa
LW		 288 /* If we get here, we're on thin ice.
289 * Here we are in a status where we have
290 * gotten a response that does not match
291 * what we requested.
292 */
293 dev->cmd_err = STU300_ERROR_UNKNOWN;
294 dev_err(&dev->pdev->dev,
295 "Unhandled interrupt! %d sr1: 0x%x sr2: 0x%x\n",
296 mr_event, status1, status2);
18904c0e
LW		 297 return 0;
298}
299
300static irqreturn_t stu300_irh(int irq, void *data)
301{
302 struct stu300_dev *dev = data;
303 int res;
304
c37faafa
LW		 305 /* Just make sure that the block is clocked */
306 clk_enable(dev->clk);
307
18904c0e
LW		 308 /* See if this was what we were waiting for */
309 spin_lock(&dev->cmd_issue_lock);
c37faafa
LW		 310
311 res = stu300_event_occurred(dev, dev->cmd_event);
312 if (res || dev->cmd_err != STU300_ERROR_NONE)
313 complete(&dev->cmd_complete);
314
18904c0e 315 spin_unlock(&dev->cmd_issue_lock);
c37faafa
LW		 316
317 clk_disable(dev->clk);
318
18904c0e
LW		 319 return IRQ_HANDLED;
320}
321
322/*
323 * Sends a command and then waits for the bits masked by *flagmask*
324 * to go high or low by IRQ awaiting.
325 */
326static int stu300_start_and_await_event(struct stu300_dev *dev,
327 u8 cr_value,
328 enum stu300_event mr_event)
329{
330 int ret;
331
332 if (unlikely(irqs_disabled())) {
333 /* TODO: implement polling for this case if need be. */
334 WARN(1, "irqs are disabled, cannot poll for event\n");
335 return -EIO;
336 }
337
338 /* Lock command issue, fill in an event we wait for */
339 spin_lock_irq(&dev->cmd_issue_lock);
340 init_completion(&dev->cmd_complete);
341 dev->cmd_err = STU300_ERROR_NONE;
342 dev->cmd_event = mr_event;
343 spin_unlock_irq(&dev->cmd_issue_lock);
344
345 /* Turn on interrupt, send command and wait. */
346 cr_value |= I2C_CR_INTERRUPT_ENABLE;
347 stu300_wr8(cr_value, dev->virtbase + I2C_CR);
348 ret = wait_for_completion_interruptible_timeout(&dev->cmd_complete,
349 STU300_TIMEOUT);
18904c0e
LW		 350 if (ret < 0) {
351 dev_err(&dev->pdev->dev,
352 "wait_for_completion_interruptible_timeout() "
353 "returned %d waiting for event %04x\n", ret, mr_event);
354 return ret;
355 }
356
357 if (ret == 0) {
358 dev_err(&dev->pdev->dev, "controller timed out "
359 "waiting for event %d, reinit hardware\n", mr_event);
360 (void) stu300_init_hw(dev);
361 return -ETIMEDOUT;
362 }
363
364 if (dev->cmd_err != STU300_ERROR_NONE) {
365 dev_err(&dev->pdev->dev, "controller (start) "
366 "error %d waiting for event %d, reinit hardware\n",
367 dev->cmd_err, mr_event);
368 (void) stu300_init_hw(dev);
369 return -EIO;
370 }
371
372 return 0;
373}
374
375/*
376 * This waits for a flag to be set, if it is not set on entry, an interrupt is
377 * configured to wait for the flag using a completion.
378 */
379static int stu300_await_event(struct stu300_dev *dev,
380 enum stu300_event mr_event)
381{
382 int ret;
18904c0e
LW		 383
384 if (unlikely(irqs_disabled())) {
385 /* TODO: implement polling for this case if need be. */
386 dev_err(&dev->pdev->dev, "irqs are disabled on this "
387 "system!\n");
388 return -EIO;
389 }
390
391 /* Is it already here? */
392 spin_lock_irq(&dev->cmd_issue_lock);
393 dev->cmd_err = STU300_ERROR_NONE;
18904c0e
LW		 394 dev->cmd_event = mr_event;
395
c37faafa 396 init_completion(&dev->cmd_complete);
18904c0e 397
c37faafa
LW		 398 /* Turn on the I2C interrupt for current operation */
399 stu300_irq_enable(dev);
18904c0e
LW		 400
401 /* Unlock the command block and wait for the event to occur */
402 spin_unlock_irq(&dev->cmd_issue_lock);
c37faafa 403
18904c0e
LW		 404 ret = wait_for_completion_interruptible_timeout(&dev->cmd_complete,
405 STU300_TIMEOUT);
18904c0e
LW		 406 if (ret < 0) {
407 dev_err(&dev->pdev->dev,
408 "wait_for_completion_interruptible_timeout()"
409 "returned %d waiting for event %04x\n", ret, mr_event);
410 return ret;
411 }
412
413 if (ret == 0) {
414 if (mr_event != STU300_EVENT_6) {
415 dev_err(&dev->pdev->dev, "controller "
416 "timed out waiting for event %d, reinit "
417 "hardware\n", mr_event);
418 (void) stu300_init_hw(dev);
419 }
420 return -ETIMEDOUT;
421 }
422
18904c0e
LW		 423 if (dev->cmd_err != STU300_ERROR_NONE) {
424 if (mr_event != STU300_EVENT_6) {
425 dev_err(&dev->pdev->dev, "controller "
426 "error (await_event) %d waiting for event %d, "
427 "reinit hardware\n", dev->cmd_err, mr_event);
428 (void) stu300_init_hw(dev);
429 }
430 return -EIO;
431 }
432
433 return 0;
434}
435
436/*
437 * Waits for the busy bit to go low by repeated polling.
438 */
439#define BUSY_RELEASE_ATTEMPTS 10
440static int stu300_wait_while_busy(struct stu300_dev *dev)
441{
442 unsigned long timeout;
443 int i;
444
445 for (i = 0; i < BUSY_RELEASE_ATTEMPTS; i++) {
446 timeout = jiffies + STU300_TIMEOUT;
447
448 while (!time_after(jiffies, timeout)) {
449 /* Is not busy? */
450 if ((stu300_r8(dev->virtbase + I2C_SR1) &
451 I2C_SR1_BUSY_IND) == 0)
452 return 0;
453 msleep(1);
454 }
455
456 dev_err(&dev->pdev->dev, "transaction timed out "
457 "waiting for device to be free (not busy). "
458 "Attempt: %d\n", i+1);
459
460 dev_err(&dev->pdev->dev, "base address = "
461 "0x%08x, reinit hardware\n", (u32) dev->virtbase);
462
463 (void) stu300_init_hw(dev);
464 }
465
466 dev_err(&dev->pdev->dev, "giving up after %d attempts "
467 "to reset the bus.\n", BUSY_RELEASE_ATTEMPTS);
468
469 return -ETIMEDOUT;
470}
471
472struct stu300_clkset {
473 unsigned long rate;
474 u32 setting;
475};
476
477static const struct stu300_clkset stu300_clktable[] = {
c37faafa
LW		 478 { 0, 0xFFU },
479 { 2500000, I2C_OAR2_FR_25_10MHZ },
480 { 10000000, I2C_OAR2_FR_10_1667MHZ },
481 { 16670000, I2C_OAR2_FR_1667_2667MHZ },
482 { 26670000, I2C_OAR2_FR_2667_40MHZ },
483 { 40000000, I2C_OAR2_FR_40_5333MHZ },
484 { 53330000, I2C_OAR2_FR_5333_66MHZ },
485 { 66000000, I2C_OAR2_FR_66_80MHZ },
486 { 80000000, I2C_OAR2_FR_80_100MHZ },
18904c0e
LW		 487 { 100000000, 0xFFU },
488};
489
c37faafa 490
18904c0e
LW		 491static int stu300_set_clk(struct stu300_dev *dev, unsigned long clkrate)
492{
493
494 u32 val;
495 int i = 0;
496
25985edc 497 /* Locate the appropriate clock setting */
42df64b1 498 while (i < ARRAY_SIZE(stu300_clktable) - 1 &&
18904c0e
LW		 499 stu300_clktable[i].rate < clkrate)
500 i++;
501
502 if (stu300_clktable[i].setting == 0xFFU) {
503 dev_err(&dev->pdev->dev, "too %s clock rate requested "
504 "(%lu Hz).\n", i ? "high" : "low", clkrate);
505 return -EINVAL;
506 }
507
508 stu300_wr8(stu300_clktable[i].setting,
509 dev->virtbase + I2C_OAR2);
510
511 dev_dbg(&dev->pdev->dev, "Clock rate %lu Hz, I2C bus speed %d Hz "
512 "virtbase %p\n", clkrate, dev->speed, dev->virtbase);
513
514 if (dev->speed > 100000)
515 /* Fast Mode I2C */
c37faafa 516 val = ((clkrate/dev->speed) - 9)/3 + 1;
18904c0e
LW		 517 else
518 /* Standard Mode I2C */
c37faafa 519 val = ((clkrate/dev->speed) - 7)/2 + 1;
18904c0e
LW		 520
521 /* According to spec the divider must be > 2 */
522 if (val < 0x002) {
523 dev_err(&dev->pdev->dev, "too low clock rate (%lu Hz).\n",
524 clkrate);
525 return -EINVAL;
526 }
527
528 /* We have 12 bits clock divider only! */
529 if (val & 0xFFFFF000U) {
530 dev_err(&dev->pdev->dev, "too high clock rate (%lu Hz).\n",
531 clkrate);
532 return -EINVAL;
533 }
534
535 if (dev->speed > 100000) {
536 /* CC6..CC0 */
537 stu300_wr8((val & I2C_CCR_CC_MASK) | I2C_CCR_FMSM,
538 dev->virtbase + I2C_CCR);
539 dev_dbg(&dev->pdev->dev, "set clock divider to 0x%08x, "
540 "Fast Mode I2C\n", val);
541 } else {
542 /* CC6..CC0 */
543 stu300_wr8((val & I2C_CCR_CC_MASK),
544 dev->virtbase + I2C_CCR);
545 dev_dbg(&dev->pdev->dev, "set clock divider to "
546 "0x%08x, Standard Mode I2C\n", val);
547 }
548
549 /* CC11..CC7 */
550 stu300_wr8(((val >> 7) & 0x1F),
551 dev->virtbase + I2C_ECCR);
552
553 return 0;
554}
555
556
557static int stu300_init_hw(struct stu300_dev *dev)
558{
559 u32 dummy;
560 unsigned long clkrate;
561 int ret;
562
563 /* Disable controller */
564 stu300_wr8(0x00, dev->virtbase + I2C_CR);
565 /*
566 * Set own address to some default value (0x00).
567 * We do not support slave mode anyway.
568 */
569 stu300_wr8(0x00, dev->virtbase + I2C_OAR1);
570 /*
571 * The I2C controller only operates properly in 26 MHz but we
572 * program this driver as if we didn't know. This will also set the two
573 * high bits of the own address to zero as well.
574 * There is no known hardware issue with running in 13 MHz
575 * However, speeds over 200 kHz are not used.
576 */
577 clkrate = clk_get_rate(dev->clk);
578 ret = stu300_set_clk(dev, clkrate);
c37faafa 579
18904c0e
LW		 580 if (ret)
581 return ret;
582 /*
583 * Enable block, do it TWICE (hardware glitch)
584 * Setting bit 7 can enable DDC mode. (Not used currently.)
585 */
586 stu300_wr8(I2C_CR_PERIPHERAL_ENABLE,
587 dev->virtbase + I2C_CR);
588 stu300_wr8(I2C_CR_PERIPHERAL_ENABLE,
589 dev->virtbase + I2C_CR);
590 /* Make a dummy read of the status register SR1 & SR2 */
591 dummy = stu300_r8(dev->virtbase + I2C_SR2);
592 dummy = stu300_r8(dev->virtbase + I2C_SR1);
593
594 return 0;
595}
596
597
598
599/* Send slave address. */
600static int stu300_send_address(struct stu300_dev *dev,
601 struct i2c_msg *msg, int resend)
602{
603 u32 val;
604 int ret;
605
606 if (msg->flags & I2C_M_TEN)
607 /* This is probably how 10 bit addresses look */
608 val = (0xf0 | (((u32) msg->addr & 0x300) >> 7)) &
609 I2C_DR_D_MASK;
610 else
611 val = ((msg->addr << 1) & I2C_DR_D_MASK);
612
613 if (msg->flags & I2C_M_RD) {
614 /* This is the direction bit */
615 val |= 0x01;
616 if (resend)
617 dev_dbg(&dev->pdev->dev, "read resend\n");
618 } else if (resend)
619 dev_dbg(&dev->pdev->dev, "write resend\n");
620 stu300_wr8(val, dev->virtbase + I2C_DR);
621
622 /* For 10bit addressing, await 10bit request (EVENT 9) */
623 if (msg->flags & I2C_M_TEN) {
624 ret = stu300_await_event(dev, STU300_EVENT_9);
625 /*
626 * The slave device wants a 10bit address, send the rest
627 * of the bits (the LSBits)
628 */
629 val = msg->addr & I2C_DR_D_MASK;
630 /* This clears "event 9" */
631 stu300_wr8(val, dev->virtbase + I2C_DR);
632 if (ret != 0)
633 return ret;
634 }
635 /* FIXME: Why no else here? two events for 10bit?
636 * Await event 6 (normal) or event 9 (10bit)
637 */
638
639 if (resend)
640 dev_dbg(&dev->pdev->dev, "await event 6\n");
641 ret = stu300_await_event(dev, STU300_EVENT_6);
642
643 /*
25985edc 644 * Clear any pending EVENT 6 no matter what happened during
18904c0e
LW		 645 * await_event.
646 */
647 val = stu300_r8(dev->virtbase + I2C_CR);
648 val |= I2C_CR_PERIPHERAL_ENABLE;
649 stu300_wr8(val, dev->virtbase + I2C_CR);
650
651 return ret;
652}
653
654static int stu300_xfer_msg(struct i2c_adapter *adap,
655 struct i2c_msg *msg, int stop)
656{
657 u32 cr;
658 u32 val;
659 u32 i;
660 int ret;
661 int attempts = 0;
662 struct stu300_dev *dev = i2c_get_adapdata(adap);
663
18904c0e
LW		 664 clk_enable(dev->clk);
665
666 /* Remove this if (0) to trace each and every message. */
667 if (0) {
668 dev_dbg(&dev->pdev->dev, "I2C message to: 0x%04x, len: %d, "
669 "flags: 0x%04x, stop: %d\n",
670 msg->addr, msg->len, msg->flags, stop);
671 }
672
673 /* Zero-length messages are not supported by this hardware */
674 if (msg->len == 0) {
675 ret = -EINVAL;
676 goto exit_disable;
677 }
678
679 /*
680 * For some reason, sending the address sometimes fails when running
681 * on the 13 MHz clock. No interrupt arrives. This is a work around,
682 * which tries to restart and send the address up to 10 times before
683 * really giving up. Usually 5 to 8 attempts are enough.
684 */
685 do {
686 if (attempts)
687 dev_dbg(&dev->pdev->dev, "wait while busy\n");
688 /* Check that the bus is free, or wait until some timeout */
689 ret = stu300_wait_while_busy(dev);
690 if (ret != 0)
691 goto exit_disable;
692
693 if (attempts)
694 dev_dbg(&dev->pdev->dev, "re-int hw\n");
695 /*
696 * According to ST, there is no problem if the clock is
697 * changed between 13 and 26 MHz during a transfer.
698 */
699 ret = stu300_init_hw(dev);
700 if (ret)
701 goto exit_disable;
702
703 /* Send a start condition */
704 cr = I2C_CR_PERIPHERAL_ENABLE;
705 /* Setting the START bit puts the block in master mode */
706 if (!(msg->flags & I2C_M_NOSTART))
707 cr |= I2C_CR_START_ENABLE;
708 if ((msg->flags & I2C_M_RD) && (msg->len > 1))
709 /* On read more than 1 byte, we need ack. */
710 cr |= I2C_CR_ACK_ENABLE;
711 /* Check that it gets through */
712 if (!(msg->flags & I2C_M_NOSTART)) {
713 if (attempts)
714 dev_dbg(&dev->pdev->dev, "send start event\n");
715 ret = stu300_start_and_await_event(dev, cr,
716 STU300_EVENT_5);
717 }
718
719 if (attempts)
720 dev_dbg(&dev->pdev->dev, "send address\n");
721
722 if (ret == 0)
723 /* Send address */
724 ret = stu300_send_address(dev, msg, attempts != 0);
725
726 if (ret != 0) {
727 attempts++;
728 dev_dbg(&dev->pdev->dev, "failed sending address, "
729 "retrying. Attempt: %d msg_index: %d/%d\n",
730 attempts, dev->msg_index, dev->msg_len);
731 }
732
733 } while (ret != 0 && attempts < NUM_ADDR_RESEND_ATTEMPTS);
734
735 if (attempts < NUM_ADDR_RESEND_ATTEMPTS && attempts > 0) {
736 dev_dbg(&dev->pdev->dev, "managed to get address "
c37faafa 737 "through after %d attempts\n", attempts);
18904c0e
LW		 738 } else if (attempts == NUM_ADDR_RESEND_ATTEMPTS) {
739 dev_dbg(&dev->pdev->dev, "I give up, tried %d times "
c37faafa
LW		 740 "to resend address.\n",
741 NUM_ADDR_RESEND_ATTEMPTS);
18904c0e
LW		 742 goto exit_disable;
743 }
744
c37faafa 745
18904c0e
LW		 746 if (msg->flags & I2C_M_RD) {
747 /* READ: we read the actual bytes one at a time */
748 for (i = 0; i < msg->len; i++) {
749 if (i == msg->len-1) {
750 /*
751 * Disable ACK and set STOP condition before
752 * reading last byte
753 */
754 val = I2C_CR_PERIPHERAL_ENABLE;
755
756 if (stop)
757 val |= I2C_CR_STOP_ENABLE;
758
759 stu300_wr8(val,
760 dev->virtbase + I2C_CR);
761 }
762 /* Wait for this byte... */
763 ret = stu300_await_event(dev, STU300_EVENT_7);
764 if (ret != 0)
765 goto exit_disable;
766 /* This clears event 7 */
767 msg->buf[i] = (u8) stu300_r8(dev->virtbase + I2C_DR);
768 }
769 } else {
770 /* WRITE: we send the actual bytes one at a time */
771 for (i = 0; i < msg->len; i++) {
772 /* Write the byte */
773 stu300_wr8(msg->buf[i],
774 dev->virtbase + I2C_DR);
775 /* Check status */
776 ret = stu300_await_event(dev, STU300_EVENT_8);
777 /* Next write to DR will clear event 8 */
778 if (ret != 0) {
779 dev_err(&dev->pdev->dev, "error awaiting "
780 "event 8 (%d)\n", ret);
781 goto exit_disable;
782 }
783 }
784 /* Check NAK */
785 if (!(msg->flags & I2C_M_IGNORE_NAK)) {
786 if (stu300_r8(dev->virtbase + I2C_SR2) &
787 I2C_SR2_AF_IND) {
788 dev_err(&dev->pdev->dev, "I2C payload "
789 "send returned NAK!\n");
790 ret = -EIO;
791 goto exit_disable;
792 }
793 }
794 if (stop) {
795 /* Send stop condition */
796 val = I2C_CR_PERIPHERAL_ENABLE;
797 val |= I2C_CR_STOP_ENABLE;
798 stu300_wr8(val, dev->virtbase + I2C_CR);
799 }
800 }
801
802 /* Check that the bus is free, or wait until some timeout occurs */
803 ret = stu300_wait_while_busy(dev);
804 if (ret != 0) {
805 dev_err(&dev->pdev->dev, "timout waiting for transfer "
806 "to commence.\n");
807 goto exit_disable;
808 }
809
810 /* Dummy read status registers */
811 val = stu300_r8(dev->virtbase + I2C_SR2);
812 val = stu300_r8(dev->virtbase + I2C_SR1);
813 ret = 0;
814
815 exit_disable:
816 /* Disable controller */
817 stu300_wr8(0x00, dev->virtbase + I2C_CR);
818 clk_disable(dev->clk);
819 return ret;
820}
821
822static int stu300_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
823 int num)
824{
825 int ret = -1;
826 int i;
c37faafa 827
18904c0e
LW		 828 struct stu300_dev *dev = i2c_get_adapdata(adap);
829 dev->msg_len = num;
c37faafa 830
18904c0e
LW		 831 for (i = 0; i < num; i++) {
832 /*
833 * Another driver appears to send stop for each message,
834 * here we only do that for the last message. Possibly some
835 * peripherals require this behaviour, then their drivers
836 * have to send single messages in order to get "stop" for
837 * each message.
838 */
839 dev->msg_index = i;
840
841 ret = stu300_xfer_msg(adap, &msgs[i], (i == (num - 1)));
c37faafa 842
18904c0e
LW		 843 if (ret != 0) {
844 num = ret;
845 break;
846 }
847 }
848
849 return num;
850}
851
852static u32 stu300_func(struct i2c_adapter *adap)
853{
854 /* This is the simplest thing you can think of... */
855 return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR;
856}
857
858static const struct i2c_algorithm stu300_algo = {
859 .master_xfer = stu300_xfer,
860 .functionality = stu300_func,
861};
862
863static int __init
864stu300_probe(struct platform_device *pdev)
865{
866 struct stu300_dev *dev;
867 struct i2c_adapter *adap;
868 struct resource *res;
869 int bus_nr;
870 int ret = 0;
871
6f535b94 872 dev = devm_kzalloc(&pdev->dev, sizeof(struct stu300_dev), GFP_KERNEL);
18904c0e
LW		 873 if (!dev) {
874 dev_err(&pdev->dev, "could not allocate device struct\n");
6f535b94 875 return -ENOMEM;
18904c0e
LW		 876 }
877
878 bus_nr = pdev->id;
2165f836 879 dev->clk = devm_clk_get(&pdev->dev, NULL);
18904c0e 880 if (IS_ERR(dev->clk)) {
18904c0e 881 dev_err(&pdev->dev, "could not retrieve i2c bus clock\n");
6f535b94 882 return PTR_ERR(dev->clk);
18904c0e
LW		 883 }
884
885 dev->pdev = pdev;
18904c0e 886 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
6f535b94
LW		 887 if (!res)
888 return -ENOENT;
18904c0e 889
84dbf809 890 dev->virtbase = devm_ioremap_resource(&pdev->dev, res);
18904c0e
LW		 891 dev_dbg(&pdev->dev, "initialize bus device I2C%d on virtual "
892 "base %p\n", bus_nr, dev->virtbase);
84dbf809
TR		 893 if (IS_ERR(dev->virtbase))
894 return PTR_ERR(dev->virtbase);
18904c0e
LW		 895
896 dev->irq = platform_get_irq(pdev, 0);
6f535b94
LW		 897 ret = devm_request_irq(&pdev->dev, dev->irq, stu300_irh, 0, NAME, dev);
898 if (ret < 0)
899 return ret;
18904c0e
LW		 900
901 dev->speed = scl_frequency;
902
a3f24c0d 903 clk_prepare_enable(dev->clk);
18904c0e
LW		 904 ret = stu300_init_hw(dev);
905 clk_disable(dev->clk);
18904c0e
LW		 906 if (ret != 0) {
907 dev_err(&dev->pdev->dev, "error initializing hardware.\n");
6f535b94 908 return -EIO;
18904c0e
LW		 909 }
910
911 /* IRQ event handling initialization */
912 spin_lock_init(&dev->cmd_issue_lock);
913 dev->cmd_event = STU300_EVENT_NONE;
914 dev->cmd_err = STU300_ERROR_NONE;
915
916 adap = &dev->adapter;
917 adap->owner = THIS_MODULE;
918 /* DDC class but actually often used for more generic I2C */
919 adap->class = I2C_CLASS_DDC;
f10820e4 920 strlcpy(adap->name, "ST Microelectronics DDC I2C adapter",
18904c0e
LW		 921 sizeof(adap->name));
922 adap->nr = bus_nr;
923 adap->algo = &stu300_algo;
924 adap->dev.parent = &pdev->dev;
8c58d891 925 adap->dev.of_node = pdev->dev.of_node;
18904c0e
LW		 926 i2c_set_adapdata(adap, dev);
927
928 /* i2c device drivers may be active on return from add_adapter() */
929 ret = i2c_add_numbered_adapter(adap);
930 if (ret) {
6f535b94 931 dev_err(&pdev->dev, "failure adding ST Micro DDC "
18904c0e 932 "I2C adapter\n");
6f535b94 933 return ret;
18904c0e 934 }
18904c0e 935
6f535b94 936 platform_set_drvdata(pdev, dev);
8c58d891
LW		 937 dev_info(&pdev->dev, "ST DDC I2C @ %p, irq %d\n",
938 dev->virtbase, dev->irq);
939 of_i2c_register_devices(adap);
940
6f535b94 941 return 0;
18904c0e
LW		 942}
943
944#ifdef CONFIG_PM
4aacc4b1 945static int stu300_suspend(struct device *device)
18904c0e 946{
4aacc4b1 947 struct stu300_dev *dev = dev_get_drvdata(device);
18904c0e
LW		 948
949 /* Turn off everything */
950 stu300_wr8(0x00, dev->virtbase + I2C_CR);
951 return 0;
952}
953
4aacc4b1 954static int stu300_resume(struct device *device)
18904c0e
LW		 955{
956 int ret = 0;
4aacc4b1 957 struct stu300_dev *dev = dev_get_drvdata(device);
18904c0e
LW		 958
959 clk_enable(dev->clk);
960 ret = stu300_init_hw(dev);
961 clk_disable(dev->clk);
962
963 if (ret != 0)
4aacc4b1 964 dev_err(device, "error re-initializing hardware.\n");
18904c0e
LW		 965 return ret;
966}
4aacc4b1
RW		 967
968static SIMPLE_DEV_PM_OPS(stu300_pm, stu300_suspend, stu300_resume);
969#define STU300_I2C_PM (&stu300_pm)
18904c0e 970#else
4aacc4b1 971#define STU300_I2C_PM NULL
18904c0e
LW		 972#endif
973
974static int __exit
975stu300_remove(struct platform_device *pdev)
976{
977 struct stu300_dev *dev = platform_get_drvdata(pdev);
978
979 i2c_del_adapter(&dev->adapter);
980 /* Turn off everything */
981 stu300_wr8(0x00, dev->virtbase + I2C_CR);
18904c0e
LW		 982 return 0;
983}
984
8c58d891
LW		 985static const struct of_device_id stu300_dt_match[] = {
986 { .compatible = "st,ddci2c" },
987 {},
988};
989
18904c0e
LW		 990static struct platform_driver stu300_i2c_driver = {
991 .driver = {
992 .name = NAME,
993 .owner = THIS_MODULE,
4aacc4b1 994 .pm = STU300_I2C_PM,
8c58d891 995 .of_match_table = stu300_dt_match,
18904c0e
LW		 996 },
997 .remove = __exit_p(stu300_remove),
18904c0e
LW		 998
999};
1000
1001static int __init stu300_init(void)
1002{
1003 return platform_driver_probe(&stu300_i2c_driver, stu300_probe);
1004}
1005
1006static void __exit stu300_exit(void)
1007{
1008 platform_driver_unregister(&stu300_i2c_driver);
1009}
1010
1011/*
1012 * The systems using this bus often have very basic devices such
1013 * as regulators on the I2C bus, so this needs to be loaded early.
1014 * Therefore it is registered in the subsys_initcall().
1015 */
1016subsys_initcall(stu300_init);
1017module_exit(stu300_exit);
1018
1019MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
1020MODULE_DESCRIPTION("ST Micro DDC I2C adapter (" NAME ")");
1021MODULE_LICENSE("GPL");
1022MODULE_ALIAS("platform:" NAME);
Linux 6.x block layer and io_uring tree(s)