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Merge branch 'i2c/for-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa...
[linux-2.6-block.git] / drivers / i2c / busses / i2c-stm32f7.c
CommitLineData
9c41e452 1// SPDX-License-Identifier: GPL-2.0
aeb068c5
PYM		 2/*
3 * Driver for STMicroelectronics STM32F7 I2C controller
4 *
5 * This I2C controller is described in the STM32F75xxx and STM32F74xxx Soc
6 * reference manual.
7 * Please see below a link to the documentation:
8 * http://www.st.com/resource/en/reference_manual/dm00124865.pdf
9 *
10 * Copyright (C) M'boumba Cedric Madianga 2017
9c41e452 11 * Copyright (C) STMicroelectronics 2017
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PYM		 12 * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
13 *
14 * This driver is based on i2c-stm32f4.c
15 *
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PYM		 16 */
17#include <linux/clk.h>
18#include <linux/delay.h>
19#include <linux/err.h>
20#include <linux/i2c.h>
6af07719 21#include <linux/i2c-smbus.h>
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PYM		 22#include <linux/interrupt.h>
23#include <linux/io.h>
24#include <linux/iopoll.h>
cb944fb9 25#include <linux/mfd/syscon.h>
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PYM		 26#include <linux/module.h>
27#include <linux/of.h>
28#include <linux/of_address.h>
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PYM		 29#include <linux/of_platform.h>
30#include <linux/platform_device.h>
4e7bca6f
PYM		 31#include <linux/pinctrl/consumer.h>
32#include <linux/pm_runtime.h>
419be8e1 33#include <linux/pm_wakeirq.h>
cb944fb9 34#include <linux/regmap.h>
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PYM		 35#include <linux/reset.h>
36#include <linux/slab.h>
37
38#include "i2c-stm32.h"
39
40/* STM32F7 I2C registers */
41#define STM32F7_I2C_CR1 0x00
42#define STM32F7_I2C_CR2 0x04
60d609f3
PYM		 43#define STM32F7_I2C_OAR1 0x08
44#define STM32F7_I2C_OAR2 0x0C
9e48155f 45#define STM32F7_I2C_PECR 0x20
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PYM		 46#define STM32F7_I2C_TIMINGR 0x10
47#define STM32F7_I2C_ISR 0x18
48#define STM32F7_I2C_ICR 0x1C
49#define STM32F7_I2C_RXDR 0x24
50#define STM32F7_I2C_TXDR 0x28
51
52/* STM32F7 I2C control 1 */
9e48155f 53#define STM32F7_I2C_CR1_PECEN BIT(23)
6af07719 54#define STM32F7_I2C_CR1_SMBHEN BIT(20)
419be8e1 55#define STM32F7_I2C_CR1_WUPEN BIT(18)
60d609f3 56#define STM32F7_I2C_CR1_SBC BIT(16)
7ecc8cfd
PYM		 57#define STM32F7_I2C_CR1_RXDMAEN BIT(15)
58#define STM32F7_I2C_CR1_TXDMAEN BIT(14)
aeb068c5 59#define STM32F7_I2C_CR1_ANFOFF BIT(12)
3d6a3d3a
AV		 60#define STM32F7_I2C_CR1_DNF_MASK GENMASK(11, 8)
61#define STM32F7_I2C_CR1_DNF(n) (((n) & 0xf) << 8)
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PYM		 62#define STM32F7_I2C_CR1_ERRIE BIT(7)
63#define STM32F7_I2C_CR1_TCIE BIT(6)
64#define STM32F7_I2C_CR1_STOPIE BIT(5)
65#define STM32F7_I2C_CR1_NACKIE BIT(4)
66#define STM32F7_I2C_CR1_ADDRIE BIT(3)
67#define STM32F7_I2C_CR1_RXIE BIT(2)
68#define STM32F7_I2C_CR1_TXIE BIT(1)
69#define STM32F7_I2C_CR1_PE BIT(0)
70#define STM32F7_I2C_ALL_IRQ_MASK (STM32F7_I2C_CR1_ERRIE \
71 | STM32F7_I2C_CR1_TCIE \
72 | STM32F7_I2C_CR1_STOPIE \
73 | STM32F7_I2C_CR1_NACKIE \
74 | STM32F7_I2C_CR1_RXIE \
75 | STM32F7_I2C_CR1_TXIE)
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PYM		 76#define STM32F7_I2C_XFER_IRQ_MASK (STM32F7_I2C_CR1_TCIE \
77 | STM32F7_I2C_CR1_STOPIE \
78 | STM32F7_I2C_CR1_NACKIE \
79 | STM32F7_I2C_CR1_RXIE \
80 | STM32F7_I2C_CR1_TXIE)
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PYM		 81
82/* STM32F7 I2C control 2 */
9e48155f 83#define STM32F7_I2C_CR2_PECBYTE BIT(26)
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PYM		 84#define STM32F7_I2C_CR2_RELOAD BIT(24)
85#define STM32F7_I2C_CR2_NBYTES_MASK GENMASK(23, 16)
86#define STM32F7_I2C_CR2_NBYTES(n) (((n) & 0xff) << 16)
87#define STM32F7_I2C_CR2_NACK BIT(15)
88#define STM32F7_I2C_CR2_STOP BIT(14)
89#define STM32F7_I2C_CR2_START BIT(13)
8c7ecc99
PYM		 90#define STM32F7_I2C_CR2_HEAD10R BIT(12)
91#define STM32F7_I2C_CR2_ADD10 BIT(11)
aeb068c5 92#define STM32F7_I2C_CR2_RD_WRN BIT(10)
8c7ecc99
PYM		 93#define STM32F7_I2C_CR2_SADD10_MASK GENMASK(9, 0)
94#define STM32F7_I2C_CR2_SADD10(n) (((n) & \
95 STM32F7_I2C_CR2_SADD10_MASK))
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PYM		 96#define STM32F7_I2C_CR2_SADD7_MASK GENMASK(7, 1)
97#define STM32F7_I2C_CR2_SADD7(n) (((n) & 0x7f) << 1)
98
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PYM		 99/* STM32F7 I2C Own Address 1 */
100#define STM32F7_I2C_OAR1_OA1EN BIT(15)
101#define STM32F7_I2C_OAR1_OA1MODE BIT(10)
102#define STM32F7_I2C_OAR1_OA1_10_MASK GENMASK(9, 0)
103#define STM32F7_I2C_OAR1_OA1_10(n) (((n) & \
104 STM32F7_I2C_OAR1_OA1_10_MASK))
105#define STM32F7_I2C_OAR1_OA1_7_MASK GENMASK(7, 1)
106#define STM32F7_I2C_OAR1_OA1_7(n) (((n) & 0x7f) << 1)
107#define STM32F7_I2C_OAR1_MASK (STM32F7_I2C_OAR1_OA1_7_MASK \
108 | STM32F7_I2C_OAR1_OA1_10_MASK \
109 | STM32F7_I2C_OAR1_OA1EN \
110 | STM32F7_I2C_OAR1_OA1MODE)
111
112/* STM32F7 I2C Own Address 2 */
113#define STM32F7_I2C_OAR2_OA2EN BIT(15)
114#define STM32F7_I2C_OAR2_OA2MSK_MASK GENMASK(10, 8)
115#define STM32F7_I2C_OAR2_OA2MSK(n) (((n) & 0x7) << 8)
116#define STM32F7_I2C_OAR2_OA2_7_MASK GENMASK(7, 1)
117#define STM32F7_I2C_OAR2_OA2_7(n) (((n) & 0x7f) << 1)
118#define STM32F7_I2C_OAR2_MASK (STM32F7_I2C_OAR2_OA2MSK_MASK \
119 | STM32F7_I2C_OAR2_OA2_7_MASK \
120 | STM32F7_I2C_OAR2_OA2EN)
121
aeb068c5 122/* STM32F7 I2C Interrupt Status */
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PYM		 123#define STM32F7_I2C_ISR_ADDCODE_MASK GENMASK(23, 17)
124#define STM32F7_I2C_ISR_ADDCODE_GET(n) \
125 (((n) & STM32F7_I2C_ISR_ADDCODE_MASK) >> 17)
126#define STM32F7_I2C_ISR_DIR BIT(16)
aeb068c5 127#define STM32F7_I2C_ISR_BUSY BIT(15)
9e48155f 128#define STM32F7_I2C_ISR_PECERR BIT(11)
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PYM		 129#define STM32F7_I2C_ISR_ARLO BIT(9)
130#define STM32F7_I2C_ISR_BERR BIT(8)
131#define STM32F7_I2C_ISR_TCR BIT(7)
132#define STM32F7_I2C_ISR_TC BIT(6)
133#define STM32F7_I2C_ISR_STOPF BIT(5)
134#define STM32F7_I2C_ISR_NACKF BIT(4)
60d609f3 135#define STM32F7_I2C_ISR_ADDR BIT(3)
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PYM		 136#define STM32F7_I2C_ISR_RXNE BIT(2)
137#define STM32F7_I2C_ISR_TXIS BIT(1)
60d609f3 138#define STM32F7_I2C_ISR_TXE BIT(0)
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PYM		 139
140/* STM32F7 I2C Interrupt Clear */
9e48155f 141#define STM32F7_I2C_ICR_PECCF BIT(11)
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PYM		 142#define STM32F7_I2C_ICR_ARLOCF BIT(9)
143#define STM32F7_I2C_ICR_BERRCF BIT(8)
144#define STM32F7_I2C_ICR_STOPCF BIT(5)
145#define STM32F7_I2C_ICR_NACKCF BIT(4)
60d609f3 146#define STM32F7_I2C_ICR_ADDRCF BIT(3)
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PYM		 147
148/* STM32F7 I2C Timing */
149#define STM32F7_I2C_TIMINGR_PRESC(n) (((n) & 0xf) << 28)
150#define STM32F7_I2C_TIMINGR_SCLDEL(n) (((n) & 0xf) << 20)
151#define STM32F7_I2C_TIMINGR_SDADEL(n) (((n) & 0xf) << 16)
152#define STM32F7_I2C_TIMINGR_SCLH(n) (((n) & 0xff) << 8)
153#define STM32F7_I2C_TIMINGR_SCLL(n) ((n) & 0xff)
154
155#define STM32F7_I2C_MAX_LEN 0xff
7ecc8cfd 156#define STM32F7_I2C_DMA_LEN_MIN 0x16
b62590a9
AV		 157enum {
158 STM32F7_SLAVE_HOSTNOTIFY,
159 STM32F7_SLAVE_7_10_BITS_ADDR,
160 STM32F7_SLAVE_7_BITS_ADDR,
161 STM32F7_I2C_MAX_SLAVE
162};
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PYM		 163
164#define STM32F7_I2C_DNF_DEFAULT 0
3d6a3d3a 165#define STM32F7_I2C_DNF_MAX 15
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PYM		 166
167#define STM32F7_I2C_ANALOG_FILTER_ENABLE 1
168#define STM32F7_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */
169#define STM32F7_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */
170
171#define STM32F7_I2C_RISE_TIME_DEFAULT 25 /* ns */
172#define STM32F7_I2C_FALL_TIME_DEFAULT 10 /* ns */
173
174#define STM32F7_PRESC_MAX BIT(4)
175#define STM32F7_SCLDEL_MAX BIT(4)
176#define STM32F7_SDADEL_MAX BIT(4)
177#define STM32F7_SCLH_MAX BIT(8)
178#define STM32F7_SCLL_MAX BIT(8)
179
4e7bca6f
PYM		 180#define STM32F7_AUTOSUSPEND_DELAY (HZ / 100)
181
ea6dd25d
AV		 182/**
183 * struct stm32f7_i2c_regs - i2c f7 registers backup
184 * @cr1: Control register 1
185 * @cr2: Control register 2
186 * @oar1: Own address 1 register
187 * @oar2: Own address 2 register
ea6dd25d
AV		 188 * @tmgr: Timing register
189 */
190struct stm32f7_i2c_regs {
191 u32 cr1;
192 u32 cr2;
193 u32 oar1;
194 u32 oar2;
ea6dd25d
AV		 195 u32 tmgr;
196};
197
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PYM		 198/**
199 * struct stm32f7_i2c_spec - private i2c specification timing
200 * @rate: I2C bus speed (Hz)
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PYM		 201 * @fall_max: Max fall time of both SDA and SCL signals (ns)
202 * @rise_max: Max rise time of both SDA and SCL signals (ns)
203 * @hddat_min: Min data hold time (ns)
204 * @vddat_max: Max data valid time (ns)
205 * @sudat_min: Min data setup time (ns)
206 * @l_min: Min low period of the SCL clock (ns)
207 * @h_min: Min high period of the SCL clock (ns)
208 */
209struct stm32f7_i2c_spec {
210 u32 rate;
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PYM		 211 u32 fall_max;
212 u32 rise_max;
213 u32 hddat_min;
214 u32 vddat_max;
215 u32 sudat_min;
216 u32 l_min;
217 u32 h_min;
218};
219
220/**
221 * struct stm32f7_i2c_setup - private I2C timing setup parameters
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PYM		 222 * @speed_freq: I2C speed frequency (Hz)
223 * @clock_src: I2C clock source frequency (Hz)
224 * @rise_time: Rise time (ns)
225 * @fall_time: Fall time (ns)
226 * @dnf: Digital filter coefficient (0-16)
227 * @analog_filter: Analog filter delay (On/Off)
0f820564 228 * @fmp_clr_offset: Fast Mode Plus clear register offset from set register
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PYM		 229 */
230struct stm32f7_i2c_setup {
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PYM		 231 u32 speed_freq;
232 u32 clock_src;
233 u32 rise_time;
234 u32 fall_time;
235 u8 dnf;
236 bool analog_filter;
0f820564 237 u32 fmp_clr_offset;
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PYM		 238};
239
240/**
241 * struct stm32f7_i2c_timings - private I2C output parameters
c599eb4f
PYM		 242 * @node: List entry
243 * @presc: Prescaler value
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PYM		 244 * @scldel: Data setup time
245 * @sdadel: Data hold time
246 * @sclh: SCL high period (master mode)
c599eb4f 247 * @scll: SCL low period (master mode)
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PYM		 248 */
249struct stm32f7_i2c_timings {
250 struct list_head node;
251 u8 presc;
252 u8 scldel;
253 u8 sdadel;
254 u8 sclh;
255 u8 scll;
256};
257
258/**
259 * struct stm32f7_i2c_msg - client specific data
8c7ecc99 260 * @addr: 8-bit or 10-bit slave addr, including r/w bit
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PYM		 261 * @count: number of bytes to be transferred
262 * @buf: data buffer
263 * @result: result of the transfer
264 * @stop: last I2C msg to be sent, i.e. STOP to be generated
9e48155f
PYM		 265 * @smbus: boolean to know if the I2C IP is used in SMBus mode
266 * @size: type of SMBus protocol
267 * @read_write: direction of SMBus protocol
268 * SMBus block read and SMBus block write - block read process call protocols
c599eb4f 269 * @smbus_buf: buffer to be used for SMBus protocol transfer. It will
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PYM		 270 * contain a maximum of 32 bytes of data + byte command + byte count + PEC
271 * This buffer has to be 32-bit aligned to be compliant with memory address
272 * register in DMA mode.
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PYM		 273 */
274struct stm32f7_i2c_msg {
8c7ecc99 275 u16 addr;
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PYM		 276 u32 count;
277 u8 *buf;
278 int result;
279 bool stop;
9e48155f
PYM		 280 bool smbus;
281 int size;
282 char read_write;
283 u8 smbus_buf[I2C_SMBUS_BLOCK_MAX + 3] __aligned(4);
aeb068c5
PYM		 284};
285
286/**
287 * struct stm32f7_i2c_dev - private data of the controller
288 * @adap: I2C adapter for this controller
289 * @dev: device for this controller
290 * @base: virtual memory area
291 * @complete: completion of I2C message
292 * @clk: hw i2c clock
09cc9a3b 293 * @bus_rate: I2C clock frequency of the controller
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PYM		 294 * @msg: Pointer to data to be written
295 * @msg_num: number of I2C messages to be executed
296 * @msg_id: message identifiant
297 * @f7_msg: customized i2c msg for driver usage
298 * @setup: I2C timing input setup
299 * @timing: I2C computed timings
60d609f3
PYM		 300 * @slave: list of slave devices registered on the I2C bus
301 * @slave_running: slave device currently used
ea6dd25d 302 * @backup_regs: backup of i2c controller registers (for suspend/resume)
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PYM		 303 * @slave_dir: transfer direction for the current slave device
304 * @master_mode: boolean to know in which mode the I2C is running (master or
305 * slave)
7ecc8cfd
PYM		 306 * @dma: dma data
307 * @use_dma: boolean to know if dma is used in the current transfer
cb944fb9 308 * @regmap: holds SYSCFG phandle for Fast Mode Plus bits
0f820564
AV		 309 * @fmp_sreg: register address for setting Fast Mode Plus bits
310 * @fmp_creg: register address for clearing Fast Mode Plus bits
3347ea9b 311 * @fmp_mask: mask for Fast Mode Plus bits in set register
419be8e1 312 * @wakeup_src: boolean to know if the device is a wakeup source
6af07719
AV		 313 * @smbus_mode: states that the controller is configured in SMBus mode
314 * @host_notify_client: SMBus host-notify client
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PYM		 315 */
316struct stm32f7_i2c_dev {
317 struct i2c_adapter adap;
318 struct device *dev;
319 void __iomem *base;
320 struct completion complete;
321 struct clk *clk;
09cc9a3b 322 unsigned int bus_rate;
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PYM		 323 struct i2c_msg *msg;
324 unsigned int msg_num;
325 unsigned int msg_id;
326 struct stm32f7_i2c_msg f7_msg;
463a9215 327 struct stm32f7_i2c_setup setup;
aeb068c5 328 struct stm32f7_i2c_timings timing;
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PYM		 329 struct i2c_client *slave[STM32F7_I2C_MAX_SLAVE];
330 struct i2c_client *slave_running;
ea6dd25d 331 struct stm32f7_i2c_regs backup_regs;
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PYM		 332 u32 slave_dir;
333 bool master_mode;
7ecc8cfd
PYM		 334 struct stm32_i2c_dma *dma;
335 bool use_dma;
cb944fb9 336 struct regmap *regmap;
0f820564
AV		 337 u32 fmp_sreg;
338 u32 fmp_creg;
3347ea9b 339 u32 fmp_mask;
419be8e1 340 bool wakeup_src;
6af07719
AV		 341 bool smbus_mode;
342 struct i2c_client *host_notify_client;
aeb068c5
PYM		 343};
344
348e46fb 345/*
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PYM		 346 * All these values are coming from I2C Specification, Version 6.0, 4th of
347 * April 2014.
348 *
349 * Table10. Characteristics of the SDA and SCL bus lines for Standard, Fast,
350 * and Fast-mode Plus I2C-bus devices
351 */
09cc9a3b
AV		 352static struct stm32f7_i2c_spec stm32f7_i2c_specs[] = {
353 {
83672db7 354 .rate = I2C_MAX_STANDARD_MODE_FREQ,
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PYM		 355 .fall_max = 300,
356 .rise_max = 1000,
357 .hddat_min = 0,
358 .vddat_max = 3450,
359 .sudat_min = 250,
360 .l_min = 4700,
361 .h_min = 4000,
362 },
09cc9a3b 363 {
83672db7 364 .rate = I2C_MAX_FAST_MODE_FREQ,
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PYM		 365 .fall_max = 300,
366 .rise_max = 300,
367 .hddat_min = 0,
368 .vddat_max = 900,
369 .sudat_min = 100,
370 .l_min = 1300,
371 .h_min = 600,
372 },
09cc9a3b 373 {
83672db7 374 .rate = I2C_MAX_FAST_MODE_PLUS_FREQ,
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PYM		 375 .fall_max = 100,
376 .rise_max = 120,
377 .hddat_min = 0,
378 .vddat_max = 450,
379 .sudat_min = 50,
380 .l_min = 500,
381 .h_min = 260,
382 },
383};
384
25f2f440 385static const struct stm32f7_i2c_setup stm32f7_setup = {
aeb068c5
PYM		 386 .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
387 .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
388 .dnf = STM32F7_I2C_DNF_DEFAULT,
389 .analog_filter = STM32F7_I2C_ANALOG_FILTER_ENABLE,
390};
391
0f820564
AV		 392static const struct stm32f7_i2c_setup stm32mp15_setup = {
393 .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
394 .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
395 .dnf = STM32F7_I2C_DNF_DEFAULT,
396 .analog_filter = STM32F7_I2C_ANALOG_FILTER_ENABLE,
397 .fmp_clr_offset = 0x40,
398};
399
aeb068c5
PYM		 400static inline void stm32f7_i2c_set_bits(void __iomem *reg, u32 mask)
401{
402 writel_relaxed(readl_relaxed(reg) | mask, reg);
403}
404
405static inline void stm32f7_i2c_clr_bits(void __iomem *reg, u32 mask)
406{
407 writel_relaxed(readl_relaxed(reg) & ~mask, reg);
408}
409
60d609f3
PYM		 410static void stm32f7_i2c_disable_irq(struct stm32f7_i2c_dev *i2c_dev, u32 mask)
411{
412 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, mask);
413}
414
09cc9a3b
AV		 415static struct stm32f7_i2c_spec *stm32f7_get_specs(u32 rate)
416{
417 int i;
418
419 for (i = 0; i < ARRAY_SIZE(stm32f7_i2c_specs); i++)
420 if (rate <= stm32f7_i2c_specs[i].rate)
421 return &stm32f7_i2c_specs[i];
422
423 return ERR_PTR(-EINVAL);
424}
425
426#define RATE_MIN(rate) ((rate) * 8 / 10)
aeb068c5
PYM		 427static int stm32f7_i2c_compute_timing(struct stm32f7_i2c_dev *i2c_dev,
428 struct stm32f7_i2c_setup *setup,
429 struct stm32f7_i2c_timings *output)
430{
09cc9a3b 431 struct stm32f7_i2c_spec *specs;
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PYM		 432 u32 p_prev = STM32F7_PRESC_MAX;
433 u32 i2cclk = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
434 setup->clock_src);
435 u32 i2cbus = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
436 setup->speed_freq);
437 u32 clk_error_prev = i2cbus;
438 u32 tsync;
439 u32 af_delay_min, af_delay_max;
440 u32 dnf_delay;
441 u32 clk_min, clk_max;
442 int sdadel_min, sdadel_max;
443 int scldel_min;
444 struct stm32f7_i2c_timings *v, *_v, *s;
445 struct list_head solutions;
446 u16 p, l, a, h;
447 int ret = 0;
448
09cc9a3b
AV		 449 specs = stm32f7_get_specs(setup->speed_freq);
450 if (specs == ERR_PTR(-EINVAL)) {
451 dev_err(i2c_dev->dev, "speed out of bound {%d}\n",
452 setup->speed_freq);
aeb068c5
PYM		 453 return -EINVAL;
454 }
455
09cc9a3b
AV		 456 if ((setup->rise_time > specs->rise_max) ||
457 (setup->fall_time > specs->fall_max)) {
aeb068c5
PYM		 458 dev_err(i2c_dev->dev,
459 "timings out of bound Rise{%d>%d}/Fall{%d>%d}\n",
09cc9a3b
AV		 460 setup->rise_time, specs->rise_max,
461 setup->fall_time, specs->fall_max);
aeb068c5
PYM		 462 return -EINVAL;
463 }
464
465 if (setup->dnf > STM32F7_I2C_DNF_MAX) {
466 dev_err(i2c_dev->dev,
467 "DNF out of bound %d/%d\n",
468 setup->dnf, STM32F7_I2C_DNF_MAX);
469 return -EINVAL;
470 }
471
aeb068c5
PYM		 472 /* Analog and Digital Filters */
473 af_delay_min =
474 (setup->analog_filter ?
475 STM32F7_I2C_ANALOG_FILTER_DELAY_MIN : 0);
476 af_delay_max =
477 (setup->analog_filter ?
478 STM32F7_I2C_ANALOG_FILTER_DELAY_MAX : 0);
479 dnf_delay = setup->dnf * i2cclk;
480
09cc9a3b 481 sdadel_min = specs->hddat_min + setup->fall_time -
aeb068c5
PYM		 482 af_delay_min - (setup->dnf + 3) * i2cclk;
483
09cc9a3b 484 sdadel_max = specs->vddat_max - setup->rise_time -
aeb068c5
PYM		 485 af_delay_max - (setup->dnf + 4) * i2cclk;
486
09cc9a3b 487 scldel_min = setup->rise_time + specs->sudat_min;
aeb068c5
PYM		 488
489 if (sdadel_min < 0)
490 sdadel_min = 0;
491 if (sdadel_max < 0)
492 sdadel_max = 0;
493
494 dev_dbg(i2c_dev->dev, "SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n",
495 sdadel_min, sdadel_max, scldel_min);
496
497 INIT_LIST_HEAD(&solutions);
498 /* Compute possible values for PRESC, SCLDEL and SDADEL */
499 for (p = 0; p < STM32F7_PRESC_MAX; p++) {
500 for (l = 0; l < STM32F7_SCLDEL_MAX; l++) {
501 u32 scldel = (l + 1) * (p + 1) * i2cclk;
502
503 if (scldel < scldel_min)
504 continue;
505
506 for (a = 0; a < STM32F7_SDADEL_MAX; a++) {
507 u32 sdadel = (a * (p + 1) + 1) * i2cclk;
508
509 if (((sdadel >= sdadel_min) &&
510 (sdadel <= sdadel_max)) &&
511 (p != p_prev)) {
512 v = kmalloc(sizeof(*v), GFP_KERNEL);
513 if (!v) {
514 ret = -ENOMEM;
515 goto exit;
516 }
517
518 v->presc = p;
519 v->scldel = l;
520 v->sdadel = a;
521 p_prev = p;
522
523 list_add_tail(&v->node,
524 &solutions);
0d735031 525 break;
aeb068c5
PYM		 526 }
527 }
0d735031
NLB		 528
529 if (p_prev == p)
530 break;
aeb068c5
PYM		 531 }
532 }
533
534 if (list_empty(&solutions)) {
535 dev_err(i2c_dev->dev, "no Prescaler solution\n");
536 ret = -EPERM;
537 goto exit;
538 }
539
540 tsync = af_delay_min + dnf_delay + (2 * i2cclk);
541 s = NULL;
09cc9a3b
AV		 542 clk_max = NSEC_PER_SEC / RATE_MIN(setup->speed_freq);
543 clk_min = NSEC_PER_SEC / setup->speed_freq;
aeb068c5
PYM		 544
545 /*
546 * Among Prescaler possibilities discovered above figures out SCL Low
547 * and High Period. Provided:
548 * - SCL Low Period has to be higher than SCL Clock Low Period
549 * defined by I2C Specification. I2C Clock has to be lower than
550 * (SCL Low Period - Analog/Digital filters) / 4.
551 * - SCL High Period has to be lower than SCL Clock High Period
552 * defined by I2C Specification
553 * - I2C Clock has to be lower than SCL High Period
554 */
555 list_for_each_entry(v, &solutions, node) {
556 u32 prescaler = (v->presc + 1) * i2cclk;
557
558 for (l = 0; l < STM32F7_SCLL_MAX; l++) {
559 u32 tscl_l = (l + 1) * prescaler + tsync;
560
09cc9a3b 561 if ((tscl_l < specs->l_min) ||
aeb068c5
PYM		 562 (i2cclk >=
563 ((tscl_l - af_delay_min - dnf_delay) / 4))) {
564 continue;
565 }
566
567 for (h = 0; h < STM32F7_SCLH_MAX; h++) {
568 u32 tscl_h = (h + 1) * prescaler + tsync;
569 u32 tscl = tscl_l + tscl_h +
570 setup->rise_time + setup->fall_time;
571
572 if ((tscl >= clk_min) && (tscl <= clk_max) &&
09cc9a3b 573 (tscl_h >= specs->h_min) &&
aeb068c5
PYM		 574 (i2cclk < tscl_h)) {
575 int clk_error = tscl - i2cbus;
576
577 if (clk_error < 0)
578 clk_error = -clk_error;
579
580 if (clk_error < clk_error_prev) {
581 clk_error_prev = clk_error;
582 v->scll = l;
583 v->sclh = h;
584 s = v;
585 }
586 }
587 }
588 }
589 }
590
591 if (!s) {
592 dev_err(i2c_dev->dev, "no solution at all\n");
593 ret = -EPERM;
594 goto exit;
595 }
596
597 output->presc = s->presc;
598 output->scldel = s->scldel;
599 output->sdadel = s->sdadel;
600 output->scll = s->scll;
601 output->sclh = s->sclh;
602
603 dev_dbg(i2c_dev->dev,
604 "Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n",
605 output->presc,
606 output->scldel, output->sdadel,
607 output->scll, output->sclh);
608
609exit:
610 /* Release list and memory */
611 list_for_each_entry_safe(v, _v, &solutions, node) {
612 list_del(&v->node);
613 kfree(v);
614 }
615
616 return ret;
617}
618
09cc9a3b
AV		 619static u32 stm32f7_get_lower_rate(u32 rate)
620{
621 int i = ARRAY_SIZE(stm32f7_i2c_specs);
622
08736e83 623 while (--i)
09cc9a3b
AV		 624 if (stm32f7_i2c_specs[i].rate < rate)
625 break;
626
627 return stm32f7_i2c_specs[i].rate;
628}
629
aeb068c5
PYM		 630static int stm32f7_i2c_setup_timing(struct stm32f7_i2c_dev *i2c_dev,
631 struct stm32f7_i2c_setup *setup)
632{
83672db7 633 struct i2c_timings timings, *t = &timings;
aeb068c5
PYM		 634 int ret = 0;
635
83672db7
AS		 636 t->bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ;
637 t->scl_rise_ns = i2c_dev->setup.rise_time;
638 t->scl_fall_ns = i2c_dev->setup.fall_time;
639
640 i2c_parse_fw_timings(i2c_dev->dev, t, false);
641
09cc9a3b
AV		 642 if (t->bus_freq_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) {
643 dev_err(i2c_dev->dev, "Invalid bus speed (%i>%i)\n",
644 t->bus_freq_hz, I2C_MAX_FAST_MODE_PLUS_FREQ);
645 return -EINVAL;
646 }
83672db7 647
09cc9a3b 648 setup->speed_freq = t->bus_freq_hz;
83672db7
AS		 649 i2c_dev->setup.rise_time = t->scl_rise_ns;
650 i2c_dev->setup.fall_time = t->scl_fall_ns;
aeb068c5
PYM		 651 setup->clock_src = clk_get_rate(i2c_dev->clk);
652
653 if (!setup->clock_src) {
654 dev_err(i2c_dev->dev, "clock rate is 0\n");
655 return -EINVAL;
656 }
657
658 do {
659 ret = stm32f7_i2c_compute_timing(i2c_dev, setup,
660 &i2c_dev->timing);
661 if (ret) {
662 dev_err(i2c_dev->dev,
663 "failed to compute I2C timings.\n");
09cc9a3b 664 if (setup->speed_freq <= I2C_MAX_STANDARD_MODE_FREQ)
aeb068c5 665 break;
09cc9a3b
AV		 666 setup->speed_freq =
667 stm32f7_get_lower_rate(setup->speed_freq);
668 dev_warn(i2c_dev->dev,
669 "downgrade I2C Speed Freq to (%i)\n",
670 setup->speed_freq);
aeb068c5
PYM		 671 }
672 } while (ret);
673
674 if (ret) {
675 dev_err(i2c_dev->dev, "Impossible to compute I2C timings.\n");
676 return ret;
677 }
678
09cc9a3b
AV		 679 dev_dbg(i2c_dev->dev, "I2C Speed(%i), Clk Source(%i)\n",
680 setup->speed_freq, setup->clock_src);
aeb068c5
PYM		 681 dev_dbg(i2c_dev->dev, "I2C Rise(%i) and Fall(%i) Time\n",
682 setup->rise_time, setup->fall_time);
683 dev_dbg(i2c_dev->dev, "I2C Analog Filter(%s), DNF(%i)\n",
684 (setup->analog_filter ? "On" : "Off"), setup->dnf);
685
09cc9a3b
AV		 686 i2c_dev->bus_rate = setup->speed_freq;
687
aeb068c5
PYM		 688 return 0;
689}
690
7ecc8cfd
PYM		 691static void stm32f7_i2c_disable_dma_req(struct stm32f7_i2c_dev *i2c_dev)
692{
693 void __iomem *base = i2c_dev->base;
694 u32 mask = STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN;
695
696 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
697}
698
699static void stm32f7_i2c_dma_callback(void *arg)
700{
701 struct stm32f7_i2c_dev *i2c_dev = (struct stm32f7_i2c_dev *)arg;
702 struct stm32_i2c_dma *dma = i2c_dev->dma;
703 struct device *dev = dma->chan_using->device->dev;
704
705 stm32f7_i2c_disable_dma_req(i2c_dev);
706 dma_unmap_single(dev, dma->dma_buf, dma->dma_len, dma->dma_data_dir);
707 complete(&dma->dma_complete);
708}
709
aeb068c5
PYM		 710static void stm32f7_i2c_hw_config(struct stm32f7_i2c_dev *i2c_dev)
711{
712 struct stm32f7_i2c_timings *t = &i2c_dev->timing;
713 u32 timing = 0;
714
715 /* Timing settings */
716 timing |= STM32F7_I2C_TIMINGR_PRESC(t->presc);
717 timing |= STM32F7_I2C_TIMINGR_SCLDEL(t->scldel);
718 timing |= STM32F7_I2C_TIMINGR_SDADEL(t->sdadel);
719 timing |= STM32F7_I2C_TIMINGR_SCLH(t->sclh);
720 timing |= STM32F7_I2C_TIMINGR_SCLL(t->scll);
721 writel_relaxed(timing, i2c_dev->base + STM32F7_I2C_TIMINGR);
722
723 /* Enable I2C */
463a9215 724 if (i2c_dev->setup.analog_filter)
aeb068c5
PYM		 725 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
726 STM32F7_I2C_CR1_ANFOFF);
727 else
728 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
729 STM32F7_I2C_CR1_ANFOFF);
3d6a3d3a
AV		 730
731 /* Program the Digital Filter */
732 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
733 STM32F7_I2C_CR1_DNF_MASK);
734 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
735 STM32F7_I2C_CR1_DNF(i2c_dev->setup.dnf));
736
aeb068c5
PYM		 737 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
738 STM32F7_I2C_CR1_PE);
739}
740
741static void stm32f7_i2c_write_tx_data(struct stm32f7_i2c_dev *i2c_dev)
742{
743 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
744 void __iomem *base = i2c_dev->base;
745
746 if (f7_msg->count) {
747 writeb_relaxed(*f7_msg->buf++, base + STM32F7_I2C_TXDR);
748 f7_msg->count--;
749 }
750}
751
752static void stm32f7_i2c_read_rx_data(struct stm32f7_i2c_dev *i2c_dev)
753{
754 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
755 void __iomem *base = i2c_dev->base;
756
757 if (f7_msg->count) {
758 *f7_msg->buf++ = readb_relaxed(base + STM32F7_I2C_RXDR);
759 f7_msg->count--;
60d609f3
PYM		 760 } else {
761 /* Flush RX buffer has no data is expected */
762 readb_relaxed(base + STM32F7_I2C_RXDR);
aeb068c5
PYM		 763 }
764}
765
766static void stm32f7_i2c_reload(struct stm32f7_i2c_dev *i2c_dev)
767{
768 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
769 u32 cr2;
770
7ecc8cfd
PYM		 771 if (i2c_dev->use_dma)
772 f7_msg->count -= STM32F7_I2C_MAX_LEN;
773
aeb068c5
PYM		 774 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
775
776 cr2 &= ~STM32F7_I2C_CR2_NBYTES_MASK;
777 if (f7_msg->count > STM32F7_I2C_MAX_LEN) {
778 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
779 } else {
780 cr2 &= ~STM32F7_I2C_CR2_RELOAD;
781 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
782 }
783
784 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
785}
786
9e48155f
PYM		 787static void stm32f7_i2c_smbus_reload(struct stm32f7_i2c_dev *i2c_dev)
788{
789 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
790 u32 cr2;
791 u8 *val;
792
793 /*
794 * For I2C_SMBUS_BLOCK_DATA && I2C_SMBUS_BLOCK_PROC_CALL, the first
795 * data received inform us how many data will follow.
796 */
797 stm32f7_i2c_read_rx_data(i2c_dev);
798
799 /*
800 * Update NBYTES with the value read to continue the transfer
801 */
802 val = f7_msg->buf - sizeof(u8);
803 f7_msg->count = *val;
804 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
805 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
806 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
807 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
808}
809
562de4ff
PYM		 810static int stm32f7_i2c_release_bus(struct i2c_adapter *i2c_adap)
811{
812 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
813
814 dev_info(i2c_dev->dev, "Trying to recover bus\n");
815
816 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
817 STM32F7_I2C_CR1_PE);
818
819 stm32f7_i2c_hw_config(i2c_dev);
820
821 return 0;
822}
823
aeb068c5
PYM		 824static int stm32f7_i2c_wait_free_bus(struct stm32f7_i2c_dev *i2c_dev)
825{
826 u32 status;
827 int ret;
828
829 ret = readl_relaxed_poll_timeout(i2c_dev->base + STM32F7_I2C_ISR,
830 status,
831 !(status & STM32F7_I2C_ISR_BUSY),
832 10, 1000);
562de4ff
PYM		 833 if (!ret)
834 return 0;
835
836 dev_info(i2c_dev->dev, "bus busy\n");
837
838 ret = stm32f7_i2c_release_bus(&i2c_dev->adap);
aeb068c5 839 if (ret) {
562de4ff
PYM		 840 dev_err(i2c_dev->dev, "Failed to recover the bus (%d)\n", ret);
841 return ret;
aeb068c5
PYM		 842 }
843
562de4ff 844 return -EBUSY;
aeb068c5
PYM		 845}
846
847static void stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
848 struct i2c_msg *msg)
849{
850 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
851 void __iomem *base = i2c_dev->base;
852 u32 cr1, cr2;
7ecc8cfd 853 int ret;
aeb068c5
PYM		 854
855 f7_msg->addr = msg->addr;
856 f7_msg->buf = msg->buf;
857 f7_msg->count = msg->len;
858 f7_msg->result = 0;
859 f7_msg->stop = (i2c_dev->msg_id >= i2c_dev->msg_num - 1);
860
861 reinit_completion(&i2c_dev->complete);
862
863 cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
864 cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
865
866 /* Set transfer direction */
867 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
868 if (msg->flags & I2C_M_RD)
869 cr2 |= STM32F7_I2C_CR2_RD_WRN;
870
871 /* Set slave address */
8c7ecc99
PYM		 872 cr2 &= ~(STM32F7_I2C_CR2_HEAD10R | STM32F7_I2C_CR2_ADD10);
873 if (msg->flags & I2C_M_TEN) {
874 cr2 &= ~STM32F7_I2C_CR2_SADD10_MASK;
875 cr2 |= STM32F7_I2C_CR2_SADD10(f7_msg->addr);
876 cr2 |= STM32F7_I2C_CR2_ADD10;
877 } else {
878 cr2 &= ~STM32F7_I2C_CR2_SADD7_MASK;
879 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
880 }
aeb068c5
PYM		 881
882 /* Set nb bytes to transfer and reload if needed */
883 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
884 if (f7_msg->count > STM32F7_I2C_MAX_LEN) {
885 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
886 cr2 |= STM32F7_I2C_CR2_RELOAD;
887 } else {
888 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
889 }
890
891 /* Enable NACK, STOP, error and transfer complete interrupts */
892 cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |
893 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE;
894
7ecc8cfd
PYM		 895 /* Clear DMA req and TX/RX interrupt */
896 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
897 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
898
899 /* Configure DMA or enable RX/TX interrupt */
900 i2c_dev->use_dma = false;
901 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) {
902 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
903 msg->flags & I2C_M_RD,
904 f7_msg->count, f7_msg->buf,
905 stm32f7_i2c_dma_callback,
906 i2c_dev);
907 if (!ret)
908 i2c_dev->use_dma = true;
909 else
910 dev_warn(i2c_dev->dev, "can't use DMA\n");
911 }
aeb068c5 912
7ecc8cfd
PYM		 913 if (!i2c_dev->use_dma) {
914 if (msg->flags & I2C_M_RD)
915 cr1 |= STM32F7_I2C_CR1_RXIE;
916 else
917 cr1 |= STM32F7_I2C_CR1_TXIE;
918 } else {
919 if (msg->flags & I2C_M_RD)
920 cr1 |= STM32F7_I2C_CR1_RXDMAEN;
921 else
922 cr1 |= STM32F7_I2C_CR1_TXDMAEN;
923 }
aeb068c5
PYM		 924
925 /* Configure Start/Repeated Start */
926 cr2 |= STM32F7_I2C_CR2_START;
927
60d609f3
PYM		 928 i2c_dev->master_mode = true;
929
aeb068c5
PYM		 930 /* Write configurations registers */
931 writel_relaxed(cr1, base + STM32F7_I2C_CR1);
932 writel_relaxed(cr2, base + STM32F7_I2C_CR2);
933}
934
9e48155f
PYM		 935static int stm32f7_i2c_smbus_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
936 unsigned short flags, u8 command,
937 union i2c_smbus_data *data)
938{
939 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
940 struct device *dev = i2c_dev->dev;
941 void __iomem *base = i2c_dev->base;
942 u32 cr1, cr2;
7ecc8cfd 943 int i, ret;
9e48155f
PYM		 944
945 f7_msg->result = 0;
946 reinit_completion(&i2c_dev->complete);
947
948 cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
949 cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
950
951 /* Set transfer direction */
952 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
953 if (f7_msg->read_write)
954 cr2 |= STM32F7_I2C_CR2_RD_WRN;
955
956 /* Set slave address */
957 cr2 &= ~(STM32F7_I2C_CR2_ADD10 | STM32F7_I2C_CR2_SADD7_MASK);
958 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
959
960 f7_msg->smbus_buf[0] = command;
961 switch (f7_msg->size) {
962 case I2C_SMBUS_QUICK:
963 f7_msg->stop = true;
964 f7_msg->count = 0;
965 break;
966 case I2C_SMBUS_BYTE:
967 f7_msg->stop = true;
968 f7_msg->count = 1;
969 break;
970 case I2C_SMBUS_BYTE_DATA:
971 if (f7_msg->read_write) {
972 f7_msg->stop = false;
973 f7_msg->count = 1;
974 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
975 } else {
976 f7_msg->stop = true;
977 f7_msg->count = 2;
978 f7_msg->smbus_buf[1] = data->byte;
979 }
980 break;
981 case I2C_SMBUS_WORD_DATA:
982 if (f7_msg->read_write) {
983 f7_msg->stop = false;
984 f7_msg->count = 1;
985 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
986 } else {
987 f7_msg->stop = true;
988 f7_msg->count = 3;
989 f7_msg->smbus_buf[1] = data->word & 0xff;
990 f7_msg->smbus_buf[2] = data->word >> 8;
991 }
992 break;
993 case I2C_SMBUS_BLOCK_DATA:
994 if (f7_msg->read_write) {
995 f7_msg->stop = false;
996 f7_msg->count = 1;
997 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
998 } else {
999 f7_msg->stop = true;
1000 if (data->block[0] > I2C_SMBUS_BLOCK_MAX ||
1001 !data->block[0]) {
1002 dev_err(dev, "Invalid block write size %d\n",
1003 data->block[0]);
1004 return -EINVAL;
1005 }
1006 f7_msg->count = data->block[0] + 2;
1007 for (i = 1; i < f7_msg->count; i++)
1008 f7_msg->smbus_buf[i] = data->block[i - 1];
1009 }
1010 break;
1011 case I2C_SMBUS_PROC_CALL:
1012 f7_msg->stop = false;
1013 f7_msg->count = 3;
1014 f7_msg->smbus_buf[1] = data->word & 0xff;
1015 f7_msg->smbus_buf[2] = data->word >> 8;
1016 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1017 f7_msg->read_write = I2C_SMBUS_READ;
1018 break;
1019 case I2C_SMBUS_BLOCK_PROC_CALL:
1020 f7_msg->stop = false;
1021 if (data->block[0] > I2C_SMBUS_BLOCK_MAX - 1) {
1022 dev_err(dev, "Invalid block write size %d\n",
1023 data->block[0]);
1024 return -EINVAL;
1025 }
1026 f7_msg->count = data->block[0] + 2;
1027 for (i = 1; i < f7_msg->count; i++)
1028 f7_msg->smbus_buf[i] = data->block[i - 1];
1029 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1030 f7_msg->read_write = I2C_SMBUS_READ;
1031 break;
473fbdf7
FG		 1032 case I2C_SMBUS_I2C_BLOCK_DATA:
1033 /* Rely on emulated i2c transfer (through master_xfer) */
1034 return -EOPNOTSUPP;
9e48155f
PYM		 1035 default:
1036 dev_err(dev, "Unsupported smbus protocol %d\n", f7_msg->size);
1037 return -EOPNOTSUPP;
1038 }
1039
1040 f7_msg->buf = f7_msg->smbus_buf;
1041
1042 /* Configure PEC */
1043 if ((flags & I2C_CLIENT_PEC) && f7_msg->size != I2C_SMBUS_QUICK) {
1044 cr1 |= STM32F7_I2C_CR1_PECEN;
1045 cr2 |= STM32F7_I2C_CR2_PECBYTE;
1046 if (!f7_msg->read_write)
1047 f7_msg->count++;
1048 } else {
1049 cr1 &= ~STM32F7_I2C_CR1_PECEN;
1050 cr2 &= ~STM32F7_I2C_CR2_PECBYTE;
1051 }
1052
1053 /* Set number of bytes to be transferred */
1054 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
1055 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
1056
1057 /* Enable NACK, STOP, error and transfer complete interrupts */
1058 cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |
1059 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE;
1060
7ecc8cfd
PYM		 1061 /* Clear DMA req and TX/RX interrupt */
1062 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
1063 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
1064
1065 /* Configure DMA or enable RX/TX interrupt */
1066 i2c_dev->use_dma = false;
1067 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) {
1068 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
1069 cr2 & STM32F7_I2C_CR2_RD_WRN,
1070 f7_msg->count, f7_msg->buf,
1071 stm32f7_i2c_dma_callback,
1072 i2c_dev);
1073 if (!ret)
1074 i2c_dev->use_dma = true;
1075 else
1076 dev_warn(i2c_dev->dev, "can't use DMA\n");
1077 }
9e48155f 1078
7ecc8cfd
PYM		 1079 if (!i2c_dev->use_dma) {
1080 if (cr2 & STM32F7_I2C_CR2_RD_WRN)
1081 cr1 |= STM32F7_I2C_CR1_RXIE;
1082 else
1083 cr1 |= STM32F7_I2C_CR1_TXIE;
1084 } else {
1085 if (cr2 & STM32F7_I2C_CR2_RD_WRN)
1086 cr1 |= STM32F7_I2C_CR1_RXDMAEN;
1087 else
1088 cr1 |= STM32F7_I2C_CR1_TXDMAEN;
1089 }
9e48155f
PYM		 1090
1091 /* Set Start bit */
1092 cr2 |= STM32F7_I2C_CR2_START;
1093
1094 i2c_dev->master_mode = true;
1095
1096 /* Write configurations registers */
1097 writel_relaxed(cr1, base + STM32F7_I2C_CR1);
1098 writel_relaxed(cr2, base + STM32F7_I2C_CR2);
1099
1100 return 0;
1101}
1102
1103static void stm32f7_i2c_smbus_rep_start(struct stm32f7_i2c_dev *i2c_dev)
1104{
1105 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1106 void __iomem *base = i2c_dev->base;
1107 u32 cr1, cr2;
7ecc8cfd 1108 int ret;
9e48155f
PYM		 1109
1110 cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
1111 cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
1112
1113 /* Set transfer direction */
1114 cr2 |= STM32F7_I2C_CR2_RD_WRN;
1115
1116 switch (f7_msg->size) {
1117 case I2C_SMBUS_BYTE_DATA:
1118 f7_msg->count = 1;
1119 break;
1120 case I2C_SMBUS_WORD_DATA:
1121 case I2C_SMBUS_PROC_CALL:
1122 f7_msg->count = 2;
1123 break;
1124 case I2C_SMBUS_BLOCK_DATA:
1125 case I2C_SMBUS_BLOCK_PROC_CALL:
1126 f7_msg->count = 1;
1127 cr2 |= STM32F7_I2C_CR2_RELOAD;
1128 break;
1129 }
1130
1131 f7_msg->buf = f7_msg->smbus_buf;
1132 f7_msg->stop = true;
1133
1134 /* Add one byte for PEC if needed */
1135 if (cr1 & STM32F7_I2C_CR1_PECEN)
1136 f7_msg->count++;
1137
1138 /* Set number of bytes to be transferred */
1139 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK);
1140 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
1141
1142 /*
1143 * Configure RX/TX interrupt:
1144 */
1145 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE);
1146 cr1 |= STM32F7_I2C_CR1_RXIE;
1147
7ecc8cfd
PYM		 1148 /*
1149 * Configure DMA or enable RX/TX interrupt:
1150 * For I2C_SMBUS_BLOCK_DATA and I2C_SMBUS_BLOCK_PROC_CALL we don't use
1151 * dma as we don't know in advance how many data will be received
1152 */
1153 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
1154 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
1155
1156 i2c_dev->use_dma = false;
1157 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN &&
1158 f7_msg->size != I2C_SMBUS_BLOCK_DATA &&
1159 f7_msg->size != I2C_SMBUS_BLOCK_PROC_CALL) {
1160 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
1161 cr2 & STM32F7_I2C_CR2_RD_WRN,
1162 f7_msg->count, f7_msg->buf,
1163 stm32f7_i2c_dma_callback,
1164 i2c_dev);
1165
1166 if (!ret)
1167 i2c_dev->use_dma = true;
1168 else
1169 dev_warn(i2c_dev->dev, "can't use DMA\n");
1170 }
1171
1172 if (!i2c_dev->use_dma)
1173 cr1 |= STM32F7_I2C_CR1_RXIE;
1174 else
1175 cr1 |= STM32F7_I2C_CR1_RXDMAEN;
1176
9e48155f
PYM		 1177 /* Configure Repeated Start */
1178 cr2 |= STM32F7_I2C_CR2_START;
1179
1180 /* Write configurations registers */
1181 writel_relaxed(cr1, base + STM32F7_I2C_CR1);
1182 writel_relaxed(cr2, base + STM32F7_I2C_CR2);
1183}
1184
1185static int stm32f7_i2c_smbus_check_pec(struct stm32f7_i2c_dev *i2c_dev)
1186{
1187 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1188 u8 count, internal_pec, received_pec;
1189
1190 internal_pec = readl_relaxed(i2c_dev->base + STM32F7_I2C_PECR);
1191
1192 switch (f7_msg->size) {
1193 case I2C_SMBUS_BYTE:
1194 case I2C_SMBUS_BYTE_DATA:
1195 received_pec = f7_msg->smbus_buf[1];
1196 break;
1197 case I2C_SMBUS_WORD_DATA:
1198 case I2C_SMBUS_PROC_CALL:
1199 received_pec = f7_msg->smbus_buf[2];
1200 break;
1201 case I2C_SMBUS_BLOCK_DATA:
1202 case I2C_SMBUS_BLOCK_PROC_CALL:
1203 count = f7_msg->smbus_buf[0];
1204 received_pec = f7_msg->smbus_buf[count];
1205 break;
1206 default:
1207 dev_err(i2c_dev->dev, "Unsupported smbus protocol for PEC\n");
1208 return -EINVAL;
1209 }
1210
1211 if (internal_pec != received_pec) {
1212 dev_err(i2c_dev->dev, "Bad PEC 0x%02x vs. 0x%02x\n",
1213 internal_pec, received_pec);
1214 return -EBADMSG;
1215 }
1216
1217 return 0;
1218}
1219
60d609f3 1220static bool stm32f7_i2c_is_addr_match(struct i2c_client *slave, u32 addcode)
aeb068c5 1221{
60d609f3
PYM		 1222 u32 addr;
1223
1224 if (!slave)
1225 return false;
1226
1227 if (slave->flags & I2C_CLIENT_TEN) {
1228 /*
1229 * For 10-bit addr, addcode = 11110XY with
1230 * X = Bit 9 of slave address
1231 * Y = Bit 8 of slave address
1232 */
1233 addr = slave->addr >> 8;
1234 addr |= 0x78;
1235 if (addr == addcode)
1236 return true;
1237 } else {
1238 addr = slave->addr & 0x7f;
1239 if (addr == addcode)
1240 return true;
1241 }
1242
1243 return false;
1244}
1245
1246static void stm32f7_i2c_slave_start(struct stm32f7_i2c_dev *i2c_dev)
1247{
1248 struct i2c_client *slave = i2c_dev->slave_running;
1249 void __iomem *base = i2c_dev->base;
1250 u32 mask;
1251 u8 value = 0;
1252
1253 if (i2c_dev->slave_dir) {
1254 /* Notify i2c slave that new read transfer is starting */
1255 i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value);
1256
1257 /*
1258 * Disable slave TX config in case of I2C combined message
1259 * (I2C Write followed by I2C Read)
1260 */
1261 mask = STM32F7_I2C_CR2_RELOAD;
1262 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, mask);
1263 mask = STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE |
1264 STM32F7_I2C_CR1_TCIE;
1265 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
1266
1267 /* Enable TX empty, STOP, NACK interrupts */
1268 mask = STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE |
1269 STM32F7_I2C_CR1_TXIE;
1270 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1271
02e64276
FG		 1272 /* Write 1st data byte */
1273 writel_relaxed(value, base + STM32F7_I2C_TXDR);
60d609f3
PYM		 1274 } else {
1275 /* Notify i2c slave that new write transfer is starting */
1276 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value);
1277
1278 /* Set reload mode to be able to ACK/NACK each received byte */
1279 mask = STM32F7_I2C_CR2_RELOAD;
1280 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1281
1282 /*
1283 * Set STOP, NACK, RX empty and transfer complete interrupts.*
1284 * Set Slave Byte Control to be able to ACK/NACK each data
1285 * byte received
1286 */
1287 mask = STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE |
1288 STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE |
1289 STM32F7_I2C_CR1_TCIE;
1290 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1291 }
1292}
1293
1294static void stm32f7_i2c_slave_addr(struct stm32f7_i2c_dev *i2c_dev)
1295{
1296 void __iomem *base = i2c_dev->base;
1297 u32 isr, addcode, dir, mask;
1298 int i;
1299
1300 isr = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1301 addcode = STM32F7_I2C_ISR_ADDCODE_GET(isr);
1302 dir = isr & STM32F7_I2C_ISR_DIR;
1303
1304 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1305 if (stm32f7_i2c_is_addr_match(i2c_dev->slave[i], addcode)) {
1306 i2c_dev->slave_running = i2c_dev->slave[i];
1307 i2c_dev->slave_dir = dir;
1308
1309 /* Start I2C slave processing */
1310 stm32f7_i2c_slave_start(i2c_dev);
1311
1312 /* Clear ADDR flag */
1313 mask = STM32F7_I2C_ICR_ADDRCF;
1314 writel_relaxed(mask, base + STM32F7_I2C_ICR);
1315 break;
1316 }
1317 }
1318}
1319
1320static int stm32f7_i2c_get_slave_id(struct stm32f7_i2c_dev *i2c_dev,
1321 struct i2c_client *slave, int *id)
1322{
1323 int i;
1324
1325 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1326 if (i2c_dev->slave[i] == slave) {
1327 *id = i;
1328 return 0;
1329 }
1330 }
1331
1332 dev_err(i2c_dev->dev, "Slave 0x%x not registered\n", slave->addr);
1333
1334 return -ENODEV;
1335}
1336
1337static int stm32f7_i2c_get_free_slave_id(struct stm32f7_i2c_dev *i2c_dev,
1338 struct i2c_client *slave, int *id)
1339{
1340 struct device *dev = i2c_dev->dev;
1341 int i;
1342
1343 /*
b62590a9
AV		 1344 * slave[STM32F7_SLAVE_HOSTNOTIFY] support only SMBus Host address (0x8)
1345 * slave[STM32F7_SLAVE_7_10_BITS_ADDR] supports 7-bit and 10-bit slave address
1346 * slave[STM32F7_SLAVE_7_BITS_ADDR] supports 7-bit slave address only
60d609f3 1347 */
6af07719 1348 if (i2c_dev->smbus_mode && (slave->addr == 0x08)) {
b62590a9 1349 if (i2c_dev->slave[STM32F7_SLAVE_HOSTNOTIFY])
6af07719 1350 goto fail;
b62590a9 1351 *id = STM32F7_SLAVE_HOSTNOTIFY;
6af07719
AV		 1352 return 0;
1353 }
1354
b62590a9
AV		 1355 for (i = STM32F7_I2C_MAX_SLAVE - 1; i > STM32F7_SLAVE_HOSTNOTIFY; i--) {
1356 if ((i == STM32F7_SLAVE_7_BITS_ADDR) &&
1357 (slave->flags & I2C_CLIENT_TEN))
60d609f3
PYM		 1358 continue;
1359 if (!i2c_dev->slave[i]) {
1360 *id = i;
1361 return 0;
1362 }
1363 }
1364
6af07719 1365fail:
60d609f3
PYM		 1366 dev_err(dev, "Slave 0x%x could not be registered\n", slave->addr);
1367
1368 return -EINVAL;
1369}
1370
1371static bool stm32f7_i2c_is_slave_registered(struct stm32f7_i2c_dev *i2c_dev)
1372{
1373 int i;
1374
1375 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1376 if (i2c_dev->slave[i])
1377 return true;
1378 }
1379
1380 return false;
1381}
1382
1383static bool stm32f7_i2c_is_slave_busy(struct stm32f7_i2c_dev *i2c_dev)
1384{
1385 int i, busy;
1386
1387 busy = 0;
1388 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1389 if (i2c_dev->slave[i])
1390 busy++;
1391 }
1392
1393 return i == busy;
1394}
1395
1396static irqreturn_t stm32f7_i2c_slave_isr_event(struct stm32f7_i2c_dev *i2c_dev)
1397{
1398 void __iomem *base = i2c_dev->base;
1399 u32 cr2, status, mask;
1400 u8 val;
1401 int ret;
1402
1403 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1404
1405 /* Slave transmitter mode */
1406 if (status & STM32F7_I2C_ISR_TXIS) {
1407 i2c_slave_event(i2c_dev->slave_running,
1408 I2C_SLAVE_READ_PROCESSED,
1409 &val);
1410
1411 /* Write data byte */
1412 writel_relaxed(val, base + STM32F7_I2C_TXDR);
1413 }
1414
1415 /* Transfer Complete Reload for Slave receiver mode */
1416 if (status & STM32F7_I2C_ISR_TCR || status & STM32F7_I2C_ISR_RXNE) {
1417 /*
1418 * Read data byte then set NBYTES to receive next byte or NACK
1419 * the current received byte
1420 */
1421 val = readb_relaxed(i2c_dev->base + STM32F7_I2C_RXDR);
1422 ret = i2c_slave_event(i2c_dev->slave_running,
1423 I2C_SLAVE_WRITE_RECEIVED,
1424 &val);
1425 if (!ret) {
1426 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
1427 cr2 |= STM32F7_I2C_CR2_NBYTES(1);
1428 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
1429 } else {
1430 mask = STM32F7_I2C_CR2_NACK;
1431 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1432 }
1433 }
1434
1435 /* NACK received */
1436 if (status & STM32F7_I2C_ISR_NACKF) {
1437 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__);
1438 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR);
1439 }
1440
1441 /* STOP received */
1442 if (status & STM32F7_I2C_ISR_STOPF) {
1443 /* Disable interrupts */
1444 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_XFER_IRQ_MASK);
1445
1446 if (i2c_dev->slave_dir) {
1447 /*
1448 * Flush TX buffer in order to not used the byte in
1449 * TXDR for the next transfer
1450 */
1451 mask = STM32F7_I2C_ISR_TXE;
1452 stm32f7_i2c_set_bits(base + STM32F7_I2C_ISR, mask);
1453 }
1454
1455 /* Clear STOP flag */
1456 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
1457
1458 /* Notify i2c slave that a STOP flag has been detected */
1459 i2c_slave_event(i2c_dev->slave_running, I2C_SLAVE_STOP, &val);
1460
1461 i2c_dev->slave_running = NULL;
1462 }
1463
1464 /* Address match received */
1465 if (status & STM32F7_I2C_ISR_ADDR)
1466 stm32f7_i2c_slave_addr(i2c_dev);
1467
1468 return IRQ_HANDLED;
aeb068c5
PYM		 1469}
1470
1471static irqreturn_t stm32f7_i2c_isr_event(int irq, void *data)
1472{
1473 struct stm32f7_i2c_dev *i2c_dev = data;
1474 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1475 void __iomem *base = i2c_dev->base;
1476 u32 status, mask;
7ecc8cfd 1477 int ret = IRQ_HANDLED;
60d609f3
PYM		 1478
1479 /* Check if the interrupt if for a slave device */
1480 if (!i2c_dev->master_mode) {
1481 ret = stm32f7_i2c_slave_isr_event(i2c_dev);
1482 return ret;
1483 }
aeb068c5
PYM		 1484
1485 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1486
1487 /* Tx empty */
1488 if (status & STM32F7_I2C_ISR_TXIS)
1489 stm32f7_i2c_write_tx_data(i2c_dev);
1490
1491 /* RX not empty */
1492 if (status & STM32F7_I2C_ISR_RXNE)
1493 stm32f7_i2c_read_rx_data(i2c_dev);
1494
1495 /* NACK received */
1496 if (status & STM32F7_I2C_ISR_NACKF) {
79d48da3
FG		 1497 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK (addr %x)\n",
1498 __func__, f7_msg->addr);
aeb068c5
PYM		 1499 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR);
1500 f7_msg->result = -ENXIO;
1501 }
1502
1503 /* STOP detection flag */
1504 if (status & STM32F7_I2C_ISR_STOPF) {
1505 /* Disable interrupts */
60d609f3
PYM		 1506 if (stm32f7_i2c_is_slave_registered(i2c_dev))
1507 mask = STM32F7_I2C_XFER_IRQ_MASK;
1508 else
1509 mask = STM32F7_I2C_ALL_IRQ_MASK;
1510 stm32f7_i2c_disable_irq(i2c_dev, mask);
aeb068c5
PYM		 1511
1512 /* Clear STOP flag */
1513 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
1514
7ecc8cfd
PYM		 1515 if (i2c_dev->use_dma) {
1516 ret = IRQ_WAKE_THREAD;
1517 } else {
1518 i2c_dev->master_mode = false;
1519 complete(&i2c_dev->complete);
1520 }
aeb068c5
PYM		 1521 }
1522
1523 /* Transfer complete */
1524 if (status & STM32F7_I2C_ISR_TC) {
1525 if (f7_msg->stop) {
1526 mask = STM32F7_I2C_CR2_STOP;
1527 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
7ecc8cfd
PYM		 1528 } else if (i2c_dev->use_dma) {
1529 ret = IRQ_WAKE_THREAD;
9e48155f
PYM		 1530 } else if (f7_msg->smbus) {
1531 stm32f7_i2c_smbus_rep_start(i2c_dev);
aeb068c5
PYM		 1532 } else {
1533 i2c_dev->msg_id++;
1534 i2c_dev->msg++;
1535 stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg);
1536 }
1537 }
1538
9e48155f
PYM		 1539 if (status & STM32F7_I2C_ISR_TCR) {
1540 if (f7_msg->smbus)
1541 stm32f7_i2c_smbus_reload(i2c_dev);
1542 else
1543 stm32f7_i2c_reload(i2c_dev);
1544 }
aeb068c5 1545
7ecc8cfd
PYM		 1546 return ret;
1547}
1548
1549static irqreturn_t stm32f7_i2c_isr_event_thread(int irq, void *data)
1550{
1551 struct stm32f7_i2c_dev *i2c_dev = data;
1552 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1553 struct stm32_i2c_dma *dma = i2c_dev->dma;
1554 u32 status;
1555 int ret;
1556
1557 /*
1558 * Wait for dma transfer completion before sending next message or
1559 * notity the end of xfer to the client
1560 */
1561 ret = wait_for_completion_timeout(&i2c_dev->dma->dma_complete, HZ);
1562 if (!ret) {
1563 dev_dbg(i2c_dev->dev, "<%s>: Timed out\n", __func__);
1564 stm32f7_i2c_disable_dma_req(i2c_dev);
1565 dmaengine_terminate_all(dma->chan_using);
1566 f7_msg->result = -ETIMEDOUT;
1567 }
1568
1569 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1570
1571 if (status & STM32F7_I2C_ISR_TC) {
1572 if (f7_msg->smbus) {
1573 stm32f7_i2c_smbus_rep_start(i2c_dev);
1574 } else {
1575 i2c_dev->msg_id++;
1576 i2c_dev->msg++;
1577 stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg);
1578 }
1579 } else {
1580 i2c_dev->master_mode = false;
1581 complete(&i2c_dev->complete);
1582 }
1583
aeb068c5
PYM		 1584 return IRQ_HANDLED;
1585}
1586
1587static irqreturn_t stm32f7_i2c_isr_error(int irq, void *data)
1588{
1589 struct stm32f7_i2c_dev *i2c_dev = data;
1590 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1591 void __iomem *base = i2c_dev->base;
1592 struct device *dev = i2c_dev->dev;
7ecc8cfd 1593 struct stm32_i2c_dma *dma = i2c_dev->dma;
6d6b0d0d 1594 u32 status;
aeb068c5
PYM		 1595
1596 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1597
1598 /* Bus error */
1599 if (status & STM32F7_I2C_ISR_BERR) {
1600 dev_err(dev, "<%s>: Bus error\n", __func__);
1601 writel_relaxed(STM32F7_I2C_ICR_BERRCF, base + STM32F7_I2C_ICR);
562de4ff 1602 stm32f7_i2c_release_bus(&i2c_dev->adap);
aeb068c5
PYM		 1603 f7_msg->result = -EIO;
1604 }
1605
1606 /* Arbitration loss */
1607 if (status & STM32F7_I2C_ISR_ARLO) {
1608 dev_dbg(dev, "<%s>: Arbitration loss\n", __func__);
1609 writel_relaxed(STM32F7_I2C_ICR_ARLOCF, base + STM32F7_I2C_ICR);
1610 f7_msg->result = -EAGAIN;
1611 }
1612
9e48155f
PYM		 1613 if (status & STM32F7_I2C_ISR_PECERR) {
1614 dev_err(dev, "<%s>: PEC error in reception\n", __func__);
1615 writel_relaxed(STM32F7_I2C_ICR_PECCF, base + STM32F7_I2C_ICR);
1616 f7_msg->result = -EINVAL;
1617 }
1618
6d6b0d0d
FG		 1619 if (!i2c_dev->slave_running) {
1620 u32 mask;
1621 /* Disable interrupts */
1622 if (stm32f7_i2c_is_slave_registered(i2c_dev))
1623 mask = STM32F7_I2C_XFER_IRQ_MASK;
1624 else
1625 mask = STM32F7_I2C_ALL_IRQ_MASK;
1626 stm32f7_i2c_disable_irq(i2c_dev, mask);
1627 }
aeb068c5 1628
7ecc8cfd
PYM		 1629 /* Disable dma */
1630 if (i2c_dev->use_dma) {
1631 stm32f7_i2c_disable_dma_req(i2c_dev);
1632 dmaengine_terminate_all(dma->chan_using);
1633 }
1634
60d609f3 1635 i2c_dev->master_mode = false;
aeb068c5
PYM		 1636 complete(&i2c_dev->complete);
1637
1638 return IRQ_HANDLED;
1639}
1640
1641static int stm32f7_i2c_xfer(struct i2c_adapter *i2c_adap,
1642 struct i2c_msg msgs[], int num)
1643{
1644 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
1645 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
7ecc8cfd 1646 struct stm32_i2c_dma *dma = i2c_dev->dma;
aeb068c5
PYM		 1647 unsigned long time_left;
1648 int ret;
1649
1650 i2c_dev->msg = msgs;
1651 i2c_dev->msg_num = num;
1652 i2c_dev->msg_id = 0;
9e48155f 1653 f7_msg->smbus = false;
aeb068c5 1654
4e7bca6f
PYM		 1655 ret = pm_runtime_get_sync(i2c_dev->dev);
1656 if (ret < 0)
aeb068c5 1657 return ret;
aeb068c5
PYM		 1658
1659 ret = stm32f7_i2c_wait_free_bus(i2c_dev);
1660 if (ret)
4e7bca6f 1661 goto pm_free;
aeb068c5
PYM		 1662
1663 stm32f7_i2c_xfer_msg(i2c_dev, msgs);
1664
1665 time_left = wait_for_completion_timeout(&i2c_dev->complete,
1666 i2c_dev->adap.timeout);
1667 ret = f7_msg->result;
1668
1669 if (!time_left) {
1670 dev_dbg(i2c_dev->dev, "Access to slave 0x%x timed out\n",
1671 i2c_dev->msg->addr);
7ecc8cfd
PYM		 1672 if (i2c_dev->use_dma)
1673 dmaengine_terminate_all(dma->chan_using);
aeb068c5
PYM		 1674 ret = -ETIMEDOUT;
1675 }
1676
4e7bca6f
PYM		 1677pm_free:
1678 pm_runtime_mark_last_busy(i2c_dev->dev);
1679 pm_runtime_put_autosuspend(i2c_dev->dev);
aeb068c5
PYM		 1680
1681 return (ret < 0) ? ret : num;
1682}
1683
9e48155f
PYM		 1684static int stm32f7_i2c_smbus_xfer(struct i2c_adapter *adapter, u16 addr,
1685 unsigned short flags, char read_write,
1686 u8 command, int size,
1687 union i2c_smbus_data *data)
1688{
1689 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adapter);
1690 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
7ecc8cfd 1691 struct stm32_i2c_dma *dma = i2c_dev->dma;
9e48155f
PYM		 1692 struct device *dev = i2c_dev->dev;
1693 unsigned long timeout;
1694 int i, ret;
1695
1696 f7_msg->addr = addr;
1697 f7_msg->size = size;
1698 f7_msg->read_write = read_write;
1699 f7_msg->smbus = true;
1700
4e7bca6f
PYM		 1701 ret = pm_runtime_get_sync(dev);
1702 if (ret < 0)
9e48155f 1703 return ret;
9e48155f
PYM		 1704
1705 ret = stm32f7_i2c_wait_free_bus(i2c_dev);
1706 if (ret)
4e7bca6f 1707 goto pm_free;
9e48155f
PYM		 1708
1709 ret = stm32f7_i2c_smbus_xfer_msg(i2c_dev, flags, command, data);
1710 if (ret)
4e7bca6f 1711 goto pm_free;
9e48155f
PYM		 1712
1713 timeout = wait_for_completion_timeout(&i2c_dev->complete,
1714 i2c_dev->adap.timeout);
1715 ret = f7_msg->result;
1716 if (ret)
4e7bca6f 1717 goto pm_free;
9e48155f
PYM		 1718
1719 if (!timeout) {
1720 dev_dbg(dev, "Access to slave 0x%x timed out\n", f7_msg->addr);
7ecc8cfd
PYM		 1721 if (i2c_dev->use_dma)
1722 dmaengine_terminate_all(dma->chan_using);
9e48155f 1723 ret = -ETIMEDOUT;
4e7bca6f 1724 goto pm_free;
9e48155f
PYM		 1725 }
1726
1727 /* Check PEC */
1728 if ((flags & I2C_CLIENT_PEC) && size != I2C_SMBUS_QUICK && read_write) {
1729 ret = stm32f7_i2c_smbus_check_pec(i2c_dev);
1730 if (ret)
4e7bca6f 1731 goto pm_free;
9e48155f
PYM		 1732 }
1733
1734 if (read_write && size != I2C_SMBUS_QUICK) {
1735 switch (size) {
1736 case I2C_SMBUS_BYTE:
1737 case I2C_SMBUS_BYTE_DATA:
1738 data->byte = f7_msg->smbus_buf[0];
1739 break;
1740 case I2C_SMBUS_WORD_DATA:
1741 case I2C_SMBUS_PROC_CALL:
1742 data->word = f7_msg->smbus_buf[0] |
1743 (f7_msg->smbus_buf[1] << 8);
1744 break;
1745 case I2C_SMBUS_BLOCK_DATA:
1746 case I2C_SMBUS_BLOCK_PROC_CALL:
1747 for (i = 0; i <= f7_msg->smbus_buf[0]; i++)
1748 data->block[i] = f7_msg->smbus_buf[i];
1749 break;
1750 default:
1751 dev_err(dev, "Unsupported smbus transaction\n");
1752 ret = -EINVAL;
1753 }
1754 }
1755
4e7bca6f
PYM		 1756pm_free:
1757 pm_runtime_mark_last_busy(dev);
1758 pm_runtime_put_autosuspend(dev);
9e48155f
PYM		 1759 return ret;
1760}
1761
419be8e1
AV		 1762static void stm32f7_i2c_enable_wakeup(struct stm32f7_i2c_dev *i2c_dev,
1763 bool enable)
1764{
1765 void __iomem *base = i2c_dev->base;
1766 u32 mask = STM32F7_I2C_CR1_WUPEN;
1767
1768 if (!i2c_dev->wakeup_src)
1769 return;
1770
1771 if (enable) {
1772 device_set_wakeup_enable(i2c_dev->dev, true);
1773 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1774 } else {
1775 device_set_wakeup_enable(i2c_dev->dev, false);
1776 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
1777 }
1778}
1779
60d609f3
PYM		 1780static int stm32f7_i2c_reg_slave(struct i2c_client *slave)
1781{
1782 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter);
1783 void __iomem *base = i2c_dev->base;
1784 struct device *dev = i2c_dev->dev;
1785 u32 oar1, oar2, mask;
1786 int id, ret;
1787
1788 if (slave->flags & I2C_CLIENT_PEC) {
1789 dev_err(dev, "SMBus PEC not supported in slave mode\n");
1790 return -EINVAL;
1791 }
1792
1793 if (stm32f7_i2c_is_slave_busy(i2c_dev)) {
1794 dev_err(dev, "Too much slave registered\n");
1795 return -EBUSY;
1796 }
1797
1798 ret = stm32f7_i2c_get_free_slave_id(i2c_dev, slave, &id);
1799 if (ret)
1800 return ret;
1801
4e7bca6f
PYM		 1802 ret = pm_runtime_get_sync(dev);
1803 if (ret < 0)
1804 return ret;
60d609f3 1805
419be8e1
AV		 1806 if (!stm32f7_i2c_is_slave_registered(i2c_dev))
1807 stm32f7_i2c_enable_wakeup(i2c_dev, true);
1808
6af07719
AV		 1809 switch (id) {
1810 case 0:
1811 /* Slave SMBus Host */
1812 i2c_dev->slave[id] = slave;
1813 break;
1814
1815 case 1:
60d609f3
PYM		 1816 /* Configure Own Address 1 */
1817 oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1);
1818 oar1 &= ~STM32F7_I2C_OAR1_MASK;
1819 if (slave->flags & I2C_CLIENT_TEN) {
1820 oar1 |= STM32F7_I2C_OAR1_OA1_10(slave->addr);
1821 oar1 |= STM32F7_I2C_OAR1_OA1MODE;
1822 } else {
1823 oar1 |= STM32F7_I2C_OAR1_OA1_7(slave->addr);
1824 }
1825 oar1 |= STM32F7_I2C_OAR1_OA1EN;
1826 i2c_dev->slave[id] = slave;
1827 writel_relaxed(oar1, i2c_dev->base + STM32F7_I2C_OAR1);
6af07719
AV		 1828 break;
1829
1830 case 2:
60d609f3
PYM		 1831 /* Configure Own Address 2 */
1832 oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2);
1833 oar2 &= ~STM32F7_I2C_OAR2_MASK;
1834 if (slave->flags & I2C_CLIENT_TEN) {
1835 ret = -EOPNOTSUPP;
4e7bca6f 1836 goto pm_free;
60d609f3
PYM		 1837 }
1838
1839 oar2 |= STM32F7_I2C_OAR2_OA2_7(slave->addr);
1840 oar2 |= STM32F7_I2C_OAR2_OA2EN;
1841 i2c_dev->slave[id] = slave;
1842 writel_relaxed(oar2, i2c_dev->base + STM32F7_I2C_OAR2);
6af07719
AV		 1843 break;
1844
1845 default:
1846 dev_err(dev, "I2C slave id not supported\n");
60d609f3 1847 ret = -ENODEV;
4e7bca6f 1848 goto pm_free;
60d609f3
PYM		 1849 }
1850
1851 /* Enable ACK */
1852 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, STM32F7_I2C_CR2_NACK);
1853
1854 /* Enable Address match interrupt, error interrupt and enable I2C */
1855 mask = STM32F7_I2C_CR1_ADDRIE | STM32F7_I2C_CR1_ERRIE |
1856 STM32F7_I2C_CR1_PE;
1857 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1858
4e7bca6f
PYM		 1859 ret = 0;
1860pm_free:
419be8e1
AV		 1861 if (!stm32f7_i2c_is_slave_registered(i2c_dev))
1862 stm32f7_i2c_enable_wakeup(i2c_dev, false);
1863
4e7bca6f
PYM		 1864 pm_runtime_mark_last_busy(dev);
1865 pm_runtime_put_autosuspend(dev);
60d609f3
PYM		 1866
1867 return ret;
1868}
1869
1870static int stm32f7_i2c_unreg_slave(struct i2c_client *slave)
1871{
1872 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter);
1873 void __iomem *base = i2c_dev->base;
1874 u32 mask;
1875 int id, ret;
1876
1877 ret = stm32f7_i2c_get_slave_id(i2c_dev, slave, &id);
1878 if (ret)
1879 return ret;
1880
1881 WARN_ON(!i2c_dev->slave[id]);
1882
4e7bca6f
PYM		 1883 ret = pm_runtime_get_sync(i2c_dev->dev);
1884 if (ret < 0)
1885 return ret;
1886
6af07719 1887 if (id == 1) {
60d609f3
PYM		 1888 mask = STM32F7_I2C_OAR1_OA1EN;
1889 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR1, mask);
6af07719 1890 } else if (id == 2) {
60d609f3
PYM		 1891 mask = STM32F7_I2C_OAR2_OA2EN;
1892 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR2, mask);
1893 }
1894
1895 i2c_dev->slave[id] = NULL;
1896
419be8e1 1897 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) {
60d609f3 1898 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_ALL_IRQ_MASK);
419be8e1
AV		 1899 stm32f7_i2c_enable_wakeup(i2c_dev, false);
1900 }
4e7bca6f
PYM		 1901
1902 pm_runtime_mark_last_busy(i2c_dev->dev);
1903 pm_runtime_put_autosuspend(i2c_dev->dev);
60d609f3
PYM		 1904
1905 return 0;
1906}
1907
3347ea9b
AV		 1908static int stm32f7_i2c_write_fm_plus_bits(struct stm32f7_i2c_dev *i2c_dev,
1909 bool enable)
1910{
0f820564
AV		 1911 int ret;
1912
09cc9a3b 1913 if (i2c_dev->bus_rate <= I2C_MAX_FAST_MODE_FREQ ||
3347ea9b
AV		 1914 IS_ERR_OR_NULL(i2c_dev->regmap))
1915 /* Optional */
1916 return 0;
1917
0f820564
AV		 1918 if (i2c_dev->fmp_sreg == i2c_dev->fmp_creg)
1919 ret = regmap_update_bits(i2c_dev->regmap,
1920 i2c_dev->fmp_sreg,
1921 i2c_dev->fmp_mask,
1922 enable ? i2c_dev->fmp_mask : 0);
1923 else
1924 ret = regmap_write(i2c_dev->regmap,
1925 enable ? i2c_dev->fmp_sreg :
1926 i2c_dev->fmp_creg,
1927 i2c_dev->fmp_mask);
1928
1929 return ret;
3347ea9b
AV		 1930}
1931
cb944fb9
PYM		 1932static int stm32f7_i2c_setup_fm_plus_bits(struct platform_device *pdev,
1933 struct stm32f7_i2c_dev *i2c_dev)
1934{
1935 struct device_node *np = pdev->dev.of_node;
1936 int ret;
cb944fb9
PYM		 1937
1938 i2c_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg-fmp");
3347ea9b 1939 if (IS_ERR(i2c_dev->regmap))
cb944fb9
PYM		 1940 /* Optional */
1941 return 0;
cb944fb9 1942
3347ea9b 1943 ret = of_property_read_u32_index(np, "st,syscfg-fmp", 1,
0f820564 1944 &i2c_dev->fmp_sreg);
cb944fb9
PYM		 1945 if (ret)
1946 return ret;
1947
0f820564
AV		 1948 i2c_dev->fmp_creg = i2c_dev->fmp_sreg +
1949 i2c_dev->setup.fmp_clr_offset;
1950
3347ea9b
AV		 1951 return of_property_read_u32_index(np, "st,syscfg-fmp", 2,
1952 &i2c_dev->fmp_mask);
cb944fb9
PYM		 1953}
1954
6af07719
AV		 1955static int stm32f7_i2c_enable_smbus_host(struct stm32f7_i2c_dev *i2c_dev)
1956{
1957 struct i2c_adapter *adap = &i2c_dev->adap;
1958 void __iomem *base = i2c_dev->base;
1959 struct i2c_client *client;
1960
1961 client = i2c_new_slave_host_notify_device(adap);
1962 if (IS_ERR(client))
1963 return PTR_ERR(client);
1964
1965 i2c_dev->host_notify_client = client;
1966
1967 /* Enable SMBus Host address */
1968 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, STM32F7_I2C_CR1_SMBHEN);
1969
1970 return 0;
1971}
1972
1973static void stm32f7_i2c_disable_smbus_host(struct stm32f7_i2c_dev *i2c_dev)
1974{
1975 void __iomem *base = i2c_dev->base;
1976
1977 if (i2c_dev->host_notify_client) {
1978 /* Disable SMBus Host address */
1979 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1,
1980 STM32F7_I2C_CR1_SMBHEN);
1981 i2c_free_slave_host_notify_device(i2c_dev->host_notify_client);
1982 }
1983}
1984
aeb068c5
PYM		 1985static u32 stm32f7_i2c_func(struct i2c_adapter *adap)
1986{
6af07719
AV		 1987 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
1988
1989 u32 func = I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SLAVE |
1990 I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
1991 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
1992 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
1993 I2C_FUNC_SMBUS_PROC_CALL | I2C_FUNC_SMBUS_PEC |
1994 I2C_FUNC_SMBUS_I2C_BLOCK;
1995
1996 if (i2c_dev->smbus_mode)
1997 func |= I2C_FUNC_SMBUS_HOST_NOTIFY;
1998
1999 return func;
aeb068c5
PYM		 2000}
2001
2252c317 2002static const struct i2c_algorithm stm32f7_i2c_algo = {
aeb068c5 2003 .master_xfer = stm32f7_i2c_xfer,
9e48155f 2004 .smbus_xfer = stm32f7_i2c_smbus_xfer,
aeb068c5 2005 .functionality = stm32f7_i2c_func,
60d609f3
PYM		 2006 .reg_slave = stm32f7_i2c_reg_slave,
2007 .unreg_slave = stm32f7_i2c_unreg_slave,
aeb068c5
PYM		 2008};
2009
2010static int stm32f7_i2c_probe(struct platform_device *pdev)
2011{
aeb068c5
PYM		 2012 struct stm32f7_i2c_dev *i2c_dev;
2013 const struct stm32f7_i2c_setup *setup;
2014 struct resource *res;
aeb068c5
PYM		 2015 struct i2c_adapter *adap;
2016 struct reset_control *rst;
7ecc8cfd 2017 dma_addr_t phy_addr;
79b44995 2018 int irq_error, irq_event, ret;
aeb068c5
PYM		 2019
2020 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
2021 if (!i2c_dev)
2022 return -ENOMEM;
2023
c02fb2b8 2024 i2c_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
aeb068c5
PYM		 2025 if (IS_ERR(i2c_dev->base))
2026 return PTR_ERR(i2c_dev->base);
7ecc8cfd 2027 phy_addr = (dma_addr_t)res->start;
aeb068c5 2028
79b44995
FG		 2029 irq_event = platform_get_irq(pdev, 0);
2030 if (irq_event <= 0) {
2031 if (irq_event != -EPROBE_DEFER)
2032 dev_err(&pdev->dev, "Failed to get IRQ event: %d\n",
2033 irq_event);
2034 return irq_event ? : -ENOENT;
aeb068c5
PYM		 2035 }
2036
79b44995 2037 irq_error = platform_get_irq(pdev, 1);
0b16cfd9 2038 if (irq_error <= 0)
79b44995 2039 return irq_error ? : -ENOENT;
aeb068c5 2040
419be8e1
AV		 2041 i2c_dev->wakeup_src = of_property_read_bool(pdev->dev.of_node,
2042 "wakeup-source");
2043
aeb068c5 2044 i2c_dev->clk = devm_clk_get(&pdev->dev, NULL);
703b3228
KK		 2045 if (IS_ERR(i2c_dev->clk))
2046 return dev_err_probe(&pdev->dev, PTR_ERR(i2c_dev->clk),
2047 "Failed to get controller clock\n");
4e7bca6f 2048
aeb068c5
PYM		 2049 ret = clk_prepare_enable(i2c_dev->clk);
2050 if (ret) {
2051 dev_err(&pdev->dev, "Failed to prepare_enable clock\n");
2052 return ret;
2053 }
2054
aeb068c5
PYM		 2055 rst = devm_reset_control_get(&pdev->dev, NULL);
2056 if (IS_ERR(rst)) {
703b3228
KK		 2057 ret = dev_err_probe(&pdev->dev, PTR_ERR(rst),
2058 "Error: Missing reset ctrl\n");
aeb068c5
PYM		 2059 goto clk_free;
2060 }
2061 reset_control_assert(rst);
2062 udelay(2);
2063 reset_control_deassert(rst);
2064
2065 i2c_dev->dev = &pdev->dev;
2066
7ecc8cfd
PYM		 2067 ret = devm_request_threaded_irq(&pdev->dev, irq_event,
2068 stm32f7_i2c_isr_event,
2069 stm32f7_i2c_isr_event_thread,
2070 IRQF_ONESHOT,
2071 pdev->name, i2c_dev);
aeb068c5
PYM		 2072 if (ret) {
2073 dev_err(&pdev->dev, "Failed to request irq event %i\n",
2074 irq_event);
2075 goto clk_free;
2076 }
2077
2078 ret = devm_request_irq(&pdev->dev, irq_error, stm32f7_i2c_isr_error, 0,
2079 pdev->name, i2c_dev);
2080 if (ret) {
2081 dev_err(&pdev->dev, "Failed to request irq error %i\n",
2082 irq_error);
2083 goto clk_free;
2084 }
2085
2086 setup = of_device_get_match_data(&pdev->dev);
771b7bf0
PYM		 2087 if (!setup) {
2088 dev_err(&pdev->dev, "Can't get device data\n");
2089 ret = -ENODEV;
2090 goto clk_free;
2091 }
463a9215 2092 i2c_dev->setup = *setup;
aeb068c5 2093
463a9215 2094 ret = stm32f7_i2c_setup_timing(i2c_dev, &i2c_dev->setup);
aeb068c5
PYM		 2095 if (ret)
2096 goto clk_free;
2097
09cc9a3b
AV		 2098 /* Setup Fast mode plus if necessary */
2099 if (i2c_dev->bus_rate > I2C_MAX_FAST_MODE_FREQ) {
3347ea9b
AV		 2100 ret = stm32f7_i2c_setup_fm_plus_bits(pdev, i2c_dev);
2101 if (ret)
2102 goto clk_free;
2103 ret = stm32f7_i2c_write_fm_plus_bits(i2c_dev, true);
2104 if (ret)
2105 goto clk_free;
2106 }
2107
aeb068c5
PYM		 2108 adap = &i2c_dev->adap;
2109 i2c_set_adapdata(adap, i2c_dev);
2110 snprintf(adap->name, sizeof(adap->name), "STM32F7 I2C(%pa)",
2111 &res->start);
2112 adap->owner = THIS_MODULE;
2113 adap->timeout = 2 * HZ;
2114 adap->retries = 3;
2115 adap->algo = &stm32f7_i2c_algo;
2116 adap->dev.parent = &pdev->dev;
2117 adap->dev.of_node = pdev->dev.of_node;
2118
2119 init_completion(&i2c_dev->complete);
2120
7ecc8cfd
PYM		 2121 /* Init DMA config if supported */
2122 i2c_dev->dma = stm32_i2c_dma_request(i2c_dev->dev, phy_addr,
2123 STM32F7_I2C_TXDR,
2124 STM32F7_I2C_RXDR);
27c90870 2125 if (IS_ERR(i2c_dev->dma)) {
d77eceb2 2126 ret = PTR_ERR(i2c_dev->dma);
27c90870
AV		 2127 /* DMA support is optional, only report other errors */
2128 if (ret != -ENODEV)
2129 goto fmp_clear;
2130 dev_dbg(i2c_dev->dev, "No DMA option: fallback using interrupts\n");
2131 i2c_dev->dma = NULL;
d77eceb2 2132 }
7ecc8cfd 2133
419be8e1
AV		 2134 if (i2c_dev->wakeup_src) {
2135 device_set_wakeup_capable(i2c_dev->dev, true);
2136
2137 ret = dev_pm_set_wake_irq(i2c_dev->dev, irq_event);
2138 if (ret) {
2139 dev_err(i2c_dev->dev, "Failed to set wake up irq\n");
2140 goto clr_wakeup_capable;
2141 }
2142 }
2143
aeb068c5
PYM		 2144 platform_set_drvdata(pdev, i2c_dev);
2145
4e7bca6f
PYM		 2146 pm_runtime_set_autosuspend_delay(i2c_dev->dev,
2147 STM32F7_AUTOSUSPEND_DELAY);
2148 pm_runtime_use_autosuspend(i2c_dev->dev);
2149 pm_runtime_set_active(i2c_dev->dev);
2150 pm_runtime_enable(i2c_dev->dev);
2151
2152 pm_runtime_get_noresume(&pdev->dev);
2153
2154 stm32f7_i2c_hw_config(i2c_dev);
2155
6af07719
AV		 2156 i2c_dev->smbus_mode = of_property_read_bool(pdev->dev.of_node, "smbus");
2157
4e7bca6f
PYM		 2158 ret = i2c_add_adapter(adap);
2159 if (ret)
2160 goto pm_disable;
aeb068c5 2161
6af07719
AV		 2162 if (i2c_dev->smbus_mode) {
2163 ret = stm32f7_i2c_enable_smbus_host(i2c_dev);
2164 if (ret) {
2165 dev_err(i2c_dev->dev,
2166 "failed to enable SMBus Host-Notify protocol (%d)\n",
2167 ret);
2168 goto i2c_adapter_remove;
2169 }
2170 }
2171
aeb068c5
PYM		 2172 dev_info(i2c_dev->dev, "STM32F7 I2C-%d bus adapter\n", adap->nr);
2173
4e7bca6f
PYM		 2174 pm_runtime_mark_last_busy(i2c_dev->dev);
2175 pm_runtime_put_autosuspend(i2c_dev->dev);
2176
aeb068c5
PYM		 2177 return 0;
2178
6af07719
AV		 2179i2c_adapter_remove:
2180 i2c_del_adapter(adap);
2181
4e7bca6f
PYM		 2182pm_disable:
2183 pm_runtime_put_noidle(i2c_dev->dev);
2184 pm_runtime_disable(i2c_dev->dev);
2185 pm_runtime_set_suspended(i2c_dev->dev);
2186 pm_runtime_dont_use_autosuspend(i2c_dev->dev);
2187
419be8e1
AV		 2188 if (i2c_dev->wakeup_src)
2189 dev_pm_clear_wake_irq(i2c_dev->dev);
2190
2191clr_wakeup_capable:
2192 if (i2c_dev->wakeup_src)
2193 device_set_wakeup_capable(i2c_dev->dev, false);
2194
53aaaa5d
AV		 2195 if (i2c_dev->dma) {
2196 stm32_i2c_dma_free(i2c_dev->dma);
2197 i2c_dev->dma = NULL;
2198 }
2199
3347ea9b
AV		 2200fmp_clear:
2201 stm32f7_i2c_write_fm_plus_bits(i2c_dev, false);
2202
aeb068c5
PYM		 2203clk_free:
2204 clk_disable_unprepare(i2c_dev->clk);
2205
2206 return ret;
2207}
2208
2209static int stm32f7_i2c_remove(struct platform_device *pdev)
2210{
2211 struct stm32f7_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
2212
6af07719
AV		 2213 stm32f7_i2c_disable_smbus_host(i2c_dev);
2214
aeb068c5 2215 i2c_del_adapter(&i2c_dev->adap);
4e7bca6f
PYM		 2216 pm_runtime_get_sync(i2c_dev->dev);
2217
419be8e1
AV		 2218 if (i2c_dev->wakeup_src) {
2219 dev_pm_clear_wake_irq(i2c_dev->dev);
2220 /*
2221 * enforce that wakeup is disabled and that the device
2222 * is marked as non wakeup capable
2223 */
2224 device_init_wakeup(i2c_dev->dev, false);
2225 }
2226
4e7bca6f
PYM		 2227 pm_runtime_put_noidle(i2c_dev->dev);
2228 pm_runtime_disable(i2c_dev->dev);
2229 pm_runtime_set_suspended(i2c_dev->dev);
2230 pm_runtime_dont_use_autosuspend(i2c_dev->dev);
2231
53aaaa5d
AV		 2232 if (i2c_dev->dma) {
2233 stm32_i2c_dma_free(i2c_dev->dma);
2234 i2c_dev->dma = NULL;
2235 }
2236
3347ea9b
AV		 2237 stm32f7_i2c_write_fm_plus_bits(i2c_dev, false);
2238
53aaaa5d
AV		 2239 clk_disable_unprepare(i2c_dev->clk);
2240
4e7bca6f
PYM		 2241 return 0;
2242}
2243
ea6dd25d 2244static int __maybe_unused stm32f7_i2c_runtime_suspend(struct device *dev)
4e7bca6f
PYM		 2245{
2246 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2247
2248 if (!stm32f7_i2c_is_slave_registered(i2c_dev))
2249 clk_disable_unprepare(i2c_dev->clk);
2250
2251 return 0;
2252}
2253
ea6dd25d 2254static int __maybe_unused stm32f7_i2c_runtime_resume(struct device *dev)
4e7bca6f
PYM		 2255{
2256 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2257 int ret;
aeb068c5 2258
4e7bca6f
PYM		 2259 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) {
2260 ret = clk_prepare_enable(i2c_dev->clk);
2261 if (ret) {
2262 dev_err(dev, "failed to prepare_enable clock\n");
2263 return ret;
2264 }
2265 }
aeb068c5
PYM		 2266
2267 return 0;
2268}
ea6dd25d 2269
419be8e1
AV		 2270#ifdef CONFIG_PM_SLEEP
2271static int stm32f7_i2c_regs_backup(struct stm32f7_i2c_dev *i2c_dev)
ea6dd25d
AV		 2272{
2273 int ret;
2274 struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs;
2275
2276 ret = pm_runtime_get_sync(i2c_dev->dev);
2277 if (ret < 0)
2278 return ret;
2279
2280 backup_regs->cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1);
2281 backup_regs->cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
2282 backup_regs->oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1);
2283 backup_regs->oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2);
ea6dd25d 2284 backup_regs->tmgr = readl_relaxed(i2c_dev->base + STM32F7_I2C_TIMINGR);
3347ea9b 2285 stm32f7_i2c_write_fm_plus_bits(i2c_dev, false);
ea6dd25d
AV		 2286
2287 pm_runtime_put_sync(i2c_dev->dev);
2288
2289 return ret;
2290}
2291
419be8e1 2292static int stm32f7_i2c_regs_restore(struct stm32f7_i2c_dev *i2c_dev)
ea6dd25d
AV		 2293{
2294 u32 cr1;
2295 int ret;
2296 struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs;
2297
2298 ret = pm_runtime_get_sync(i2c_dev->dev);
2299 if (ret < 0)
2300 return ret;
2301
2302 cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1);
2303 if (cr1 & STM32F7_I2C_CR1_PE)
2304 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
2305 STM32F7_I2C_CR1_PE);
2306
2307 writel_relaxed(backup_regs->tmgr, i2c_dev->base + STM32F7_I2C_TIMINGR);
2308 writel_relaxed(backup_regs->cr1 & ~STM32F7_I2C_CR1_PE,
2309 i2c_dev->base + STM32F7_I2C_CR1);
2310 if (backup_regs->cr1 & STM32F7_I2C_CR1_PE)
2311 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
2312 STM32F7_I2C_CR1_PE);
2313 writel_relaxed(backup_regs->cr2, i2c_dev->base + STM32F7_I2C_CR2);
2314 writel_relaxed(backup_regs->oar1, i2c_dev->base + STM32F7_I2C_OAR1);
2315 writel_relaxed(backup_regs->oar2, i2c_dev->base + STM32F7_I2C_OAR2);
3347ea9b 2316 stm32f7_i2c_write_fm_plus_bits(i2c_dev, true);
ea6dd25d
AV		 2317
2318 pm_runtime_put_sync(i2c_dev->dev);
2319
2320 return ret;
2321}
2322
419be8e1 2323static int stm32f7_i2c_suspend(struct device *dev)
ea6dd25d
AV		 2324{
2325 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2326 int ret;
2327
2328 i2c_mark_adapter_suspended(&i2c_dev->adap);
ea6dd25d 2329
4e1d9a73 2330 if (!device_may_wakeup(dev) && !device_wakeup_path(dev)) {
419be8e1
AV		 2331 ret = stm32f7_i2c_regs_backup(i2c_dev);
2332 if (ret < 0) {
2333 i2c_mark_adapter_resumed(&i2c_dev->adap);
2334 return ret;
2335 }
2336
2337 pinctrl_pm_select_sleep_state(dev);
2338 pm_runtime_force_suspend(dev);
2339 }
ea6dd25d
AV		 2340
2341 return 0;
2342}
2343
419be8e1 2344static int stm32f7_i2c_resume(struct device *dev)
ea6dd25d
AV		 2345{
2346 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2347 int ret;
2348
4e1d9a73 2349 if (!device_may_wakeup(dev) && !device_wakeup_path(dev)) {
419be8e1
AV		 2350 ret = pm_runtime_force_resume(dev);
2351 if (ret < 0)
2352 return ret;
2353 pinctrl_pm_select_default_state(dev);
2354
2355 ret = stm32f7_i2c_regs_restore(i2c_dev);
2356 if (ret < 0)
2357 return ret;
2358 }
ea6dd25d 2359
ea6dd25d
AV		 2360 i2c_mark_adapter_resumed(&i2c_dev->adap);
2361
2362 return 0;
2363}
419be8e1 2364#endif
4e7bca6f
PYM		 2365
2366static const struct dev_pm_ops stm32f7_i2c_pm_ops = {
2367 SET_RUNTIME_PM_OPS(stm32f7_i2c_runtime_suspend,
2368 stm32f7_i2c_runtime_resume, NULL)
ea6dd25d 2369 SET_SYSTEM_SLEEP_PM_OPS(stm32f7_i2c_suspend, stm32f7_i2c_resume)
4e7bca6f 2370};
aeb068c5
PYM		 2371
2372static const struct of_device_id stm32f7_i2c_match[] = {
2373 { .compatible = "st,stm32f7-i2c", .data = &stm32f7_setup},
0f820564 2374 { .compatible = "st,stm32mp15-i2c", .data = &stm32mp15_setup},
aeb068c5
PYM		 2375 {},
2376};
2377MODULE_DEVICE_TABLE(of, stm32f7_i2c_match);
2378
2379static struct platform_driver stm32f7_i2c_driver = {
2380 .driver = {
2381 .name = "stm32f7-i2c",
2382 .of_match_table = stm32f7_i2c_match,
4e7bca6f 2383 .pm = &stm32f7_i2c_pm_ops,
aeb068c5
PYM		 2384 },
2385 .probe = stm32f7_i2c_probe,
2386 .remove = stm32f7_i2c_remove,
2387};
2388
2389module_platform_driver(stm32f7_i2c_driver);
2390
2391MODULE_AUTHOR("M'boumba Cedric Madianga <cedric.madianga@gmail.com>");
2392MODULE_DESCRIPTION("STMicroelectronics STM32F7 I2C driver");
2393MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)