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Merge tag 'i2c-for-6.10-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa...
[linux-block.git] / drivers / i2c / busses / i2c-sh_mobile.c
CommitLineData
6055af5e 1// SPDX-License-Identifier: GPL-2.0
da672773
MD		 2/*
3 * SuperH Mobile I2C Controller
4 *
9d899ed4 5 * Copyright (C) 2014-19 Wolfram Sang <wsa@sang-engineering.com>
da672773
MD		 6 * Copyright (C) 2008 Magnus Damm
7 *
8 * Portions of the code based on out-of-tree driver i2c-sh7343.c
9 * Copyright (c) 2006 Carlos Munoz <carlos@kenati.com>
da672773
MD		 10 */
11
5bbe6879
WS		 12#include <linux/clk.h>
13#include <linux/delay.h>
2d09581b
WS		 14#include <linux/dmaengine.h>
15#include <linux/dma-mapping.h>
5bbe6879
WS		 16#include <linux/err.h>
17#include <linux/i2c.h>
5bbe6879
WS		 18#include <linux/init.h>
19#include <linux/interrupt.h>
20#include <linux/io.h>
da672773
MD		 21#include <linux/kernel.h>
22#include <linux/module.h>
59738ab2 23#include <linux/of.h>
da672773 24#include <linux/platform_device.h>
f1a3b994 25#include <linux/pm_runtime.h>
5a0e3ad6 26#include <linux/slab.h>
da672773 27
4eb00c9f
MD		 28/* Transmit operation: */
29/* */
30/* 0 byte transmit */
e7890297 31/* BUS: S A8 ACK P(*) */
4eb00c9f
MD		 32/* IRQ: DTE WAIT */
33/* ICIC: */
a4fde7e5 34/* ICCR: 0x94 0x90 */
4eb00c9f
MD		 35/* ICDR: A8 */
36/* */
37/* 1 byte transmit */
e7890297 38/* BUS: S A8 ACK D8(1) ACK P(*) */
4eb00c9f
MD		 39/* IRQ: DTE WAIT WAIT */
40/* ICIC: -DTE */
a4fde7e5 41/* ICCR: 0x94 0x90 */
4eb00c9f
MD		 42/* ICDR: A8 D8(1) */
43/* */
44/* 2 byte transmit */
e7890297 45/* BUS: S A8 ACK D8(1) ACK D8(2) ACK P(*) */
4eb00c9f
MD		 46/* IRQ: DTE WAIT WAIT WAIT */
47/* ICIC: -DTE */
a4fde7e5 48/* ICCR: 0x94 0x90 */
4eb00c9f
MD		 49/* ICDR: A8 D8(1) D8(2) */
50/* */
51/* 3 bytes or more, +---------+ gets repeated */
52/* */
53/* */
54/* Receive operation: */
55/* */
56/* 0 byte receive - not supported since slave may hold SDA low */
57/* */
58/* 1 byte receive [TX] | [RX] */
e7890297 59/* BUS: S A8 ACK | D8(1) ACK P(*) */
4eb00c9f
MD		 60/* IRQ: DTE WAIT | WAIT DTE */
61/* ICIC: -DTE | +DTE */
62/* ICCR: 0x94 0x81 | 0xc0 */
63/* ICDR: A8 | D8(1) */
64/* */
65/* 2 byte receive [TX]| [RX] */
e7890297 66/* BUS: S A8 ACK | D8(1) ACK D8(2) ACK P(*) */
4eb00c9f
MD		 67/* IRQ: DTE WAIT | WAIT WAIT DTE */
68/* ICIC: -DTE | +DTE */
69/* ICCR: 0x94 0x81 | 0xc0 */
70/* ICDR: A8 | D8(1) D8(2) */
71/* */
e7890297 72/* 3 byte receive [TX] | [RX] (*) */
4eb00c9f
MD		 73/* BUS: S A8 ACK | D8(1) ACK D8(2) ACK D8(3) ACK P */
74/* IRQ: DTE WAIT | WAIT WAIT WAIT DTE */
75/* ICIC: -DTE | +DTE */
76/* ICCR: 0x94 0x81 | 0xc0 */
77/* ICDR: A8 | D8(1) D8(2) D8(3) */
78/* */
79/* 4 bytes or more, this part is repeated +---------+ */
80/* */
81/* */
82/* Interrupt order and BUSY flag */
83/* ___ _ */
84/* SDA ___\___XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXAAAAAAAAA___/ */
85/* SCL \_/1\_/2\_/3\_/4\_/5\_/6\_/7\_/8\___/9\_____/ */
86/* */
e7890297 87/* S D7 D6 D5 D4 D3 D2 D1 D0 P(*) */
4eb00c9f
MD		 88/* ___ */
89/* WAIT IRQ ________________________________/ \___________ */
90/* TACK IRQ ____________________________________/ \_______ */
91/* DTE IRQ __________________________________________/ \_ */
92/* AL IRQ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX */
93/* _______________________________________________ */
94/* BUSY __/ \_ */
95/* */
e7890297
GL		 96/* (*) The STOP condition is only sent by the master at the end of the last */
97/* I2C message or if the I2C_M_STOP flag is set. Similarly, the BUSY bit is */
98/* only cleared after the STOP condition, so, between messages we have to */
99/* poll for the DTE bit. */
100/* */
4eb00c9f 101
da672773
MD		 102enum sh_mobile_i2c_op {
103 OP_START = 0,
4eb00c9f
MD		 104 OP_TX_FIRST,
105 OP_TX,
da672773
MD		 106 OP_TX_STOP,
107 OP_TX_TO_RX,
4eb00c9f 108 OP_RX,
da672773 109 OP_RX_STOP,
4eb00c9f 110 OP_RX_STOP_DATA,
da672773
MD		 111};
112
113struct sh_mobile_i2c_data {
114 struct device *dev;
115 void __iomem *reg;
116 struct i2c_adapter adap;
81f81153 117 unsigned long bus_speed;
ebd5ac16 118 unsigned int clks_per_count;
da672773 119 struct clk *clk;
962b6032 120 u_int8_t icic;
962b6032 121 u_int8_t flags;
23a61291
SK		 122 u_int16_t iccl;
123 u_int16_t icch;
da672773
MD		 124
125 spinlock_t lock;
126 wait_queue_head_t wait;
127 struct i2c_msg *msg;
128 int pos;
129 int sr;
e7890297 130 bool send_stop;
32e22409 131 bool stop_after_dma;
a49cc1fe 132 bool atomic_xfer;
2d09581b 133
55f5f986 134 struct resource *res;
2d09581b
WS		 135 struct dma_chan *dma_tx;
136 struct dma_chan *dma_rx;
137 struct scatterlist sg;
138 enum dma_data_direction dma_direction;
fe23aa9a 139 u8 *dma_buf;
da672773
MD		 140};
141
67240dfc
WS		 142struct sh_mobile_dt_config {
143 int clks_per_count;
12742b6a 144 int (*setup)(struct sh_mobile_i2c_data *pd);
67240dfc
WS		 145};
146
962b6032
MD		 147#define IIC_FLAG_HAS_ICIC67 (1 << 0)
148
da672773 149/* Register offsets */
12a55f2d
MD		 150#define ICDR 0x00
151#define ICCR 0x04
152#define ICSR 0x08
153#define ICIC 0x0c
154#define ICCL 0x10
155#define ICCH 0x14
3ded3743 156#define ICSTART 0x70
da672773
MD		 157
158/* Register bits */
159#define ICCR_ICE 0x80
160#define ICCR_RACK 0x40
161#define ICCR_TRS 0x10
162#define ICCR_BBSY 0x04
163#define ICCR_SCP 0x01
164
165#define ICSR_SCLM 0x80
166#define ICSR_SDAM 0x40
167#define SW_DONE 0x20
168#define ICSR_BUSY 0x10
169#define ICSR_AL 0x08
170#define ICSR_TACK 0x04
171#define ICSR_WAIT 0x02
172#define ICSR_DTE 0x01
173
962b6032
MD		 174#define ICIC_ICCLB8 0x80
175#define ICIC_ICCHB8 0x40
2d09581b
WS		 176#define ICIC_TDMAE 0x20
177#define ICIC_RDMAE 0x10
da672773
MD		 178#define ICIC_ALE 0x08
179#define ICIC_TACKE 0x04
180#define ICIC_WAITE 0x02
181#define ICIC_DTEE 0x01
182
3ded3743
WS		 183#define ICSTART_ICSTART 0x10
184
12a55f2d
MD		 185static void iic_wr(struct sh_mobile_i2c_data *pd, int offs, unsigned char data)
186{
962b6032
MD		 187 if (offs == ICIC)
188 data |= pd->icic;
189
12a55f2d
MD		 190 iowrite8(data, pd->reg + offs);
191}
192
193static unsigned char iic_rd(struct sh_mobile_i2c_data *pd, int offs)
194{
195 return ioread8(pd->reg + offs);
196}
197
198static void iic_set_clr(struct sh_mobile_i2c_data *pd, int offs,
199 unsigned char set, unsigned char clr)
200{
201 iic_wr(pd, offs, (iic_rd(pd, offs) | set) & ~clr);
202}
203
ed4121e1 204static u32 sh_mobile_i2c_iccl(unsigned long count_khz, u32 tLOW, u32 tf)
23a61291
SK		 205{
206 /*
207 * Conditional expression:
208 * ICCL >= COUNT_CLK * (tLOW + tf)
209 *
210 * SH-Mobile IIC hardware starts counting the LOW period of
211 * the SCL signal (tLOW) as soon as it pulls the SCL line.
212 * In order to meet the tLOW timing spec, we need to take into
213 * account the fall time of SCL signal (tf). Default tf value
214 * should be 0.3 us, for safety.
215 */
ed4121e1 216 return (((count_khz * (tLOW + tf)) + 5000) / 10000);
23a61291
SK		 217}
218
ed4121e1 219static u32 sh_mobile_i2c_icch(unsigned long count_khz, u32 tHIGH, u32 tf)
23a61291
SK		 220{
221 /*
222 * Conditional expression:
223 * ICCH >= COUNT_CLK * (tHIGH + tf)
224 *
225 * SH-Mobile IIC hardware is aware of SCL transition period 'tr',
226 * and can ignore it. SH-Mobile IIC controller starts counting
227 * the HIGH period of the SCL signal (tHIGH) after the SCL input
228 * voltage increases at VIH.
229 *
230 * Afterward it turned out calculating ICCH using only tHIGH spec
231 * will result in violation of the tHD;STA timing spec. We need
232 * to take into account the fall time of SDA signal (tf) at START
233 * condition, in order to meet both tHIGH and tHD;STA specs.
234 */
ed4121e1 235 return (((count_khz * (tHIGH + tf)) + 5000) / 10000);
23a61291
SK		 236}
237
c3449f73
WS		 238static int sh_mobile_i2c_check_timing(struct sh_mobile_i2c_data *pd)
239{
240 u16 max_val = pd->flags & IIC_FLAG_HAS_ICIC67 ? 0x1ff : 0xff;
241
242 if (pd->iccl > max_val || pd->icch > max_val) {
243 dev_err(pd->dev, "timing values out of range: L/H=0x%x/0x%x\n",
244 pd->iccl, pd->icch);
245 return -EINVAL;
246 }
247
248 /* one more bit of ICCL in ICIC */
249 if (pd->iccl & 0x100)
250 pd->icic |= ICIC_ICCLB8;
251 else
252 pd->icic &= ~ICIC_ICCLB8;
253
254 /* one more bit of ICCH in ICIC */
255 if (pd->icch & 0x100)
256 pd->icic |= ICIC_ICCHB8;
257 else
258 pd->icic &= ~ICIC_ICCHB8;
259
260 dev_dbg(pd->dev, "timing values: L/H=0x%x/0x%x\n", pd->iccl, pd->icch);
261 return 0;
262}
263
6ed7053c 264static int sh_mobile_i2c_init(struct sh_mobile_i2c_data *pd)
da672773 265{
23a61291
SK		 266 unsigned long i2c_clk_khz;
267 u32 tHIGH, tLOW, tf;
a5616bd0 268
023c22fd 269 i2c_clk_khz = clk_get_rate(pd->clk) / 1000 / pd->clks_per_count;
23a61291 270
90224e64 271 if (pd->bus_speed == I2C_MAX_STANDARD_MODE_FREQ) {
23a61291
SK		 272 tLOW = 47; /* tLOW = 4.7 us */
273 tHIGH = 40; /* tHD;STA = tHIGH = 4.0 us */
274 tf = 3; /* tf = 0.3 us */
90224e64 275 } else if (pd->bus_speed == I2C_MAX_FAST_MODE_FREQ) {
23a61291
SK		 276 tLOW = 13; /* tLOW = 1.3 us */
277 tHIGH = 6; /* tHD;STA = tHIGH = 0.6 us */
278 tf = 3; /* tf = 0.3 us */
23a61291
SK		 279 } else {
280 dev_err(pd->dev, "unrecognized bus speed %lu Hz\n",
281 pd->bus_speed);
6ed7053c 282 return -EINVAL;
962b6032
MD		 283 }
284
ed4121e1 285 pd->iccl = sh_mobile_i2c_iccl(i2c_clk_khz, tLOW, tf);
7663ebef
WS		 286 pd->icch = sh_mobile_i2c_icch(i2c_clk_khz, tHIGH, tf);
287
c3449f73 288 return sh_mobile_i2c_check_timing(pd);
7b0e6292
SK		 289}
290
4ecfb9d3
WS		 291static int sh_mobile_i2c_v2_init(struct sh_mobile_i2c_data *pd)
292{
293 unsigned long clks_per_cycle;
294
295 /* L = 5, H = 4, L + H = 9 */
296 clks_per_cycle = clk_get_rate(pd->clk) / pd->bus_speed;
297 pd->iccl = DIV_ROUND_UP(clks_per_cycle * 5 / 9 - 1, pd->clks_per_count);
298 pd->icch = DIV_ROUND_UP(clks_per_cycle * 4 / 9 - 5, pd->clks_per_count);
299
300 return sh_mobile_i2c_check_timing(pd);
301}
302
d16f2bfe 303static unsigned char i2c_op(struct sh_mobile_i2c_data *pd, enum sh_mobile_i2c_op op)
da672773
MD		 304{
305 unsigned char ret = 0;
306 unsigned long flags;
307
d16f2bfe 308 dev_dbg(pd->dev, "op %d\n", op);
da672773
MD		 309
310 spin_lock_irqsave(&pd->lock, flags);
311
312 switch (op) {
4eb00c9f 313 case OP_START: /* issue start and trigger DTE interrupt */
a78f6a41 314 iic_wr(pd, ICCR, ICCR_ICE | ICCR_TRS | ICCR_BBSY);
da672773 315 break;
d16f2bfe 316 case OP_TX_FIRST: /* disable DTE interrupt and write client address */
12a55f2d 317 iic_wr(pd, ICIC, ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
d16f2bfe 318 iic_wr(pd, ICDR, i2c_8bit_addr_from_msg(pd->msg));
da672773 319 break;
4eb00c9f 320 case OP_TX: /* write data */
d16f2bfe 321 iic_wr(pd, ICDR, pd->msg->buf[pd->pos]);
da672773 322 break;
a4fde7e5 323 case OP_TX_STOP: /* issue a stop (or rep_start) */
a78f6a41
WS		 324 iic_wr(pd, ICCR, pd->send_stop ? ICCR_ICE | ICCR_TRS
325 : ICCR_ICE | ICCR_TRS | ICCR_BBSY);
4eb00c9f
MD		 326 break;
327 case OP_TX_TO_RX: /* select read mode */
a78f6a41 328 iic_wr(pd, ICCR, ICCR_ICE | ICCR_SCP);
da672773 329 break;
4eb00c9f 330 case OP_RX: /* just read data */
12a55f2d 331 ret = iic_rd(pd, ICDR);
da672773 332 break;
4eb00c9f 333 case OP_RX_STOP: /* enable DTE interrupt, issue stop */
a49cc1fe
UH		 334 if (!pd->atomic_xfer)
335 iic_wr(pd, ICIC,
336 ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
a78f6a41 337 iic_wr(pd, ICCR, ICCR_ICE | ICCR_RACK);
4eb00c9f
MD		 338 break;
339 case OP_RX_STOP_DATA: /* enable DTE interrupt, read data, issue stop */
a49cc1fe
UH		 340 if (!pd->atomic_xfer)
341 iic_wr(pd, ICIC,
342 ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
12a55f2d 343 ret = iic_rd(pd, ICDR);
a78f6a41 344 iic_wr(pd, ICCR, ICCR_ICE | ICCR_RACK);
da672773
MD		 345 break;
346 }
347
348 spin_unlock_irqrestore(&pd->lock, flags);
349
350 dev_dbg(pd->dev, "op %d, data out 0x%02x\n", op, ret);
351 return ret;
352}
353
4eb00c9f
MD		 354static int sh_mobile_i2c_isr_tx(struct sh_mobile_i2c_data *pd)
355{
2d09581b 356 if (pd->pos == pd->msg->len) {
d16f2bfe 357 i2c_op(pd, OP_TX_STOP);
4eb00c9f 358 return 1;
2d09581b 359 }
4eb00c9f 360
e659f36d 361 if (pd->pos == -1)
d16f2bfe
WS		 362 i2c_op(pd, OP_TX_FIRST);
363 else
364 i2c_op(pd, OP_TX);
4eb00c9f
MD		 365
366 pd->pos++;
367 return 0;
368}
369
370static int sh_mobile_i2c_isr_rx(struct sh_mobile_i2c_data *pd)
371{
4eb00c9f
MD		 372 int real_pos;
373
9d899ed4 374 /* switch from TX (address) to RX (data) adds two interrupts */
63c52460 375 real_pos = pd->pos - 2;
4eb00c9f 376
63c52460
WS		 377 if (pd->pos == -1) {
378 i2c_op(pd, OP_TX_FIRST);
379 } else if (pd->pos == 0) {
380 i2c_op(pd, OP_TX_TO_RX);
381 } else if (pd->pos == pd->msg->len) {
382 if (pd->stop_after_dma) {
383 /* Simulate PIO end condition after DMA transfer */
384 i2c_op(pd, OP_RX_STOP);
385 pd->pos++;
386 goto done;
2967f9ca 387 }
4eb00c9f 388
63c52460
WS		 389 if (real_pos < 0)
390 i2c_op(pd, OP_RX_STOP);
391 else
34765c19 392 pd->msg->buf[real_pos] = i2c_op(pd, OP_RX_STOP_DATA);
63c52460 393 } else if (real_pos >= 0) {
34765c19 394 pd->msg->buf[real_pos] = i2c_op(pd, OP_RX);
63c52460 395 }
4eb00c9f 396
63c52460 397 done:
4eb00c9f
MD		 398 pd->pos++;
399 return pd->pos == (pd->msg->len + 2);
400}
401
da672773
MD		 402static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id)
403{
530834b1 404 struct sh_mobile_i2c_data *pd = dev_id;
4eb00c9f 405 unsigned char sr;
2d09581b 406 int wakeup = 0;
da672773 407
12a55f2d 408 sr = iic_rd(pd, ICSR);
4eb00c9f 409 pd->sr |= sr; /* remember state */
da672773
MD		 410
411 dev_dbg(pd->dev, "i2c_isr 0x%02x 0x%02x %s %d %d!\n", sr, pd->sr,
4eb00c9f
MD		 412 (pd->msg->flags & I2C_M_RD) ? "read" : "write",
413 pd->pos, pd->msg->len);
da672773 414
2d09581b
WS		 415 /* Kick off TxDMA after preface was done */
416 if (pd->dma_direction == DMA_TO_DEVICE && pd->pos == 0)
417 iic_set_clr(pd, ICIC, ICIC_TDMAE, 0);
418 else if (sr & (ICSR_AL | ICSR_TACK))
4eb00c9f 419 /* don't interrupt transaction - continue to issue stop */
12a55f2d 420 iic_wr(pd, ICSR, sr & ~(ICSR_AL | ICSR_TACK));
2d09581b 421 else if (pd->msg->flags & I2C_M_RD)
4eb00c9f
MD		 422 wakeup = sh_mobile_i2c_isr_rx(pd);
423 else
424 wakeup = sh_mobile_i2c_isr_tx(pd);
da672773 425
2d09581b
WS		 426 /* Kick off RxDMA after preface was done */
427 if (pd->dma_direction == DMA_FROM_DEVICE && pd->pos == 1)
428 iic_set_clr(pd, ICIC, ICIC_RDMAE, 0);
429
4eb00c9f 430 if (sr & ICSR_WAIT) /* TODO: add delay here to support slow acks */
12a55f2d 431 iic_wr(pd, ICSR, sr & ~ICSR_WAIT);
da672773 432
da672773
MD		 433 if (wakeup) {
434 pd->sr |= SW_DONE;
a49cc1fe
UH		 435 if (!pd->atomic_xfer)
436 wake_up(&pd->wait);
da672773
MD		 437 }
438
29fb08c3
SK		 439 /* defeat write posting to avoid spurious WAIT interrupts */
440 iic_rd(pd, ICSR);
441
da672773
MD		 442 return IRQ_HANDLED;
443}
444
44df8a79 445static void sh_mobile_i2c_cleanup_dma(struct sh_mobile_i2c_data *pd, bool terminate)
8cfcae9f
WS		 446{
447 struct dma_chan *chan = pd->dma_direction == DMA_FROM_DEVICE
448 ? pd->dma_rx : pd->dma_tx;
449
44df8a79
WS		 450 /* only allowed from thread context! */
451 if (terminate)
452 dmaengine_terminate_sync(chan);
453
8cfcae9f
WS		 454 dma_unmap_single(chan->device->dev, sg_dma_address(&pd->sg),
455 pd->msg->len, pd->dma_direction);
456
457 pd->dma_direction = DMA_NONE;
458}
459
2d09581b
WS		 460static void sh_mobile_i2c_dma_callback(void *data)
461{
462 struct sh_mobile_i2c_data *pd = data;
463
44df8a79 464 sh_mobile_i2c_cleanup_dma(pd, false);
2d09581b 465 pd->pos = pd->msg->len;
32e22409 466 pd->stop_after_dma = true;
2d09581b
WS		 467
468 iic_set_clr(pd, ICIC, 0, ICIC_TDMAE | ICIC_RDMAE);
469}
470
55f5f986
WS		 471static struct dma_chan *sh_mobile_i2c_request_dma_chan(struct device *dev,
472 enum dma_transfer_direction dir, dma_addr_t port_addr)
473{
474 struct dma_chan *chan;
475 struct dma_slave_config cfg;
476 char *chan_name = dir == DMA_MEM_TO_DEV ? "tx" : "rx";
477 int ret;
478
efa42b5e 479 chan = dma_request_chan(dev, chan_name);
55f5f986 480 if (IS_ERR(chan)) {
75fdc518
ER		 481 dev_dbg(dev, "request_channel failed for %s (%ld)\n", chan_name,
482 PTR_ERR(chan));
55f5f986
WS		 483 return chan;
484 }
485
486 memset(&cfg, 0, sizeof(cfg));
487 cfg.direction = dir;
488 if (dir == DMA_MEM_TO_DEV) {
489 cfg.dst_addr = port_addr;
490 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
491 } else {
492 cfg.src_addr = port_addr;
493 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
494 }
495
496 ret = dmaengine_slave_config(chan, &cfg);
497 if (ret) {
498 dev_dbg(dev, "slave_config failed for %s (%d)\n", chan_name, ret);
499 dma_release_channel(chan);
500 return ERR_PTR(ret);
501 }
502
503 dev_dbg(dev, "got DMA channel for %s\n", chan_name);
504 return chan;
505}
506
2d09581b
WS		 507static void sh_mobile_i2c_xfer_dma(struct sh_mobile_i2c_data *pd)
508{
509 bool read = pd->msg->flags & I2C_M_RD;
510 enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
511 struct dma_chan *chan = read ? pd->dma_rx : pd->dma_tx;
512 struct dma_async_tx_descriptor *txdesc;
513 dma_addr_t dma_addr;
514 dma_cookie_t cookie;
515
55f5f986
WS		 516 if (PTR_ERR(chan) == -EPROBE_DEFER) {
517 if (read)
518 chan = pd->dma_rx = sh_mobile_i2c_request_dma_chan(pd->dev, DMA_DEV_TO_MEM,
519 pd->res->start + ICDR);
520 else
521 chan = pd->dma_tx = sh_mobile_i2c_request_dma_chan(pd->dev, DMA_MEM_TO_DEV,
522 pd->res->start + ICDR);
523 }
524
e844a799 525 if (IS_ERR(chan))
2d09581b
WS		 526 return;
527
fe23aa9a 528 dma_addr = dma_map_single(chan->device->dev, pd->dma_buf, pd->msg->len, dir);
488d69ea 529 if (dma_mapping_error(chan->device->dev, dma_addr)) {
2d09581b
WS		 530 dev_dbg(pd->dev, "dma map failed, using PIO\n");
531 return;
532 }
533
534 sg_dma_len(&pd->sg) = pd->msg->len;
535 sg_dma_address(&pd->sg) = dma_addr;
536
537 pd->dma_direction = dir;
538
539 txdesc = dmaengine_prep_slave_sg(chan, &pd->sg, 1,
540 read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV,
541 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
542 if (!txdesc) {
543 dev_dbg(pd->dev, "dma prep slave sg failed, using PIO\n");
44df8a79 544 sh_mobile_i2c_cleanup_dma(pd, false);
2d09581b
WS		 545 return;
546 }
547
548 txdesc->callback = sh_mobile_i2c_dma_callback;
549 txdesc->callback_param = pd;
550
551 cookie = dmaengine_submit(txdesc);
552 if (dma_submit_error(cookie)) {
553 dev_dbg(pd->dev, "submitting dma failed, using PIO\n");
44df8a79 554 sh_mobile_i2c_cleanup_dma(pd, false);
2d09581b
WS		 555 return;
556 }
557
558 dma_async_issue_pending(chan);
559}
560
531db501
WS		 561static void start_ch(struct sh_mobile_i2c_data *pd, struct i2c_msg *usr_msg,
562 bool do_init)
da672773 563{
e7890297
GL		 564 if (do_init) {
565 /* Initialize channel registers */
4ed152c4 566 iic_wr(pd, ICCR, ICCR_SCP);
da672773 567
e7890297 568 /* Enable channel and configure rx ack */
4ed152c4 569 iic_wr(pd, ICCR, ICCR_ICE | ICCR_SCP);
da672773 570
e7890297
GL		 571 /* Set the clock */
572 iic_wr(pd, ICCL, pd->iccl & 0xff);
573 iic_wr(pd, ICCH, pd->icch & 0xff);
574 }
da672773
MD		 575
576 pd->msg = usr_msg;
577 pd->pos = -1;
578 pd->sr = 0;
579
a49cc1fe
UH		 580 if (pd->atomic_xfer)
581 return;
582
fe23aa9a
WS		 583 pd->dma_buf = i2c_get_dma_safe_msg_buf(pd->msg, 8);
584 if (pd->dma_buf)
2d09581b
WS		 585 sh_mobile_i2c_xfer_dma(pd);
586
4eb00c9f 587 /* Enable all interrupts to begin with */
12a55f2d 588 iic_wr(pd, ICIC, ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
da672773
MD		 589}
590
e7890297
GL		 591static int poll_dte(struct sh_mobile_i2c_data *pd)
592{
593 int i;
594
595 for (i = 1000; i; i--) {
596 u_int8_t val = iic_rd(pd, ICSR);
597
598 if (val & ICSR_DTE)
599 break;
600
601 if (val & ICSR_TACK)
5a72b25e 602 return -ENXIO;
e7890297
GL		 603
604 udelay(10);
605 }
606
5a72b25e 607 return i ? 0 : -ETIMEDOUT;
e7890297
GL		 608}
609
4b382318
GL		 610static int poll_busy(struct sh_mobile_i2c_data *pd)
611{
612 int i;
613
614 for (i = 1000; i; i--) {
615 u_int8_t val = iic_rd(pd, ICSR);
616
617 dev_dbg(pd->dev, "val 0x%02x pd->sr 0x%02x\n", val, pd->sr);
618
619 /* the interrupt handler may wake us up before the
620 * transfer is finished, so poll the hardware
621 * until we're done.
622 */
623 if (!(val & ICSR_BUSY)) {
624 /* handle missing acknowledge and arbitration lost */
5a72b25e
WS		 625 val |= pd->sr;
626 if (val & ICSR_TACK)
627 return -ENXIO;
628 if (val & ICSR_AL)
629 return -EAGAIN;
4b382318
GL		 630 break;
631 }
632
633 udelay(10);
634 }
635
5a72b25e 636 return i ? 0 : -ETIMEDOUT;
4b382318
GL		 637}
638
a49cc1fe
UH		 639static int sh_mobile_xfer(struct sh_mobile_i2c_data *pd,
640 struct i2c_msg *msgs, int num)
da672773 641{
da672773
MD		 642 struct i2c_msg *msg;
643 int err = 0;
365322fb 644 int i;
a49cc1fe 645 long time_left;
da672773 646
91a5e63e
WS		 647 /* Wake up device and enable clock */
648 pm_runtime_get_sync(pd->dev);
da672773
MD		 649
650 /* Process all messages */
651 for (i = 0; i < num; i++) {
e7890297 652 bool do_start = pd->send_stop || !i;
da672773 653 msg = &msgs[i];
e7890297 654 pd->send_stop = i == num - 1 || msg->flags & I2C_M_STOP;
32e22409 655 pd->stop_after_dma = false;
da672773 656
531db501 657 start_ch(pd, msg, do_start);
da672773 658
e7890297 659 if (do_start)
d16f2bfe 660 i2c_op(pd, OP_START);
da672773 661
a49cc1fe
UH		 662 if (pd->atomic_xfer) {
663 unsigned long j = jiffies + pd->adap.timeout;
664
665 time_left = time_before_eq(jiffies, j);
666 while (time_left &&
667 !(pd->sr & (ICSR_TACK | SW_DONE))) {
668 unsigned char sr = iic_rd(pd, ICSR);
669
670 if (sr & (ICSR_AL | ICSR_TACK |
671 ICSR_WAIT | ICSR_DTE)) {
672 sh_mobile_i2c_isr(0, pd);
673 udelay(150);
674 } else {
675 cpu_relax();
676 }
677 time_left = time_before_eq(jiffies, j);
678 }
679 } else {
680 /* The interrupt handler takes care of the rest... */
681 time_left = wait_event_timeout(pd->wait,
682 pd->sr & (ICSR_TACK | SW_DONE),
683 pd->adap.timeout);
684
685 /* 'stop_after_dma' tells if DMA xfer was complete */
686 i2c_put_dma_safe_msg_buf(pd->dma_buf, pd->msg,
687 pd->stop_after_dma);
688 }
cebc07d8 689
a49cc1fe 690 if (!time_left) {
2d09581b 691 if (pd->dma_direction != DMA_NONE)
44df8a79 692 sh_mobile_i2c_cleanup_dma(pd, true);
2d09581b 693
5687265b
GL		 694 err = -ETIMEDOUT;
695 break;
696 }
da672773 697
e7890297
GL		 698 if (pd->send_stop)
699 err = poll_busy(pd);
700 else
701 err = poll_dte(pd);
4b382318 702 if (err < 0)
da672773 703 break;
da672773
MD		 704 }
705
91a5e63e 706 /* Disable channel */
4ed152c4 707 iic_wr(pd, ICCR, ICCR_SCP);
91a5e63e
WS		 708
709 /* Disable clock and mark device as idle */
91a5e63e 710 pm_runtime_put_sync(pd->dev);
da672773 711
a4d16493 712 return err ?: num;
da672773
MD		 713}
714
a49cc1fe
UH		 715static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter,
716 struct i2c_msg *msgs,
717 int num)
718{
719 struct sh_mobile_i2c_data *pd = i2c_get_adapdata(adapter);
720
721 pd->atomic_xfer = false;
722 return sh_mobile_xfer(pd, msgs, num);
723}
724
725static int sh_mobile_i2c_xfer_atomic(struct i2c_adapter *adapter,
726 struct i2c_msg *msgs,
727 int num)
728{
729 struct sh_mobile_i2c_data *pd = i2c_get_adapdata(adapter);
730
731 pd->atomic_xfer = true;
732 return sh_mobile_xfer(pd, msgs, num);
733}
734
da672773
MD		 735static u32 sh_mobile_i2c_func(struct i2c_adapter *adapter)
736{
e7890297 737 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
da672773
MD		 738}
739
92d9d0df 740static const struct i2c_algorithm sh_mobile_i2c_algorithm = {
a49cc1fe
UH		 741 .functionality = sh_mobile_i2c_func,
742 .master_xfer = sh_mobile_i2c_xfer,
743 .master_xfer_atomic = sh_mobile_i2c_xfer_atomic,
da672773
MD		 744};
745
7957c2e2
WS		 746static const struct i2c_adapter_quirks sh_mobile_i2c_quirks = {
747 .flags = I2C_AQ_NO_ZERO_LEN_READ,
748};
749
3ded3743 750/*
9d899ed4 751 * r8a7740 has an errata regarding I2C I/O pad reset needing this workaround.
3ded3743 752 */
12742b6a 753static int sh_mobile_i2c_r8a7740_workaround(struct sh_mobile_i2c_data *pd)
3ded3743
WS		 754{
755 iic_set_clr(pd, ICCR, ICCR_ICE, 0);
756 iic_rd(pd, ICCR); /* dummy read */
757
758 iic_set_clr(pd, ICSTART, ICSTART_ICSTART, 0);
759 iic_rd(pd, ICSTART); /* dummy read */
760
761 udelay(10);
762
763 iic_wr(pd, ICCR, ICCR_SCP);
764 iic_wr(pd, ICSTART, 0);
765
766 udelay(10);
767
768 iic_wr(pd, ICCR, ICCR_TRS);
769 udelay(10);
770 iic_wr(pd, ICCR, 0);
771 udelay(10);
772 iic_wr(pd, ICCR, ICCR_TRS);
773 udelay(10);
12742b6a 774
7a7fd335 775 return sh_mobile_i2c_v2_init(pd);
3ded3743
WS		 776}
777
67240dfc
WS		 778static const struct sh_mobile_dt_config default_dt_config = {
779 .clks_per_count = 1,
b3750b62 780 .setup = sh_mobile_i2c_init,
67240dfc
WS		 781};
782
78df445e 783static const struct sh_mobile_dt_config fast_clock_dt_config = {
4ecfb9d3
WS		 784 .clks_per_count = 2,
785 .setup = sh_mobile_i2c_v2_init,
786};
787
3ded3743
WS		 788static const struct sh_mobile_dt_config r8a7740_dt_config = {
789 .clks_per_count = 1,
790 .setup = sh_mobile_i2c_r8a7740_workaround,
791};
792
67240dfc 793static const struct of_device_id sh_mobile_i2c_dt_ids[] = {
78df445e 794 { .compatible = "renesas,iic-r8a73a4", .data = &fast_clock_dt_config },
3ded3743 795 { .compatible = "renesas,iic-r8a7740", .data = &r8a7740_dt_config },
7a7fd335
GU		 796 { .compatible = "renesas,iic-r8a774c0", .data = &fast_clock_dt_config },
797 { .compatible = "renesas,iic-r8a7790", .data = &fast_clock_dt_config },
798 { .compatible = "renesas,iic-r8a7791", .data = &fast_clock_dt_config },
799 { .compatible = "renesas,iic-r8a7792", .data = &fast_clock_dt_config },
800 { .compatible = "renesas,iic-r8a7793", .data = &fast_clock_dt_config },
801 { .compatible = "renesas,iic-r8a7794", .data = &fast_clock_dt_config },
802 { .compatible = "renesas,iic-r8a7795", .data = &fast_clock_dt_config },
803 { .compatible = "renesas,iic-r8a77990", .data = &fast_clock_dt_config },
78df445e 804 { .compatible = "renesas,iic-sh73a0", .data = &fast_clock_dt_config },
7a7fd335
GU		 805 { .compatible = "renesas,rcar-gen2-iic", .data = &fast_clock_dt_config },
806 { .compatible = "renesas,rcar-gen3-iic", .data = &fast_clock_dt_config },
b880ccaf 807 { .compatible = "renesas,rmobile-iic", .data = &default_dt_config },
67240dfc
WS		 808 {},
809};
810MODULE_DEVICE_TABLE(of, sh_mobile_i2c_dt_ids);
811
2d09581b
WS		 812static void sh_mobile_i2c_release_dma(struct sh_mobile_i2c_data *pd)
813{
e844a799 814 if (!IS_ERR(pd->dma_tx)) {
2d09581b 815 dma_release_channel(pd->dma_tx);
e844a799 816 pd->dma_tx = ERR_PTR(-EPROBE_DEFER);
2d09581b
WS		 817 }
818
e844a799 819 if (!IS_ERR(pd->dma_rx)) {
2d09581b 820 dma_release_channel(pd->dma_rx);
e844a799 821 pd->dma_rx = ERR_PTR(-EPROBE_DEFER);
2d09581b
WS		 822 }
823}
824
530834b1 825static int sh_mobile_i2c_hook_irqs(struct platform_device *dev, struct sh_mobile_i2c_data *pd)
da672773 826{
aab799e4 827 struct device_node *np = dev_of_node(&dev->dev);
7fe8a999 828 int k = 0, ret;
da672773 829
aab799e4
LP		 830 if (np) {
831 int irq;
832
833 while ((irq = platform_get_irq_optional(dev, k)) != -ENXIO) {
834 if (irq < 0)
835 return irq;
836 ret = devm_request_irq(&dev->dev, irq, sh_mobile_i2c_isr,
837 0, dev_name(&dev->dev), pd);
7fe8a999 838 if (ret) {
aab799e4 839 dev_err(&dev->dev, "cannot request IRQ %d\n", irq);
7fe8a999 840 return ret;
82b20d8b 841 }
aab799e4 842 k++;
bf3c39f5 843 }
aab799e4
LP		 844 } else {
845 struct resource *res;
846 resource_size_t n;
847
848 while ((res = platform_get_resource(dev, IORESOURCE_IRQ, k))) {
849 for (n = res->start; n <= res->end; n++) {
850 ret = devm_request_irq(&dev->dev, n, sh_mobile_i2c_isr,
851 0, dev_name(&dev->dev), pd);
852 if (ret) {
853 dev_err(&dev->dev, "cannot request IRQ %pa\n", &n);
854 return ret;
855 }
856 }
857 k++;
da672773 858 }
da672773
MD		 859 }
860
7fe8a999 861 return k > 0 ? 0 : -ENOENT;
da672773
MD		 862}
863
864static int sh_mobile_i2c_probe(struct platform_device *dev)
865{
866 struct sh_mobile_i2c_data *pd;
867 struct i2c_adapter *adap;
ad59c5ea 868 const struct sh_mobile_dt_config *config;
da672773 869 int ret;
88c289ec 870 u32 bus_speed;
da672773 871
4fd31c2e
WS		 872 pd = devm_kzalloc(&dev->dev, sizeof(struct sh_mobile_i2c_data), GFP_KERNEL);
873 if (!pd)
da672773 874 return -ENOMEM;
da672773 875
4fd31c2e 876 pd->clk = devm_clk_get(&dev->dev, NULL);
da672773 877 if (IS_ERR(pd->clk)) {
1082d5d2 878 dev_err(&dev->dev, "cannot get clock\n");
4fd31c2e 879 return PTR_ERR(pd->clk);
da672773
MD		 880 }
881
530834b1 882 ret = sh_mobile_i2c_hook_irqs(dev, pd);
7fe8a999 883 if (ret)
4fd31c2e 884 return ret;
da672773
MD		 885
886 pd->dev = &dev->dev;
887 platform_set_drvdata(dev, pd);
888
3735e431 889 pd->reg = devm_platform_get_and_ioremap_resource(dev, 0, &pd->res);
7fe8a999
WS		 890 if (IS_ERR(pd->reg))
891 return PTR_ERR(pd->reg);
da672773 892
88c289ec 893 ret = of_property_read_u32(dev->dev.of_node, "clock-frequency", &bus_speed);
90224e64 894 pd->bus_speed = (ret || !bus_speed) ? I2C_MAX_STANDARD_MODE_FREQ : bus_speed;
ebd5ac16 895 pd->clks_per_count = 1;
67240dfc 896
9e422131 897 /* Newer variants come with two new bits in ICIC */
3735e431 898 if (resource_size(pd->res) > 0x17)
9e422131
WS		 899 pd->flags |= IIC_FLAG_HAS_ICIC67;
900
023c22fd
WS		 901 pm_runtime_enable(&dev->dev);
902 pm_runtime_get_sync(&dev->dev);
903
ad59c5ea
GU		 904 config = of_device_get_match_data(&dev->dev);
905 if (config) {
90b84c05 906 pd->clks_per_count = config->clks_per_count;
b3750b62
WS		 907 ret = config->setup(pd);
908 } else {
909 ret = sh_mobile_i2c_init(pd);
67240dfc 910 }
023c22fd
WS		 911
912 pm_runtime_put_sync(&dev->dev);
6ed7053c
WS		 913 if (ret)
914 return ret;
7b0e6292 915
2d09581b
WS		 916 /* Init DMA */
917 sg_init_table(&pd->sg, 1);
918 pd->dma_direction = DMA_NONE;
55f5f986 919 pd->dma_rx = pd->dma_tx = ERR_PTR(-EPROBE_DEFER);
2d09581b 920
da672773
MD		 921 /* setup the private data */
922 adap = &pd->adap;
923 i2c_set_adapdata(adap, pd);
924
925 adap->owner = THIS_MODULE;
926 adap->algo = &sh_mobile_i2c_algorithm;
7957c2e2 927 adap->quirks = &sh_mobile_i2c_quirks;
da672773
MD		 928 adap->dev.parent = &dev->dev;
929 adap->retries = 5;
930 adap->nr = dev->id;
ad337074 931 adap->dev.of_node = dev->dev.of_node;
da672773 932
ea1558ce 933 strscpy(adap->name, dev->name, sizeof(adap->name));
da672773 934
a5616bd0
MD		 935 spin_lock_init(&pd->lock);
936 init_waitqueue_head(&pd->wait);
da672773
MD		 937
938 ret = i2c_add_numbered_adapter(adap);
939 if (ret < 0) {
2d09581b 940 sh_mobile_i2c_release_dma(pd);
7fe8a999 941 return ret;
da672773
MD		 942 }
943
55f5f986 944 dev_info(&dev->dev, "I2C adapter %d, bus speed %lu Hz\n", adap->nr, pd->bus_speed);
ad337074 945
da672773 946 return 0;
da672773
MD		 947}
948
e190a0c3 949static void sh_mobile_i2c_remove(struct platform_device *dev)
da672773
MD		 950{
951 struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev);
952
953 i2c_del_adapter(&pd->adap);
2d09581b 954 sh_mobile_i2c_release_dma(pd);
f1a3b994 955 pm_runtime_disable(&dev->dev);
da672773
MD		 956}
957
e8a61e5a
GU		 958static int sh_mobile_i2c_suspend(struct device *dev)
959{
960 struct sh_mobile_i2c_data *pd = dev_get_drvdata(dev);
961
962 i2c_mark_adapter_suspended(&pd->adap);
963 return 0;
964}
965
966static int sh_mobile_i2c_resume(struct device *dev)
967{
968 struct sh_mobile_i2c_data *pd = dev_get_drvdata(dev);
969
970 i2c_mark_adapter_resumed(&pd->adap);
971 return 0;
972}
973
974static const struct dev_pm_ops sh_mobile_i2c_pm_ops = {
426b6742
PC		 975 NOIRQ_SYSTEM_SLEEP_PM_OPS(sh_mobile_i2c_suspend,
976 sh_mobile_i2c_resume)
e8a61e5a
GU		 977};
978
da672773
MD		 979static struct platform_driver sh_mobile_i2c_driver = {
980 .driver = {
981 .name = "i2c-sh_mobile",
ad337074 982 .of_match_table = sh_mobile_i2c_dt_ids,
426b6742 983 .pm = pm_sleep_ptr(&sh_mobile_i2c_pm_ops),
da672773
MD		 984 },
985 .probe = sh_mobile_i2c_probe,
e190a0c3 986 .remove_new = sh_mobile_i2c_remove,
da672773
MD		 987};
988
989static int __init sh_mobile_i2c_adap_init(void)
990{
991 return platform_driver_register(&sh_mobile_i2c_driver);
992}
2d09581b 993subsys_initcall(sh_mobile_i2c_adap_init);
da672773
MD		 994
995static void __exit sh_mobile_i2c_adap_exit(void)
996{
997 platform_driver_unregister(&sh_mobile_i2c_driver);
998}
da672773
MD		 999module_exit(sh_mobile_i2c_adap_exit);
1000
1001MODULE_DESCRIPTION("SuperH Mobile I2C Bus Controller driver");
f80531c8
JN		 1002MODULE_AUTHOR("Magnus Damm");
1003MODULE_AUTHOR("Wolfram Sang");
da672773 1004MODULE_LICENSE("GPL v2");
7ef0c12a 1005MODULE_ALIAS("platform:i2c-sh_mobile");
Linux 6.x block layer and io_uring tree(s)