Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* linux/drivers/i2c/busses/i2c-s3c2410.c |
2 | * | |
3 | * Copyright (C) 2004,2005 Simtec Electronics | |
4 | * Ben Dooks <ben@simtec.co.uk> | |
5 | * | |
6 | * S3C2410 I2C Controller | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | #include <linux/kernel.h> | |
24 | #include <linux/module.h> | |
25 | ||
26 | #include <linux/i2c.h> | |
27 | #include <linux/i2c-id.h> | |
28 | #include <linux/init.h> | |
29 | #include <linux/time.h> | |
30 | #include <linux/interrupt.h> | |
1da177e4 LT |
31 | #include <linux/delay.h> |
32 | #include <linux/errno.h> | |
33 | #include <linux/err.h> | |
d052d1be | 34 | #include <linux/platform_device.h> |
f8ce2547 | 35 | #include <linux/clk.h> |
61c7cff8 | 36 | #include <linux/cpufreq.h> |
1da177e4 | 37 | |
a09e64fb | 38 | #include <mach/hardware.h> |
1da177e4 LT |
39 | #include <asm/irq.h> |
40 | #include <asm/io.h> | |
41 | ||
a09e64fb | 42 | #include <mach/regs-gpio.h> |
9498cb79 BD |
43 | #include <plat/regs-iic.h> |
44 | #include <plat/iic.h> | |
1da177e4 LT |
45 | |
46 | /* i2c controller state */ | |
47 | ||
48 | enum s3c24xx_i2c_state { | |
49 | STATE_IDLE, | |
50 | STATE_START, | |
51 | STATE_READ, | |
52 | STATE_WRITE, | |
53 | STATE_STOP | |
54 | }; | |
55 | ||
56 | struct s3c24xx_i2c { | |
57 | spinlock_t lock; | |
58 | wait_queue_head_t wait; | |
59 | ||
60 | struct i2c_msg *msg; | |
61 | unsigned int msg_num; | |
62 | unsigned int msg_idx; | |
63 | unsigned int msg_ptr; | |
64 | ||
e00a8cdf BD |
65 | unsigned int tx_setup; |
66 | ||
1da177e4 | 67 | enum s3c24xx_i2c_state state; |
61c7cff8 | 68 | unsigned long clkrate; |
1da177e4 LT |
69 | |
70 | void __iomem *regs; | |
71 | struct clk *clk; | |
72 | struct device *dev; | |
73 | struct resource *irq; | |
74 | struct resource *ioarea; | |
75 | struct i2c_adapter adap; | |
61c7cff8 BD |
76 | |
77 | #ifdef CONFIG_CPU_FREQ | |
78 | struct notifier_block freq_transition; | |
79 | #endif | |
1da177e4 LT |
80 | }; |
81 | ||
82 | /* default platform data to use if not supplied in the platform_device | |
83 | */ | |
84 | ||
85 | static struct s3c2410_platform_i2c s3c24xx_i2c_default_platform = { | |
86 | .flags = 0, | |
87 | .slave_addr = 0x10, | |
88 | .bus_freq = 100*1000, | |
89 | .max_freq = 400*1000, | |
90 | .sda_delay = S3C2410_IICLC_SDA_DELAY5 | S3C2410_IICLC_FILTER_ON, | |
91 | }; | |
92 | ||
93 | /* s3c24xx_i2c_is2440() | |
94 | * | |
95 | * return true is this is an s3c2440 | |
96 | */ | |
97 | ||
98 | static inline int s3c24xx_i2c_is2440(struct s3c24xx_i2c *i2c) | |
99 | { | |
100 | struct platform_device *pdev = to_platform_device(i2c->dev); | |
101 | ||
102 | return !strcmp(pdev->name, "s3c2440-i2c"); | |
103 | } | |
104 | ||
105 | ||
106 | /* s3c24xx_i2c_get_platformdata | |
107 | * | |
108 | * get the platform data associated with the given device, or return | |
109 | * the default if there is none | |
110 | */ | |
111 | ||
112 | static inline struct s3c2410_platform_i2c *s3c24xx_i2c_get_platformdata(struct device *dev) | |
113 | { | |
114 | if (dev->platform_data != NULL) | |
115 | return (struct s3c2410_platform_i2c *)dev->platform_data; | |
116 | ||
117 | return &s3c24xx_i2c_default_platform; | |
118 | } | |
119 | ||
120 | /* s3c24xx_i2c_master_complete | |
121 | * | |
122 | * complete the message and wake up the caller, using the given return code, | |
123 | * or zero to mean ok. | |
124 | */ | |
125 | ||
126 | static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret) | |
127 | { | |
128 | dev_dbg(i2c->dev, "master_complete %d\n", ret); | |
129 | ||
130 | i2c->msg_ptr = 0; | |
131 | i2c->msg = NULL; | |
132 | i2c->msg_idx ++; | |
133 | i2c->msg_num = 0; | |
134 | if (ret) | |
135 | i2c->msg_idx = ret; | |
136 | ||
137 | wake_up(&i2c->wait); | |
138 | } | |
139 | ||
140 | static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c) | |
141 | { | |
142 | unsigned long tmp; | |
143 | ||
144 | tmp = readl(i2c->regs + S3C2410_IICCON); | |
145 | writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON); | |
146 | ||
147 | } | |
148 | ||
149 | static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c) | |
150 | { | |
151 | unsigned long tmp; | |
152 | ||
153 | tmp = readl(i2c->regs + S3C2410_IICCON); | |
154 | writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON); | |
155 | ||
156 | } | |
157 | ||
158 | /* irq enable/disable functions */ | |
159 | ||
160 | static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c) | |
161 | { | |
162 | unsigned long tmp; | |
163 | ||
164 | tmp = readl(i2c->regs + S3C2410_IICCON); | |
165 | writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON); | |
166 | } | |
167 | ||
168 | static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c) | |
169 | { | |
170 | unsigned long tmp; | |
171 | ||
172 | tmp = readl(i2c->regs + S3C2410_IICCON); | |
173 | writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON); | |
174 | } | |
175 | ||
176 | ||
177 | /* s3c24xx_i2c_message_start | |
178 | * | |
179 | * put the start of a message onto the bus | |
180 | */ | |
181 | ||
182 | static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c, | |
183 | struct i2c_msg *msg) | |
184 | { | |
185 | unsigned int addr = (msg->addr & 0x7f) << 1; | |
186 | unsigned long stat; | |
187 | unsigned long iiccon; | |
188 | ||
189 | stat = 0; | |
190 | stat |= S3C2410_IICSTAT_TXRXEN; | |
191 | ||
192 | if (msg->flags & I2C_M_RD) { | |
193 | stat |= S3C2410_IICSTAT_MASTER_RX; | |
194 | addr |= 1; | |
195 | } else | |
196 | stat |= S3C2410_IICSTAT_MASTER_TX; | |
197 | ||
198 | if (msg->flags & I2C_M_REV_DIR_ADDR) | |
199 | addr ^= 1; | |
200 | ||
201 | // todo - check for wether ack wanted or not | |
202 | s3c24xx_i2c_enable_ack(i2c); | |
203 | ||
204 | iiccon = readl(i2c->regs + S3C2410_IICCON); | |
205 | writel(stat, i2c->regs + S3C2410_IICSTAT); | |
206 | ||
207 | dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr); | |
208 | writeb(addr, i2c->regs + S3C2410_IICDS); | |
209 | ||
e00a8cdf BD |
210 | /* delay here to ensure the data byte has gotten onto the bus |
211 | * before the transaction is started */ | |
212 | ||
213 | ndelay(i2c->tx_setup); | |
214 | ||
1da177e4 LT |
215 | dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon); |
216 | writel(iiccon, i2c->regs + S3C2410_IICCON); | |
217 | ||
218 | stat |= S3C2410_IICSTAT_START; | |
219 | writel(stat, i2c->regs + S3C2410_IICSTAT); | |
220 | } | |
221 | ||
222 | static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret) | |
223 | { | |
224 | unsigned long iicstat = readl(i2c->regs + S3C2410_IICSTAT); | |
225 | ||
226 | dev_dbg(i2c->dev, "STOP\n"); | |
227 | ||
228 | /* stop the transfer */ | |
229 | iicstat &= ~ S3C2410_IICSTAT_START; | |
230 | writel(iicstat, i2c->regs + S3C2410_IICSTAT); | |
231 | ||
232 | i2c->state = STATE_STOP; | |
233 | ||
234 | s3c24xx_i2c_master_complete(i2c, ret); | |
235 | s3c24xx_i2c_disable_irq(i2c); | |
236 | } | |
237 | ||
238 | /* helper functions to determine the current state in the set of | |
239 | * messages we are sending */ | |
240 | ||
241 | /* is_lastmsg() | |
242 | * | |
243 | * returns TRUE if the current message is the last in the set | |
244 | */ | |
245 | ||
246 | static inline int is_lastmsg(struct s3c24xx_i2c *i2c) | |
247 | { | |
248 | return i2c->msg_idx >= (i2c->msg_num - 1); | |
249 | } | |
250 | ||
251 | /* is_msglast | |
252 | * | |
253 | * returns TRUE if we this is the last byte in the current message | |
254 | */ | |
255 | ||
256 | static inline int is_msglast(struct s3c24xx_i2c *i2c) | |
257 | { | |
258 | return i2c->msg_ptr == i2c->msg->len-1; | |
259 | } | |
260 | ||
261 | /* is_msgend | |
262 | * | |
263 | * returns TRUE if we reached the end of the current message | |
264 | */ | |
265 | ||
266 | static inline int is_msgend(struct s3c24xx_i2c *i2c) | |
267 | { | |
268 | return i2c->msg_ptr >= i2c->msg->len; | |
269 | } | |
270 | ||
271 | /* i2s_s3c_irq_nextbyte | |
272 | * | |
273 | * process an interrupt and work out what to do | |
274 | */ | |
275 | ||
276 | static int i2s_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat) | |
277 | { | |
278 | unsigned long tmp; | |
279 | unsigned char byte; | |
280 | int ret = 0; | |
281 | ||
282 | switch (i2c->state) { | |
283 | ||
284 | case STATE_IDLE: | |
08882d20 | 285 | dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __func__); |
1da177e4 LT |
286 | goto out; |
287 | break; | |
288 | ||
289 | case STATE_STOP: | |
08882d20 | 290 | dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__); |
1da177e4 LT |
291 | s3c24xx_i2c_disable_irq(i2c); |
292 | goto out_ack; | |
293 | ||
294 | case STATE_START: | |
295 | /* last thing we did was send a start condition on the | |
296 | * bus, or started a new i2c message | |
297 | */ | |
298 | ||
63f5c289 | 299 | if (iicstat & S3C2410_IICSTAT_LASTBIT && |
1da177e4 LT |
300 | !(i2c->msg->flags & I2C_M_IGNORE_NAK)) { |
301 | /* ack was not received... */ | |
302 | ||
303 | dev_dbg(i2c->dev, "ack was not received\n"); | |
63f5c289 | 304 | s3c24xx_i2c_stop(i2c, -ENXIO); |
1da177e4 LT |
305 | goto out_ack; |
306 | } | |
307 | ||
308 | if (i2c->msg->flags & I2C_M_RD) | |
309 | i2c->state = STATE_READ; | |
310 | else | |
311 | i2c->state = STATE_WRITE; | |
312 | ||
313 | /* terminate the transfer if there is nothing to do | |
63f5c289 | 314 | * as this is used by the i2c probe to find devices. */ |
1da177e4 LT |
315 | |
316 | if (is_lastmsg(i2c) && i2c->msg->len == 0) { | |
317 | s3c24xx_i2c_stop(i2c, 0); | |
318 | goto out_ack; | |
319 | } | |
320 | ||
321 | if (i2c->state == STATE_READ) | |
322 | goto prepare_read; | |
323 | ||
324 | /* fall through to the write state, as we will need to | |
325 | * send a byte as well */ | |
326 | ||
327 | case STATE_WRITE: | |
328 | /* we are writing data to the device... check for the | |
329 | * end of the message, and if so, work out what to do | |
330 | */ | |
331 | ||
2709781b BD |
332 | if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) { |
333 | if (iicstat & S3C2410_IICSTAT_LASTBIT) { | |
334 | dev_dbg(i2c->dev, "WRITE: No Ack\n"); | |
335 | ||
336 | s3c24xx_i2c_stop(i2c, -ECONNREFUSED); | |
337 | goto out_ack; | |
338 | } | |
339 | } | |
340 | ||
1da177e4 | 341 | retry_write: |
2709781b | 342 | |
1da177e4 LT |
343 | if (!is_msgend(i2c)) { |
344 | byte = i2c->msg->buf[i2c->msg_ptr++]; | |
345 | writeb(byte, i2c->regs + S3C2410_IICDS); | |
e00a8cdf BD |
346 | |
347 | /* delay after writing the byte to allow the | |
348 | * data setup time on the bus, as writing the | |
349 | * data to the register causes the first bit | |
350 | * to appear on SDA, and SCL will change as | |
351 | * soon as the interrupt is acknowledged */ | |
352 | ||
353 | ndelay(i2c->tx_setup); | |
354 | ||
1da177e4 LT |
355 | } else if (!is_lastmsg(i2c)) { |
356 | /* we need to go to the next i2c message */ | |
357 | ||
358 | dev_dbg(i2c->dev, "WRITE: Next Message\n"); | |
359 | ||
360 | i2c->msg_ptr = 0; | |
361 | i2c->msg_idx ++; | |
362 | i2c->msg++; | |
363 | ||
364 | /* check to see if we need to do another message */ | |
365 | if (i2c->msg->flags & I2C_M_NOSTART) { | |
366 | ||
367 | if (i2c->msg->flags & I2C_M_RD) { | |
368 | /* cannot do this, the controller | |
369 | * forces us to send a new START | |
370 | * when we change direction */ | |
371 | ||
372 | s3c24xx_i2c_stop(i2c, -EINVAL); | |
373 | } | |
374 | ||
375 | goto retry_write; | |
376 | } else { | |
377 | ||
378 | /* send the new start */ | |
379 | s3c24xx_i2c_message_start(i2c, i2c->msg); | |
380 | i2c->state = STATE_START; | |
381 | } | |
382 | ||
383 | } else { | |
384 | /* send stop */ | |
385 | ||
386 | s3c24xx_i2c_stop(i2c, 0); | |
387 | } | |
388 | break; | |
389 | ||
390 | case STATE_READ: | |
391 | /* we have a byte of data in the data register, do | |
392 | * something with it, and then work out wether we are | |
393 | * going to do any more read/write | |
394 | */ | |
395 | ||
1da177e4 LT |
396 | byte = readb(i2c->regs + S3C2410_IICDS); |
397 | i2c->msg->buf[i2c->msg_ptr++] = byte; | |
398 | ||
399 | prepare_read: | |
400 | if (is_msglast(i2c)) { | |
401 | /* last byte of buffer */ | |
402 | ||
403 | if (is_lastmsg(i2c)) | |
404 | s3c24xx_i2c_disable_ack(i2c); | |
405 | ||
406 | } else if (is_msgend(i2c)) { | |
407 | /* ok, we've read the entire buffer, see if there | |
408 | * is anything else we need to do */ | |
409 | ||
410 | if (is_lastmsg(i2c)) { | |
411 | /* last message, send stop and complete */ | |
412 | dev_dbg(i2c->dev, "READ: Send Stop\n"); | |
413 | ||
414 | s3c24xx_i2c_stop(i2c, 0); | |
415 | } else { | |
416 | /* go to the next transfer */ | |
417 | dev_dbg(i2c->dev, "READ: Next Transfer\n"); | |
418 | ||
419 | i2c->msg_ptr = 0; | |
420 | i2c->msg_idx++; | |
421 | i2c->msg++; | |
422 | } | |
423 | } | |
424 | ||
425 | break; | |
426 | } | |
427 | ||
428 | /* acknowlegde the IRQ and get back on with the work */ | |
429 | ||
430 | out_ack: | |
431 | tmp = readl(i2c->regs + S3C2410_IICCON); | |
432 | tmp &= ~S3C2410_IICCON_IRQPEND; | |
433 | writel(tmp, i2c->regs + S3C2410_IICCON); | |
434 | out: | |
435 | return ret; | |
436 | } | |
437 | ||
438 | /* s3c24xx_i2c_irq | |
439 | * | |
440 | * top level IRQ servicing routine | |
441 | */ | |
442 | ||
7d12e780 | 443 | static irqreturn_t s3c24xx_i2c_irq(int irqno, void *dev_id) |
1da177e4 LT |
444 | { |
445 | struct s3c24xx_i2c *i2c = dev_id; | |
446 | unsigned long status; | |
447 | unsigned long tmp; | |
448 | ||
449 | status = readl(i2c->regs + S3C2410_IICSTAT); | |
450 | ||
451 | if (status & S3C2410_IICSTAT_ARBITR) { | |
452 | // deal with arbitration loss | |
453 | dev_err(i2c->dev, "deal with arbitration loss\n"); | |
454 | } | |
455 | ||
456 | if (i2c->state == STATE_IDLE) { | |
457 | dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n"); | |
458 | ||
459 | tmp = readl(i2c->regs + S3C2410_IICCON); | |
460 | tmp &= ~S3C2410_IICCON_IRQPEND; | |
461 | writel(tmp, i2c->regs + S3C2410_IICCON); | |
462 | goto out; | |
463 | } | |
464 | ||
465 | /* pretty much this leaves us with the fact that we've | |
466 | * transmitted or received whatever byte we last sent */ | |
467 | ||
468 | i2s_s3c_irq_nextbyte(i2c, status); | |
469 | ||
470 | out: | |
471 | return IRQ_HANDLED; | |
472 | } | |
473 | ||
474 | ||
475 | /* s3c24xx_i2c_set_master | |
476 | * | |
477 | * get the i2c bus for a master transaction | |
478 | */ | |
479 | ||
480 | static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c) | |
481 | { | |
482 | unsigned long iicstat; | |
483 | int timeout = 400; | |
484 | ||
485 | while (timeout-- > 0) { | |
486 | iicstat = readl(i2c->regs + S3C2410_IICSTAT); | |
487 | ||
488 | if (!(iicstat & S3C2410_IICSTAT_BUSBUSY)) | |
489 | return 0; | |
490 | ||
491 | msleep(1); | |
492 | } | |
493 | ||
494 | dev_dbg(i2c->dev, "timeout: GPEDAT is %08x\n", | |
495 | __raw_readl(S3C2410_GPEDAT)); | |
496 | ||
497 | return -ETIMEDOUT; | |
498 | } | |
499 | ||
500 | /* s3c24xx_i2c_doxfer | |
501 | * | |
502 | * this starts an i2c transfer | |
503 | */ | |
504 | ||
505 | static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c, struct i2c_msg *msgs, int num) | |
506 | { | |
507 | unsigned long timeout; | |
508 | int ret; | |
509 | ||
da6801e3 | 510 | if (!(readl(i2c->regs + S3C2410_IICCON) & S3C2410_IICCON_IRQEN)) |
61c7cff8 BD |
511 | return -EIO; |
512 | ||
1da177e4 LT |
513 | ret = s3c24xx_i2c_set_master(i2c); |
514 | if (ret != 0) { | |
515 | dev_err(i2c->dev, "cannot get bus (error %d)\n", ret); | |
516 | ret = -EAGAIN; | |
517 | goto out; | |
518 | } | |
519 | ||
520 | spin_lock_irq(&i2c->lock); | |
521 | ||
522 | i2c->msg = msgs; | |
523 | i2c->msg_num = num; | |
524 | i2c->msg_ptr = 0; | |
525 | i2c->msg_idx = 0; | |
526 | i2c->state = STATE_START; | |
527 | ||
528 | s3c24xx_i2c_enable_irq(i2c); | |
529 | s3c24xx_i2c_message_start(i2c, msgs); | |
530 | spin_unlock_irq(&i2c->lock); | |
531 | ||
532 | timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5); | |
533 | ||
534 | ret = i2c->msg_idx; | |
535 | ||
536 | /* having these next two as dev_err() makes life very | |
537 | * noisy when doing an i2cdetect */ | |
538 | ||
539 | if (timeout == 0) | |
540 | dev_dbg(i2c->dev, "timeout\n"); | |
541 | else if (ret != num) | |
542 | dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret); | |
543 | ||
544 | /* ensure the stop has been through the bus */ | |
545 | ||
546 | msleep(1); | |
547 | ||
548 | out: | |
549 | return ret; | |
550 | } | |
551 | ||
552 | /* s3c24xx_i2c_xfer | |
553 | * | |
554 | * first port of call from the i2c bus code when an message needs | |
44bbe87e | 555 | * transferring across the i2c bus. |
1da177e4 LT |
556 | */ |
557 | ||
558 | static int s3c24xx_i2c_xfer(struct i2c_adapter *adap, | |
559 | struct i2c_msg *msgs, int num) | |
560 | { | |
561 | struct s3c24xx_i2c *i2c = (struct s3c24xx_i2c *)adap->algo_data; | |
562 | int retry; | |
563 | int ret; | |
564 | ||
565 | for (retry = 0; retry < adap->retries; retry++) { | |
566 | ||
567 | ret = s3c24xx_i2c_doxfer(i2c, msgs, num); | |
568 | ||
569 | if (ret != -EAGAIN) | |
570 | return ret; | |
571 | ||
572 | dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry); | |
573 | ||
574 | udelay(100); | |
575 | } | |
576 | ||
577 | return -EREMOTEIO; | |
578 | } | |
579 | ||
580 | /* declare our i2c functionality */ | |
581 | static u32 s3c24xx_i2c_func(struct i2c_adapter *adap) | |
582 | { | |
583 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING; | |
584 | } | |
585 | ||
586 | /* i2c bus registration info */ | |
587 | ||
8f9082c5 | 588 | static const struct i2c_algorithm s3c24xx_i2c_algorithm = { |
1da177e4 LT |
589 | .master_xfer = s3c24xx_i2c_xfer, |
590 | .functionality = s3c24xx_i2c_func, | |
591 | }; | |
592 | ||
593 | static struct s3c24xx_i2c s3c24xx_i2c = { | |
e00a8cdf BD |
594 | .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_i2c.lock), |
595 | .wait = __WAIT_QUEUE_HEAD_INITIALIZER(s3c24xx_i2c.wait), | |
596 | .tx_setup = 50, | |
597 | .adap = { | |
1da177e4 LT |
598 | .name = "s3c2410-i2c", |
599 | .owner = THIS_MODULE, | |
600 | .algo = &s3c24xx_i2c_algorithm, | |
601 | .retries = 2, | |
3401b2ff | 602 | .class = I2C_CLASS_HWMON | I2C_CLASS_SPD, |
1da177e4 LT |
603 | }, |
604 | }; | |
605 | ||
606 | /* s3c24xx_i2c_calcdivisor | |
607 | * | |
608 | * return the divisor settings for a given frequency | |
609 | */ | |
610 | ||
611 | static int s3c24xx_i2c_calcdivisor(unsigned long clkin, unsigned int wanted, | |
612 | unsigned int *div1, unsigned int *divs) | |
613 | { | |
614 | unsigned int calc_divs = clkin / wanted; | |
615 | unsigned int calc_div1; | |
616 | ||
617 | if (calc_divs > (16*16)) | |
618 | calc_div1 = 512; | |
619 | else | |
620 | calc_div1 = 16; | |
621 | ||
622 | calc_divs += calc_div1-1; | |
623 | calc_divs /= calc_div1; | |
624 | ||
625 | if (calc_divs == 0) | |
626 | calc_divs = 1; | |
627 | if (calc_divs > 17) | |
628 | calc_divs = 17; | |
629 | ||
630 | *divs = calc_divs; | |
631 | *div1 = calc_div1; | |
632 | ||
633 | return clkin / (calc_divs * calc_div1); | |
634 | } | |
635 | ||
636 | /* freq_acceptable | |
637 | * | |
638 | * test wether a frequency is within the acceptable range of error | |
639 | */ | |
640 | ||
641 | static inline int freq_acceptable(unsigned int freq, unsigned int wanted) | |
642 | { | |
643 | int diff = freq - wanted; | |
644 | ||
645 | return (diff >= -2 && diff <= 2); | |
646 | } | |
647 | ||
61c7cff8 | 648 | /* s3c24xx_i2c_clockrate |
1da177e4 LT |
649 | * |
650 | * work out a divisor for the user requested frequency setting, | |
651 | * either by the requested frequency, or scanning the acceptable | |
652 | * range of frequencies until something is found | |
653 | */ | |
654 | ||
61c7cff8 | 655 | static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got) |
1da177e4 | 656 | { |
61c7cff8 | 657 | struct s3c2410_platform_i2c *pdata; |
1da177e4 | 658 | unsigned long clkin = clk_get_rate(i2c->clk); |
1da177e4 | 659 | unsigned int divs, div1; |
61c7cff8 | 660 | u32 iiccon; |
1da177e4 LT |
661 | int freq; |
662 | int start, end; | |
663 | ||
61c7cff8 BD |
664 | i2c->clkrate = clkin; |
665 | ||
666 | pdata = s3c24xx_i2c_get_platformdata(i2c->adap.dev.parent); | |
1da177e4 LT |
667 | clkin /= 1000; /* clkin now in KHz */ |
668 | ||
61c7cff8 | 669 | dev_dbg(i2c->dev, "pdata %p, freq %lu %lu..%lu\n", |
1da177e4 LT |
670 | pdata, pdata->bus_freq, pdata->min_freq, pdata->max_freq); |
671 | ||
672 | if (pdata->bus_freq != 0) { | |
673 | freq = s3c24xx_i2c_calcdivisor(clkin, pdata->bus_freq/1000, | |
674 | &div1, &divs); | |
675 | if (freq_acceptable(freq, pdata->bus_freq/1000)) | |
676 | goto found; | |
677 | } | |
678 | ||
679 | /* ok, we may have to search for something suitable... */ | |
680 | ||
681 | start = (pdata->max_freq == 0) ? pdata->bus_freq : pdata->max_freq; | |
682 | end = pdata->min_freq; | |
683 | ||
684 | start /= 1000; | |
685 | end /= 1000; | |
686 | ||
687 | /* search loop... */ | |
688 | ||
689 | for (; start > end; start--) { | |
690 | freq = s3c24xx_i2c_calcdivisor(clkin, start, &div1, &divs); | |
691 | if (freq_acceptable(freq, start)) | |
692 | goto found; | |
693 | } | |
694 | ||
695 | /* cannot find frequency spec */ | |
696 | ||
697 | return -EINVAL; | |
698 | ||
699 | found: | |
700 | *got = freq; | |
61c7cff8 BD |
701 | |
702 | iiccon = readl(i2c->regs + S3C2410_IICCON); | |
703 | iiccon &= ~(S3C2410_IICCON_SCALEMASK | S3C2410_IICCON_TXDIV_512); | |
704 | iiccon |= (divs-1); | |
705 | ||
706 | if (div1 == 512) | |
707 | iiccon |= S3C2410_IICCON_TXDIV_512; | |
708 | ||
709 | writel(iiccon, i2c->regs + S3C2410_IICCON); | |
710 | ||
711 | return 0; | |
712 | } | |
713 | ||
714 | #ifdef CONFIG_CPU_FREQ | |
715 | ||
716 | #define freq_to_i2c(_n) container_of(_n, struct s3c24xx_i2c, freq_transition) | |
717 | ||
718 | static int s3c24xx_i2c_cpufreq_transition(struct notifier_block *nb, | |
719 | unsigned long val, void *data) | |
720 | { | |
721 | struct s3c24xx_i2c *i2c = freq_to_i2c(nb); | |
722 | unsigned long flags; | |
723 | unsigned int got; | |
724 | int delta_f; | |
725 | int ret; | |
726 | ||
727 | delta_f = clk_get_rate(i2c->clk) - i2c->clkrate; | |
728 | ||
729 | /* if we're post-change and the input clock has slowed down | |
730 | * or at pre-change and the clock is about to speed up, then | |
731 | * adjust our clock rate. <0 is slow, >0 speedup. | |
732 | */ | |
733 | ||
734 | if ((val == CPUFREQ_POSTCHANGE && delta_f < 0) || | |
735 | (val == CPUFREQ_PRECHANGE && delta_f > 0)) { | |
736 | spin_lock_irqsave(&i2c->lock, flags); | |
737 | ret = s3c24xx_i2c_clockrate(i2c, &got); | |
738 | spin_unlock_irqrestore(&i2c->lock, flags); | |
739 | ||
740 | if (ret < 0) | |
741 | dev_err(i2c->dev, "cannot find frequency\n"); | |
742 | else | |
743 | dev_info(i2c->dev, "setting freq %d\n", got); | |
744 | } | |
745 | ||
1da177e4 LT |
746 | return 0; |
747 | } | |
748 | ||
61c7cff8 BD |
749 | static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c) |
750 | { | |
751 | i2c->freq_transition.notifier_call = s3c24xx_i2c_cpufreq_transition; | |
752 | ||
753 | return cpufreq_register_notifier(&i2c->freq_transition, | |
754 | CPUFREQ_TRANSITION_NOTIFIER); | |
755 | } | |
756 | ||
757 | static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c) | |
758 | { | |
759 | cpufreq_unregister_notifier(&i2c->freq_transition, | |
760 | CPUFREQ_TRANSITION_NOTIFIER); | |
761 | } | |
762 | ||
763 | #else | |
764 | static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c) | |
765 | { | |
1da177e4 LT |
766 | return 0; |
767 | } | |
768 | ||
61c7cff8 BD |
769 | static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c) |
770 | { | |
771 | } | |
772 | #endif | |
773 | ||
1da177e4 LT |
774 | /* s3c24xx_i2c_init |
775 | * | |
776 | * initialise the controller, set the IO lines and frequency | |
777 | */ | |
778 | ||
779 | static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c) | |
780 | { | |
781 | unsigned long iicon = S3C2410_IICCON_IRQEN | S3C2410_IICCON_ACKEN; | |
782 | struct s3c2410_platform_i2c *pdata; | |
783 | unsigned int freq; | |
784 | ||
785 | /* get the plafrom data */ | |
786 | ||
787 | pdata = s3c24xx_i2c_get_platformdata(i2c->adap.dev.parent); | |
788 | ||
789 | /* inititalise the gpio */ | |
790 | ||
791 | s3c2410_gpio_cfgpin(S3C2410_GPE15, S3C2410_GPE15_IICSDA); | |
792 | s3c2410_gpio_cfgpin(S3C2410_GPE14, S3C2410_GPE14_IICSCL); | |
793 | ||
794 | /* write slave address */ | |
795 | ||
796 | writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD); | |
797 | ||
798 | dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr); | |
799 | ||
61c7cff8 BD |
800 | writel(iicon, i2c->regs + S3C2410_IICCON); |
801 | ||
1da177e4 LT |
802 | /* we need to work out the divisors for the clock... */ |
803 | ||
61c7cff8 BD |
804 | if (s3c24xx_i2c_clockrate(i2c, &freq) != 0) { |
805 | writel(0, i2c->regs + S3C2410_IICCON); | |
1da177e4 LT |
806 | dev_err(i2c->dev, "cannot meet bus frequency required\n"); |
807 | return -EINVAL; | |
808 | } | |
809 | ||
810 | /* todo - check that the i2c lines aren't being dragged anywhere */ | |
811 | ||
812 | dev_info(i2c->dev, "bus frequency set to %d KHz\n", freq); | |
813 | dev_dbg(i2c->dev, "S3C2410_IICCON=0x%02lx\n", iicon); | |
1da177e4 LT |
814 | |
815 | /* check for s3c2440 i2c controller */ | |
816 | ||
817 | if (s3c24xx_i2c_is2440(i2c)) { | |
818 | dev_dbg(i2c->dev, "S3C2440_IICLC=%08x\n", pdata->sda_delay); | |
819 | ||
820 | writel(pdata->sda_delay, i2c->regs + S3C2440_IICLC); | |
821 | } | |
822 | ||
823 | return 0; | |
824 | } | |
825 | ||
1da177e4 LT |
826 | /* s3c24xx_i2c_probe |
827 | * | |
828 | * called by the bus driver when a suitable device is found | |
829 | */ | |
830 | ||
3ae5eaec | 831 | static int s3c24xx_i2c_probe(struct platform_device *pdev) |
1da177e4 | 832 | { |
1da177e4 | 833 | struct s3c24xx_i2c *i2c = &s3c24xx_i2c; |
399dee23 | 834 | struct s3c2410_platform_i2c *pdata; |
1da177e4 LT |
835 | struct resource *res; |
836 | int ret; | |
837 | ||
399dee23 BD |
838 | pdata = s3c24xx_i2c_get_platformdata(&pdev->dev); |
839 | ||
1da177e4 LT |
840 | /* find the clock and enable it */ |
841 | ||
3ae5eaec RK |
842 | i2c->dev = &pdev->dev; |
843 | i2c->clk = clk_get(&pdev->dev, "i2c"); | |
1da177e4 | 844 | if (IS_ERR(i2c->clk)) { |
3ae5eaec | 845 | dev_err(&pdev->dev, "cannot get clock\n"); |
1da177e4 | 846 | ret = -ENOENT; |
5b68790c | 847 | goto err_noclk; |
1da177e4 LT |
848 | } |
849 | ||
3ae5eaec | 850 | dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk); |
1da177e4 | 851 | |
1da177e4 LT |
852 | clk_enable(i2c->clk); |
853 | ||
854 | /* map the registers */ | |
855 | ||
856 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
857 | if (res == NULL) { | |
3ae5eaec | 858 | dev_err(&pdev->dev, "cannot find IO resource\n"); |
1da177e4 | 859 | ret = -ENOENT; |
5b68790c | 860 | goto err_clk; |
1da177e4 LT |
861 | } |
862 | ||
863 | i2c->ioarea = request_mem_region(res->start, (res->end-res->start)+1, | |
864 | pdev->name); | |
865 | ||
866 | if (i2c->ioarea == NULL) { | |
3ae5eaec | 867 | dev_err(&pdev->dev, "cannot request IO\n"); |
1da177e4 | 868 | ret = -ENXIO; |
5b68790c | 869 | goto err_clk; |
1da177e4 LT |
870 | } |
871 | ||
872 | i2c->regs = ioremap(res->start, (res->end-res->start)+1); | |
873 | ||
874 | if (i2c->regs == NULL) { | |
3ae5eaec | 875 | dev_err(&pdev->dev, "cannot map IO\n"); |
1da177e4 | 876 | ret = -ENXIO; |
5b68790c | 877 | goto err_ioarea; |
1da177e4 LT |
878 | } |
879 | ||
3ae5eaec | 880 | dev_dbg(&pdev->dev, "registers %p (%p, %p)\n", i2c->regs, i2c->ioarea, res); |
1da177e4 LT |
881 | |
882 | /* setup info block for the i2c core */ | |
883 | ||
884 | i2c->adap.algo_data = i2c; | |
3ae5eaec | 885 | i2c->adap.dev.parent = &pdev->dev; |
1da177e4 LT |
886 | |
887 | /* initialise the i2c controller */ | |
888 | ||
889 | ret = s3c24xx_i2c_init(i2c); | |
890 | if (ret != 0) | |
5b68790c | 891 | goto err_iomap; |
1da177e4 LT |
892 | |
893 | /* find the IRQ for this unit (note, this relies on the init call to | |
894 | * ensure no current IRQs pending | |
895 | */ | |
896 | ||
897 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
898 | if (res == NULL) { | |
3ae5eaec | 899 | dev_err(&pdev->dev, "cannot find IRQ\n"); |
1da177e4 | 900 | ret = -ENOENT; |
5b68790c | 901 | goto err_iomap; |
1da177e4 LT |
902 | } |
903 | ||
dace1453 | 904 | ret = request_irq(res->start, s3c24xx_i2c_irq, IRQF_DISABLED, |
1da177e4 LT |
905 | pdev->name, i2c); |
906 | ||
907 | if (ret != 0) { | |
3ae5eaec | 908 | dev_err(&pdev->dev, "cannot claim IRQ\n"); |
5b68790c | 909 | goto err_iomap; |
1da177e4 LT |
910 | } |
911 | ||
912 | i2c->irq = res; | |
913 | ||
a1ba1583 AP |
914 | dev_dbg(&pdev->dev, "irq resource %p (%lu)\n", res, |
915 | (unsigned long)res->start); | |
1da177e4 | 916 | |
61c7cff8 | 917 | ret = s3c24xx_i2c_register_cpufreq(i2c); |
1da177e4 | 918 | if (ret < 0) { |
61c7cff8 | 919 | dev_err(&pdev->dev, "failed to register cpufreq notifier\n"); |
5b68790c | 920 | goto err_irq; |
1da177e4 LT |
921 | } |
922 | ||
399dee23 BD |
923 | /* Note, previous versions of the driver used i2c_add_adapter() |
924 | * to add the bus at any number. We now pass the bus number via | |
925 | * the platform data, so if unset it will now default to always | |
926 | * being bus 0. | |
927 | */ | |
928 | ||
929 | i2c->adap.nr = pdata->bus_num; | |
930 | ||
931 | ret = i2c_add_numbered_adapter(&i2c->adap); | |
1da177e4 | 932 | if (ret < 0) { |
3ae5eaec | 933 | dev_err(&pdev->dev, "failed to add bus to i2c core\n"); |
61c7cff8 | 934 | goto err_cpufreq; |
1da177e4 LT |
935 | } |
936 | ||
3ae5eaec | 937 | platform_set_drvdata(pdev, i2c); |
1da177e4 | 938 | |
3ae5eaec | 939 | dev_info(&pdev->dev, "%s: S3C I2C adapter\n", i2c->adap.dev.bus_id); |
5b68790c | 940 | return 0; |
1da177e4 | 941 | |
61c7cff8 BD |
942 | err_cpufreq: |
943 | s3c24xx_i2c_deregister_cpufreq(i2c); | |
944 | ||
5b68790c BD |
945 | err_irq: |
946 | free_irq(i2c->irq->start, i2c); | |
947 | ||
948 | err_iomap: | |
949 | iounmap(i2c->regs); | |
950 | ||
951 | err_ioarea: | |
952 | release_resource(i2c->ioarea); | |
953 | kfree(i2c->ioarea); | |
954 | ||
955 | err_clk: | |
956 | clk_disable(i2c->clk); | |
957 | clk_put(i2c->clk); | |
1da177e4 | 958 | |
5b68790c | 959 | err_noclk: |
1da177e4 LT |
960 | return ret; |
961 | } | |
962 | ||
963 | /* s3c24xx_i2c_remove | |
964 | * | |
965 | * called when device is removed from the bus | |
966 | */ | |
967 | ||
3ae5eaec | 968 | static int s3c24xx_i2c_remove(struct platform_device *pdev) |
1da177e4 | 969 | { |
3ae5eaec | 970 | struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev); |
5b68790c | 971 | |
61c7cff8 BD |
972 | s3c24xx_i2c_deregister_cpufreq(i2c); |
973 | ||
5b68790c BD |
974 | i2c_del_adapter(&i2c->adap); |
975 | free_irq(i2c->irq->start, i2c); | |
976 | ||
977 | clk_disable(i2c->clk); | |
978 | clk_put(i2c->clk); | |
979 | ||
980 | iounmap(i2c->regs); | |
981 | ||
982 | release_resource(i2c->ioarea); | |
983 | kfree(i2c->ioarea); | |
1da177e4 LT |
984 | |
985 | return 0; | |
986 | } | |
987 | ||
988 | #ifdef CONFIG_PM | |
3ae5eaec | 989 | static int s3c24xx_i2c_resume(struct platform_device *dev) |
1da177e4 | 990 | { |
3ae5eaec | 991 | struct s3c24xx_i2c *i2c = platform_get_drvdata(dev); |
9480e307 RK |
992 | |
993 | if (i2c != NULL) | |
1da177e4 | 994 | s3c24xx_i2c_init(i2c); |
1da177e4 LT |
995 | |
996 | return 0; | |
997 | } | |
998 | ||
999 | #else | |
1000 | #define s3c24xx_i2c_resume NULL | |
1001 | #endif | |
1002 | ||
1003 | /* device driver for platform bus bits */ | |
1004 | ||
3ae5eaec | 1005 | static struct platform_driver s3c2410_i2c_driver = { |
1da177e4 LT |
1006 | .probe = s3c24xx_i2c_probe, |
1007 | .remove = s3c24xx_i2c_remove, | |
1008 | .resume = s3c24xx_i2c_resume, | |
3ae5eaec RK |
1009 | .driver = { |
1010 | .owner = THIS_MODULE, | |
1011 | .name = "s3c2410-i2c", | |
1012 | }, | |
1da177e4 LT |
1013 | }; |
1014 | ||
3ae5eaec | 1015 | static struct platform_driver s3c2440_i2c_driver = { |
1da177e4 LT |
1016 | .probe = s3c24xx_i2c_probe, |
1017 | .remove = s3c24xx_i2c_remove, | |
1018 | .resume = s3c24xx_i2c_resume, | |
3ae5eaec RK |
1019 | .driver = { |
1020 | .owner = THIS_MODULE, | |
1021 | .name = "s3c2440-i2c", | |
1022 | }, | |
1da177e4 LT |
1023 | }; |
1024 | ||
1025 | static int __init i2c_adap_s3c_init(void) | |
1026 | { | |
1027 | int ret; | |
1028 | ||
3ae5eaec | 1029 | ret = platform_driver_register(&s3c2410_i2c_driver); |
e32e28ed | 1030 | if (ret == 0) { |
3ae5eaec | 1031 | ret = platform_driver_register(&s3c2440_i2c_driver); |
e32e28ed | 1032 | if (ret) |
3ae5eaec | 1033 | platform_driver_unregister(&s3c2410_i2c_driver); |
e32e28ed | 1034 | } |
1da177e4 LT |
1035 | |
1036 | return ret; | |
1037 | } | |
1038 | ||
1039 | static void __exit i2c_adap_s3c_exit(void) | |
1040 | { | |
3ae5eaec RK |
1041 | platform_driver_unregister(&s3c2410_i2c_driver); |
1042 | platform_driver_unregister(&s3c2440_i2c_driver); | |
1da177e4 LT |
1043 | } |
1044 | ||
1045 | module_init(i2c_adap_s3c_init); | |
1046 | module_exit(i2c_adap_s3c_exit); | |
1047 | ||
1048 | MODULE_DESCRIPTION("S3C24XX I2C Bus driver"); | |
1049 | MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>"); | |
1050 | MODULE_LICENSE("GPL"); | |
add8eda7 | 1051 | MODULE_ALIAS("platform:s3c2410-i2c"); |
d150a4bb | 1052 | MODULE_ALIAS("platform:s3c2440-i2c"); |