[linux-block.git] / drivers / i2c / busses / i2c-riic.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Renesas RIIC driver
 *
 * Copyright (C) 2013 Wolfram Sang <wsa@sang-engineering.com>
 * Copyright (C) 2013 Renesas Solutions Corp.
 */

/*
 * This i2c core has a lot of interrupts, namely 8. We use their chaining as
 * some kind of state machine.
 *
 * 1) The main xfer routine kicks off a transmission by putting the start bit
 * (or repeated start) on the bus and enabling the transmit interrupt (TIE)
 * since we need to send the slave address + RW bit in every case.
 *
 * 2) TIE sends slave address + RW bit and selects how to continue.
 *
 * 3a) Write case: We keep utilizing TIE as long as we have data to send. If we
 * are done, we switch over to the transmission done interrupt (TEIE) and mark
 * the message as completed (includes sending STOP) there.
 *
 * 3b) Read case: We switch over to receive interrupt (RIE). One dummy read is
 * needed to start clocking, then we keep receiving until we are done. Note
 * that we use the RDRFS mode all the time, i.e. we ACK/NACK every byte by
 * writing to the ACKBT bit. I tried using the RDRFS mode only at the end of a
 * message to create the final NACK as sketched in the datasheet. This caused
 * some subtle races (when byte n was processed and byte n+1 was already
 * waiting), though, and I started with the safe approach.
 *
 * 4) If we got a NACK somewhere, we flag the error and stop the transmission
 * via NAKIE.
 *
 * Also check the comments in the interrupt routines for some gory details.
 */

#include <linux/clk.h>
#include <linux/completion.h>
#include <linux/err.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/reset.h>

#define RIIC_ICCR1	0x00
#define RIIC_ICCR2	0x04
#define RIIC_ICMR1	0x08
#define RIIC_ICMR3	0x10
#define RIIC_ICSER	0x18
#define RIIC_ICIER	0x1c
#define RIIC_ICSR2	0x24
#define RIIC_ICBRL	0x34
#define RIIC_ICBRH	0x38
#define RIIC_ICDRT	0x3c
#define RIIC_ICDRR	0x40

#define ICCR1_ICE	0x80
#define ICCR1_IICRST	0x40
#define ICCR1_SOWP	0x10

#define ICCR2_BBSY	0x80
#define ICCR2_SP	0x08
#define ICCR2_RS	0x04
#define ICCR2_ST	0x02

#define ICMR1_CKS_MASK	0x70
#define ICMR1_BCWP	0x08
#define ICMR1_CKS(_x)	((((_x) << 4) & ICMR1_CKS_MASK) | ICMR1_BCWP)

#define ICMR3_RDRFS	0x20
#define ICMR3_ACKWP	0x10
#define ICMR3_ACKBT	0x08

#define ICIER_TIE	0x80
#define ICIER_TEIE	0x40
#define ICIER_RIE	0x20
#define ICIER_NAKIE	0x10
#define ICIER_SPIE	0x08

#define ICSR2_NACKF	0x10

#define ICBR_RESERVED	0xe0 /* Should be 1 on writes */

#define RIIC_INIT_MSG	-1

struct riic_dev {
	void __iomem *base;
	u8 *buf;
	struct i2c_msg *msg;
	int bytes_left;
	int err;
	int is_last;
	struct completion msg_done;
	struct i2c_adapter adapter;
	struct clk *clk;
};

struct riic_irq_desc {
	int res_num;
	irq_handler_t isr;
	char *name;
};

static inline void riic_clear_set_bit(struct riic_dev *riic, u8 clear, u8 set, u8 reg)
{
	writeb((readb(riic->base + reg) & ~clear) | set, riic->base + reg);
}

static int riic_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
{
	struct riic_dev *riic = i2c_get_adapdata(adap);
	unsigned long time_left;
	int i;
	u8 start_bit;

	pm_runtime_get_sync(adap->dev.parent);

	if (readb(riic->base + RIIC_ICCR2) & ICCR2_BBSY) {
		riic->err = -EBUSY;
		goto out;
	}

	reinit_completion(&riic->msg_done);
	riic->err = 0;

	writeb(0, riic->base + RIIC_ICSR2);

	for (i = 0, start_bit = ICCR2_ST; i < num; i++) {
		riic->bytes_left = RIIC_INIT_MSG;
		riic->buf = msgs[i].buf;
		riic->msg = &msgs[i];
		riic->is_last = (i == num - 1);

		writeb(ICIER_NAKIE | ICIER_TIE, riic->base + RIIC_ICIER);

		writeb(start_bit, riic->base + RIIC_ICCR2);

		time_left = wait_for_completion_timeout(&riic->msg_done, riic->adapter.timeout);
		if (time_left == 0)
			riic->err = -ETIMEDOUT;

		if (riic->err)
			break;

		start_bit = ICCR2_RS;
	}

 out:
	pm_runtime_put(adap->dev.parent);

	return riic->err ?: num;
}

static irqreturn_t riic_tdre_isr(int irq, void *data)
{
	struct riic_dev *riic = data;
	u8 val;

	if (!riic->bytes_left)
		return IRQ_NONE;

	if (riic->bytes_left == RIIC_INIT_MSG) {
		if (riic->msg->flags & I2C_M_RD)
			/* On read, switch over to receive interrupt */
			riic_clear_set_bit(riic, ICIER_TIE, ICIER_RIE, RIIC_ICIER);
		else
			/* On write, initialize length */
			riic->bytes_left = riic->msg->len;

		val = i2c_8bit_addr_from_msg(riic->msg);
	} else {
		val = *riic->buf;
		riic->buf++;
		riic->bytes_left--;
	}

	/*
	 * Switch to transmission ended interrupt when done. Do check here
	 * after bytes_left was initialized to support SMBUS_QUICK (new msg has
	 * 0 length then)
	 */
	if (riic->bytes_left == 0)
		riic_clear_set_bit(riic, ICIER_TIE, ICIER_TEIE, RIIC_ICIER);

	/*
	 * This acks the TIE interrupt. We get another TIE immediately if our
	 * value could be moved to the shadow shift register right away. So
	 * this must be after updates to ICIER (where we want to disable TIE)!
	 */
	writeb(val, riic->base + RIIC_ICDRT);

	return IRQ_HANDLED;
}

static irqreturn_t riic_tend_isr(int irq, void *data)
{
	struct riic_dev *riic = data;

	if (readb(riic->base + RIIC_ICSR2) & ICSR2_NACKF) {
		/* We got a NACKIE */
		readb(riic->base + RIIC_ICDRR);	/* dummy read */
		riic_clear_set_bit(riic, ICSR2_NACKF, 0, RIIC_ICSR2);
		riic->err = -ENXIO;
	} else if (riic->bytes_left) {
		return IRQ_NONE;
	}

	if (riic->is_last || riic->err) {
		riic_clear_set_bit(riic, ICIER_TEIE, ICIER_SPIE, RIIC_ICIER);
		writeb(ICCR2_SP, riic->base + RIIC_ICCR2);
	} else {
		/* Transfer is complete, but do not send STOP */
		riic_clear_set_bit(riic, ICIER_TEIE, 0, RIIC_ICIER);
		complete(&riic->msg_done);
	}

	return IRQ_HANDLED;
}

static irqreturn_t riic_rdrf_isr(int irq, void *data)
{
	struct riic_dev *riic = data;

	if (!riic->bytes_left)
		return IRQ_NONE;

	if (riic->bytes_left == RIIC_INIT_MSG) {
		riic->bytes_left = riic->msg->len;
		readb(riic->base + RIIC_ICDRR);	/* dummy read */
		return IRQ_HANDLED;
	}

	if (riic->bytes_left == 1) {
		/* STOP must come before we set ACKBT! */
		if (riic->is_last) {
			riic_clear_set_bit(riic, 0, ICIER_SPIE, RIIC_ICIER);
			writeb(ICCR2_SP, riic->base + RIIC_ICCR2);
		}

		riic_clear_set_bit(riic, 0, ICMR3_ACKBT, RIIC_ICMR3);

	} else {
		riic_clear_set_bit(riic, ICMR3_ACKBT, 0, RIIC_ICMR3);
	}

	/* Reading acks the RIE interrupt */
	*riic->buf = readb(riic->base + RIIC_ICDRR);
	riic->buf++;
	riic->bytes_left--;

	return IRQ_HANDLED;
}

static irqreturn_t riic_stop_isr(int irq, void *data)
{
	struct riic_dev *riic = data;

	/* read back registers to confirm writes have fully propagated */
	writeb(0, riic->base + RIIC_ICSR2);
	readb(riic->base + RIIC_ICSR2);
	writeb(0, riic->base + RIIC_ICIER);
	readb(riic->base + RIIC_ICIER);

	complete(&riic->msg_done);

	return IRQ_HANDLED;
}

static u32 riic_func(struct i2c_adapter *adap)
{
	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
}

static const struct i2c_algorithm riic_algo = {
	.master_xfer	= riic_xfer,
	.functionality	= riic_func,
};

static int riic_init_hw(struct riic_dev *riic, struct i2c_timings *t)
{
	int ret = 0;
	unsigned long rate;
	int total_ticks, cks, brl, brh;

	pm_runtime_get_sync(riic->adapter.dev.parent);

	if (t->bus_freq_hz > I2C_MAX_FAST_MODE_FREQ) {
		dev_err(&riic->adapter.dev,
			"unsupported bus speed (%dHz). %d max\n",
			t->bus_freq_hz, I2C_MAX_FAST_MODE_FREQ);
		ret = -EINVAL;
		goto out;
	}

	rate = clk_get_rate(riic->clk);

	/*
	 * Assume the default register settings:
	 *  FER.SCLE = 1 (SCL sync circuit enabled, adds 2 or 3 cycles)
	 *  FER.NFE = 1 (noise circuit enabled)
	 *  MR3.NF = 0 (1 cycle of noise filtered out)
	 *
	 * Freq (CKS=000) = (I2CCLK + tr + tf)/ (BRH + 3 + 1) + (BRL + 3 + 1)
	 * Freq (CKS!=000) = (I2CCLK + tr + tf)/ (BRH + 2 + 1) + (BRL + 2 + 1)
	 */

	/*
	 * Determine reference clock rate. We must be able to get the desired
	 * frequency with only 62 clock ticks max (31 high, 31 low).
	 * Aim for a duty of 60% LOW, 40% HIGH.
	 */
	total_ticks = DIV_ROUND_UP(rate, t->bus_freq_hz);

	for (cks = 0; cks < 7; cks++) {
		/*
		 * 60% low time must be less than BRL + 2 + 1
		 * BRL max register value is 0x1F.
		 */
		brl = ((total_ticks * 6) / 10);
		if (brl <= (0x1F + 3))
			break;

		total_ticks /= 2;
		rate /= 2;
	}

	if (brl > (0x1F + 3)) {
		dev_err(&riic->adapter.dev, "invalid speed (%lu). Too slow.\n",
			(unsigned long)t->bus_freq_hz);
		ret = -EINVAL;
		goto out;
	}

	brh = total_ticks - brl;

	/* Remove automatic clock ticks for sync circuit and NF */
	if (cks == 0) {
		brl -= 4;
		brh -= 4;
	} else {
		brl -= 3;
		brh -= 3;
	}

	/*
	 * Remove clock ticks for rise and fall times. Convert ns to clock
	 * ticks.
	 */
	brl -= t->scl_fall_ns / (1000000000 / rate);
	brh -= t->scl_rise_ns / (1000000000 / rate);

	/* Adjust for min register values for when SCLE=1 and NFE=1 */
	if (brl < 1)
		brl = 1;
	if (brh < 1)
		brh = 1;

	pr_debug("i2c-riic: freq=%lu, duty=%d, fall=%lu, rise=%lu, cks=%d, brl=%d, brh=%d\n",
		 rate / total_ticks, ((brl + 3) * 100) / (brl + brh + 6),
		 t->scl_fall_ns / (1000000000 / rate),
		 t->scl_rise_ns / (1000000000 / rate), cks, brl, brh);

	/* Changing the order of accessing IICRST and ICE may break things! */
	writeb(ICCR1_IICRST | ICCR1_SOWP, riic->base + RIIC_ICCR1);
	riic_clear_set_bit(riic, 0, ICCR1_ICE, RIIC_ICCR1);

	writeb(ICMR1_CKS(cks), riic->base + RIIC_ICMR1);
	writeb(brh | ICBR_RESERVED, riic->base + RIIC_ICBRH);
	writeb(brl | ICBR_RESERVED, riic->base + RIIC_ICBRL);

	writeb(0, riic->base + RIIC_ICSER);
	writeb(ICMR3_ACKWP | ICMR3_RDRFS, riic->base + RIIC_ICMR3);

	riic_clear_set_bit(riic, ICCR1_IICRST, 0, RIIC_ICCR1);

out:
	pm_runtime_put(riic->adapter.dev.parent);
	return ret;
}

static struct riic_irq_desc riic_irqs[] = {
	{ .res_num = 0, .isr = riic_tend_isr, .name = "riic-tend" },
	{ .res_num = 1, .isr = riic_rdrf_isr, .name = "riic-rdrf" },
	{ .res_num = 2, .isr = riic_tdre_isr, .name = "riic-tdre" },
	{ .res_num = 3, .isr = riic_stop_isr, .name = "riic-stop" },
	{ .res_num = 5, .isr = riic_tend_isr, .name = "riic-nack" },
};

static void riic_reset_control_assert(void *data)
{
	reset_control_assert(data);
}

static int riic_i2c_probe(struct platform_device *pdev)
{
	struct riic_dev *riic;
	struct i2c_adapter *adap;
	struct resource *res;
	struct i2c_timings i2c_t;
	struct reset_control *rstc;
	int i, ret;

	riic = devm_kzalloc(&pdev->dev, sizeof(*riic), GFP_KERNEL);
	if (!riic)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	riic->base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(riic->base))
		return PTR_ERR(riic->base);

	riic->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(riic->clk)) {
		dev_err(&pdev->dev, "missing controller clock");
		return PTR_ERR(riic->clk);
	}

	rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
	if (IS_ERR(rstc))
		return dev_err_probe(&pdev->dev, PTR_ERR(rstc),
				     "Error: missing reset ctrl\n");

	ret = reset_control_deassert(rstc);
	if (ret)
		return ret;

	ret = devm_add_action_or_reset(&pdev->dev, riic_reset_control_assert, rstc);
	if (ret)
		return ret;

	for (i = 0; i < ARRAY_SIZE(riic_irqs); i++) {
		ret = platform_get_irq(pdev, riic_irqs[i].res_num);
		if (ret < 0)
			return ret;

		ret = devm_request_irq(&pdev->dev, ret, riic_irqs[i].isr,
				       0, riic_irqs[i].name, riic);
		if (ret) {
			dev_err(&pdev->dev, "failed to request irq %s\n", riic_irqs[i].name);
			return ret;
		}
	}

	adap = &riic->adapter;
	i2c_set_adapdata(adap, riic);
	strscpy(adap->name, "Renesas RIIC adapter", sizeof(adap->name));
	adap->owner = THIS_MODULE;
	adap->algo = &riic_algo;
	adap->dev.parent = &pdev->dev;
	adap->dev.of_node = pdev->dev.of_node;

	init_completion(&riic->msg_done);

	i2c_parse_fw_timings(&pdev->dev, &i2c_t, true);

	pm_runtime_enable(&pdev->dev);

	ret = riic_init_hw(riic, &i2c_t);
	if (ret)
		goto out;

	ret = i2c_add_adapter(adap);
	if (ret)
		goto out;

	platform_set_drvdata(pdev, riic);

	dev_info(&pdev->dev, "registered with %dHz bus speed\n",
		 i2c_t.bus_freq_hz);
	return 0;

out:
	pm_runtime_disable(&pdev->dev);
	return ret;
}

static int riic_i2c_remove(struct platform_device *pdev)
{
	struct riic_dev *riic = platform_get_drvdata(pdev);

	pm_runtime_get_sync(&pdev->dev);
	writeb(0, riic->base + RIIC_ICIER);
	pm_runtime_put(&pdev->dev);
	i2c_del_adapter(&riic->adapter);
	pm_runtime_disable(&pdev->dev);

	return 0;
}

static const struct of_device_id riic_i2c_dt_ids[] = {
	{ .compatible = "renesas,riic-rz", },
	{ /* Sentinel */ },
};

static struct platform_driver riic_i2c_driver = {
	.probe		= riic_i2c_probe,
	.remove		= riic_i2c_remove,
	.driver		= {
		.name	= "i2c-riic",
		.of_match_table = riic_i2c_dt_ids,
	},
};

module_platform_driver(riic_i2c_driver);

MODULE_DESCRIPTION("Renesas RIIC adapter");
MODULE_AUTHOR("Wolfram Sang <wsa@sang-engineering.com>");
MODULE_LICENSE("GPL v2");
MODULE_DEVICE_TABLE(of, riic_i2c_dt_ids);
Commit	Line	Data
6055af5e	1	// SPDX-License-Identifier: GPL-2.0
310c18a4 WS	2	/*
	3	* Renesas RIIC driver
	4	*
	5	* Copyright (C) 2013 Wolfram Sang <wsa@sang-engineering.com>
	6	* Copyright (C) 2013 Renesas Solutions Corp.
310c18a4 WS	7	*/
	8
	9	/*
	10	* This i2c core has a lot of interrupts, namely 8. We use their chaining as
	11	* some kind of state machine.
	12	*
	13	* 1) The main xfer routine kicks off a transmission by putting the start bit
	14	* (or repeated start) on the bus and enabling the transmit interrupt (TIE)
	15	* since we need to send the slave address + RW bit in every case.
	16	*
	17	* 2) TIE sends slave address + RW bit and selects how to continue.
	18	*
	19	* 3a) Write case: We keep utilizing TIE as long as we have data to send. If we
	20	* are done, we switch over to the transmission done interrupt (TEIE) and mark
	21	* the message as completed (includes sending STOP) there.
	22	*
	23	* 3b) Read case: We switch over to receive interrupt (RIE). One dummy read is
	24	* needed to start clocking, then we keep receiving until we are done. Note
	25	* that we use the RDRFS mode all the time, i.e. we ACK/NACK every byte by
	26	* writing to the ACKBT bit. I tried using the RDRFS mode only at the end of a
	27	* message to create the final NACK as sketched in the datasheet. This caused
	28	* some subtle races (when byte n was processed and byte n+1 was already
	29	* waiting), though, and I started with the safe approach.
	30	*
	31	* 4) If we got a NACK somewhere, we flag the error and stop the transmission
	32	* via NAKIE.
	33	*
	34	* Also check the comments in the interrupt routines for some gory details.
	35	*/
	36
	37	#include <linux/clk.h>
	38	#include <linux/completion.h>
	39	#include <linux/err.h>
	40	#include <linux/i2c.h>
	41	#include <linux/interrupt.h>
	42	#include <linux/io.h>
	43	#include <linux/module.h>
	44	#include <linux/of.h>
010e765b	45	#include <linux/of_device.h>
310c18a4	46	#include <linux/platform_device.h>
d303ce59	47	#include <linux/pm_runtime.h>
010e765b	48	#include <linux/reset.h>
310c18a4 WS	49
	50	#define RIIC_ICCR1 0x00
	51	#define RIIC_ICCR2 0x04
	52	#define RIIC_ICMR1 0x08
	53	#define RIIC_ICMR3 0x10
	54	#define RIIC_ICSER 0x18
	55	#define RIIC_ICIER 0x1c
	56	#define RIIC_ICSR2 0x24
	57	#define RIIC_ICBRL 0x34
	58	#define RIIC_ICBRH 0x38
	59	#define RIIC_ICDRT 0x3c
	60	#define RIIC_ICDRR 0x40
	61
	62	#define ICCR1_ICE 0x80
	63	#define ICCR1_IICRST 0x40
	64	#define ICCR1_SOWP 0x10
	65
	66	#define ICCR2_BBSY 0x80
	67	#define ICCR2_SP 0x08
	68	#define ICCR2_RS 0x04
	69	#define ICCR2_ST 0x02
	70
	71	#define ICMR1_CKS_MASK 0x70
	72	#define ICMR1_BCWP 0x08
	73	#define ICMR1_CKS(_x) ((((_x) << 4) & ICMR1_CKS_MASK) \| ICMR1_BCWP)
	74
	75	#define ICMR3_RDRFS 0x20
	76	#define ICMR3_ACKWP 0x10
	77	#define ICMR3_ACKBT 0x08
	78
	79	#define ICIER_TIE 0x80
	80	#define ICIER_TEIE 0x40
	81	#define ICIER_RIE 0x20
	82	#define ICIER_NAKIE 0x10
71ccea09	83	#define ICIER_SPIE 0x08
310c18a4 WS	84
	85	#define ICSR2_NACKF 0x10
	86
310c18a4	87	#define ICBR_RESERVED 0xe0 /* Should be 1 on writes */
310c18a4 WS	88
	89	#define RIIC_INIT_MSG -1
	90
	91	struct riic_dev {
	92	void __iomem *base;
	93	u8 *buf;
	94	struct i2c_msg *msg;
	95	int bytes_left;
	96	int err;
	97	int is_last;
	98	struct completion msg_done;
	99	struct i2c_adapter adapter;
	100	struct clk *clk;
	101	};
	102
	103	struct riic_irq_desc {
	104	int res_num;
	105	irq_handler_t isr;
	106	char *name;
	107	};
	108
	109	static inline void riic_clear_set_bit(struct riic_dev *riic, u8 clear, u8 set, u8 reg)
	110	{
	111	writeb((readb(riic->base + reg) & ~clear) \| set, riic->base + reg);
	112	}
	113
	114	static int riic_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
	115	{
	116	struct riic_dev *riic = i2c_get_adapdata(adap);
	117	unsigned long time_left;
d303ce59	118	int i;
310c18a4 WS	119	u8 start_bit;
310c18a4 WS	120
d303ce59	121	pm_runtime_get_sync(adap->dev.parent);
310c18a4 WS	122
	123	if (readb(riic->base + RIIC_ICCR2) & ICCR2_BBSY) {
	124	riic->err = -EBUSY;
	125	goto out;
	126	}
	127
	128	reinit_completion(&riic->msg_done);
	129	riic->err = 0;
	130
	131	writeb(0, riic->base + RIIC_ICSR2);
	132
	133	for (i = 0, start_bit = ICCR2_ST; i < num; i++) {
	134	riic->bytes_left = RIIC_INIT_MSG;
	135	riic->buf = msgs[i].buf;
	136	riic->msg = &msgs[i];
	137	riic->is_last = (i == num - 1);
	138
	139	writeb(ICIER_NAKIE \| ICIER_TIE, riic->base + RIIC_ICIER);
	140
	141	writeb(start_bit, riic->base + RIIC_ICCR2);
	142
	143	time_left = wait_for_completion_timeout(&riic->msg_done, riic->adapter.timeout);
	144	if (time_left == 0)
	145	riic->err = -ETIMEDOUT;
	146
	147	if (riic->err)
	148	break;
	149
	150	start_bit = ICCR2_RS;
	151	}
	152
	153	out:
d303ce59	154	pm_runtime_put(adap->dev.parent);
310c18a4 WS	155
	156	return riic->err ?: num;
	157	}
	158
	159	static irqreturn_t riic_tdre_isr(int irq, void *data)
	160	{
	161	struct riic_dev *riic = data;
	162	u8 val;
	163
	164	if (!riic->bytes_left)
	165	return IRQ_NONE;
	166
	167	if (riic->bytes_left == RIIC_INIT_MSG) {
30a64757	168	if (riic->msg->flags & I2C_M_RD)
310c18a4 WS	169	/* On read, switch over to receive interrupt */
	170	riic_clear_set_bit(riic, ICIER_TIE, ICIER_RIE, RIIC_ICIER);
	171	else
	172	/* On write, initialize length */
	173	riic->bytes_left = riic->msg->len;
	174
30a64757	175	val = i2c_8bit_addr_from_msg(riic->msg);
310c18a4 WS	176	} else {
	177	val = *riic->buf;
	178	riic->buf++;
	179	riic->bytes_left--;
	180	}
	181
	182	/*
	183	* Switch to transmission ended interrupt when done. Do check here
	184	* after bytes_left was initialized to support SMBUS_QUICK (new msg has
	185	* 0 length then)
	186	*/
	187	if (riic->bytes_left == 0)
	188	riic_clear_set_bit(riic, ICIER_TIE, ICIER_TEIE, RIIC_ICIER);
	189
	190	/*
	191	* This acks the TIE interrupt. We get another TIE immediately if our
	192	* value could be moved to the shadow shift register right away. So
	193	* this must be after updates to ICIER (where we want to disable TIE)!
	194	*/
	195	writeb(val, riic->base + RIIC_ICDRT);
	196
	197	return IRQ_HANDLED;
	198	}
	199
	200	static irqreturn_t riic_tend_isr(int irq, void *data)
	201	{
	202	struct riic_dev *riic = data;
	203
	204	if (readb(riic->base + RIIC_ICSR2) & ICSR2_NACKF) {
	205	/* We got a NACKIE */
	206	readb(riic->base + RIIC_ICDRR); /* dummy read */
a71e2ac1	207	riic_clear_set_bit(riic, ICSR2_NACKF, 0, RIIC_ICSR2);
310c18a4 WS	208	riic->err = -ENXIO;
	209	} else if (riic->bytes_left) {
	210	return IRQ_NONE;
	211	}
	212
71ccea09	213	if (riic->is_last \|\| riic->err) {
2501c1bb	214	riic_clear_set_bit(riic, ICIER_TEIE, ICIER_SPIE, RIIC_ICIER);
310c18a4	215	writeb(ICCR2_SP, riic->base + RIIC_ICCR2);
2501c1bb CB	216	} else {
	217	/* Transfer is complete, but do not send STOP */
	218	riic_clear_set_bit(riic, ICIER_TEIE, 0, RIIC_ICIER);
	219	complete(&riic->msg_done);
71ccea09	220	}
310c18a4 WS	221
	222	return IRQ_HANDLED;
	223	}
	224
	225	static irqreturn_t riic_rdrf_isr(int irq, void *data)
	226	{
	227	struct riic_dev *riic = data;
	228
	229	if (!riic->bytes_left)
	230	return IRQ_NONE;
	231
	232	if (riic->bytes_left == RIIC_INIT_MSG) {
	233	riic->bytes_left = riic->msg->len;
	234	readb(riic->base + RIIC_ICDRR); /* dummy read */
	235	return IRQ_HANDLED;
	236	}
	237
	238	if (riic->bytes_left == 1) {
	239	/* STOP must come before we set ACKBT! */
71ccea09 CB	240	if (riic->is_last) {
71ccea09 CB	241	riic_clear_set_bit(riic, 0, ICIER_SPIE, RIIC_ICIER);
310c18a4	242	writeb(ICCR2_SP, riic->base + RIIC_ICCR2);
71ccea09	243	}
310c18a4 WS	244
	245	riic_clear_set_bit(riic, 0, ICMR3_ACKBT, RIIC_ICMR3);
	246
310c18a4 WS	247	} else {
	248	riic_clear_set_bit(riic, ICMR3_ACKBT, 0, RIIC_ICMR3);
	249	}
	250
	251	/* Reading acks the RIE interrupt */
	252	*riic->buf = readb(riic->base + RIIC_ICDRR);
	253	riic->buf++;
	254	riic->bytes_left--;
	255
	256	return IRQ_HANDLED;
	257	}
	258
71ccea09 CB	259	static irqreturn_t riic_stop_isr(int irq, void *data)
	260	{
	261	struct riic_dev *riic = data;
	262
	263	/* read back registers to confirm writes have fully propagated */
	264	writeb(0, riic->base + RIIC_ICSR2);
	265	readb(riic->base + RIIC_ICSR2);
	266	writeb(0, riic->base + RIIC_ICIER);
	267	readb(riic->base + RIIC_ICIER);
	268
	269	complete(&riic->msg_done);
	270
	271	return IRQ_HANDLED;
	272	}
	273
310c18a4 WS	274	static u32 riic_func(struct i2c_adapter *adap)
	275	{
	276	return I2C_FUNC_I2C \| I2C_FUNC_SMBUS_EMUL;
	277	}
	278
	279	static const struct i2c_algorithm riic_algo = {
	280	.master_xfer = riic_xfer,
	281	.functionality = riic_func,
	282	};
	283
d982d665	284	static int riic_init_hw(struct riic_dev riic, struct i2c_timings t)
310c18a4	285	{
d303ce59	286	int ret = 0;
310c18a4	287	unsigned long rate;
d982d665	288	int total_ticks, cks, brl, brh;
310c18a4	289
d303ce59	290	pm_runtime_get_sync(riic->adapter.dev.parent);
310c18a4	291
90224e64	292	if (t->bus_freq_hz > I2C_MAX_FAST_MODE_FREQ) {
d982d665	293	dev_err(&riic->adapter.dev,
90224e64 AS	294	"unsupported bus speed (%dHz). %d max\n",
90224e64 AS	295	t->bus_freq_hz, I2C_MAX_FAST_MODE_FREQ);
d303ce59 GU	296	ret = -EINVAL;
d303ce59 GU	297	goto out;
d982d665 CB	298	}
	299
	300	rate = clk_get_rate(riic->clk);
	301
310c18a4	302	/*
d982d665 CB	303	* Assume the default register settings:
	304	* FER.SCLE = 1 (SCL sync circuit enabled, adds 2 or 3 cycles)
	305	* FER.NFE = 1 (noise circuit enabled)
	306	* MR3.NF = 0 (1 cycle of noise filtered out)
	307	*
	308	* Freq (CKS=000) = (I2CCLK + tr + tf)/ (BRH + 3 + 1) + (BRL + 3 + 1)
	309	* Freq (CKS!=000) = (I2CCLK + tr + tf)/ (BRH + 2 + 1) + (BRL + 2 + 1)
310c18a4	310	*/
d982d665 CB	311
	312	/*
	313	* Determine reference clock rate. We must be able to get the desired
	314	* frequency with only 62 clock ticks max (31 high, 31 low).
	315	* Aim for a duty of 60% LOW, 40% HIGH.
	316	*/
	317	total_ticks = DIV_ROUND_UP(rate, t->bus_freq_hz);
	318
	319	for (cks = 0; cks < 7; cks++) {
	320	/*
	321	* 60% low time must be less than BRL + 2 + 1
	322	* BRL max register value is 0x1F.
	323	*/
	324	brl = ((total_ticks * 6) / 10);
	325	if (brl <= (0x1F + 3))
	326	break;
	327
	328	total_ticks /= 2;
	329	rate /= 2;
	330	}
	331
	332	if (brl > (0x1F + 3)) {
	333	dev_err(&riic->adapter.dev, "invalid speed (%lu). Too slow.\n",
	334	(unsigned long)t->bus_freq_hz);
d303ce59 GU	335	ret = -EINVAL;
d303ce59 GU	336	goto out;
310c18a4 WS	337	}
310c18a4 WS	338
d982d665 CB	339	brh = total_ticks - brl;
	340
	341	/* Remove automatic clock ticks for sync circuit and NF */
	342	if (cks == 0) {
	343	brl -= 4;
	344	brh -= 4;
	345	} else {
	346	brl -= 3;
	347	brh -= 3;
	348	}
	349
	350	/*
	351	* Remove clock ticks for rise and fall times. Convert ns to clock
	352	* ticks.
	353	*/
	354	brl -= t->scl_fall_ns / (1000000000 / rate);
	355	brh -= t->scl_rise_ns / (1000000000 / rate);
	356
	357	/* Adjust for min register values for when SCLE=1 and NFE=1 */
	358	if (brl < 1)
	359	brl = 1;
	360	if (brh < 1)
	361	brh = 1;
	362
	363	pr_debug("i2c-riic: freq=%lu, duty=%d, fall=%lu, rise=%lu, cks=%d, brl=%d, brh=%d\n",
	364	rate / total_ticks, ((brl + 3) * 100) / (brl + brh + 6),
	365	t->scl_fall_ns / (1000000000 / rate),
	366	t->scl_rise_ns / (1000000000 / rate), cks, brl, brh);
	367
310c18a4 WS	368	/* Changing the order of accessing IICRST and ICE may break things! */
	369	writeb(ICCR1_IICRST \| ICCR1_SOWP, riic->base + RIIC_ICCR1);
	370	riic_clear_set_bit(riic, 0, ICCR1_ICE, RIIC_ICCR1);
	371
d982d665 CB	372	writeb(ICMR1_CKS(cks), riic->base + RIIC_ICMR1);
	373	writeb(brh \| ICBR_RESERVED, riic->base + RIIC_ICBRH);
	374	writeb(brl \| ICBR_RESERVED, riic->base + RIIC_ICBRL);
310c18a4 WS	375
	376	writeb(0, riic->base + RIIC_ICSER);
	377	writeb(ICMR3_ACKWP \| ICMR3_RDRFS, riic->base + RIIC_ICMR3);
	378
	379	riic_clear_set_bit(riic, ICCR1_IICRST, 0, RIIC_ICCR1);
	380
d303ce59 GU	381	out:
	382	pm_runtime_put(riic->adapter.dev.parent);
	383	return ret;
310c18a4 WS	384	}
	385
	386	static struct riic_irq_desc riic_irqs[] = {
	387	{ .res_num = 0, .isr = riic_tend_isr, .name = "riic-tend" },
	388	{ .res_num = 1, .isr = riic_rdrf_isr, .name = "riic-rdrf" },
	389	{ .res_num = 2, .isr = riic_tdre_isr, .name = "riic-tdre" },
71ccea09	390	{ .res_num = 3, .isr = riic_stop_isr, .name = "riic-stop" },
310c18a4 WS	391	{ .res_num = 5, .isr = riic_tend_isr, .name = "riic-nack" },
	392	};
	393
da2e86c0 LP	394	static void riic_reset_control_assert(void *data)
	395	{
	396	reset_control_assert(data);
	397	}
	398
310c18a4 WS	399	static int riic_i2c_probe(struct platform_device *pdev)
310c18a4 WS	400	{
310c18a4 WS	401	struct riic_dev *riic;
	402	struct i2c_adapter *adap;
	403	struct resource *res;
d982d665	404	struct i2c_timings i2c_t;
010e765b	405	struct reset_control *rstc;
310c18a4 WS	406	int i, ret;
	407
	408	riic = devm_kzalloc(&pdev->dev, sizeof(*riic), GFP_KERNEL);
	409	if (!riic)
	410	return -ENOMEM;
	411
	412	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	413	riic->base = devm_ioremap_resource(&pdev->dev, res);
	414	if (IS_ERR(riic->base))
	415	return PTR_ERR(riic->base);
	416
	417	riic->clk = devm_clk_get(&pdev->dev, NULL);
	418	if (IS_ERR(riic->clk)) {
	419	dev_err(&pdev->dev, "missing controller clock");
	420	return PTR_ERR(riic->clk);
	421	}
	422
da2e86c0 LP	423	rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
	424	if (IS_ERR(rstc))
	425	return dev_err_probe(&pdev->dev, PTR_ERR(rstc),
	426	"Error: missing reset ctrl\n");
010e765b	427
da2e86c0 LP	428	ret = reset_control_deassert(rstc);
	429	if (ret)
	430	return ret;
	431
	432	ret = devm_add_action_or_reset(&pdev->dev, riic_reset_control_assert, rstc);
	433	if (ret)
	434	return ret;
010e765b	435
310c18a4	436	for (i = 0; i < ARRAY_SIZE(riic_irqs); i++) {
8ab1ff9b LP	437	ret = platform_get_irq(pdev, riic_irqs[i].res_num);
	438	if (ret < 0)
	439	return ret;
310c18a4	440
8ab1ff9b LP	441	ret = devm_request_irq(&pdev->dev, ret, riic_irqs[i].isr,
8ab1ff9b LP	442	0, riic_irqs[i].name, riic);
310c18a4 WS	443	if (ret) {
	444	dev_err(&pdev->dev, "failed to request irq %s\n", riic_irqs[i].name);
	445	return ret;
	446	}
	447	}
	448
	449	adap = &riic->adapter;
	450	i2c_set_adapdata(adap, riic);
ea1558ce	451	strscpy(adap->name, "Renesas RIIC adapter", sizeof(adap->name));
310c18a4 WS	452	adap->owner = THIS_MODULE;
	453	adap->algo = &riic_algo;
	454	adap->dev.parent = &pdev->dev;
	455	adap->dev.of_node = pdev->dev.of_node;
	456
	457	init_completion(&riic->msg_done);
	458
d982d665 CB	459	i2c_parse_fw_timings(&pdev->dev, &i2c_t, true);
d982d665 CB	460
d303ce59 GU	461	pm_runtime_enable(&pdev->dev);
d303ce59 GU	462
d982d665	463	ret = riic_init_hw(riic, &i2c_t);
310c18a4	464	if (ret)
d303ce59	465	goto out;
310c18a4 WS	466
310c18a4 WS	467	ret = i2c_add_adapter(adap);
ea734404	468	if (ret)
d303ce59	469	goto out;
310c18a4 WS	470
	471	platform_set_drvdata(pdev, riic);
	472
d982d665 CB	473	dev_info(&pdev->dev, "registered with %dHz bus speed\n",
d982d665 CB	474	i2c_t.bus_freq_hz);
310c18a4	475	return 0;
d303ce59 GU	476
	477	out:
	478	pm_runtime_disable(&pdev->dev);
	479	return ret;
310c18a4 WS	480	}
	481
	482	static int riic_i2c_remove(struct platform_device *pdev)
	483	{
	484	struct riic_dev *riic = platform_get_drvdata(pdev);
	485
d303ce59	486	pm_runtime_get_sync(&pdev->dev);
310c18a4	487	writeb(0, riic->base + RIIC_ICIER);
d303ce59	488	pm_runtime_put(&pdev->dev);
310c18a4	489	i2c_del_adapter(&riic->adapter);
d303ce59	490	pm_runtime_disable(&pdev->dev);
310c18a4 WS	491
	492	return 0;
	493	}
	494
eae45e5d	495	static const struct of_device_id riic_i2c_dt_ids[] = {
da2e86c0	496	{ .compatible = "renesas,riic-rz", },
310c18a4 WS	497	{ /* Sentinel */ },
	498	};
	499
	500	static struct platform_driver riic_i2c_driver = {
	501	.probe = riic_i2c_probe,
	502	.remove = riic_i2c_remove,
	503	.driver = {
	504	.name = "i2c-riic",
310c18a4 WS	505	.of_match_table = riic_i2c_dt_ids,
	506	},
	507	};
	508
	509	module_platform_driver(riic_i2c_driver);
	510
	511	MODULE_DESCRIPTION("Renesas RIIC adapter");
	512	MODULE_AUTHOR("Wolfram Sang <wsa@sang-engineering.com>");
	513	MODULE_LICENSE("GPL v2");
	514	MODULE_DEVICE_TABLE(of, riic_i2c_dt_ids);