[linux-2.6-block.git] / drivers / i2c / busses / i2c-qup.c

/*
 * Copyright (c) 2009-2013, The Linux Foundation. All rights reserved.
 * Copyright (c) 2014, Sony Mobile Communications AB.
 *
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>

/* QUP Registers */
#define QUP_CONFIG		0x000
#define QUP_STATE		0x004
#define QUP_IO_MODE		0x008
#define QUP_SW_RESET		0x00c
#define QUP_OPERATIONAL		0x018
#define QUP_ERROR_FLAGS		0x01c
#define QUP_ERROR_FLAGS_EN	0x020
#define QUP_HW_VERSION		0x030
#define QUP_MX_OUTPUT_CNT	0x100
#define QUP_OUT_FIFO_BASE	0x110
#define QUP_MX_WRITE_CNT	0x150
#define QUP_MX_INPUT_CNT	0x200
#define QUP_MX_READ_CNT		0x208
#define QUP_IN_FIFO_BASE	0x218
#define QUP_I2C_CLK_CTL		0x400
#define QUP_I2C_STATUS		0x404

/* QUP States and reset values */
#define QUP_RESET_STATE		0
#define QUP_RUN_STATE		1
#define QUP_PAUSE_STATE		3
#define QUP_STATE_MASK		3

#define QUP_STATE_VALID		BIT(2)
#define QUP_I2C_MAST_GEN	BIT(4)

#define QUP_OPERATIONAL_RESET	0x000ff0
#define QUP_I2C_STATUS_RESET	0xfffffc

/* QUP OPERATIONAL FLAGS */
#define QUP_I2C_NACK_FLAG	BIT(3)
#define QUP_OUT_NOT_EMPTY	BIT(4)
#define QUP_IN_NOT_EMPTY	BIT(5)
#define QUP_OUT_FULL		BIT(6)
#define QUP_OUT_SVC_FLAG	BIT(8)
#define QUP_IN_SVC_FLAG		BIT(9)
#define QUP_MX_OUTPUT_DONE	BIT(10)
#define QUP_MX_INPUT_DONE	BIT(11)

/* I2C mini core related values */
#define QUP_CLOCK_AUTO_GATE	BIT(13)
#define I2C_MINI_CORE		(2 << 8)
#define I2C_N_VAL		15
/* Most significant word offset in FIFO port */
#define QUP_MSW_SHIFT		(I2C_N_VAL + 1)

/* Packing/Unpacking words in FIFOs, and IO modes */
#define QUP_OUTPUT_BLK_MODE	(1 << 10)
#define QUP_INPUT_BLK_MODE	(1 << 12)
#define QUP_UNPACK_EN		BIT(14)
#define QUP_PACK_EN		BIT(15)

#define QUP_REPACK_EN		(QUP_UNPACK_EN | QUP_PACK_EN)

#define QUP_OUTPUT_BLOCK_SIZE(x)(((x) >> 0) & 0x03)
#define QUP_OUTPUT_FIFO_SIZE(x)	(((x) >> 2) & 0x07)
#define QUP_INPUT_BLOCK_SIZE(x)	(((x) >> 5) & 0x03)
#define QUP_INPUT_FIFO_SIZE(x)	(((x) >> 7) & 0x07)

/* QUP tags */
#define QUP_TAG_START		(1 << 8)
#define QUP_TAG_DATA		(2 << 8)
#define QUP_TAG_STOP		(3 << 8)
#define QUP_TAG_REC		(4 << 8)

/* Status, Error flags */
#define I2C_STATUS_WR_BUFFER_FULL	BIT(0)
#define I2C_STATUS_BUS_ACTIVE		BIT(8)
#define I2C_STATUS_ERROR_MASK		0x38000fc
#define QUP_STATUS_ERROR_FLAGS		0x7c

#define QUP_READ_LIMIT			256
#define SET_BIT				0x1
#define RESET_BIT			0x0
#define ONE_BYTE			0x1

struct qup_i2c_dev {
	struct device		*dev;
	void __iomem		*base;
	int			irq;
	struct clk		*clk;
	struct clk		*pclk;
	struct i2c_adapter	adap;

	int			clk_ctl;
	int			out_fifo_sz;
	int			in_fifo_sz;
	int			out_blk_sz;
	int			in_blk_sz;

	unsigned long		one_byte_t;

	struct i2c_msg		*msg;
	/* Current posion in user message buffer */
	int			pos;
	/* I2C protocol errors */
	u32			bus_err;
	/* QUP core errors */
	u32			qup_err;

	struct completion	xfer;
};

static irqreturn_t qup_i2c_interrupt(int irq, void *dev)
{
	struct qup_i2c_dev *qup = dev;
	u32 bus_err;
	u32 qup_err;
	u32 opflags;

	bus_err = readl(qup->base + QUP_I2C_STATUS);
	qup_err = readl(qup->base + QUP_ERROR_FLAGS);
	opflags = readl(qup->base + QUP_OPERATIONAL);

	if (!qup->msg) {
		/* Clear Error interrupt */
		writel(QUP_RESET_STATE, qup->base + QUP_STATE);
		return IRQ_HANDLED;
	}

	bus_err &= I2C_STATUS_ERROR_MASK;
	qup_err &= QUP_STATUS_ERROR_FLAGS;

	if (qup_err) {
		/* Clear Error interrupt */
		writel(qup_err, qup->base + QUP_ERROR_FLAGS);
		goto done;
	}

	if (bus_err) {
		/* Clear Error interrupt */
		writel(QUP_RESET_STATE, qup->base + QUP_STATE);
		goto done;
	}

	if (opflags & QUP_IN_SVC_FLAG)
		writel(QUP_IN_SVC_FLAG, qup->base + QUP_OPERATIONAL);

	if (opflags & QUP_OUT_SVC_FLAG)
		writel(QUP_OUT_SVC_FLAG, qup->base + QUP_OPERATIONAL);

done:
	qup->qup_err = qup_err;
	qup->bus_err = bus_err;
	complete(&qup->xfer);
	return IRQ_HANDLED;
}

static int qup_i2c_poll_state_mask(struct qup_i2c_dev *qup,
				   u32 req_state, u32 req_mask)
{
	int retries = 1;
	u32 state;

	/*
	 * State transition takes 3 AHB clocks cycles + 3 I2C master clock
	 * cycles. So retry once after a 1uS delay.
	 */
	do {
		state = readl(qup->base + QUP_STATE);

		if (state & QUP_STATE_VALID &&
		    (state & req_mask) == req_state)
			return 0;

		udelay(1);
	} while (retries--);

	return -ETIMEDOUT;
}

static int qup_i2c_poll_state(struct qup_i2c_dev *qup, u32 req_state)
{
	return qup_i2c_poll_state_mask(qup, req_state, QUP_STATE_MASK);
}

static int qup_i2c_poll_state_valid(struct qup_i2c_dev *qup)
{
	return qup_i2c_poll_state_mask(qup, 0, 0);
}

static int qup_i2c_poll_state_i2c_master(struct qup_i2c_dev *qup)
{
	return qup_i2c_poll_state_mask(qup, QUP_I2C_MAST_GEN, QUP_I2C_MAST_GEN);
}

static int qup_i2c_change_state(struct qup_i2c_dev *qup, u32 state)
{
	if (qup_i2c_poll_state_valid(qup) != 0)
		return -EIO;

	writel(state, qup->base + QUP_STATE);

	if (qup_i2c_poll_state(qup, state) != 0)
		return -EIO;
	return 0;
}

/**
 * qup_i2c_wait_ready - wait for a give number of bytes in tx/rx path
 * @qup: The qup_i2c_dev device
 * @op: The bit/event to wait on
 * @val: value of the bit to wait on, 0 or 1
 * @len: The length the bytes to be transferred
 */
static int qup_i2c_wait_ready(struct qup_i2c_dev *qup, int op, bool val,
			      int len)
{
	unsigned long timeout;
	u32 opflags;
	u32 status;
	u32 shift = __ffs(op);

	len *= qup->one_byte_t;
	/* timeout after a wait of twice the max time */
	timeout = jiffies + len * 4;

	for (;;) {
		opflags = readl(qup->base + QUP_OPERATIONAL);
		status = readl(qup->base + QUP_I2C_STATUS);

		if (((opflags & op) >> shift) == val) {
			if (op == QUP_OUT_NOT_EMPTY) {
				if (!(status & I2C_STATUS_BUS_ACTIVE))
					return 0;
			} else {
				return 0;
			}
		}

		if (time_after(jiffies, timeout))
			return -ETIMEDOUT;

		usleep_range(len, len * 2);
	}
}

static void qup_i2c_set_write_mode(struct qup_i2c_dev *qup, struct i2c_msg *msg)
{
	/* Number of entries to shift out, including the start */
	int total = msg->len + 1;

	if (total < qup->out_fifo_sz) {
		/* FIFO mode */
		writel(QUP_REPACK_EN, qup->base + QUP_IO_MODE);
		writel(total, qup->base + QUP_MX_WRITE_CNT);
	} else {
		/* BLOCK mode (transfer data on chunks) */
		writel(QUP_OUTPUT_BLK_MODE | QUP_REPACK_EN,
		       qup->base + QUP_IO_MODE);
		writel(total, qup->base + QUP_MX_OUTPUT_CNT);
	}
}

static int qup_i2c_issue_write(struct qup_i2c_dev *qup, struct i2c_msg *msg)
{
	u32 addr = msg->addr << 1;
	u32 qup_tag;
	int idx;
	u32 val;
	int ret = 0;

	if (qup->pos == 0) {
		val = QUP_TAG_START | addr;
		idx = 1;
	} else {
		val = 0;
		idx = 0;
	}

	while (qup->pos < msg->len) {
		/* Check that there's space in the FIFO for our pair */
		ret = qup_i2c_wait_ready(qup, QUP_OUT_FULL, RESET_BIT,
					 4 * ONE_BYTE);
		if (ret)
			return ret;

		if (qup->pos == msg->len - 1)
			qup_tag = QUP_TAG_STOP;
		else
			qup_tag = QUP_TAG_DATA;

		if (idx & 1)
			val |= (qup_tag | msg->buf[qup->pos]) << QUP_MSW_SHIFT;
		else
			val = qup_tag | msg->buf[qup->pos];

		/* Write out the pair and the last odd value */
		if (idx & 1 || qup->pos == msg->len - 1)
			writel(val, qup->base + QUP_OUT_FIFO_BASE);

		qup->pos++;
		idx++;
	}

	return ret;
}

static int qup_i2c_write_one(struct qup_i2c_dev *qup, struct i2c_msg *msg)
{
	unsigned long left;
	int ret;

	qup->msg = msg;
	qup->pos = 0;

	enable_irq(qup->irq);

	qup_i2c_set_write_mode(qup, msg);

	ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
	if (ret)
		goto err;

	writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);

	do {
		ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
		if (ret)
			goto err;

		ret = qup_i2c_issue_write(qup, msg);
		if (ret)
			goto err;

		ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
		if (ret)
			goto err;

		left = wait_for_completion_timeout(&qup->xfer, HZ);
		if (!left) {
			writel(1, qup->base + QUP_SW_RESET);
			ret = -ETIMEDOUT;
			goto err;
		}

		if (qup->bus_err || qup->qup_err) {
			if (qup->bus_err & QUP_I2C_NACK_FLAG)
				dev_err(qup->dev, "NACK from %x\n", msg->addr);
			ret = -EIO;
			goto err;
		}
	} while (qup->pos < msg->len);

	/* Wait for the outstanding data in the fifo to drain */
	ret = qup_i2c_wait_ready(qup, QUP_OUT_NOT_EMPTY, RESET_BIT, ONE_BYTE);

err:
	disable_irq(qup->irq);
	qup->msg = NULL;

	return ret;
}

static void qup_i2c_set_read_mode(struct qup_i2c_dev *qup, int len)
{
	if (len < qup->in_fifo_sz) {
		/* FIFO mode */
		writel(QUP_REPACK_EN, qup->base + QUP_IO_MODE);
		writel(len, qup->base + QUP_MX_READ_CNT);
	} else {
		/* BLOCK mode (transfer data on chunks) */
		writel(QUP_INPUT_BLK_MODE | QUP_REPACK_EN,
		       qup->base + QUP_IO_MODE);
		writel(len, qup->base + QUP_MX_INPUT_CNT);
	}
}

static void qup_i2c_issue_read(struct qup_i2c_dev *qup, struct i2c_msg *msg)
{
	u32 addr, len, val;

	addr = (msg->addr << 1) | 1;

	/* 0 is used to specify a length 256 (QUP_READ_LIMIT) */
	len = (msg->len == QUP_READ_LIMIT) ? 0 : msg->len;

	val = ((QUP_TAG_REC | len) << QUP_MSW_SHIFT) | QUP_TAG_START | addr;
	writel(val, qup->base + QUP_OUT_FIFO_BASE);
}


static int qup_i2c_read_fifo(struct qup_i2c_dev *qup, struct i2c_msg *msg)
{
	u32 val = 0;
	int idx;
	int ret = 0;

	for (idx = 0; qup->pos < msg->len; idx++) {
		if ((idx & 1) == 0) {
			/* Check that FIFO have data */
			ret = qup_i2c_wait_ready(qup, QUP_IN_NOT_EMPTY,
						 SET_BIT, 4 * ONE_BYTE);
			if (ret)
				return ret;

			/* Reading 2 words at time */
			val = readl(qup->base + QUP_IN_FIFO_BASE);

			msg->buf[qup->pos++] = val & 0xFF;
		} else {
			msg->buf[qup->pos++] = val >> QUP_MSW_SHIFT;
		}
	}

	return ret;
}

static int qup_i2c_read_one(struct qup_i2c_dev *qup, struct i2c_msg *msg)
{
	unsigned long left;
	int ret;

	qup->msg = msg;
	qup->pos  = 0;

	enable_irq(qup->irq);

	qup_i2c_set_read_mode(qup, msg->len);

	ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
	if (ret)
		goto err;

	writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);

	ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
	if (ret)
		goto err;

	qup_i2c_issue_read(qup, msg);

	ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
	if (ret)
		goto err;

	do {
		left = wait_for_completion_timeout(&qup->xfer, HZ);
		if (!left) {
			writel(1, qup->base + QUP_SW_RESET);
			ret = -ETIMEDOUT;
			goto err;
		}

		if (qup->bus_err || qup->qup_err) {
			if (qup->bus_err & QUP_I2C_NACK_FLAG)
				dev_err(qup->dev, "NACK from %x\n", msg->addr);
			ret = -EIO;
			goto err;
		}

		ret = qup_i2c_read_fifo(qup, msg);
		if (ret)
			goto err;
	} while (qup->pos < msg->len);

err:
	disable_irq(qup->irq);
	qup->msg = NULL;

	return ret;
}

static int qup_i2c_xfer(struct i2c_adapter *adap,
			struct i2c_msg msgs[],
			int num)
{
	struct qup_i2c_dev *qup = i2c_get_adapdata(adap);
	int ret, idx;

	ret = pm_runtime_get_sync(qup->dev);
	if (ret < 0)
		goto out;

	writel(1, qup->base + QUP_SW_RESET);
	ret = qup_i2c_poll_state(qup, QUP_RESET_STATE);
	if (ret)
		goto out;

	/* Configure QUP as I2C mini core */
	writel(I2C_MINI_CORE | I2C_N_VAL, qup->base + QUP_CONFIG);

	for (idx = 0; idx < num; idx++) {
		if (msgs[idx].len == 0) {
			ret = -EINVAL;
			goto out;
		}

		if (qup_i2c_poll_state_i2c_master(qup)) {
			ret = -EIO;
			goto out;
		}

		if (msgs[idx].flags & I2C_M_RD)
			ret = qup_i2c_read_one(qup, &msgs[idx]);
		else
			ret = qup_i2c_write_one(qup, &msgs[idx]);

		if (ret)
			break;

		ret = qup_i2c_change_state(qup, QUP_RESET_STATE);
		if (ret)
			break;
	}

	if (ret == 0)
		ret = num;
out:

	pm_runtime_mark_last_busy(qup->dev);
	pm_runtime_put_autosuspend(qup->dev);

	return ret;
}

static u32 qup_i2c_func(struct i2c_adapter *adap)
{
	return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
}

static const struct i2c_algorithm qup_i2c_algo = {
	.master_xfer	= qup_i2c_xfer,
	.functionality	= qup_i2c_func,
};

/*
 * The QUP block will issue a NACK and STOP on the bus when reaching
 * the end of the read, the length of the read is specified as one byte
 * which limits the possible read to 256 (QUP_READ_LIMIT) bytes.
 */
static struct i2c_adapter_quirks qup_i2c_quirks = {
	.max_read_len = QUP_READ_LIMIT,
};

static void qup_i2c_enable_clocks(struct qup_i2c_dev *qup)
{
	clk_prepare_enable(qup->clk);
	clk_prepare_enable(qup->pclk);
}

static void qup_i2c_disable_clocks(struct qup_i2c_dev *qup)
{
	u32 config;

	qup_i2c_change_state(qup, QUP_RESET_STATE);
	clk_disable_unprepare(qup->clk);
	config = readl(qup->base + QUP_CONFIG);
	config |= QUP_CLOCK_AUTO_GATE;
	writel(config, qup->base + QUP_CONFIG);
	clk_disable_unprepare(qup->pclk);
}

static int qup_i2c_probe(struct platform_device *pdev)
{
	static const int blk_sizes[] = {4, 16, 32};
	struct device_node *node = pdev->dev.of_node;
	struct qup_i2c_dev *qup;
	unsigned long one_bit_t;
	struct resource *res;
	u32 io_mode, hw_ver, size;
	int ret, fs_div, hs_div;
	int src_clk_freq;
	u32 clk_freq = 100000;

	qup = devm_kzalloc(&pdev->dev, sizeof(*qup), GFP_KERNEL);
	if (!qup)
		return -ENOMEM;

	qup->dev = &pdev->dev;
	init_completion(&qup->xfer);
	platform_set_drvdata(pdev, qup);

	of_property_read_u32(node, "clock-frequency", &clk_freq);

	/* We support frequencies up to FAST Mode (400KHz) */
	if (!clk_freq || clk_freq > 400000) {
		dev_err(qup->dev, "clock frequency not supported %d\n",
			clk_freq);
		return -EINVAL;
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	qup->base = devm_ioremap_resource(qup->dev, res);
	if (IS_ERR(qup->base))
		return PTR_ERR(qup->base);

	qup->irq = platform_get_irq(pdev, 0);
	if (qup->irq < 0) {
		dev_err(qup->dev, "No IRQ defined\n");
		return qup->irq;
	}

	qup->clk = devm_clk_get(qup->dev, "core");
	if (IS_ERR(qup->clk)) {
		dev_err(qup->dev, "Could not get core clock\n");
		return PTR_ERR(qup->clk);
	}

	qup->pclk = devm_clk_get(qup->dev, "iface");
	if (IS_ERR(qup->pclk)) {
		dev_err(qup->dev, "Could not get iface clock\n");
		return PTR_ERR(qup->pclk);
	}

	qup_i2c_enable_clocks(qup);

	/*
	 * Bootloaders might leave a pending interrupt on certain QUP's,
	 * so we reset the core before registering for interrupts.
	 */
	writel(1, qup->base + QUP_SW_RESET);
	ret = qup_i2c_poll_state_valid(qup);
	if (ret)
		goto fail;

	ret = devm_request_irq(qup->dev, qup->irq, qup_i2c_interrupt,
			       IRQF_TRIGGER_HIGH, "i2c_qup", qup);
	if (ret) {
		dev_err(qup->dev, "Request %d IRQ failed\n", qup->irq);
		goto fail;
	}
	disable_irq(qup->irq);

	hw_ver = readl(qup->base + QUP_HW_VERSION);
	dev_dbg(qup->dev, "Revision %x\n", hw_ver);

	io_mode = readl(qup->base + QUP_IO_MODE);

	/*
	 * The block/fifo size w.r.t. 'actual data' is 1/2 due to 'tag'
	 * associated with each byte written/received
	 */
	size = QUP_OUTPUT_BLOCK_SIZE(io_mode);
	if (size >= ARRAY_SIZE(blk_sizes)) {
		ret = -EIO;
		goto fail;
	}
	qup->out_blk_sz = blk_sizes[size] / 2;

	size = QUP_INPUT_BLOCK_SIZE(io_mode);
	if (size >= ARRAY_SIZE(blk_sizes)) {
		ret = -EIO;
		goto fail;
	}
	qup->in_blk_sz = blk_sizes[size] / 2;

	size = QUP_OUTPUT_FIFO_SIZE(io_mode);
	qup->out_fifo_sz = qup->out_blk_sz * (2 << size);

	size = QUP_INPUT_FIFO_SIZE(io_mode);
	qup->in_fifo_sz = qup->in_blk_sz * (2 << size);

	src_clk_freq = clk_get_rate(qup->clk);
	fs_div = ((src_clk_freq / clk_freq) / 2) - 3;
	hs_div = 3;
	qup->clk_ctl = (hs_div << 8) | (fs_div & 0xff);

	/*
	 * Time it takes for a byte to be clocked out on the bus.
	 * Each byte takes 9 clock cycles (8 bits + 1 ack).
	 */
	one_bit_t = (USEC_PER_SEC / clk_freq) + 1;
	qup->one_byte_t = one_bit_t * 9;

	dev_dbg(qup->dev, "IN:block:%d, fifo:%d, OUT:block:%d, fifo:%d\n",
		qup->in_blk_sz, qup->in_fifo_sz,
		qup->out_blk_sz, qup->out_fifo_sz);

	i2c_set_adapdata(&qup->adap, qup);
	qup->adap.algo = &qup_i2c_algo;
	qup->adap.quirks = &qup_i2c_quirks;
	qup->adap.dev.parent = qup->dev;
	qup->adap.dev.of_node = pdev->dev.of_node;
	strlcpy(qup->adap.name, "QUP I2C adapter", sizeof(qup->adap.name));

	pm_runtime_set_autosuspend_delay(qup->dev, MSEC_PER_SEC);
	pm_runtime_use_autosuspend(qup->dev);
	pm_runtime_set_active(qup->dev);
	pm_runtime_enable(qup->dev);

	ret = i2c_add_adapter(&qup->adap);
	if (ret)
		goto fail_runtime;

	return 0;

fail_runtime:
	pm_runtime_disable(qup->dev);
	pm_runtime_set_suspended(qup->dev);
fail:
	qup_i2c_disable_clocks(qup);
	return ret;
}

static int qup_i2c_remove(struct platform_device *pdev)
{
	struct qup_i2c_dev *qup = platform_get_drvdata(pdev);

	disable_irq(qup->irq);
	qup_i2c_disable_clocks(qup);
	i2c_del_adapter(&qup->adap);
	pm_runtime_disable(qup->dev);
	pm_runtime_set_suspended(qup->dev);
	return 0;
}

#ifdef CONFIG_PM
static int qup_i2c_pm_suspend_runtime(struct device *device)
{
	struct qup_i2c_dev *qup = dev_get_drvdata(device);

	dev_dbg(device, "pm_runtime: suspending...\n");
	qup_i2c_disable_clocks(qup);
	return 0;
}

static int qup_i2c_pm_resume_runtime(struct device *device)
{
	struct qup_i2c_dev *qup = dev_get_drvdata(device);

	dev_dbg(device, "pm_runtime: resuming...\n");
	qup_i2c_enable_clocks(qup);
	return 0;
}
#endif

#ifdef CONFIG_PM_SLEEP
static int qup_i2c_suspend(struct device *device)
{
	qup_i2c_pm_suspend_runtime(device);
	return 0;
}

static int qup_i2c_resume(struct device *device)
{
	qup_i2c_pm_resume_runtime(device);
	pm_runtime_mark_last_busy(device);
	pm_request_autosuspend(device);
	return 0;
}
#endif

static const struct dev_pm_ops qup_i2c_qup_pm_ops = {
	SET_SYSTEM_SLEEP_PM_OPS(
		qup_i2c_suspend,
		qup_i2c_resume)
	SET_RUNTIME_PM_OPS(
		qup_i2c_pm_suspend_runtime,
		qup_i2c_pm_resume_runtime,
		NULL)
};

static const struct of_device_id qup_i2c_dt_match[] = {
	{ .compatible = "qcom,i2c-qup-v1.1.1" },
	{ .compatible = "qcom,i2c-qup-v2.1.1" },
	{ .compatible = "qcom,i2c-qup-v2.2.1" },
	{}
};
MODULE_DEVICE_TABLE(of, qup_i2c_dt_match);

static struct platform_driver qup_i2c_driver = {
	.probe  = qup_i2c_probe,
	.remove = qup_i2c_remove,
	.driver = {
		.name = "i2c_qup",
		.pm = &qup_i2c_qup_pm_ops,
		.of_match_table = qup_i2c_dt_match,
	},
};

module_platform_driver(qup_i2c_driver);

MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:i2c_qup");
Commit	Line	Data
10c5a842 BA	1	/*
	2	* Copyright (c) 2009-2013, The Linux Foundation. All rights reserved.
	3	* Copyright (c) 2014, Sony Mobile Communications AB.
	4	*
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 and
	8	* only version 2 as published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	*/
	16
	17	#include <linux/clk.h>
	18	#include <linux/delay.h>
	19	#include <linux/err.h>
	20	#include <linux/i2c.h>
	21	#include <linux/interrupt.h>
	22	#include <linux/io.h>
	23	#include <linux/module.h>
	24	#include <linux/of.h>
	25	#include <linux/platform_device.h>
	26	#include <linux/pm_runtime.h>
	27
	28	/* QUP Registers */
	29	#define QUP_CONFIG 0x000
	30	#define QUP_STATE 0x004
	31	#define QUP_IO_MODE 0x008
	32	#define QUP_SW_RESET 0x00c
	33	#define QUP_OPERATIONAL 0x018
	34	#define QUP_ERROR_FLAGS 0x01c
	35	#define QUP_ERROR_FLAGS_EN 0x020
	36	#define QUP_HW_VERSION 0x030
	37	#define QUP_MX_OUTPUT_CNT 0x100
	38	#define QUP_OUT_FIFO_BASE 0x110
	39	#define QUP_MX_WRITE_CNT 0x150
	40	#define QUP_MX_INPUT_CNT 0x200
	41	#define QUP_MX_READ_CNT 0x208
	42	#define QUP_IN_FIFO_BASE 0x218
	43	#define QUP_I2C_CLK_CTL 0x400
	44	#define QUP_I2C_STATUS 0x404
	45
	46	/* QUP States and reset values */
	47	#define QUP_RESET_STATE 0
	48	#define QUP_RUN_STATE 1
	49	#define QUP_PAUSE_STATE 3
	50	#define QUP_STATE_MASK 3
	51
	52	#define QUP_STATE_VALID BIT(2)
	53	#define QUP_I2C_MAST_GEN BIT(4)
	54
	55	#define QUP_OPERATIONAL_RESET 0x000ff0
	56	#define QUP_I2C_STATUS_RESET 0xfffffc
	57
	58	/* QUP OPERATIONAL FLAGS */
	59	#define QUP_I2C_NACK_FLAG BIT(3)
	60	#define QUP_OUT_NOT_EMPTY BIT(4)
	61	#define QUP_IN_NOT_EMPTY BIT(5)
	62	#define QUP_OUT_FULL BIT(6)
	63	#define QUP_OUT_SVC_FLAG BIT(8)
	64	#define QUP_IN_SVC_FLAG BIT(9)
65	#define QUP_MX_OUTPUT_DONE BIT(10)
66	#define QUP_MX_INPUT_DONE BIT(11)
67
68	/* I2C mini core related values */
69	#define QUP_CLOCK_AUTO_GATE BIT(13)
70	#define I2C_MINI_CORE (2 << 8)
71	#define I2C_N_VAL 15
72	/* Most significant word offset in FIFO port */
73	#define QUP_MSW_SHIFT (I2C_N_VAL + 1)
74
75	/* Packing/Unpacking words in FIFOs, and IO modes */
76	#define QUP_OUTPUT_BLK_MODE (1 << 10)
77	#define QUP_INPUT_BLK_MODE (1 << 12)
78	#define QUP_UNPACK_EN BIT(14)
79	#define QUP_PACK_EN BIT(15)
80
81	#define QUP_REPACK_EN (QUP_UNPACK_EN \| QUP_PACK_EN)
82
83	#define QUP_OUTPUT_BLOCK_SIZE(x)(((x) >> 0) & 0x03)
84	#define QUP_OUTPUT_FIFO_SIZE(x) (((x) >> 2) & 0x07)
85	#define QUP_INPUT_BLOCK_SIZE(x) (((x) >> 5) & 0x03)
86	#define QUP_INPUT_FIFO_SIZE(x) (((x) >> 7) & 0x07)
87
88	/* QUP tags */
89	#define QUP_TAG_START (1 << 8)
90	#define QUP_TAG_DATA (2 << 8)
91	#define QUP_TAG_STOP (3 << 8)
92	#define QUP_TAG_REC (4 << 8)
93
94	/* Status, Error flags */
95	#define I2C_STATUS_WR_BUFFER_FULL BIT(0)
96	#define I2C_STATUS_BUS_ACTIVE BIT(8)
97	#define I2C_STATUS_ERROR_MASK 0x38000fc
98	#define QUP_STATUS_ERROR_FLAGS 0x7c
99
100	#define QUP_READ_LIMIT 256
c4f0c5fb S	101	#define SET_BIT 0x1
	102	#define RESET_BIT 0x0
	103	#define ONE_BYTE 0x1
10c5a842 BA	104
	105	struct qup_i2c_dev {
	106	struct device *dev;
	107	void __iomem *base;
	108	int irq;
	109	struct clk *clk;
	110	struct clk *pclk;
	111	struct i2c_adapter adap;
	112
	113	int clk_ctl;
	114	int out_fifo_sz;
	115	int in_fifo_sz;
	116	int out_blk_sz;
	117	int in_blk_sz;
	118
	119	unsigned long one_byte_t;
	120
	121	struct i2c_msg *msg;
	122	/* Current posion in user message buffer */
	123	int pos;
	124	/* I2C protocol errors */
	125	u32 bus_err;
	126	/* QUP core errors */
	127	u32 qup_err;
	128
	129	struct completion xfer;
	130	};
	131
	132	static irqreturn_t qup_i2c_interrupt(int irq, void *dev)
	133	{
	134	struct qup_i2c_dev *qup = dev;
	135	u32 bus_err;
	136	u32 qup_err;
	137	u32 opflags;
	138
	139	bus_err = readl(qup->base + QUP_I2C_STATUS);
	140	qup_err = readl(qup->base + QUP_ERROR_FLAGS);
	141	opflags = readl(qup->base + QUP_OPERATIONAL);
	142
	143	if (!qup->msg) {
	144	/* Clear Error interrupt */
	145	writel(QUP_RESET_STATE, qup->base + QUP_STATE);
	146	return IRQ_HANDLED;
	147	}
	148
	149	bus_err &= I2C_STATUS_ERROR_MASK;
	150	qup_err &= QUP_STATUS_ERROR_FLAGS;
	151
	152	if (qup_err) {
	153	/* Clear Error interrupt */
	154	writel(qup_err, qup->base + QUP_ERROR_FLAGS);
	155	goto done;
	156	}
	157
	158	if (bus_err) {
	159	/* Clear Error interrupt */
	160	writel(QUP_RESET_STATE, qup->base + QUP_STATE);
	161	goto done;
	162	}
	163
	164	if (opflags & QUP_IN_SVC_FLAG)
	165	writel(QUP_IN_SVC_FLAG, qup->base + QUP_OPERATIONAL);
	166
	167	if (opflags & QUP_OUT_SVC_FLAG)
168	writel(QUP_OUT_SVC_FLAG, qup->base + QUP_OPERATIONAL);
169
170	done:
171	qup->qup_err = qup_err;
172	qup->bus_err = bus_err;
173	complete(&qup->xfer);
174	return IRQ_HANDLED;
175	}
176
177	static int qup_i2c_poll_state_mask(struct qup_i2c_dev *qup,
178	u32 req_state, u32 req_mask)
179	{
180	int retries = 1;
181	u32 state;
182
183	/*
184	* State transition takes 3 AHB clocks cycles + 3 I2C master clock
185	* cycles. So retry once after a 1uS delay.
186	*/
187	do {
188	state = readl(qup->base + QUP_STATE);
189
190	if (state & QUP_STATE_VALID &&
191	(state & req_mask) == req_state)
192	return 0;
193
194	udelay(1);
195	} while (retries--);
196
197	return -ETIMEDOUT;
198	}
199
200	static int qup_i2c_poll_state(struct qup_i2c_dev *qup, u32 req_state)
201	{
202	return qup_i2c_poll_state_mask(qup, req_state, QUP_STATE_MASK);
203	}
204
205	static int qup_i2c_poll_state_valid(struct qup_i2c_dev *qup)
206	{
207	return qup_i2c_poll_state_mask(qup, 0, 0);
208	}
209
210	static int qup_i2c_poll_state_i2c_master(struct qup_i2c_dev *qup)
211	{
212	return qup_i2c_poll_state_mask(qup, QUP_I2C_MAST_GEN, QUP_I2C_MAST_GEN);
213	}
214
215	static int qup_i2c_change_state(struct qup_i2c_dev *qup, u32 state)
216	{
217	if (qup_i2c_poll_state_valid(qup) != 0)
218	return -EIO;
219
220	writel(state, qup->base + QUP_STATE);
221
222	if (qup_i2c_poll_state(qup, state) != 0)
223	return -EIO;
224	return 0;
225	}
226
c4f0c5fb S	227	/**
	228	* qup_i2c_wait_ready - wait for a give number of bytes in tx/rx path
	229	* @qup: The qup_i2c_dev device
	230	* @op: The bit/event to wait on
	231	* @val: value of the bit to wait on, 0 or 1
	232	* @len: The length the bytes to be transferred
	233	*/
	234	static int qup_i2c_wait_ready(struct qup_i2c_dev *qup, int op, bool val,
	235	int len)
10c5a842 BA	236	{
	237	unsigned long timeout;
	238	u32 opflags;
	239	u32 status;
c4f0c5fb	240	u32 shift = __ffs(op);
10c5a842	241
c4f0c5fb S	242	len *= qup->one_byte_t;
	243	/* timeout after a wait of twice the max time */
	244	timeout = jiffies + len * 4;
10c5a842 BA	245
	246	for (;;) {
	247	opflags = readl(qup->base + QUP_OPERATIONAL);
	248	status = readl(qup->base + QUP_I2C_STATUS);
	249
c4f0c5fb S	250	if (((opflags & op) >> shift) == val) {
	251	if (op == QUP_OUT_NOT_EMPTY) {
	252	if (!(status & I2C_STATUS_BUS_ACTIVE))
	253	return 0;
	254	} else {
	255	return 0;
	256	}
	257	}
10c5a842 BA	258
	259	if (time_after(jiffies, timeout))
	260	return -ETIMEDOUT;
	261
c4f0c5fb	262	usleep_range(len, len * 2);
10c5a842 BA	263	}
	264	}
	265
	266	static void qup_i2c_set_write_mode(struct qup_i2c_dev qup, struct i2c_msg msg)
	267	{
	268	/* Number of entries to shift out, including the start */
	269	int total = msg->len + 1;
	270
	271	if (total < qup->out_fifo_sz) {
	272	/* FIFO mode */
	273	writel(QUP_REPACK_EN, qup->base + QUP_IO_MODE);
	274	writel(total, qup->base + QUP_MX_WRITE_CNT);
	275	} else {
	276	/* BLOCK mode (transfer data on chunks) */
	277	writel(QUP_OUTPUT_BLK_MODE \| QUP_REPACK_EN,
	278	qup->base + QUP_IO_MODE);
	279	writel(total, qup->base + QUP_MX_OUTPUT_CNT);
	280	}
	281	}
	282
c4f0c5fb	283	static int qup_i2c_issue_write(struct qup_i2c_dev qup, struct i2c_msg msg)
10c5a842 BA	284	{
	285	u32 addr = msg->addr << 1;
	286	u32 qup_tag;
10c5a842 BA	287	int idx;
10c5a842 BA	288	u32 val;
c4f0c5fb	289	int ret = 0;
10c5a842 BA	290
	291	if (qup->pos == 0) {
	292	val = QUP_TAG_START \| addr;
	293	idx = 1;
	294	} else {
	295	val = 0;
	296	idx = 0;
	297	}
	298
	299	while (qup->pos < msg->len) {
	300	/* Check that there's space in the FIFO for our pair */
c4f0c5fb S	301	ret = qup_i2c_wait_ready(qup, QUP_OUT_FULL, RESET_BIT,
	302	4 * ONE_BYTE);
	303	if (ret)
	304	return ret;
10c5a842 BA	305
	306	if (qup->pos == msg->len - 1)
	307	qup_tag = QUP_TAG_STOP;
	308	else
	309	qup_tag = QUP_TAG_DATA;
	310
	311	if (idx & 1)
	312	val \|= (qup_tag \| msg->buf[qup->pos]) << QUP_MSW_SHIFT;
	313	else
	314	val = qup_tag \| msg->buf[qup->pos];
	315
	316	/* Write out the pair and the last odd value */
	317	if (idx & 1 \|\| qup->pos == msg->len - 1)
	318	writel(val, qup->base + QUP_OUT_FIFO_BASE);
	319
	320	qup->pos++;
	321	idx++;
	322	}
c4f0c5fb S	323
c4f0c5fb S	324	return ret;
10c5a842 BA	325	}
	326
	327	static int qup_i2c_write_one(struct qup_i2c_dev qup, struct i2c_msg msg)
	328	{
	329	unsigned long left;
	330	int ret;
	331
	332	qup->msg = msg;
	333	qup->pos = 0;
	334
	335	enable_irq(qup->irq);
	336
	337	qup_i2c_set_write_mode(qup, msg);
	338
	339	ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
	340	if (ret)
	341	goto err;
	342
	343	writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
	344
	345	do {
	346	ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
	347	if (ret)
	348	goto err;
	349
c4f0c5fb S	350	ret = qup_i2c_issue_write(qup, msg);
	351	if (ret)
	352	goto err;
10c5a842 BA	353
	354	ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
	355	if (ret)
	356	goto err;
	357
	358	left = wait_for_completion_timeout(&qup->xfer, HZ);
	359	if (!left) {
	360	writel(1, qup->base + QUP_SW_RESET);
	361	ret = -ETIMEDOUT;
	362	goto err;
	363	}
	364
	365	if (qup->bus_err \|\| qup->qup_err) {
	366	if (qup->bus_err & QUP_I2C_NACK_FLAG)
	367	dev_err(qup->dev, "NACK from %x\n", msg->addr);
	368	ret = -EIO;
	369	goto err;
	370	}
	371	} while (qup->pos < msg->len);
	372
	373	/* Wait for the outstanding data in the fifo to drain */
c4f0c5fb	374	ret = qup_i2c_wait_ready(qup, QUP_OUT_NOT_EMPTY, RESET_BIT, ONE_BYTE);
10c5a842 BA	375
	376	err:
	377	disable_irq(qup->irq);
	378	qup->msg = NULL;
	379
	380	return ret;
	381	}
	382
	383	static void qup_i2c_set_read_mode(struct qup_i2c_dev *qup, int len)
	384	{
	385	if (len < qup->in_fifo_sz) {
	386	/* FIFO mode */
	387	writel(QUP_REPACK_EN, qup->base + QUP_IO_MODE);
	388	writel(len, qup->base + QUP_MX_READ_CNT);
	389	} else {
	390	/* BLOCK mode (transfer data on chunks) */
	391	writel(QUP_INPUT_BLK_MODE \| QUP_REPACK_EN,
	392	qup->base + QUP_IO_MODE);
	393	writel(len, qup->base + QUP_MX_INPUT_CNT);
	394	}
	395	}
	396
	397	static void qup_i2c_issue_read(struct qup_i2c_dev qup, struct i2c_msg msg)
	398	{
	399	u32 addr, len, val;
	400
	401	addr = (msg->addr << 1) \| 1;
	402
	403	/* 0 is used to specify a length 256 (QUP_READ_LIMIT) */
	404	len = (msg->len == QUP_READ_LIMIT) ? 0 : msg->len;
	405
	406	val = ((QUP_TAG_REC \| len) << QUP_MSW_SHIFT) \| QUP_TAG_START \| addr;
	407	writel(val, qup->base + QUP_OUT_FIFO_BASE);
	408	}
	409
	410
c4f0c5fb	411	static int qup_i2c_read_fifo(struct qup_i2c_dev qup, struct i2c_msg msg)
10c5a842	412	{
10c5a842 BA	413	u32 val = 0;
10c5a842 BA	414	int idx;
c4f0c5fb	415	int ret = 0;
10c5a842 BA	416
	417	for (idx = 0; qup->pos < msg->len; idx++) {
	418	if ((idx & 1) == 0) {
	419	/* Check that FIFO have data */
c4f0c5fb S	420	ret = qup_i2c_wait_ready(qup, QUP_IN_NOT_EMPTY,
	421	SET_BIT, 4 * ONE_BYTE);
	422	if (ret)
	423	return ret;
10c5a842 BA	424
	425	/* Reading 2 words at time */
	426	val = readl(qup->base + QUP_IN_FIFO_BASE);
	427
	428	msg->buf[qup->pos++] = val & 0xFF;
	429	} else {
	430	msg->buf[qup->pos++] = val >> QUP_MSW_SHIFT;
	431	}
	432	}
c4f0c5fb S	433
c4f0c5fb S	434	return ret;
10c5a842 BA	435	}
	436
	437	static int qup_i2c_read_one(struct qup_i2c_dev qup, struct i2c_msg msg)
	438	{
	439	unsigned long left;
	440	int ret;
	441
10c5a842 BA	442	qup->msg = msg;
	443	qup->pos = 0;
	444
	445	enable_irq(qup->irq);
	446
	447	qup_i2c_set_read_mode(qup, msg->len);
	448
	449	ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
	450	if (ret)
	451	goto err;
	452
	453	writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
	454
	455	ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
	456	if (ret)
	457	goto err;
	458
	459	qup_i2c_issue_read(qup, msg);
	460
	461	ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
	462	if (ret)
	463	goto err;
	464
	465	do {
	466	left = wait_for_completion_timeout(&qup->xfer, HZ);
	467	if (!left) {
	468	writel(1, qup->base + QUP_SW_RESET);
	469	ret = -ETIMEDOUT;
	470	goto err;
	471	}
	472
	473	if (qup->bus_err \|\| qup->qup_err) {
	474	if (qup->bus_err & QUP_I2C_NACK_FLAG)
	475	dev_err(qup->dev, "NACK from %x\n", msg->addr);
	476	ret = -EIO;
	477	goto err;
	478	}
	479
c4f0c5fb S	480	ret = qup_i2c_read_fifo(qup, msg);
	481	if (ret)
	482	goto err;
10c5a842 BA	483	} while (qup->pos < msg->len);
	484
	485	err:
	486	disable_irq(qup->irq);
	487	qup->msg = NULL;
	488
	489	return ret;
	490	}
	491
	492	static int qup_i2c_xfer(struct i2c_adapter *adap,
	493	struct i2c_msg msgs[],
	494	int num)
	495	{
	496	struct qup_i2c_dev *qup = i2c_get_adapdata(adap);
	497	int ret, idx;
	498
	499	ret = pm_runtime_get_sync(qup->dev);
fa01d096	500	if (ret < 0)
10c5a842 BA	501	goto out;
	502
	503	writel(1, qup->base + QUP_SW_RESET);
	504	ret = qup_i2c_poll_state(qup, QUP_RESET_STATE);
	505	if (ret)
	506	goto out;
	507
	508	/* Configure QUP as I2C mini core */
	509	writel(I2C_MINI_CORE \| I2C_N_VAL, qup->base + QUP_CONFIG);
	510
	511	for (idx = 0; idx < num; idx++) {
	512	if (msgs[idx].len == 0) {
	513	ret = -EINVAL;
	514	goto out;
	515	}
	516
	517	if (qup_i2c_poll_state_i2c_master(qup)) {
	518	ret = -EIO;
	519	goto out;
	520	}
	521
	522	if (msgs[idx].flags & I2C_M_RD)
	523	ret = qup_i2c_read_one(qup, &msgs[idx]);
	524	else
	525	ret = qup_i2c_write_one(qup, &msgs[idx]);
	526
	527	if (ret)
	528	break;
	529
	530	ret = qup_i2c_change_state(qup, QUP_RESET_STATE);
	531	if (ret)
	532	break;
	533	}
	534
	535	if (ret == 0)
	536	ret = num;
	537	out:
	538
	539	pm_runtime_mark_last_busy(qup->dev);
	540	pm_runtime_put_autosuspend(qup->dev);
	541
	542	return ret;
	543	}
	544
	545	static u32 qup_i2c_func(struct i2c_adapter *adap)
	546	{
	547	return I2C_FUNC_I2C \| (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
	548	}
	549
	550	static const struct i2c_algorithm qup_i2c_algo = {
	551	.master_xfer = qup_i2c_xfer,
	552	.functionality = qup_i2c_func,
	553	};
	554
994647db WS	555	/*
	556	* The QUP block will issue a NACK and STOP on the bus when reaching
	557	* the end of the read, the length of the read is specified as one byte
	558	* which limits the possible read to 256 (QUP_READ_LIMIT) bytes.
	559	*/
	560	static struct i2c_adapter_quirks qup_i2c_quirks = {
	561	.max_read_len = QUP_READ_LIMIT,
	562	};
	563
10c5a842 BA	564	static void qup_i2c_enable_clocks(struct qup_i2c_dev *qup)
	565	{
	566	clk_prepare_enable(qup->clk);
	567	clk_prepare_enable(qup->pclk);
	568	}
	569
	570	static void qup_i2c_disable_clocks(struct qup_i2c_dev *qup)
	571	{
	572	u32 config;
	573
	574	qup_i2c_change_state(qup, QUP_RESET_STATE);
	575	clk_disable_unprepare(qup->clk);
	576	config = readl(qup->base + QUP_CONFIG);
	577	config \|= QUP_CLOCK_AUTO_GATE;
	578	writel(config, qup->base + QUP_CONFIG);
	579	clk_disable_unprepare(qup->pclk);
	580	}
	581
	582	static int qup_i2c_probe(struct platform_device *pdev)
	583	{
	584	static const int blk_sizes[] = {4, 16, 32};
	585	struct device_node *node = pdev->dev.of_node;
	586	struct qup_i2c_dev *qup;
	587	unsigned long one_bit_t;
	588	struct resource *res;
	589	u32 io_mode, hw_ver, size;
	590	int ret, fs_div, hs_div;
	591	int src_clk_freq;
cf23e335	592	u32 clk_freq = 100000;
10c5a842 BA	593
	594	qup = devm_kzalloc(&pdev->dev, sizeof(*qup), GFP_KERNEL);
	595	if (!qup)
	596	return -ENOMEM;
	597
	598	qup->dev = &pdev->dev;
	599	init_completion(&qup->xfer);
	600	platform_set_drvdata(pdev, qup);
	601
	602	of_property_read_u32(node, "clock-frequency", &clk_freq);
	603
	604	/* We support frequencies up to FAST Mode (400KHz) */
	605	if (!clk_freq \|\| clk_freq > 400000) {
	606	dev_err(qup->dev, "clock frequency not supported %d\n",
	607	clk_freq);
	608	return -EINVAL;
	609	}
	610
	611	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	612	qup->base = devm_ioremap_resource(qup->dev, res);
	613	if (IS_ERR(qup->base))
	614	return PTR_ERR(qup->base);
	615
	616	qup->irq = platform_get_irq(pdev, 0);
	617	if (qup->irq < 0) {
	618	dev_err(qup->dev, "No IRQ defined\n");
	619	return qup->irq;
	620	}
	621
	622	qup->clk = devm_clk_get(qup->dev, "core");
	623	if (IS_ERR(qup->clk)) {
	624	dev_err(qup->dev, "Could not get core clock\n");
	625	return PTR_ERR(qup->clk);
	626	}
	627
	628	qup->pclk = devm_clk_get(qup->dev, "iface");
	629	if (IS_ERR(qup->pclk)) {
	630	dev_err(qup->dev, "Could not get iface clock\n");
	631	return PTR_ERR(qup->pclk);
	632	}
	633
	634	qup_i2c_enable_clocks(qup);
	635
	636	/*
	637	* Bootloaders might leave a pending interrupt on certain QUP's,
	638	* so we reset the core before registering for interrupts.
	639	*/
	640	writel(1, qup->base + QUP_SW_RESET);
	641	ret = qup_i2c_poll_state_valid(qup);
	642	if (ret)
	643	goto fail;
	644
	645	ret = devm_request_irq(qup->dev, qup->irq, qup_i2c_interrupt,
	646	IRQF_TRIGGER_HIGH, "i2c_qup", qup);
	647	if (ret) {
	648	dev_err(qup->dev, "Request %d IRQ failed\n", qup->irq);
	649	goto fail;
	650	}
	651	disable_irq(qup->irq);
	652
	653	hw_ver = readl(qup->base + QUP_HW_VERSION);
	654	dev_dbg(qup->dev, "Revision %x\n", hw_ver);
	655
	656	io_mode = readl(qup->base + QUP_IO_MODE);
657
658	/*
659	* The block/fifo size w.r.t. 'actual data' is 1/2 due to 'tag'
660	* associated with each byte written/received
661	*/
662	size = QUP_OUTPUT_BLOCK_SIZE(io_mode);
3cf357df PG	663	if (size >= ARRAY_SIZE(blk_sizes)) {
	664	ret = -EIO;
	665	goto fail;
	666	}
10c5a842 BA	667	qup->out_blk_sz = blk_sizes[size] / 2;
	668
	669	size = QUP_INPUT_BLOCK_SIZE(io_mode);
3cf357df PG	670	if (size >= ARRAY_SIZE(blk_sizes)) {
	671	ret = -EIO;
	672	goto fail;
	673	}
10c5a842 BA	674	qup->in_blk_sz = blk_sizes[size] / 2;
	675
	676	size = QUP_OUTPUT_FIFO_SIZE(io_mode);
	677	qup->out_fifo_sz = qup->out_blk_sz * (2 << size);
	678
	679	size = QUP_INPUT_FIFO_SIZE(io_mode);
	680	qup->in_fifo_sz = qup->in_blk_sz * (2 << size);
	681
	682	src_clk_freq = clk_get_rate(qup->clk);
	683	fs_div = ((src_clk_freq / clk_freq) / 2) - 3;
	684	hs_div = 3;
	685	qup->clk_ctl = (hs_div << 8) \| (fs_div & 0xff);
	686
	687	/*
	688	* Time it takes for a byte to be clocked out on the bus.
	689	* Each byte takes 9 clock cycles (8 bits + 1 ack).
	690	*/
	691	one_bit_t = (USEC_PER_SEC / clk_freq) + 1;
	692	qup->one_byte_t = one_bit_t * 9;
	693
	694	dev_dbg(qup->dev, "IN:block:%d, fifo:%d, OUT:block:%d, fifo:%d\n",
	695	qup->in_blk_sz, qup->in_fifo_sz,
	696	qup->out_blk_sz, qup->out_fifo_sz);
	697
	698	i2c_set_adapdata(&qup->adap, qup);
	699	qup->adap.algo = &qup_i2c_algo;
994647db	700	qup->adap.quirks = &qup_i2c_quirks;
10c5a842 BA	701	qup->adap.dev.parent = qup->dev;
	702	qup->adap.dev.of_node = pdev->dev.of_node;
	703	strlcpy(qup->adap.name, "QUP I2C adapter", sizeof(qup->adap.name));
	704
10c5a842 BA	705	pm_runtime_set_autosuspend_delay(qup->dev, MSEC_PER_SEC);
	706	pm_runtime_use_autosuspend(qup->dev);
	707	pm_runtime_set_active(qup->dev);
	708	pm_runtime_enable(qup->dev);
86b59bbf AG	709
	710	ret = i2c_add_adapter(&qup->adap);
	711	if (ret)
	712	goto fail_runtime;
	713
10c5a842 BA	714	return 0;
10c5a842 BA	715
86b59bbf AG	716	fail_runtime:
	717	pm_runtime_disable(qup->dev);
	718	pm_runtime_set_suspended(qup->dev);
10c5a842 BA	719	fail:
	720	qup_i2c_disable_clocks(qup);
	721	return ret;
	722	}
	723
	724	static int qup_i2c_remove(struct platform_device *pdev)
	725	{
	726	struct qup_i2c_dev *qup = platform_get_drvdata(pdev);
	727
	728	disable_irq(qup->irq);
	729	qup_i2c_disable_clocks(qup);
	730	i2c_del_adapter(&qup->adap);
	731	pm_runtime_disable(qup->dev);
	732	pm_runtime_set_suspended(qup->dev);
	733	return 0;
	734	}
	735
	736	#ifdef CONFIG_PM
	737	static int qup_i2c_pm_suspend_runtime(struct device *device)
	738	{
	739	struct qup_i2c_dev *qup = dev_get_drvdata(device);
	740
	741	dev_dbg(device, "pm_runtime: suspending...\n");
	742	qup_i2c_disable_clocks(qup);
	743	return 0;
	744	}
	745
	746	static int qup_i2c_pm_resume_runtime(struct device *device)
	747	{
	748	struct qup_i2c_dev *qup = dev_get_drvdata(device);
	749
	750	dev_dbg(device, "pm_runtime: resuming...\n");
	751	qup_i2c_enable_clocks(qup);
	752	return 0;
	753	}
	754	#endif
	755
	756	#ifdef CONFIG_PM_SLEEP
	757	static int qup_i2c_suspend(struct device *device)
	758	{
	759	qup_i2c_pm_suspend_runtime(device);
	760	return 0;
	761	}
	762
	763	static int qup_i2c_resume(struct device *device)
	764	{
	765	qup_i2c_pm_resume_runtime(device);
	766	pm_runtime_mark_last_busy(device);
	767	pm_request_autosuspend(device);
	768	return 0;
	769	}
	770	#endif
	771
	772	static const struct dev_pm_ops qup_i2c_qup_pm_ops = {
	773	SET_SYSTEM_SLEEP_PM_OPS(
	774	qup_i2c_suspend,
	775	qup_i2c_resume)
	776	SET_RUNTIME_PM_OPS(
	777	qup_i2c_pm_suspend_runtime,
	778	qup_i2c_pm_resume_runtime,
	779	NULL)
	780	};
	781
	782	static const struct of_device_id qup_i2c_dt_match[] = {
783	{ .compatible = "qcom,i2c-qup-v1.1.1" },
784	{ .compatible = "qcom,i2c-qup-v2.1.1" },
785	{ .compatible = "qcom,i2c-qup-v2.2.1" },
786	{}
787	};
788	MODULE_DEVICE_TABLE(of, qup_i2c_dt_match);
789
790	static struct platform_driver qup_i2c_driver = {
791	.probe = qup_i2c_probe,
792	.remove = qup_i2c_remove,
793	.driver = {
794	.name = "i2c_qup",
10c5a842 BA	795	.pm = &qup_i2c_qup_pm_ops,
	796	.of_match_table = qup_i2c_dt_match,
	797	},
	798	};
	799
	800	module_platform_driver(qup_i2c_driver);
	801
	802	MODULE_LICENSE("GPL v2");
	803	MODULE_ALIAS("platform:i2c_qup");