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i2c: qup: Add bam dma capabilities
[linux-2.6-block.git] / drivers / i2c / busses / i2c-qup.c
CommitLineData
10c5a842
BA		 1/*
2 * Copyright (c) 2009-2013, The Linux Foundation. All rights reserved.
3 * Copyright (c) 2014, Sony Mobile Communications AB.
4 *
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 and
8 * only version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
9cedf3b2 17#include <linux/atomic.h>
10c5a842
BA		 18#include <linux/clk.h>
19#include <linux/delay.h>
9cedf3b2
S		 20#include <linux/dmaengine.h>
21#include <linux/dmapool.h>
22#include <linux/dma-mapping.h>
10c5a842
BA		 23#include <linux/err.h>
24#include <linux/i2c.h>
25#include <linux/interrupt.h>
26#include <linux/io.h>
27#include <linux/module.h>
28#include <linux/of.h>
29#include <linux/platform_device.h>
30#include <linux/pm_runtime.h>
9cedf3b2 31#include <linux/scatterlist.h>
10c5a842
BA		 32
33/* QUP Registers */
34#define QUP_CONFIG 0x000
35#define QUP_STATE 0x004
36#define QUP_IO_MODE 0x008
37#define QUP_SW_RESET 0x00c
38#define QUP_OPERATIONAL 0x018
39#define QUP_ERROR_FLAGS 0x01c
40#define QUP_ERROR_FLAGS_EN 0x020
9cedf3b2 41#define QUP_OPERATIONAL_MASK 0x028
10c5a842
BA		 42#define QUP_HW_VERSION 0x030
43#define QUP_MX_OUTPUT_CNT 0x100
44#define QUP_OUT_FIFO_BASE 0x110
45#define QUP_MX_WRITE_CNT 0x150
46#define QUP_MX_INPUT_CNT 0x200
47#define QUP_MX_READ_CNT 0x208
48#define QUP_IN_FIFO_BASE 0x218
49#define QUP_I2C_CLK_CTL 0x400
50#define QUP_I2C_STATUS 0x404
191424bb 51#define QUP_I2C_MASTER_GEN 0x408
10c5a842
BA		 52
53/* QUP States and reset values */
54#define QUP_RESET_STATE 0
55#define QUP_RUN_STATE 1
56#define QUP_PAUSE_STATE 3
57#define QUP_STATE_MASK 3
58
59#define QUP_STATE_VALID BIT(2)
60#define QUP_I2C_MAST_GEN BIT(4)
9cedf3b2 61#define QUP_I2C_FLUSH BIT(6)
10c5a842
BA		 62
63#define QUP_OPERATIONAL_RESET 0x000ff0
64#define QUP_I2C_STATUS_RESET 0xfffffc
65
66/* QUP OPERATIONAL FLAGS */
67#define QUP_I2C_NACK_FLAG BIT(3)
68#define QUP_OUT_NOT_EMPTY BIT(4)
69#define QUP_IN_NOT_EMPTY BIT(5)
70#define QUP_OUT_FULL BIT(6)
71#define QUP_OUT_SVC_FLAG BIT(8)
72#define QUP_IN_SVC_FLAG BIT(9)
73#define QUP_MX_OUTPUT_DONE BIT(10)
74#define QUP_MX_INPUT_DONE BIT(11)
75
76/* I2C mini core related values */
77#define QUP_CLOCK_AUTO_GATE BIT(13)
78#define I2C_MINI_CORE (2 << 8)
79#define I2C_N_VAL 15
191424bb
S		 80#define I2C_N_VAL_V2 7
81
10c5a842
BA		 82/* Most significant word offset in FIFO port */
83#define QUP_MSW_SHIFT (I2C_N_VAL + 1)
84
85/* Packing/Unpacking words in FIFOs, and IO modes */
86#define QUP_OUTPUT_BLK_MODE (1 << 10)
9cedf3b2 87#define QUP_OUTPUT_BAM_MODE (3 << 10)
10c5a842 88#define QUP_INPUT_BLK_MODE (1 << 12)
9cedf3b2
S		 89#define QUP_INPUT_BAM_MODE (3 << 12)
90#define QUP_BAM_MODE (QUP_OUTPUT_BAM_MODE | QUP_INPUT_BAM_MODE)
10c5a842
BA		 91#define QUP_UNPACK_EN BIT(14)
92#define QUP_PACK_EN BIT(15)
93
94#define QUP_REPACK_EN (QUP_UNPACK_EN | QUP_PACK_EN)
191424bb 95#define QUP_V2_TAGS_EN 1
10c5a842
BA		 96
97#define QUP_OUTPUT_BLOCK_SIZE(x)(((x) >> 0) & 0x03)
98#define QUP_OUTPUT_FIFO_SIZE(x) (((x) >> 2) & 0x07)
99#define QUP_INPUT_BLOCK_SIZE(x) (((x) >> 5) & 0x03)
100#define QUP_INPUT_FIFO_SIZE(x) (((x) >> 7) & 0x07)
101
102/* QUP tags */
103#define QUP_TAG_START (1 << 8)
104#define QUP_TAG_DATA (2 << 8)
105#define QUP_TAG_STOP (3 << 8)
106#define QUP_TAG_REC (4 << 8)
9cedf3b2
S		 107#define QUP_BAM_INPUT_EOT 0x93
108#define QUP_BAM_FLUSH_STOP 0x96
10c5a842 109
191424bb
S		 110/* QUP v2 tags */
111#define QUP_TAG_V2_START 0x81
112#define QUP_TAG_V2_DATAWR 0x82
113#define QUP_TAG_V2_DATAWR_STOP 0x83
114#define QUP_TAG_V2_DATARD 0x85
115#define QUP_TAG_V2_DATARD_STOP 0x87
116
10c5a842
BA		 117/* Status, Error flags */
118#define I2C_STATUS_WR_BUFFER_FULL BIT(0)
119#define I2C_STATUS_BUS_ACTIVE BIT(8)
120#define I2C_STATUS_ERROR_MASK 0x38000fc
121#define QUP_STATUS_ERROR_FLAGS 0x7c
122
123#define QUP_READ_LIMIT 256
c4f0c5fb
S		 124#define SET_BIT 0x1
125#define RESET_BIT 0x0
126#define ONE_BYTE 0x1
f7418793 127#define QUP_I2C_MX_CONFIG_DURING_RUN BIT(31)
10c5a842 128
9cedf3b2
S		 129#define MX_TX_RX_LEN SZ_64K
130#define MX_BLOCKS (MX_TX_RX_LEN / QUP_READ_LIMIT)
131
132/* Max timeout in ms for 32k bytes */
133#define TOUT_MAX 300
134
191424bb
S		 135struct qup_i2c_block {
136 int count;
137 int pos;
138 int tx_tag_len;
139 int rx_tag_len;
140 int data_len;
141 u8 tags[6];
142};
143
9cedf3b2
S		 144struct qup_i2c_tag {
145 u8 *start;
146 dma_addr_t addr;
147};
148
149struct qup_i2c_bam {
150 struct qup_i2c_tag tag;
151 struct dma_chan *dma;
152 struct scatterlist *sg;
153};
154
10c5a842
BA		 155struct qup_i2c_dev {
156 struct device *dev;
157 void __iomem *base;
158 int irq;
159 struct clk *clk;
160 struct clk *pclk;
161 struct i2c_adapter adap;
162
163 int clk_ctl;
164 int out_fifo_sz;
165 int in_fifo_sz;
166 int out_blk_sz;
167 int in_blk_sz;
168
169 unsigned long one_byte_t;
191424bb 170 struct qup_i2c_block blk;
10c5a842
BA		 171
172 struct i2c_msg *msg;
173 /* Current posion in user message buffer */
174 int pos;
175 /* I2C protocol errors */
176 u32 bus_err;
177 /* QUP core errors */
178 u32 qup_err;
179
f7418793
S		 180 /* To check if this is the last msg */
181 bool is_last;
182
183 /* To configure when bus is in run state */
184 int config_run;
185
9cedf3b2
S		 186 /* dma parameters */
187 bool is_dma;
188 struct dma_pool *dpool;
189 struct qup_i2c_tag start_tag;
190 struct qup_i2c_bam brx;
191 struct qup_i2c_bam btx;
192
10c5a842
BA		 193 struct completion xfer;
194};
195
196static irqreturn_t qup_i2c_interrupt(int irq, void *dev)
197{
198 struct qup_i2c_dev *qup = dev;
199 u32 bus_err;
200 u32 qup_err;
201 u32 opflags;
202
203 bus_err = readl(qup->base + QUP_I2C_STATUS);
204 qup_err = readl(qup->base + QUP_ERROR_FLAGS);
205 opflags = readl(qup->base + QUP_OPERATIONAL);
206
207 if (!qup->msg) {
208 /* Clear Error interrupt */
209 writel(QUP_RESET_STATE, qup->base + QUP_STATE);
210 return IRQ_HANDLED;
211 }
212
213 bus_err &= I2C_STATUS_ERROR_MASK;
214 qup_err &= QUP_STATUS_ERROR_FLAGS;
215
216 if (qup_err) {
217 /* Clear Error interrupt */
218 writel(qup_err, qup->base + QUP_ERROR_FLAGS);
219 goto done;
220 }
221
222 if (bus_err) {
223 /* Clear Error interrupt */
224 writel(QUP_RESET_STATE, qup->base + QUP_STATE);
225 goto done;
226 }
227
228 if (opflags & QUP_IN_SVC_FLAG)
229 writel(QUP_IN_SVC_FLAG, qup->base + QUP_OPERATIONAL);
230
231 if (opflags & QUP_OUT_SVC_FLAG)
232 writel(QUP_OUT_SVC_FLAG, qup->base + QUP_OPERATIONAL);
233
234done:
235 qup->qup_err = qup_err;
236 qup->bus_err = bus_err;
237 complete(&qup->xfer);
238 return IRQ_HANDLED;
239}
240
241static int qup_i2c_poll_state_mask(struct qup_i2c_dev *qup,
242 u32 req_state, u32 req_mask)
243{
244 int retries = 1;
245 u32 state;
246
247 /*
248 * State transition takes 3 AHB clocks cycles + 3 I2C master clock
249 * cycles. So retry once after a 1uS delay.
250 */
251 do {
252 state = readl(qup->base + QUP_STATE);
253
254 if (state & QUP_STATE_VALID &&
255 (state & req_mask) == req_state)
256 return 0;
257
258 udelay(1);
259 } while (retries--);
260
261 return -ETIMEDOUT;
262}
263
264static int qup_i2c_poll_state(struct qup_i2c_dev *qup, u32 req_state)
265{
266 return qup_i2c_poll_state_mask(qup, req_state, QUP_STATE_MASK);
267}
268
9cedf3b2
S		 269static void qup_i2c_flush(struct qup_i2c_dev *qup)
270{
271 u32 val = readl(qup->base + QUP_STATE);
272
273 val |= QUP_I2C_FLUSH;
274 writel(val, qup->base + QUP_STATE);
275}
276
10c5a842
BA		 277static int qup_i2c_poll_state_valid(struct qup_i2c_dev *qup)
278{
279 return qup_i2c_poll_state_mask(qup, 0, 0);
280}
281
282static int qup_i2c_poll_state_i2c_master(struct qup_i2c_dev *qup)
283{
284 return qup_i2c_poll_state_mask(qup, QUP_I2C_MAST_GEN, QUP_I2C_MAST_GEN);
285}
286
287static int qup_i2c_change_state(struct qup_i2c_dev *qup, u32 state)
288{
289 if (qup_i2c_poll_state_valid(qup) != 0)
290 return -EIO;
291
292 writel(state, qup->base + QUP_STATE);
293
294 if (qup_i2c_poll_state(qup, state) != 0)
295 return -EIO;
296 return 0;
297}
298
c4f0c5fb
S		 299/**
300 * qup_i2c_wait_ready - wait for a give number of bytes in tx/rx path
301 * @qup: The qup_i2c_dev device
302 * @op: The bit/event to wait on
303 * @val: value of the bit to wait on, 0 or 1
304 * @len: The length the bytes to be transferred
305 */
306static int qup_i2c_wait_ready(struct qup_i2c_dev *qup, int op, bool val,
307 int len)
10c5a842
BA		 308{
309 unsigned long timeout;
310 u32 opflags;
311 u32 status;
c4f0c5fb 312 u32 shift = __ffs(op);
10c5a842 313
c4f0c5fb
S		 314 len *= qup->one_byte_t;
315 /* timeout after a wait of twice the max time */
316 timeout = jiffies + len * 4;
10c5a842
BA		 317
318 for (;;) {
319 opflags = readl(qup->base + QUP_OPERATIONAL);
320 status = readl(qup->base + QUP_I2C_STATUS);
321
c4f0c5fb 322 if (((opflags & op) >> shift) == val) {
f7418793 323 if ((op == QUP_OUT_NOT_EMPTY) && qup->is_last) {
c4f0c5fb
S		 324 if (!(status & I2C_STATUS_BUS_ACTIVE))
325 return 0;
326 } else {
327 return 0;
328 }
329 }
10c5a842
BA		 330
331 if (time_after(jiffies, timeout))
332 return -ETIMEDOUT;
333
c4f0c5fb 334 usleep_range(len, len * 2);
10c5a842
BA		 335 }
336}
337
191424bb
S		 338static void qup_i2c_set_write_mode_v2(struct qup_i2c_dev *qup,
339 struct i2c_msg *msg)
340{
341 /* Number of entries to shift out, including the tags */
342 int total = msg->len + qup->blk.tx_tag_len;
343
f7418793
S		 344 total |= qup->config_run;
345
191424bb
S		 346 if (total < qup->out_fifo_sz) {
347 /* FIFO mode */
348 writel(QUP_REPACK_EN, qup->base + QUP_IO_MODE);
349 writel(total, qup->base + QUP_MX_WRITE_CNT);
350 } else {
351 /* BLOCK mode (transfer data on chunks) */
352 writel(QUP_OUTPUT_BLK_MODE | QUP_REPACK_EN,
353 qup->base + QUP_IO_MODE);
354 writel(total, qup->base + QUP_MX_OUTPUT_CNT);
355 }
356}
357
10c5a842
BA		 358static void qup_i2c_set_write_mode(struct qup_i2c_dev *qup, struct i2c_msg *msg)
359{
360 /* Number of entries to shift out, including the start */
361 int total = msg->len + 1;
362
363 if (total < qup->out_fifo_sz) {
364 /* FIFO mode */
365 writel(QUP_REPACK_EN, qup->base + QUP_IO_MODE);
366 writel(total, qup->base + QUP_MX_WRITE_CNT);
367 } else {
368 /* BLOCK mode (transfer data on chunks) */
369 writel(QUP_OUTPUT_BLK_MODE | QUP_REPACK_EN,
370 qup->base + QUP_IO_MODE);
371 writel(total, qup->base + QUP_MX_OUTPUT_CNT);
372 }
373}
374
c4f0c5fb 375static int qup_i2c_issue_write(struct qup_i2c_dev *qup, struct i2c_msg *msg)
10c5a842
BA		 376{
377 u32 addr = msg->addr << 1;
378 u32 qup_tag;
10c5a842
BA		 379 int idx;
380 u32 val;
c4f0c5fb 381 int ret = 0;
10c5a842
BA		 382
383 if (qup->pos == 0) {
384 val = QUP_TAG_START | addr;
385 idx = 1;
386 } else {
387 val = 0;
388 idx = 0;
389 }
390
391 while (qup->pos < msg->len) {
392 /* Check that there's space in the FIFO for our pair */
c4f0c5fb
S		 393 ret = qup_i2c_wait_ready(qup, QUP_OUT_FULL, RESET_BIT,
394 4 * ONE_BYTE);
395 if (ret)
396 return ret;
10c5a842
BA		 397
398 if (qup->pos == msg->len - 1)
399 qup_tag = QUP_TAG_STOP;
400 else
401 qup_tag = QUP_TAG_DATA;
402
403 if (idx & 1)
404 val |= (qup_tag | msg->buf[qup->pos]) << QUP_MSW_SHIFT;
405 else
406 val = qup_tag | msg->buf[qup->pos];
407
408 /* Write out the pair and the last odd value */
409 if (idx & 1 || qup->pos == msg->len - 1)
410 writel(val, qup->base + QUP_OUT_FIFO_BASE);
411
412 qup->pos++;
413 idx++;
414 }
c4f0c5fb
S		 415
416 return ret;
10c5a842
BA		 417}
418
191424bb
S		 419static void qup_i2c_set_blk_data(struct qup_i2c_dev *qup,
420 struct i2c_msg *msg)
421{
422 memset(&qup->blk, 0, sizeof(qup->blk));
423
424 qup->blk.data_len = msg->len;
425 qup->blk.count = (msg->len + QUP_READ_LIMIT - 1) / QUP_READ_LIMIT;
426
427 /* 4 bytes for first block and 2 writes for rest */
428 qup->blk.tx_tag_len = 4 + (qup->blk.count - 1) * 2;
429
430 /* There are 2 tag bytes that are read in to fifo for every block */
431 if (msg->flags & I2C_M_RD)
432 qup->blk.rx_tag_len = qup->blk.count * 2;
433}
434
435static int qup_i2c_send_data(struct qup_i2c_dev *qup, int tlen, u8 *tbuf,
436 int dlen, u8 *dbuf)
437{
438 u32 val = 0, idx = 0, pos = 0, i = 0, t;
439 int len = tlen + dlen;
440 u8 *buf = tbuf;
441 int ret = 0;
442
443 while (len > 0) {
444 ret = qup_i2c_wait_ready(qup, QUP_OUT_FULL,
445 RESET_BIT, 4 * ONE_BYTE);
446 if (ret) {
447 dev_err(qup->dev, "timeout for fifo out full");
448 return ret;
449 }
450
451 t = (len >= 4) ? 4 : len;
452
453 while (idx < t) {
454 if (!i && (pos >= tlen)) {
455 buf = dbuf;
456 pos = 0;
457 i = 1;
458 }
459 val |= buf[pos++] << (idx++ * 8);
460 }
461
462 writel(val, qup->base + QUP_OUT_FIFO_BASE);
463 idx = 0;
464 val = 0;
465 len -= 4;
466 }
467
468 return ret;
469}
470
471static int qup_i2c_get_data_len(struct qup_i2c_dev *qup)
472{
473 int data_len;
474
475 if (qup->blk.data_len > QUP_READ_LIMIT)
476 data_len = QUP_READ_LIMIT;
477 else
478 data_len = qup->blk.data_len;
479
480 return data_len;
481}
482
483static int qup_i2c_set_tags(u8 *tags, struct qup_i2c_dev *qup,
9cedf3b2 484 struct i2c_msg *msg, int is_dma)
191424bb
S		 485{
486 u16 addr = (msg->addr << 1) | ((msg->flags & I2C_M_RD) == I2C_M_RD);
487 int len = 0;
488 int data_len;
489
9cedf3b2
S		 490 int last = (qup->blk.pos == (qup->blk.count - 1)) && (qup->is_last);
491
191424bb
S		 492 if (qup->blk.pos == 0) {
493 tags[len++] = QUP_TAG_V2_START;
494 tags[len++] = addr & 0xff;
495
496 if (msg->flags & I2C_M_TEN)
497 tags[len++] = addr >> 8;
498 }
499
500 /* Send _STOP commands for the last block */
9cedf3b2 501 if (last) {
191424bb
S		 502 if (msg->flags & I2C_M_RD)
503 tags[len++] = QUP_TAG_V2_DATARD_STOP;
504 else
505 tags[len++] = QUP_TAG_V2_DATAWR_STOP;
506 } else {
507 if (msg->flags & I2C_M_RD)
508 tags[len++] = QUP_TAG_V2_DATARD;
509 else
510 tags[len++] = QUP_TAG_V2_DATAWR;
511 }
512
513 data_len = qup_i2c_get_data_len(qup);
514
515 /* 0 implies 256 bytes */
516 if (data_len == QUP_READ_LIMIT)
517 tags[len++] = 0;
518 else
519 tags[len++] = data_len;
520
9cedf3b2
S		 521 if ((msg->flags & I2C_M_RD) && last && is_dma) {
522 tags[len++] = QUP_BAM_INPUT_EOT;
523 tags[len++] = QUP_BAM_FLUSH_STOP;
524 }
525
191424bb
S		 526 return len;
527}
528
529static int qup_i2c_issue_xfer_v2(struct qup_i2c_dev *qup, struct i2c_msg *msg)
530{
531 int data_len = 0, tag_len, index;
532 int ret;
533
9cedf3b2 534 tag_len = qup_i2c_set_tags(qup->blk.tags, qup, msg, 0);
191424bb
S		 535 index = msg->len - qup->blk.data_len;
536
537 /* only tags are written for read */
538 if (!(msg->flags & I2C_M_RD))
539 data_len = qup_i2c_get_data_len(qup);
540
541 ret = qup_i2c_send_data(qup, tag_len, qup->blk.tags,
542 data_len, &msg->buf[index]);
543 qup->blk.data_len -= data_len;
544
545 return ret;
546}
547
9cedf3b2
S		 548static void qup_i2c_bam_cb(void *data)
549{
550 struct qup_i2c_dev *qup = data;
551
552 complete(&qup->xfer);
553}
554
555static int qup_sg_set_buf(struct scatterlist *sg, void *buf,
556 struct qup_i2c_tag *tg, unsigned int buflen,
557 struct qup_i2c_dev *qup, int map, int dir)
558{
559 int ret;
560
561 sg_set_buf(sg, buf, buflen);
562 ret = dma_map_sg(qup->dev, sg, 1, dir);
563 if (!ret)
564 return -EINVAL;
565
566 if (!map)
567 sg_dma_address(sg) = tg->addr + ((u8 *)buf - tg->start);
568
569 return 0;
570}
571
572static void qup_i2c_rel_dma(struct qup_i2c_dev *qup)
573{
574 if (qup->btx.dma)
575 dma_release_channel(qup->btx.dma);
576 if (qup->brx.dma)
577 dma_release_channel(qup->brx.dma);
578 qup->btx.dma = NULL;
579 qup->brx.dma = NULL;
580}
581
582static int qup_i2c_req_dma(struct qup_i2c_dev *qup)
583{
584 int err;
585
586 if (!qup->btx.dma) {
587 qup->btx.dma = dma_request_slave_channel_reason(qup->dev, "tx");
588 if (IS_ERR(qup->btx.dma)) {
589 err = PTR_ERR(qup->btx.dma);
590 qup->btx.dma = NULL;
591 dev_err(qup->dev, "\n tx channel not available");
592 return err;
593 }
594 }
595
596 if (!qup->brx.dma) {
597 qup->brx.dma = dma_request_slave_channel_reason(qup->dev, "rx");
598 if (IS_ERR(qup->brx.dma)) {
599 dev_err(qup->dev, "\n rx channel not available");
600 err = PTR_ERR(qup->brx.dma);
601 qup->brx.dma = NULL;
602 qup_i2c_rel_dma(qup);
603 return err;
604 }
605 }
606 return 0;
607}
608
609static int qup_i2c_bam_do_xfer(struct qup_i2c_dev *qup, struct i2c_msg *msg,
610 int num)
611{
612 struct dma_async_tx_descriptor *txd, *rxd = NULL;
613 int ret = 0, idx = 0, limit = QUP_READ_LIMIT;
614 dma_cookie_t cookie_rx, cookie_tx;
615 u32 rx_nents = 0, tx_nents = 0, len, blocks, rem;
616 u32 i, tlen, tx_len, tx_buf = 0, rx_buf = 0, off = 0;
617 u8 *tags;
618
619 while (idx < num) {
620 blocks = (msg->len + limit) / limit;
621 rem = msg->len % limit;
622 tx_len = 0, len = 0, i = 0;
623
624 qup->is_last = (idx == (num - 1));
625
626 qup_i2c_set_blk_data(qup, msg);
627
628 if (msg->flags & I2C_M_RD) {
629 rx_nents += (blocks * 2) + 1;
630 tx_nents += 1;
631
632 while (qup->blk.pos < blocks) {
633 /* length set to '0' implies 256 bytes */
634 tlen = (i == (blocks - 1)) ? rem : 0;
635 tags = &qup->start_tag.start[off + len];
636 len += qup_i2c_set_tags(tags, qup, msg, 1);
637
638 /* scratch buf to read the start and len tags */
639 ret = qup_sg_set_buf(&qup->brx.sg[rx_buf++],
640 &qup->brx.tag.start[0],
641 &qup->brx.tag,
642 2, qup, 0, 0);
643
644 if (ret)
645 return ret;
646
647 ret = qup_sg_set_buf(&qup->brx.sg[rx_buf++],
648 &msg->buf[limit * i],
649 NULL, tlen, qup,
650 1, DMA_FROM_DEVICE);
651 if (ret)
652 return ret;
653
654 i++;
655 qup->blk.pos = i;
656 }
657 ret = qup_sg_set_buf(&qup->btx.sg[tx_buf++],
658 &qup->start_tag.start[off],
659 &qup->start_tag, len, qup, 0, 0);
660 if (ret)
661 return ret;
662
663 off += len;
664 /* scratch buf to read the BAM EOT and FLUSH tags */
665 ret = qup_sg_set_buf(&qup->brx.sg[rx_buf++],
666 &qup->brx.tag.start[0],
667 &qup->brx.tag, 2,
668 qup, 0, 0);
669 if (ret)
670 return ret;
671 } else {
672 tx_nents += (blocks * 2);
673
674 while (qup->blk.pos < blocks) {
675 tlen = (i == (blocks - 1)) ? rem : 0;
676 tags = &qup->start_tag.start[off + tx_len];
677 len = qup_i2c_set_tags(tags, qup, msg, 1);
678
679 ret = qup_sg_set_buf(&qup->btx.sg[tx_buf++],
680 tags,
681 &qup->start_tag, len,
682 qup, 0, 0);
683 if (ret)
684 return ret;
685
686 tx_len += len;
687 ret = qup_sg_set_buf(&qup->btx.sg[tx_buf++],
688 &msg->buf[limit * i],
689 NULL, tlen, qup, 1,
690 DMA_TO_DEVICE);
691 if (ret)
692 return ret;
693 i++;
694 qup->blk.pos = i;
695 }
696 off += tx_len;
697
698 if (idx == (num - 1)) {
699 len = 1;
700 if (rx_nents) {
701 qup->btx.tag.start[0] =
702 QUP_BAM_INPUT_EOT;
703 len++;
704 }
705 qup->btx.tag.start[len - 1] =
706 QUP_BAM_FLUSH_STOP;
707 ret = qup_sg_set_buf(&qup->btx.sg[tx_buf++],
708 &qup->btx.tag.start[0],
709 &qup->btx.tag, len,
710 qup, 0, 0);
711 if (ret)
712 return ret;
713 tx_nents += 1;
714 }
715 }
716 idx++;
717 msg++;
718 }
719
720 txd = dmaengine_prep_slave_sg(qup->btx.dma, qup->btx.sg, tx_nents,
721 DMA_MEM_TO_DEV,
722 DMA_PREP_INTERRUPT | DMA_PREP_FENCE);
723 if (!txd) {
724 dev_err(qup->dev, "failed to get tx desc\n");
725 ret = -EINVAL;
726 goto desc_err;
727 }
728
729 if (!rx_nents) {
730 txd->callback = qup_i2c_bam_cb;
731 txd->callback_param = qup;
732 }
733
734 cookie_tx = dmaengine_submit(txd);
735 if (dma_submit_error(cookie_tx)) {
736 ret = -EINVAL;
737 goto desc_err;
738 }
739
740 dma_async_issue_pending(qup->btx.dma);
741
742 if (rx_nents) {
743 rxd = dmaengine_prep_slave_sg(qup->brx.dma, qup->brx.sg,
744 rx_nents, DMA_DEV_TO_MEM,
745 DMA_PREP_INTERRUPT);
746 if (!rxd) {
747 dev_err(qup->dev, "failed to get rx desc\n");
748 ret = -EINVAL;
749
750 /* abort TX descriptors */
751 dmaengine_terminate_all(qup->btx.dma);
752 goto desc_err;
753 }
754
755 rxd->callback = qup_i2c_bam_cb;
756 rxd->callback_param = qup;
757 cookie_rx = dmaengine_submit(rxd);
758 if (dma_submit_error(cookie_rx)) {
759 ret = -EINVAL;
760 goto desc_err;
761 }
762
763 dma_async_issue_pending(qup->brx.dma);
764 }
765
766 if (!wait_for_completion_timeout(&qup->xfer, TOUT_MAX * HZ)) {
767 dev_err(qup->dev, "normal trans timed out\n");
768 ret = -ETIMEDOUT;
769 }
770
771 if (ret || qup->bus_err || qup->qup_err) {
772 if (qup->bus_err & QUP_I2C_NACK_FLAG) {
773 msg--;
774 dev_err(qup->dev, "NACK from %x\n", msg->addr);
775 ret = -EIO;
776
777 if (qup_i2c_change_state(qup, QUP_RUN_STATE)) {
778 dev_err(qup->dev, "change to run state timed out");
779 return ret;
780 }
781
782 if (rx_nents)
783 writel(QUP_BAM_INPUT_EOT,
784 qup->base + QUP_OUT_FIFO_BASE);
785
786 writel(QUP_BAM_FLUSH_STOP,
787 qup->base + QUP_OUT_FIFO_BASE);
788
789 qup_i2c_flush(qup);
790
791 /* wait for remaining interrupts to occur */
792 if (!wait_for_completion_timeout(&qup->xfer, HZ))
793 dev_err(qup->dev, "flush timed out\n");
794
795 qup_i2c_rel_dma(qup);
796 }
797 }
798
799 dma_unmap_sg(qup->dev, qup->btx.sg, tx_nents, DMA_TO_DEVICE);
800
801 if (rx_nents)
802 dma_unmap_sg(qup->dev, qup->brx.sg, rx_nents,
803 DMA_FROM_DEVICE);
804desc_err:
805 return ret;
806}
807
808static int qup_i2c_bam_xfer(struct i2c_adapter *adap, struct i2c_msg *msg,
809 int num)
810{
811 struct qup_i2c_dev *qup = i2c_get_adapdata(adap);
812 int ret = 0;
813
814 enable_irq(qup->irq);
815 ret = qup_i2c_req_dma(qup);
816
817 if (ret)
818 goto out;
819
820 qup->bus_err = 0;
821 qup->qup_err = 0;
822
823 writel(0, qup->base + QUP_MX_INPUT_CNT);
824 writel(0, qup->base + QUP_MX_OUTPUT_CNT);
825
826 /* set BAM mode */
827 writel(QUP_REPACK_EN | QUP_BAM_MODE, qup->base + QUP_IO_MODE);
828
829 /* mask fifo irqs */
830 writel((0x3 << 8), qup->base + QUP_OPERATIONAL_MASK);
831
832 /* set RUN STATE */
833 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
834 if (ret)
835 goto out;
836
837 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
838
839 qup->msg = msg;
840 ret = qup_i2c_bam_do_xfer(qup, qup->msg, num);
841out:
842 disable_irq(qup->irq);
843
844 qup->msg = NULL;
845 return ret;
846}
847
191424bb
S		 848static int qup_i2c_wait_for_complete(struct qup_i2c_dev *qup,
849 struct i2c_msg *msg)
10c5a842
BA		 850{
851 unsigned long left;
191424bb
S		 852 int ret = 0;
853
854 left = wait_for_completion_timeout(&qup->xfer, HZ);
855 if (!left) {
856 writel(1, qup->base + QUP_SW_RESET);
857 ret = -ETIMEDOUT;
858 }
859
860 if (qup->bus_err || qup->qup_err) {
861 if (qup->bus_err & QUP_I2C_NACK_FLAG) {
862 dev_err(qup->dev, "NACK from %x\n", msg->addr);
863 ret = -EIO;
864 }
865 }
866
867 return ret;
868}
869
870static int qup_i2c_write_one_v2(struct qup_i2c_dev *qup, struct i2c_msg *msg)
871{
872 int ret = 0;
873
874 qup->msg = msg;
875 qup->pos = 0;
876 enable_irq(qup->irq);
877 qup_i2c_set_blk_data(qup, msg);
878 qup_i2c_set_write_mode_v2(qup, msg);
879
880 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
881 if (ret)
882 goto err;
883
884 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
885
886 do {
887 ret = qup_i2c_issue_xfer_v2(qup, msg);
888 if (ret)
889 goto err;
890
891 ret = qup_i2c_wait_for_complete(qup, msg);
892 if (ret)
893 goto err;
894
895 qup->blk.pos++;
896 } while (qup->blk.pos < qup->blk.count);
897
898 ret = qup_i2c_wait_ready(qup, QUP_OUT_NOT_EMPTY, RESET_BIT, ONE_BYTE);
899
900err:
901 disable_irq(qup->irq);
902 qup->msg = NULL;
903
904 return ret;
905}
906
907static int qup_i2c_write_one(struct qup_i2c_dev *qup, struct i2c_msg *msg)
908{
10c5a842
BA		 909 int ret;
910
911 qup->msg = msg;
912 qup->pos = 0;
913
914 enable_irq(qup->irq);
915
916 qup_i2c_set_write_mode(qup, msg);
917
918 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
919 if (ret)
920 goto err;
921
922 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
923
924 do {
925 ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
926 if (ret)
927 goto err;
928
c4f0c5fb
S		 929 ret = qup_i2c_issue_write(qup, msg);
930 if (ret)
931 goto err;
10c5a842
BA		 932
933 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
934 if (ret)
935 goto err;
936
191424bb
S		 937 ret = qup_i2c_wait_for_complete(qup, msg);
938 if (ret)
10c5a842 939 goto err;
10c5a842
BA		 940 } while (qup->pos < msg->len);
941
942 /* Wait for the outstanding data in the fifo to drain */
c4f0c5fb 943 ret = qup_i2c_wait_ready(qup, QUP_OUT_NOT_EMPTY, RESET_BIT, ONE_BYTE);
10c5a842
BA		 944err:
945 disable_irq(qup->irq);
946 qup->msg = NULL;
947
948 return ret;
949}
950
951static void qup_i2c_set_read_mode(struct qup_i2c_dev *qup, int len)
952{
953 if (len < qup->in_fifo_sz) {
954 /* FIFO mode */
955 writel(QUP_REPACK_EN, qup->base + QUP_IO_MODE);
956 writel(len, qup->base + QUP_MX_READ_CNT);
957 } else {
958 /* BLOCK mode (transfer data on chunks) */
959 writel(QUP_INPUT_BLK_MODE | QUP_REPACK_EN,
960 qup->base + QUP_IO_MODE);
961 writel(len, qup->base + QUP_MX_INPUT_CNT);
962 }
963}
964
191424bb
S		 965static void qup_i2c_set_read_mode_v2(struct qup_i2c_dev *qup, int len)
966{
967 int tx_len = qup->blk.tx_tag_len;
968
969 len += qup->blk.rx_tag_len;
f7418793
S		 970 len |= qup->config_run;
971 tx_len |= qup->config_run;
191424bb
S		 972
973 if (len < qup->in_fifo_sz) {
974 /* FIFO mode */
975 writel(QUP_REPACK_EN, qup->base + QUP_IO_MODE);
191424bb 976 writel(tx_len, qup->base + QUP_MX_WRITE_CNT);
f7418793 977 writel(len, qup->base + QUP_MX_READ_CNT);
191424bb
S		 978 } else {
979 /* BLOCK mode (transfer data on chunks) */
980 writel(QUP_INPUT_BLK_MODE | QUP_REPACK_EN,
981 qup->base + QUP_IO_MODE);
191424bb 982 writel(tx_len, qup->base + QUP_MX_OUTPUT_CNT);
f7418793 983 writel(len, qup->base + QUP_MX_INPUT_CNT);
191424bb
S		 984 }
985}
986
10c5a842
BA		 987static void qup_i2c_issue_read(struct qup_i2c_dev *qup, struct i2c_msg *msg)
988{
989 u32 addr, len, val;
990
991 addr = (msg->addr << 1) | 1;
992
993 /* 0 is used to specify a length 256 (QUP_READ_LIMIT) */
994 len = (msg->len == QUP_READ_LIMIT) ? 0 : msg->len;
995
996 val = ((QUP_TAG_REC | len) << QUP_MSW_SHIFT) | QUP_TAG_START | addr;
997 writel(val, qup->base + QUP_OUT_FIFO_BASE);
998}
999
1000
c4f0c5fb 1001static int qup_i2c_read_fifo(struct qup_i2c_dev *qup, struct i2c_msg *msg)
10c5a842 1002{
10c5a842
BA		 1003 u32 val = 0;
1004 int idx;
c4f0c5fb 1005 int ret = 0;
10c5a842
BA		 1006
1007 for (idx = 0; qup->pos < msg->len; idx++) {
1008 if ((idx & 1) == 0) {
1009 /* Check that FIFO have data */
c4f0c5fb
S		 1010 ret = qup_i2c_wait_ready(qup, QUP_IN_NOT_EMPTY,
1011 SET_BIT, 4 * ONE_BYTE);
1012 if (ret)
1013 return ret;
10c5a842
BA		 1014
1015 /* Reading 2 words at time */
1016 val = readl(qup->base + QUP_IN_FIFO_BASE);
1017
1018 msg->buf[qup->pos++] = val & 0xFF;
1019 } else {
1020 msg->buf[qup->pos++] = val >> QUP_MSW_SHIFT;
1021 }
1022 }
c4f0c5fb
S		 1023
1024 return ret;
10c5a842
BA		 1025}
1026
191424bb
S		 1027static int qup_i2c_read_fifo_v2(struct qup_i2c_dev *qup,
1028 struct i2c_msg *msg)
1029{
1030 u32 val;
1031 int idx, pos = 0, ret = 0, total;
1032
1033 total = qup_i2c_get_data_len(qup);
1034
1035 /* 2 extra bytes for read tags */
1036 while (pos < (total + 2)) {
1037 /* Check that FIFO have data */
1038 ret = qup_i2c_wait_ready(qup, QUP_IN_NOT_EMPTY,
1039 SET_BIT, 4 * ONE_BYTE);
1040 if (ret) {
1041 dev_err(qup->dev, "timeout for fifo not empty");
1042 return ret;
1043 }
1044 val = readl(qup->base + QUP_IN_FIFO_BASE);
1045
1046 for (idx = 0; idx < 4; idx++, val >>= 8, pos++) {
1047 /* first 2 bytes are tag bytes */
1048 if (pos < 2)
1049 continue;
1050
1051 if (pos >= (total + 2))
1052 goto out;
1053
1054 msg->buf[qup->pos++] = val & 0xff;
1055 }
1056 }
1057
1058out:
1059 qup->blk.data_len -= total;
1060
1061 return ret;
1062}
1063
1064static int qup_i2c_read_one_v2(struct qup_i2c_dev *qup, struct i2c_msg *msg)
1065{
1066 int ret = 0;
1067
1068 qup->msg = msg;
1069 qup->pos = 0;
1070 enable_irq(qup->irq);
1071 qup_i2c_set_blk_data(qup, msg);
1072 qup_i2c_set_read_mode_v2(qup, msg->len);
1073
1074 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
1075 if (ret)
1076 goto err;
1077
1078 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
1079
1080 do {
1081 ret = qup_i2c_issue_xfer_v2(qup, msg);
1082 if (ret)
1083 goto err;
1084
1085 ret = qup_i2c_wait_for_complete(qup, msg);
1086 if (ret)
1087 goto err;
1088
1089 ret = qup_i2c_read_fifo_v2(qup, msg);
1090 if (ret)
1091 goto err;
1092
1093 qup->blk.pos++;
1094 } while (qup->blk.pos < qup->blk.count);
1095
1096err:
1097 disable_irq(qup->irq);
1098 qup->msg = NULL;
1099
1100 return ret;
1101}
1102
10c5a842
BA		 1103static int qup_i2c_read_one(struct qup_i2c_dev *qup, struct i2c_msg *msg)
1104{
10c5a842
BA		 1105 int ret;
1106
10c5a842
BA		 1107 qup->msg = msg;
1108 qup->pos = 0;
1109
1110 enable_irq(qup->irq);
10c5a842
BA		 1111 qup_i2c_set_read_mode(qup, msg->len);
1112
1113 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
1114 if (ret)
1115 goto err;
1116
1117 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
1118
1119 ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
1120 if (ret)
1121 goto err;
1122
1123 qup_i2c_issue_read(qup, msg);
1124
1125 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
1126 if (ret)
1127 goto err;
1128
1129 do {
191424bb
S		 1130 ret = qup_i2c_wait_for_complete(qup, msg);
1131 if (ret)
10c5a842 1132 goto err;
10c5a842 1133
c4f0c5fb
S		 1134 ret = qup_i2c_read_fifo(qup, msg);
1135 if (ret)
1136 goto err;
10c5a842
BA		 1137 } while (qup->pos < msg->len);
1138
1139err:
1140 disable_irq(qup->irq);
1141 qup->msg = NULL;
1142
1143 return ret;
1144}
1145
1146static int qup_i2c_xfer(struct i2c_adapter *adap,
1147 struct i2c_msg msgs[],
1148 int num)
1149{
1150 struct qup_i2c_dev *qup = i2c_get_adapdata(adap);
1151 int ret, idx;
1152
1153 ret = pm_runtime_get_sync(qup->dev);
fa01d096 1154 if (ret < 0)
10c5a842
BA		 1155 goto out;
1156
1157 writel(1, qup->base + QUP_SW_RESET);
1158 ret = qup_i2c_poll_state(qup, QUP_RESET_STATE);
1159 if (ret)
1160 goto out;
1161
1162 /* Configure QUP as I2C mini core */
1163 writel(I2C_MINI_CORE | I2C_N_VAL, qup->base + QUP_CONFIG);
1164
1165 for (idx = 0; idx < num; idx++) {
1166 if (msgs[idx].len == 0) {
1167 ret = -EINVAL;
1168 goto out;
1169 }
1170
1171 if (qup_i2c_poll_state_i2c_master(qup)) {
1172 ret = -EIO;
1173 goto out;
1174 }
1175
1176 if (msgs[idx].flags & I2C_M_RD)
1177 ret = qup_i2c_read_one(qup, &msgs[idx]);
1178 else
1179 ret = qup_i2c_write_one(qup, &msgs[idx]);
1180
1181 if (ret)
1182 break;
1183
1184 ret = qup_i2c_change_state(qup, QUP_RESET_STATE);
1185 if (ret)
1186 break;
1187 }
1188
1189 if (ret == 0)
1190 ret = num;
1191out:
1192
1193 pm_runtime_mark_last_busy(qup->dev);
1194 pm_runtime_put_autosuspend(qup->dev);
1195
1196 return ret;
1197}
1198
191424bb
S		 1199static int qup_i2c_xfer_v2(struct i2c_adapter *adap,
1200 struct i2c_msg msgs[],
1201 int num)
1202{
1203 struct qup_i2c_dev *qup = i2c_get_adapdata(adap);
9cedf3b2 1204 int ret, len, idx = 0, use_dma = 0;
191424bb
S		 1205
1206 ret = pm_runtime_get_sync(qup->dev);
1207 if (ret < 0)
1208 goto out;
1209
1210 writel(1, qup->base + QUP_SW_RESET);
1211 ret = qup_i2c_poll_state(qup, QUP_RESET_STATE);
1212 if (ret)
1213 goto out;
1214
1215 /* Configure QUP as I2C mini core */
1216 writel(I2C_MINI_CORE | I2C_N_VAL_V2, qup->base + QUP_CONFIG);
1217 writel(QUP_V2_TAGS_EN, qup->base + QUP_I2C_MASTER_GEN);
1218
9cedf3b2
S		 1219 if ((qup->is_dma)) {
1220 /* All i2c_msgs should be transferred using either dma or cpu */
1221 for (idx = 0; idx < num; idx++) {
1222 if (msgs[idx].len == 0) {
1223 ret = -EINVAL;
1224 goto out;
1225 }
1226
1227 len = (msgs[idx].len > qup->out_fifo_sz) ||
1228 (msgs[idx].len > qup->in_fifo_sz);
1229
1230 if ((!is_vmalloc_addr(msgs[idx].buf)) && len) {
1231 use_dma = 1;
1232 } else {
1233 use_dma = 0;
1234 break;
1235 }
1236 }
1237 }
1238
1239 do {
191424bb
S		 1240 if (msgs[idx].len == 0) {
1241 ret = -EINVAL;
1242 goto out;
1243 }
1244
1245 if (qup_i2c_poll_state_i2c_master(qup)) {
1246 ret = -EIO;
1247 goto out;
1248 }
1249
f7418793
S		 1250 qup->is_last = (idx == (num - 1));
1251 if (idx)
1252 qup->config_run = QUP_I2C_MX_CONFIG_DURING_RUN;
1253 else
1254 qup->config_run = 0;
1255
191424bb
S		 1256 reinit_completion(&qup->xfer);
1257
9cedf3b2
S		 1258 if (use_dma) {
1259 ret = qup_i2c_bam_xfer(adap, &msgs[idx], num);
1260 } else {
1261 if (msgs[idx].flags & I2C_M_RD)
1262 ret = qup_i2c_read_one_v2(qup, &msgs[idx]);
1263 else
1264 ret = qup_i2c_write_one_v2(qup, &msgs[idx]);
1265 }
1266 } while ((idx++ < (num - 1)) && !use_dma && !ret);
191424bb 1267
f7418793
S		 1268 if (!ret)
1269 ret = qup_i2c_change_state(qup, QUP_RESET_STATE);
1270
191424bb
S		 1271 if (ret == 0)
1272 ret = num;
1273out:
1274 pm_runtime_mark_last_busy(qup->dev);
1275 pm_runtime_put_autosuspend(qup->dev);
1276
1277 return ret;
1278}
1279
10c5a842
BA		 1280static u32 qup_i2c_func(struct i2c_adapter *adap)
1281{
1282 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
1283}
1284
1285static const struct i2c_algorithm qup_i2c_algo = {
1286 .master_xfer = qup_i2c_xfer,
1287 .functionality = qup_i2c_func,
1288};
1289
191424bb
S		 1290static const struct i2c_algorithm qup_i2c_algo_v2 = {
1291 .master_xfer = qup_i2c_xfer_v2,
1292 .functionality = qup_i2c_func,
1293};
1294
994647db
WS		 1295/*
1296 * The QUP block will issue a NACK and STOP on the bus when reaching
1297 * the end of the read, the length of the read is specified as one byte
1298 * which limits the possible read to 256 (QUP_READ_LIMIT) bytes.
1299 */
1300static struct i2c_adapter_quirks qup_i2c_quirks = {
1301 .max_read_len = QUP_READ_LIMIT,
1302};
1303
10c5a842
BA		 1304static void qup_i2c_enable_clocks(struct qup_i2c_dev *qup)
1305{
1306 clk_prepare_enable(qup->clk);
1307 clk_prepare_enable(qup->pclk);
1308}
1309
1310static void qup_i2c_disable_clocks(struct qup_i2c_dev *qup)
1311{
1312 u32 config;
1313
1314 qup_i2c_change_state(qup, QUP_RESET_STATE);
1315 clk_disable_unprepare(qup->clk);
1316 config = readl(qup->base + QUP_CONFIG);
1317 config |= QUP_CLOCK_AUTO_GATE;
1318 writel(config, qup->base + QUP_CONFIG);
1319 clk_disable_unprepare(qup->pclk);
1320}
1321
1322static int qup_i2c_probe(struct platform_device *pdev)
1323{
1324 static const int blk_sizes[] = {4, 16, 32};
1325 struct device_node *node = pdev->dev.of_node;
1326 struct qup_i2c_dev *qup;
1327 unsigned long one_bit_t;
1328 struct resource *res;
1329 u32 io_mode, hw_ver, size;
1330 int ret, fs_div, hs_div;
1331 int src_clk_freq;
cf23e335 1332 u32 clk_freq = 100000;
9cedf3b2 1333 int blocks;
10c5a842
BA		 1334
1335 qup = devm_kzalloc(&pdev->dev, sizeof(*qup), GFP_KERNEL);
1336 if (!qup)
1337 return -ENOMEM;
1338
1339 qup->dev = &pdev->dev;
1340 init_completion(&qup->xfer);
1341 platform_set_drvdata(pdev, qup);
1342
1343 of_property_read_u32(node, "clock-frequency", &clk_freq);
1344
191424bb
S		 1345 if (of_device_is_compatible(pdev->dev.of_node, "qcom,i2c-qup-v1.1.1")) {
1346 qup->adap.algo = &qup_i2c_algo;
1347 qup->adap.quirks = &qup_i2c_quirks;
1348 } else {
1349 qup->adap.algo = &qup_i2c_algo_v2;
9cedf3b2
S		 1350 ret = qup_i2c_req_dma(qup);
1351
1352 if (ret == -EPROBE_DEFER)
1353 goto fail_dma;
1354 else if (ret != 0)
1355 goto nodma;
1356
1357 blocks = (MX_BLOCKS << 1) + 1;
1358 qup->btx.sg = devm_kzalloc(&pdev->dev,
1359 sizeof(*qup->btx.sg) * blocks,
1360 GFP_KERNEL);
1361 if (!qup->btx.sg) {
1362 ret = -ENOMEM;
1363 goto fail_dma;
1364 }
1365 sg_init_table(qup->btx.sg, blocks);
1366
1367 qup->brx.sg = devm_kzalloc(&pdev->dev,
1368 sizeof(*qup->brx.sg) * blocks,
1369 GFP_KERNEL);
1370 if (!qup->brx.sg) {
1371 ret = -ENOMEM;
1372 goto fail_dma;
1373 }
1374 sg_init_table(qup->brx.sg, blocks);
1375
1376 /* 2 tag bytes for each block + 5 for start, stop tags */
1377 size = blocks * 2 + 5;
1378 qup->dpool = dma_pool_create("qup_i2c-dma-pool", &pdev->dev,
1379 size, 4, 0);
1380
1381 qup->start_tag.start = dma_pool_alloc(qup->dpool, GFP_KERNEL,
1382 &qup->start_tag.addr);
1383 if (!qup->start_tag.start) {
1384 ret = -ENOMEM;
1385 goto fail_dma;
1386 }
1387
1388 qup->brx.tag.start = dma_pool_alloc(qup->dpool,
1389 GFP_KERNEL,
1390 &qup->brx.tag.addr);
1391 if (!qup->brx.tag.start) {
1392 ret = -ENOMEM;
1393 goto fail_dma;
1394 }
1395
1396 qup->btx.tag.start = dma_pool_alloc(qup->dpool,
1397 GFP_KERNEL,
1398 &qup->btx.tag.addr);
1399 if (!qup->btx.tag.start) {
1400 ret = -ENOMEM;
1401 goto fail_dma;
1402 }
1403 qup->is_dma = true;
191424bb
S		 1404 }
1405
9cedf3b2 1406nodma:
10c5a842
BA		 1407 /* We support frequencies up to FAST Mode (400KHz) */
1408 if (!clk_freq || clk_freq > 400000) {
1409 dev_err(qup->dev, "clock frequency not supported %d\n",
1410 clk_freq);
1411 return -EINVAL;
1412 }
1413
1414 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1415 qup->base = devm_ioremap_resource(qup->dev, res);
1416 if (IS_ERR(qup->base))
1417 return PTR_ERR(qup->base);
1418
1419 qup->irq = platform_get_irq(pdev, 0);
1420 if (qup->irq < 0) {
1421 dev_err(qup->dev, "No IRQ defined\n");
1422 return qup->irq;
1423 }
1424
1425 qup->clk = devm_clk_get(qup->dev, "core");
1426 if (IS_ERR(qup->clk)) {
1427 dev_err(qup->dev, "Could not get core clock\n");
1428 return PTR_ERR(qup->clk);
1429 }
1430
1431 qup->pclk = devm_clk_get(qup->dev, "iface");
1432 if (IS_ERR(qup->pclk)) {
1433 dev_err(qup->dev, "Could not get iface clock\n");
1434 return PTR_ERR(qup->pclk);
1435 }
1436
1437 qup_i2c_enable_clocks(qup);
1438
1439 /*
1440 * Bootloaders might leave a pending interrupt on certain QUP's,
1441 * so we reset the core before registering for interrupts.
1442 */
1443 writel(1, qup->base + QUP_SW_RESET);
1444 ret = qup_i2c_poll_state_valid(qup);
1445 if (ret)
1446 goto fail;
1447
1448 ret = devm_request_irq(qup->dev, qup->irq, qup_i2c_interrupt,
1449 IRQF_TRIGGER_HIGH, "i2c_qup", qup);
1450 if (ret) {
1451 dev_err(qup->dev, "Request %d IRQ failed\n", qup->irq);
1452 goto fail;
1453 }
1454 disable_irq(qup->irq);
1455
1456 hw_ver = readl(qup->base + QUP_HW_VERSION);
1457 dev_dbg(qup->dev, "Revision %x\n", hw_ver);
1458
1459 io_mode = readl(qup->base + QUP_IO_MODE);
1460
1461 /*
1462 * The block/fifo size w.r.t. 'actual data' is 1/2 due to 'tag'
1463 * associated with each byte written/received
1464 */
1465 size = QUP_OUTPUT_BLOCK_SIZE(io_mode);
3cf357df
PG		 1466 if (size >= ARRAY_SIZE(blk_sizes)) {
1467 ret = -EIO;
1468 goto fail;
1469 }
10c5a842
BA		 1470 qup->out_blk_sz = blk_sizes[size] / 2;
1471
1472 size = QUP_INPUT_BLOCK_SIZE(io_mode);
3cf357df
PG		 1473 if (size >= ARRAY_SIZE(blk_sizes)) {
1474 ret = -EIO;
1475 goto fail;
1476 }
10c5a842
BA		 1477 qup->in_blk_sz = blk_sizes[size] / 2;
1478
1479 size = QUP_OUTPUT_FIFO_SIZE(io_mode);
1480 qup->out_fifo_sz = qup->out_blk_sz * (2 << size);
1481
1482 size = QUP_INPUT_FIFO_SIZE(io_mode);
1483 qup->in_fifo_sz = qup->in_blk_sz * (2 << size);
1484
1485 src_clk_freq = clk_get_rate(qup->clk);
1486 fs_div = ((src_clk_freq / clk_freq) / 2) - 3;
1487 hs_div = 3;
1488 qup->clk_ctl = (hs_div << 8) | (fs_div & 0xff);
1489
1490 /*
1491 * Time it takes for a byte to be clocked out on the bus.
1492 * Each byte takes 9 clock cycles (8 bits + 1 ack).
1493 */
1494 one_bit_t = (USEC_PER_SEC / clk_freq) + 1;
1495 qup->one_byte_t = one_bit_t * 9;
1496
1497 dev_dbg(qup->dev, "IN:block:%d, fifo:%d, OUT:block:%d, fifo:%d\n",
1498 qup->in_blk_sz, qup->in_fifo_sz,
1499 qup->out_blk_sz, qup->out_fifo_sz);
1500
1501 i2c_set_adapdata(&qup->adap, qup);
10c5a842
BA		 1502 qup->adap.dev.parent = qup->dev;
1503 qup->adap.dev.of_node = pdev->dev.of_node;
9cedf3b2 1504 qup->is_last = true;
f7418793 1505
10c5a842
BA		 1506 strlcpy(qup->adap.name, "QUP I2C adapter", sizeof(qup->adap.name));
1507
10c5a842
BA		 1508 pm_runtime_set_autosuspend_delay(qup->dev, MSEC_PER_SEC);
1509 pm_runtime_use_autosuspend(qup->dev);
1510 pm_runtime_set_active(qup->dev);
1511 pm_runtime_enable(qup->dev);
86b59bbf
AG		 1512
1513 ret = i2c_add_adapter(&qup->adap);
1514 if (ret)
1515 goto fail_runtime;
1516
10c5a842
BA		 1517 return 0;
1518
86b59bbf
AG		 1519fail_runtime:
1520 pm_runtime_disable(qup->dev);
1521 pm_runtime_set_suspended(qup->dev);
10c5a842
BA		 1522fail:
1523 qup_i2c_disable_clocks(qup);
9cedf3b2
S		 1524fail_dma:
1525 if (qup->btx.dma)
1526 dma_release_channel(qup->btx.dma);
1527 if (qup->brx.dma)
1528 dma_release_channel(qup->brx.dma);
10c5a842
BA		 1529 return ret;
1530}
1531
1532static int qup_i2c_remove(struct platform_device *pdev)
1533{
1534 struct qup_i2c_dev *qup = platform_get_drvdata(pdev);
1535
9cedf3b2
S		 1536 if (qup->is_dma) {
1537 dma_pool_free(qup->dpool, qup->start_tag.start,
1538 qup->start_tag.addr);
1539 dma_pool_free(qup->dpool, qup->brx.tag.start,
1540 qup->brx.tag.addr);
1541 dma_pool_free(qup->dpool, qup->btx.tag.start,
1542 qup->btx.tag.addr);
1543 dma_pool_destroy(qup->dpool);
1544 dma_release_channel(qup->btx.dma);
1545 dma_release_channel(qup->brx.dma);
1546 }
1547
10c5a842
BA		 1548 disable_irq(qup->irq);
1549 qup_i2c_disable_clocks(qup);
1550 i2c_del_adapter(&qup->adap);
1551 pm_runtime_disable(qup->dev);
1552 pm_runtime_set_suspended(qup->dev);
1553 return 0;
1554}
1555
1556#ifdef CONFIG_PM
1557static int qup_i2c_pm_suspend_runtime(struct device *device)
1558{
1559 struct qup_i2c_dev *qup = dev_get_drvdata(device);
1560
1561 dev_dbg(device, "pm_runtime: suspending...\n");
1562 qup_i2c_disable_clocks(qup);
1563 return 0;
1564}
1565
1566static int qup_i2c_pm_resume_runtime(struct device *device)
1567{
1568 struct qup_i2c_dev *qup = dev_get_drvdata(device);
1569
1570 dev_dbg(device, "pm_runtime: resuming...\n");
1571 qup_i2c_enable_clocks(qup);
1572 return 0;
1573}
1574#endif
1575
1576#ifdef CONFIG_PM_SLEEP
1577static int qup_i2c_suspend(struct device *device)
1578{
1579 qup_i2c_pm_suspend_runtime(device);
1580 return 0;
1581}
1582
1583static int qup_i2c_resume(struct device *device)
1584{
1585 qup_i2c_pm_resume_runtime(device);
1586 pm_runtime_mark_last_busy(device);
1587 pm_request_autosuspend(device);
1588 return 0;
1589}
1590#endif
1591
1592static const struct dev_pm_ops qup_i2c_qup_pm_ops = {
1593 SET_SYSTEM_SLEEP_PM_OPS(
1594 qup_i2c_suspend,
1595 qup_i2c_resume)
1596 SET_RUNTIME_PM_OPS(
1597 qup_i2c_pm_suspend_runtime,
1598 qup_i2c_pm_resume_runtime,
1599 NULL)
1600};
1601
1602static const struct of_device_id qup_i2c_dt_match[] = {
1603 { .compatible = "qcom,i2c-qup-v1.1.1" },
1604 { .compatible = "qcom,i2c-qup-v2.1.1" },
1605 { .compatible = "qcom,i2c-qup-v2.2.1" },
1606 {}
1607};
1608MODULE_DEVICE_TABLE(of, qup_i2c_dt_match);
1609
1610static struct platform_driver qup_i2c_driver = {
1611 .probe = qup_i2c_probe,
1612 .remove = qup_i2c_remove,
1613 .driver = {
1614 .name = "i2c_qup",
10c5a842
BA		 1615 .pm = &qup_i2c_qup_pm_ops,
1616 .of_match_table = qup_i2c_dt_match,
1617 },
1618};
1619
1620module_platform_driver(qup_i2c_driver);
1621
1622MODULE_LICENSE("GPL v2");
1623MODULE_ALIAS("platform:i2c_qup");
Linux 6.x block layer and io_uring tree(s)