Commit | Line | Data |
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b652b438 RK |
1 | /* |
2 | * i2c_adap_pxa.c | |
3 | * | |
4 | * I2C adapter for the PXA I2C bus access. | |
5 | * | |
6 | * Copyright (C) 2002 Intrinsyc Software Inc. | |
7 | * Copyright (C) 2004-2005 Deep Blue Solutions Ltd. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * History: | |
14 | * Apr 2002: Initial version [CS] | |
15 | * Jun 2002: Properly seperated algo/adap [FB] | |
16 | * Jan 2003: Fixed several bugs concerning interrupt handling [Kai-Uwe Bloem] | |
17 | * Jan 2003: added limited signal handling [Kai-Uwe Bloem] | |
18 | * Sep 2004: Major rework to ensure efficient bus handling [RMK] | |
19 | * Dec 2004: Added support for PXA27x and slave device probing [Liam Girdwood] | |
20 | * Feb 2005: Rework slave mode handling [RMK] | |
21 | */ | |
22 | #include <linux/kernel.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/i2c.h> | |
25 | #include <linux/i2c-id.h> | |
26 | #include <linux/init.h> | |
27 | #include <linux/time.h> | |
28 | #include <linux/sched.h> | |
29 | #include <linux/delay.h> | |
30 | #include <linux/errno.h> | |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/i2c-pxa.h> | |
d052d1be | 33 | #include <linux/platform_device.h> |
c3cef3f3 RK |
34 | #include <linux/err.h> |
35 | #include <linux/clk.h> | |
b652b438 | 36 | |
a09e64fb | 37 | #include <mach/hardware.h> |
b652b438 | 38 | #include <asm/irq.h> |
a7b4e550 | 39 | #include <asm/io.h> |
a09e64fb | 40 | #include <mach/i2c.h> |
283afa06 EM |
41 | |
42 | /* | |
43 | * I2C registers and bit definitions | |
44 | */ | |
45 | #define IBMR (0x00) | |
46 | #define IDBR (0x08) | |
47 | #define ICR (0x10) | |
48 | #define ISR (0x18) | |
49 | #define ISAR (0x20) | |
50 | ||
51 | #define ICR_START (1 << 0) /* start bit */ | |
52 | #define ICR_STOP (1 << 1) /* stop bit */ | |
53 | #define ICR_ACKNAK (1 << 2) /* send ACK(0) or NAK(1) */ | |
54 | #define ICR_TB (1 << 3) /* transfer byte bit */ | |
55 | #define ICR_MA (1 << 4) /* master abort */ | |
56 | #define ICR_SCLE (1 << 5) /* master clock enable */ | |
57 | #define ICR_IUE (1 << 6) /* unit enable */ | |
58 | #define ICR_GCD (1 << 7) /* general call disable */ | |
59 | #define ICR_ITEIE (1 << 8) /* enable tx interrupts */ | |
60 | #define ICR_IRFIE (1 << 9) /* enable rx interrupts */ | |
61 | #define ICR_BEIE (1 << 10) /* enable bus error ints */ | |
62 | #define ICR_SSDIE (1 << 11) /* slave STOP detected int enable */ | |
63 | #define ICR_ALDIE (1 << 12) /* enable arbitration interrupt */ | |
64 | #define ICR_SADIE (1 << 13) /* slave address detected int enable */ | |
65 | #define ICR_UR (1 << 14) /* unit reset */ | |
66 | #define ICR_FM (1 << 15) /* fast mode */ | |
67 | ||
68 | #define ISR_RWM (1 << 0) /* read/write mode */ | |
69 | #define ISR_ACKNAK (1 << 1) /* ack/nak status */ | |
70 | #define ISR_UB (1 << 2) /* unit busy */ | |
71 | #define ISR_IBB (1 << 3) /* bus busy */ | |
72 | #define ISR_SSD (1 << 4) /* slave stop detected */ | |
73 | #define ISR_ALD (1 << 5) /* arbitration loss detected */ | |
74 | #define ISR_ITE (1 << 6) /* tx buffer empty */ | |
75 | #define ISR_IRF (1 << 7) /* rx buffer full */ | |
76 | #define ISR_GCAD (1 << 8) /* general call address detected */ | |
77 | #define ISR_SAD (1 << 9) /* slave address detected */ | |
78 | #define ISR_BED (1 << 10) /* bus error no ACK/NAK */ | |
b652b438 RK |
79 | |
80 | struct pxa_i2c { | |
81 | spinlock_t lock; | |
82 | wait_queue_head_t wait; | |
83 | struct i2c_msg *msg; | |
84 | unsigned int msg_num; | |
85 | unsigned int msg_idx; | |
86 | unsigned int msg_ptr; | |
87 | unsigned int slave_addr; | |
88 | ||
89 | struct i2c_adapter adap; | |
c3cef3f3 | 90 | struct clk *clk; |
b652b438 RK |
91 | #ifdef CONFIG_I2C_PXA_SLAVE |
92 | struct i2c_slave_client *slave; | |
93 | #endif | |
94 | ||
95 | unsigned int irqlogidx; | |
96 | u32 isrlog[32]; | |
97 | u32 icrlog[32]; | |
a7b4e550 GL |
98 | |
99 | void __iomem *reg_base; | |
9ba63c4f | 100 | unsigned int reg_shift; |
a7b4e550 GL |
101 | |
102 | unsigned long iobase; | |
103 | unsigned long iosize; | |
104 | ||
105 | int irq; | |
c46c9482 JC |
106 | unsigned int use_pio :1; |
107 | unsigned int fast_mode :1; | |
b652b438 RK |
108 | }; |
109 | ||
9ba63c4f MR |
110 | #define _IBMR(i2c) ((i2c)->reg_base + (0x0 << (i2c)->reg_shift)) |
111 | #define _IDBR(i2c) ((i2c)->reg_base + (0x4 << (i2c)->reg_shift)) | |
112 | #define _ICR(i2c) ((i2c)->reg_base + (0x8 << (i2c)->reg_shift)) | |
113 | #define _ISR(i2c) ((i2c)->reg_base + (0xc << (i2c)->reg_shift)) | |
114 | #define _ISAR(i2c) ((i2c)->reg_base + (0x10 << (i2c)->reg_shift)) | |
a7b4e550 | 115 | |
b652b438 RK |
116 | /* |
117 | * I2C Slave mode address | |
118 | */ | |
119 | #define I2C_PXA_SLAVE_ADDR 0x1 | |
120 | ||
b652b438 RK |
121 | #ifdef DEBUG |
122 | ||
123 | struct bits { | |
124 | u32 mask; | |
125 | const char *set; | |
126 | const char *unset; | |
127 | }; | |
ed11399d | 128 | #define PXA_BIT(m, s, u) { .mask = m, .set = s, .unset = u } |
b652b438 RK |
129 | |
130 | static inline void | |
131 | decode_bits(const char *prefix, const struct bits *bits, int num, u32 val) | |
132 | { | |
133 | printk("%s %08x: ", prefix, val); | |
134 | while (num--) { | |
135 | const char *str = val & bits->mask ? bits->set : bits->unset; | |
136 | if (str) | |
137 | printk("%s ", str); | |
138 | bits++; | |
139 | } | |
140 | } | |
141 | ||
142 | static const struct bits isr_bits[] = { | |
ed11399d JS |
143 | PXA_BIT(ISR_RWM, "RX", "TX"), |
144 | PXA_BIT(ISR_ACKNAK, "NAK", "ACK"), | |
145 | PXA_BIT(ISR_UB, "Bsy", "Rdy"), | |
146 | PXA_BIT(ISR_IBB, "BusBsy", "BusRdy"), | |
147 | PXA_BIT(ISR_SSD, "SlaveStop", NULL), | |
148 | PXA_BIT(ISR_ALD, "ALD", NULL), | |
149 | PXA_BIT(ISR_ITE, "TxEmpty", NULL), | |
150 | PXA_BIT(ISR_IRF, "RxFull", NULL), | |
151 | PXA_BIT(ISR_GCAD, "GenCall", NULL), | |
152 | PXA_BIT(ISR_SAD, "SlaveAddr", NULL), | |
153 | PXA_BIT(ISR_BED, "BusErr", NULL), | |
b652b438 RK |
154 | }; |
155 | ||
156 | static void decode_ISR(unsigned int val) | |
157 | { | |
6fd60fa9 | 158 | decode_bits(KERN_DEBUG "ISR", isr_bits, ARRAY_SIZE(isr_bits), val); |
b652b438 RK |
159 | printk("\n"); |
160 | } | |
161 | ||
162 | static const struct bits icr_bits[] = { | |
ed11399d JS |
163 | PXA_BIT(ICR_START, "START", NULL), |
164 | PXA_BIT(ICR_STOP, "STOP", NULL), | |
165 | PXA_BIT(ICR_ACKNAK, "ACKNAK", NULL), | |
166 | PXA_BIT(ICR_TB, "TB", NULL), | |
167 | PXA_BIT(ICR_MA, "MA", NULL), | |
168 | PXA_BIT(ICR_SCLE, "SCLE", "scle"), | |
169 | PXA_BIT(ICR_IUE, "IUE", "iue"), | |
170 | PXA_BIT(ICR_GCD, "GCD", NULL), | |
171 | PXA_BIT(ICR_ITEIE, "ITEIE", NULL), | |
172 | PXA_BIT(ICR_IRFIE, "IRFIE", NULL), | |
173 | PXA_BIT(ICR_BEIE, "BEIE", NULL), | |
174 | PXA_BIT(ICR_SSDIE, "SSDIE", NULL), | |
175 | PXA_BIT(ICR_ALDIE, "ALDIE", NULL), | |
176 | PXA_BIT(ICR_SADIE, "SADIE", NULL), | |
177 | PXA_BIT(ICR_UR, "UR", "ur"), | |
b652b438 RK |
178 | }; |
179 | ||
d6a7b5f8 | 180 | #ifdef CONFIG_I2C_PXA_SLAVE |
b652b438 RK |
181 | static void decode_ICR(unsigned int val) |
182 | { | |
6fd60fa9 | 183 | decode_bits(KERN_DEBUG "ICR", icr_bits, ARRAY_SIZE(icr_bits), val); |
b652b438 RK |
184 | printk("\n"); |
185 | } | |
d6a7b5f8 | 186 | #endif |
b652b438 RK |
187 | |
188 | static unsigned int i2c_debug = DEBUG; | |
189 | ||
190 | static void i2c_pxa_show_state(struct pxa_i2c *i2c, int lno, const char *fname) | |
191 | { | |
a7b4e550 GL |
192 | dev_dbg(&i2c->adap.dev, "state:%s:%d: ISR=%08x, ICR=%08x, IBMR=%02x\n", fname, lno, |
193 | readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c))); | |
b652b438 RK |
194 | } |
195 | ||
08882d20 | 196 | #define show_state(i2c) i2c_pxa_show_state(i2c, __LINE__, __func__) |
b652b438 RK |
197 | #else |
198 | #define i2c_debug 0 | |
199 | ||
200 | #define show_state(i2c) do { } while (0) | |
201 | #define decode_ISR(val) do { } while (0) | |
202 | #define decode_ICR(val) do { } while (0) | |
203 | #endif | |
204 | ||
6fd60fa9 | 205 | #define eedbg(lvl, x...) do { if ((lvl) < 1) { printk(KERN_DEBUG "" x); } } while(0) |
b652b438 RK |
206 | |
207 | static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret); | |
b7a36701 | 208 | static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id); |
b652b438 RK |
209 | |
210 | static void i2c_pxa_scream_blue_murder(struct pxa_i2c *i2c, const char *why) | |
211 | { | |
212 | unsigned int i; | |
213 | printk("i2c: error: %s\n", why); | |
214 | printk("i2c: msg_num: %d msg_idx: %d msg_ptr: %d\n", | |
215 | i2c->msg_num, i2c->msg_idx, i2c->msg_ptr); | |
6fd60fa9 | 216 | printk("i2c: ICR: %08x ISR: %08x\n" |
a7b4e550 | 217 | "i2c: log: ", readl(_ICR(i2c)), readl(_ISR(i2c))); |
b652b438 RK |
218 | for (i = 0; i < i2c->irqlogidx; i++) |
219 | printk("[%08x:%08x] ", i2c->isrlog[i], i2c->icrlog[i]); | |
220 | printk("\n"); | |
221 | } | |
222 | ||
223 | static inline int i2c_pxa_is_slavemode(struct pxa_i2c *i2c) | |
224 | { | |
a7b4e550 | 225 | return !(readl(_ICR(i2c)) & ICR_SCLE); |
b652b438 RK |
226 | } |
227 | ||
228 | static void i2c_pxa_abort(struct pxa_i2c *i2c) | |
229 | { | |
387fa6a5 | 230 | int i = 250; |
b652b438 RK |
231 | |
232 | if (i2c_pxa_is_slavemode(i2c)) { | |
6fd60fa9 | 233 | dev_dbg(&i2c->adap.dev, "%s: called in slave mode\n", __func__); |
b652b438 RK |
234 | return; |
235 | } | |
236 | ||
387fa6a5 | 237 | while ((i > 0) && (readl(_IBMR(i2c)) & 0x1) == 0) { |
a7b4e550 | 238 | unsigned long icr = readl(_ICR(i2c)); |
b652b438 RK |
239 | |
240 | icr &= ~ICR_START; | |
241 | icr |= ICR_ACKNAK | ICR_STOP | ICR_TB; | |
242 | ||
a7b4e550 | 243 | writel(icr, _ICR(i2c)); |
b652b438 RK |
244 | |
245 | show_state(i2c); | |
246 | ||
387fa6a5 DB |
247 | mdelay(1); |
248 | i --; | |
b652b438 RK |
249 | } |
250 | ||
a7b4e550 GL |
251 | writel(readl(_ICR(i2c)) & ~(ICR_MA | ICR_START | ICR_STOP), |
252 | _ICR(i2c)); | |
b652b438 RK |
253 | } |
254 | ||
255 | static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c *i2c) | |
256 | { | |
257 | int timeout = DEF_TIMEOUT; | |
258 | ||
a7b4e550 GL |
259 | while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) { |
260 | if ((readl(_ISR(i2c)) & ISR_SAD) != 0) | |
b652b438 RK |
261 | timeout += 4; |
262 | ||
263 | msleep(2); | |
264 | show_state(i2c); | |
265 | } | |
266 | ||
267 | if (timeout <= 0) | |
268 | show_state(i2c); | |
269 | ||
270 | return timeout <= 0 ? I2C_RETRY : 0; | |
271 | } | |
272 | ||
273 | static int i2c_pxa_wait_master(struct pxa_i2c *i2c) | |
274 | { | |
275 | unsigned long timeout = jiffies + HZ*4; | |
276 | ||
277 | while (time_before(jiffies, timeout)) { | |
278 | if (i2c_debug > 1) | |
6fd60fa9 | 279 | dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n", |
a7b4e550 | 280 | __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c))); |
b652b438 | 281 | |
a7b4e550 | 282 | if (readl(_ISR(i2c)) & ISR_SAD) { |
b652b438 | 283 | if (i2c_debug > 0) |
6fd60fa9 | 284 | dev_dbg(&i2c->adap.dev, "%s: Slave detected\n", __func__); |
b652b438 RK |
285 | goto out; |
286 | } | |
287 | ||
288 | /* wait for unit and bus being not busy, and we also do a | |
289 | * quick check of the i2c lines themselves to ensure they've | |
290 | * gone high... | |
291 | */ | |
a7b4e550 | 292 | if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) == 0 && readl(_IBMR(i2c)) == 3) { |
b652b438 | 293 | if (i2c_debug > 0) |
6fd60fa9 | 294 | dev_dbg(&i2c->adap.dev, "%s: done\n", __func__); |
b652b438 RK |
295 | return 1; |
296 | } | |
297 | ||
298 | msleep(1); | |
299 | } | |
300 | ||
301 | if (i2c_debug > 0) | |
6fd60fa9 | 302 | dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__); |
b652b438 RK |
303 | out: |
304 | return 0; | |
305 | } | |
306 | ||
307 | static int i2c_pxa_set_master(struct pxa_i2c *i2c) | |
308 | { | |
309 | if (i2c_debug) | |
6fd60fa9 | 310 | dev_dbg(&i2c->adap.dev, "setting to bus master\n"); |
b652b438 | 311 | |
a7b4e550 | 312 | if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) != 0) { |
6fd60fa9 | 313 | dev_dbg(&i2c->adap.dev, "%s: unit is busy\n", __func__); |
b652b438 | 314 | if (!i2c_pxa_wait_master(i2c)) { |
6fd60fa9 | 315 | dev_dbg(&i2c->adap.dev, "%s: error: unit busy\n", __func__); |
b652b438 RK |
316 | return I2C_RETRY; |
317 | } | |
318 | } | |
319 | ||
a7b4e550 | 320 | writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c)); |
b652b438 RK |
321 | return 0; |
322 | } | |
323 | ||
324 | #ifdef CONFIG_I2C_PXA_SLAVE | |
325 | static int i2c_pxa_wait_slave(struct pxa_i2c *i2c) | |
326 | { | |
327 | unsigned long timeout = jiffies + HZ*1; | |
328 | ||
329 | /* wait for stop */ | |
330 | ||
331 | show_state(i2c); | |
332 | ||
333 | while (time_before(jiffies, timeout)) { | |
334 | if (i2c_debug > 1) | |
6fd60fa9 | 335 | dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n", |
a7b4e550 | 336 | __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c))); |
b652b438 | 337 | |
a7b4e550 GL |
338 | if ((readl(_ISR(i2c)) & (ISR_UB|ISR_IBB)) == 0 || |
339 | (readl(_ISR(i2c)) & ISR_SAD) != 0 || | |
340 | (readl(_ICR(i2c)) & ICR_SCLE) == 0) { | |
b652b438 | 341 | if (i2c_debug > 1) |
6fd60fa9 | 342 | dev_dbg(&i2c->adap.dev, "%s: done\n", __func__); |
b652b438 RK |
343 | return 1; |
344 | } | |
345 | ||
346 | msleep(1); | |
347 | } | |
348 | ||
349 | if (i2c_debug > 0) | |
6fd60fa9 | 350 | dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__); |
b652b438 RK |
351 | return 0; |
352 | } | |
353 | ||
354 | /* | |
355 | * clear the hold on the bus, and take of anything else | |
356 | * that has been configured | |
357 | */ | |
358 | static void i2c_pxa_set_slave(struct pxa_i2c *i2c, int errcode) | |
359 | { | |
360 | show_state(i2c); | |
361 | ||
362 | if (errcode < 0) { | |
363 | udelay(100); /* simple delay */ | |
364 | } else { | |
365 | /* we need to wait for the stop condition to end */ | |
366 | ||
367 | /* if we where in stop, then clear... */ | |
a7b4e550 | 368 | if (readl(_ICR(i2c)) & ICR_STOP) { |
b652b438 | 369 | udelay(100); |
a7b4e550 | 370 | writel(readl(_ICR(i2c)) & ~ICR_STOP, _ICR(i2c)); |
b652b438 RK |
371 | } |
372 | ||
373 | if (!i2c_pxa_wait_slave(i2c)) { | |
6fd60fa9 RK |
374 | dev_err(&i2c->adap.dev, "%s: wait timedout\n", |
375 | __func__); | |
b652b438 RK |
376 | return; |
377 | } | |
378 | } | |
379 | ||
a7b4e550 GL |
380 | writel(readl(_ICR(i2c)) & ~(ICR_STOP|ICR_ACKNAK|ICR_MA), _ICR(i2c)); |
381 | writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c)); | |
b652b438 RK |
382 | |
383 | if (i2c_debug) { | |
a7b4e550 GL |
384 | dev_dbg(&i2c->adap.dev, "ICR now %08x, ISR %08x\n", readl(_ICR(i2c)), readl(_ISR(i2c))); |
385 | decode_ICR(readl(_ICR(i2c))); | |
b652b438 RK |
386 | } |
387 | } | |
388 | #else | |
389 | #define i2c_pxa_set_slave(i2c, err) do { } while (0) | |
390 | #endif | |
391 | ||
392 | static void i2c_pxa_reset(struct pxa_i2c *i2c) | |
393 | { | |
394 | pr_debug("Resetting I2C Controller Unit\n"); | |
395 | ||
396 | /* abort any transfer currently under way */ | |
397 | i2c_pxa_abort(i2c); | |
398 | ||
399 | /* reset according to 9.8 */ | |
a7b4e550 GL |
400 | writel(ICR_UR, _ICR(i2c)); |
401 | writel(I2C_ISR_INIT, _ISR(i2c)); | |
402 | writel(readl(_ICR(i2c)) & ~ICR_UR, _ICR(i2c)); | |
b652b438 | 403 | |
a7b4e550 | 404 | writel(i2c->slave_addr, _ISAR(i2c)); |
b652b438 RK |
405 | |
406 | /* set control register values */ | |
c46c9482 | 407 | writel(I2C_ICR_INIT | (i2c->fast_mode ? ICR_FM : 0), _ICR(i2c)); |
b652b438 RK |
408 | |
409 | #ifdef CONFIG_I2C_PXA_SLAVE | |
6fd60fa9 | 410 | dev_info(&i2c->adap.dev, "Enabling slave mode\n"); |
a7b4e550 | 411 | writel(readl(_ICR(i2c)) | ICR_SADIE | ICR_ALDIE | ICR_SSDIE, _ICR(i2c)); |
b652b438 RK |
412 | #endif |
413 | ||
414 | i2c_pxa_set_slave(i2c, 0); | |
415 | ||
416 | /* enable unit */ | |
a7b4e550 | 417 | writel(readl(_ICR(i2c)) | ICR_IUE, _ICR(i2c)); |
b652b438 RK |
418 | udelay(100); |
419 | } | |
420 | ||
421 | ||
422 | #ifdef CONFIG_I2C_PXA_SLAVE | |
b652b438 RK |
423 | /* |
424 | * PXA I2C Slave mode | |
425 | */ | |
426 | ||
427 | static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr) | |
428 | { | |
429 | if (isr & ISR_BED) { | |
430 | /* what should we do here? */ | |
431 | } else { | |
84b5abe6 RK |
432 | int ret = 0; |
433 | ||
434 | if (i2c->slave != NULL) | |
435 | ret = i2c->slave->read(i2c->slave->data); | |
b652b438 | 436 | |
a7b4e550 GL |
437 | writel(ret, _IDBR(i2c)); |
438 | writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); /* allow next byte */ | |
b652b438 RK |
439 | } |
440 | } | |
441 | ||
442 | static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr) | |
443 | { | |
a7b4e550 | 444 | unsigned int byte = readl(_IDBR(i2c)); |
b652b438 RK |
445 | |
446 | if (i2c->slave != NULL) | |
447 | i2c->slave->write(i2c->slave->data, byte); | |
448 | ||
a7b4e550 | 449 | writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); |
b652b438 RK |
450 | } |
451 | ||
452 | static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr) | |
453 | { | |
454 | int timeout; | |
455 | ||
456 | if (i2c_debug > 0) | |
6fd60fa9 | 457 | dev_dbg(&i2c->adap.dev, "SAD, mode is slave-%cx\n", |
b652b438 RK |
458 | (isr & ISR_RWM) ? 'r' : 't'); |
459 | ||
460 | if (i2c->slave != NULL) | |
461 | i2c->slave->event(i2c->slave->data, | |
462 | (isr & ISR_RWM) ? I2C_SLAVE_EVENT_START_READ : I2C_SLAVE_EVENT_START_WRITE); | |
463 | ||
464 | /* | |
465 | * slave could interrupt in the middle of us generating a | |
466 | * start condition... if this happens, we'd better back off | |
467 | * and stop holding the poor thing up | |
468 | */ | |
a7b4e550 GL |
469 | writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c)); |
470 | writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); | |
b652b438 RK |
471 | |
472 | timeout = 0x10000; | |
473 | ||
474 | while (1) { | |
a7b4e550 | 475 | if ((readl(_IBMR(i2c)) & 2) == 2) |
b652b438 RK |
476 | break; |
477 | ||
478 | timeout--; | |
479 | ||
480 | if (timeout <= 0) { | |
6fd60fa9 | 481 | dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n"); |
b652b438 RK |
482 | break; |
483 | } | |
484 | } | |
485 | ||
a7b4e550 | 486 | writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c)); |
b652b438 RK |
487 | } |
488 | ||
489 | static void i2c_pxa_slave_stop(struct pxa_i2c *i2c) | |
490 | { | |
491 | if (i2c_debug > 2) | |
6fd60fa9 | 492 | dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop)\n"); |
b652b438 RK |
493 | |
494 | if (i2c->slave != NULL) | |
495 | i2c->slave->event(i2c->slave->data, I2C_SLAVE_EVENT_STOP); | |
496 | ||
497 | if (i2c_debug > 2) | |
6fd60fa9 | 498 | dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop) acked\n"); |
b652b438 RK |
499 | |
500 | /* | |
501 | * If we have a master-mode message waiting, | |
502 | * kick it off now that the slave has completed. | |
503 | */ | |
504 | if (i2c->msg) | |
505 | i2c_pxa_master_complete(i2c, I2C_RETRY); | |
506 | } | |
507 | #else | |
508 | static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr) | |
509 | { | |
510 | if (isr & ISR_BED) { | |
511 | /* what should we do here? */ | |
512 | } else { | |
a7b4e550 GL |
513 | writel(0, _IDBR(i2c)); |
514 | writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); | |
b652b438 RK |
515 | } |
516 | } | |
517 | ||
518 | static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr) | |
519 | { | |
a7b4e550 | 520 | writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c)); |
b652b438 RK |
521 | } |
522 | ||
523 | static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr) | |
524 | { | |
525 | int timeout; | |
526 | ||
527 | /* | |
528 | * slave could interrupt in the middle of us generating a | |
529 | * start condition... if this happens, we'd better back off | |
530 | * and stop holding the poor thing up | |
531 | */ | |
a7b4e550 GL |
532 | writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c)); |
533 | writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c)); | |
b652b438 RK |
534 | |
535 | timeout = 0x10000; | |
536 | ||
537 | while (1) { | |
a7b4e550 | 538 | if ((readl(_IBMR(i2c)) & 2) == 2) |
b652b438 RK |
539 | break; |
540 | ||
541 | timeout--; | |
542 | ||
543 | if (timeout <= 0) { | |
6fd60fa9 | 544 | dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n"); |
b652b438 RK |
545 | break; |
546 | } | |
547 | } | |
548 | ||
a7b4e550 | 549 | writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c)); |
b652b438 RK |
550 | } |
551 | ||
552 | static void i2c_pxa_slave_stop(struct pxa_i2c *i2c) | |
553 | { | |
554 | if (i2c->msg) | |
555 | i2c_pxa_master_complete(i2c, I2C_RETRY); | |
556 | } | |
557 | #endif | |
558 | ||
559 | /* | |
560 | * PXA I2C Master mode | |
561 | */ | |
562 | ||
563 | static inline unsigned int i2c_pxa_addr_byte(struct i2c_msg *msg) | |
564 | { | |
565 | unsigned int addr = (msg->addr & 0x7f) << 1; | |
566 | ||
567 | if (msg->flags & I2C_M_RD) | |
568 | addr |= 1; | |
569 | ||
570 | return addr; | |
571 | } | |
572 | ||
573 | static inline void i2c_pxa_start_message(struct pxa_i2c *i2c) | |
574 | { | |
575 | u32 icr; | |
576 | ||
577 | /* | |
578 | * Step 1: target slave address into IDBR | |
579 | */ | |
a7b4e550 | 580 | writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c)); |
b652b438 RK |
581 | |
582 | /* | |
583 | * Step 2: initiate the write. | |
584 | */ | |
a7b4e550 GL |
585 | icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE); |
586 | writel(icr | ICR_START | ICR_TB, _ICR(i2c)); | |
b652b438 RK |
587 | } |
588 | ||
7d054817 JD |
589 | static inline void i2c_pxa_stop_message(struct pxa_i2c *i2c) |
590 | { | |
591 | u32 icr; | |
592 | ||
593 | /* | |
594 | * Clear the STOP and ACK flags | |
595 | */ | |
596 | icr = readl(_ICR(i2c)); | |
597 | icr &= ~(ICR_STOP | ICR_ACKNAK); | |
0cfe61e1 | 598 | writel(icr, _ICR(i2c)); |
7d054817 JD |
599 | } |
600 | ||
b7a36701 MR |
601 | static int i2c_pxa_pio_set_master(struct pxa_i2c *i2c) |
602 | { | |
603 | /* make timeout the same as for interrupt based functions */ | |
604 | long timeout = 2 * DEF_TIMEOUT; | |
605 | ||
606 | /* | |
607 | * Wait for the bus to become free. | |
608 | */ | |
609 | while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) { | |
610 | udelay(1000); | |
611 | show_state(i2c); | |
612 | } | |
613 | ||
614 | if (timeout <= 0) { | |
615 | show_state(i2c); | |
616 | dev_err(&i2c->adap.dev, | |
617 | "i2c_pxa: timeout waiting for bus free\n"); | |
618 | return I2C_RETRY; | |
619 | } | |
620 | ||
621 | /* | |
622 | * Set master mode. | |
623 | */ | |
624 | writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c)); | |
625 | ||
626 | return 0; | |
627 | } | |
628 | ||
629 | static int i2c_pxa_do_pio_xfer(struct pxa_i2c *i2c, | |
630 | struct i2c_msg *msg, int num) | |
631 | { | |
632 | unsigned long timeout = 500000; /* 5 seconds */ | |
633 | int ret = 0; | |
634 | ||
635 | ret = i2c_pxa_pio_set_master(i2c); | |
636 | if (ret) | |
637 | goto out; | |
638 | ||
639 | i2c->msg = msg; | |
640 | i2c->msg_num = num; | |
641 | i2c->msg_idx = 0; | |
642 | i2c->msg_ptr = 0; | |
643 | i2c->irqlogidx = 0; | |
644 | ||
645 | i2c_pxa_start_message(i2c); | |
646 | ||
647 | while (timeout-- && i2c->msg_num > 0) { | |
648 | i2c_pxa_handler(0, i2c); | |
649 | udelay(10); | |
650 | } | |
651 | ||
652 | i2c_pxa_stop_message(i2c); | |
653 | ||
654 | /* | |
655 | * We place the return code in i2c->msg_idx. | |
656 | */ | |
657 | ret = i2c->msg_idx; | |
658 | ||
659 | out: | |
660 | if (timeout == 0) | |
661 | i2c_pxa_scream_blue_murder(i2c, "timeout"); | |
662 | ||
663 | return ret; | |
664 | } | |
665 | ||
b652b438 | 666 | /* |
3fb9a655 | 667 | * We are protected by the adapter bus mutex. |
b652b438 RK |
668 | */ |
669 | static int i2c_pxa_do_xfer(struct pxa_i2c *i2c, struct i2c_msg *msg, int num) | |
670 | { | |
671 | long timeout; | |
672 | int ret; | |
673 | ||
674 | /* | |
675 | * Wait for the bus to become free. | |
676 | */ | |
677 | ret = i2c_pxa_wait_bus_not_busy(i2c); | |
678 | if (ret) { | |
6fd60fa9 | 679 | dev_err(&i2c->adap.dev, "i2c_pxa: timeout waiting for bus free\n"); |
b652b438 RK |
680 | goto out; |
681 | } | |
682 | ||
683 | /* | |
684 | * Set master mode. | |
685 | */ | |
686 | ret = i2c_pxa_set_master(i2c); | |
687 | if (ret) { | |
6fd60fa9 | 688 | dev_err(&i2c->adap.dev, "i2c_pxa_set_master: error %d\n", ret); |
b652b438 RK |
689 | goto out; |
690 | } | |
691 | ||
692 | spin_lock_irq(&i2c->lock); | |
693 | ||
694 | i2c->msg = msg; | |
695 | i2c->msg_num = num; | |
696 | i2c->msg_idx = 0; | |
697 | i2c->msg_ptr = 0; | |
698 | i2c->irqlogidx = 0; | |
699 | ||
700 | i2c_pxa_start_message(i2c); | |
701 | ||
702 | spin_unlock_irq(&i2c->lock); | |
703 | ||
704 | /* | |
705 | * The rest of the processing occurs in the interrupt handler. | |
706 | */ | |
707 | timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5); | |
7d054817 | 708 | i2c_pxa_stop_message(i2c); |
b652b438 RK |
709 | |
710 | /* | |
711 | * We place the return code in i2c->msg_idx. | |
712 | */ | |
713 | ret = i2c->msg_idx; | |
714 | ||
715 | if (timeout == 0) | |
716 | i2c_pxa_scream_blue_murder(i2c, "timeout"); | |
717 | ||
718 | out: | |
719 | return ret; | |
720 | } | |
721 | ||
b7a36701 MR |
722 | static int i2c_pxa_pio_xfer(struct i2c_adapter *adap, |
723 | struct i2c_msg msgs[], int num) | |
724 | { | |
725 | struct pxa_i2c *i2c = adap->algo_data; | |
726 | int ret, i; | |
727 | ||
728 | /* If the I2C controller is disabled we need to reset it | |
729 | (probably due to a suspend/resume destroying state). We do | |
730 | this here as we can then avoid worrying about resuming the | |
731 | controller before its users. */ | |
732 | if (!(readl(_ICR(i2c)) & ICR_IUE)) | |
733 | i2c_pxa_reset(i2c); | |
734 | ||
735 | for (i = adap->retries; i >= 0; i--) { | |
736 | ret = i2c_pxa_do_pio_xfer(i2c, msgs, num); | |
737 | if (ret != I2C_RETRY) | |
738 | goto out; | |
739 | ||
740 | if (i2c_debug) | |
741 | dev_dbg(&adap->dev, "Retrying transmission\n"); | |
742 | udelay(100); | |
743 | } | |
744 | i2c_pxa_scream_blue_murder(i2c, "exhausted retries"); | |
745 | ret = -EREMOTEIO; | |
746 | out: | |
747 | i2c_pxa_set_slave(i2c, ret); | |
748 | return ret; | |
749 | } | |
750 | ||
b652b438 RK |
751 | /* |
752 | * i2c_pxa_master_complete - complete the message and wake up. | |
753 | */ | |
754 | static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret) | |
755 | { | |
756 | i2c->msg_ptr = 0; | |
757 | i2c->msg = NULL; | |
758 | i2c->msg_idx ++; | |
759 | i2c->msg_num = 0; | |
760 | if (ret) | |
761 | i2c->msg_idx = ret; | |
b7a36701 MR |
762 | if (!i2c->use_pio) |
763 | wake_up(&i2c->wait); | |
b652b438 RK |
764 | } |
765 | ||
766 | static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr) | |
767 | { | |
a7b4e550 | 768 | u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB); |
b652b438 RK |
769 | |
770 | again: | |
771 | /* | |
772 | * If ISR_ALD is set, we lost arbitration. | |
773 | */ | |
774 | if (isr & ISR_ALD) { | |
775 | /* | |
776 | * Do we need to do anything here? The PXA docs | |
777 | * are vague about what happens. | |
778 | */ | |
779 | i2c_pxa_scream_blue_murder(i2c, "ALD set"); | |
780 | ||
781 | /* | |
782 | * We ignore this error. We seem to see spurious ALDs | |
783 | * for seemingly no reason. If we handle them as I think | |
784 | * they should, we end up causing an I2C error, which | |
785 | * is painful for some systems. | |
786 | */ | |
787 | return; /* ignore */ | |
788 | } | |
789 | ||
790 | if (isr & ISR_BED) { | |
791 | int ret = BUS_ERROR; | |
792 | ||
793 | /* | |
794 | * I2C bus error - either the device NAK'd us, or | |
795 | * something more serious happened. If we were NAK'd | |
796 | * on the initial address phase, we can retry. | |
797 | */ | |
798 | if (isr & ISR_ACKNAK) { | |
799 | if (i2c->msg_ptr == 0 && i2c->msg_idx == 0) | |
800 | ret = I2C_RETRY; | |
801 | else | |
802 | ret = XFER_NAKED; | |
803 | } | |
804 | i2c_pxa_master_complete(i2c, ret); | |
805 | } else if (isr & ISR_RWM) { | |
806 | /* | |
807 | * Read mode. We have just sent the address byte, and | |
808 | * now we must initiate the transfer. | |
809 | */ | |
810 | if (i2c->msg_ptr == i2c->msg->len - 1 && | |
811 | i2c->msg_idx == i2c->msg_num - 1) | |
812 | icr |= ICR_STOP | ICR_ACKNAK; | |
813 | ||
814 | icr |= ICR_ALDIE | ICR_TB; | |
815 | } else if (i2c->msg_ptr < i2c->msg->len) { | |
816 | /* | |
817 | * Write mode. Write the next data byte. | |
818 | */ | |
a7b4e550 | 819 | writel(i2c->msg->buf[i2c->msg_ptr++], _IDBR(i2c)); |
b652b438 RK |
820 | |
821 | icr |= ICR_ALDIE | ICR_TB; | |
822 | ||
823 | /* | |
824 | * If this is the last byte of the last message, send | |
825 | * a STOP. | |
826 | */ | |
827 | if (i2c->msg_ptr == i2c->msg->len && | |
828 | i2c->msg_idx == i2c->msg_num - 1) | |
829 | icr |= ICR_STOP; | |
830 | } else if (i2c->msg_idx < i2c->msg_num - 1) { | |
831 | /* | |
832 | * Next segment of the message. | |
833 | */ | |
834 | i2c->msg_ptr = 0; | |
835 | i2c->msg_idx ++; | |
836 | i2c->msg++; | |
837 | ||
838 | /* | |
839 | * If we aren't doing a repeated start and address, | |
840 | * go back and try to send the next byte. Note that | |
841 | * we do not support switching the R/W direction here. | |
842 | */ | |
843 | if (i2c->msg->flags & I2C_M_NOSTART) | |
844 | goto again; | |
845 | ||
846 | /* | |
847 | * Write the next address. | |
848 | */ | |
a7b4e550 | 849 | writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c)); |
b652b438 RK |
850 | |
851 | /* | |
852 | * And trigger a repeated start, and send the byte. | |
853 | */ | |
854 | icr &= ~ICR_ALDIE; | |
855 | icr |= ICR_START | ICR_TB; | |
856 | } else { | |
857 | if (i2c->msg->len == 0) { | |
858 | /* | |
859 | * Device probes have a message length of zero | |
860 | * and need the bus to be reset before it can | |
861 | * be used again. | |
862 | */ | |
863 | i2c_pxa_reset(i2c); | |
864 | } | |
865 | i2c_pxa_master_complete(i2c, 0); | |
866 | } | |
867 | ||
868 | i2c->icrlog[i2c->irqlogidx-1] = icr; | |
869 | ||
a7b4e550 | 870 | writel(icr, _ICR(i2c)); |
b652b438 RK |
871 | show_state(i2c); |
872 | } | |
873 | ||
874 | static void i2c_pxa_irq_rxfull(struct pxa_i2c *i2c, u32 isr) | |
875 | { | |
a7b4e550 | 876 | u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB); |
b652b438 RK |
877 | |
878 | /* | |
879 | * Read the byte. | |
880 | */ | |
a7b4e550 | 881 | i2c->msg->buf[i2c->msg_ptr++] = readl(_IDBR(i2c)); |
b652b438 RK |
882 | |
883 | if (i2c->msg_ptr < i2c->msg->len) { | |
884 | /* | |
885 | * If this is the last byte of the last | |
886 | * message, send a STOP. | |
887 | */ | |
888 | if (i2c->msg_ptr == i2c->msg->len - 1) | |
889 | icr |= ICR_STOP | ICR_ACKNAK; | |
890 | ||
891 | icr |= ICR_ALDIE | ICR_TB; | |
892 | } else { | |
893 | i2c_pxa_master_complete(i2c, 0); | |
894 | } | |
895 | ||
896 | i2c->icrlog[i2c->irqlogidx-1] = icr; | |
897 | ||
a7b4e550 | 898 | writel(icr, _ICR(i2c)); |
b652b438 RK |
899 | } |
900 | ||
7d12e780 | 901 | static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id) |
b652b438 RK |
902 | { |
903 | struct pxa_i2c *i2c = dev_id; | |
a7b4e550 | 904 | u32 isr = readl(_ISR(i2c)); |
b652b438 RK |
905 | |
906 | if (i2c_debug > 2 && 0) { | |
6fd60fa9 | 907 | dev_dbg(&i2c->adap.dev, "%s: ISR=%08x, ICR=%08x, IBMR=%02x\n", |
a7b4e550 | 908 | __func__, isr, readl(_ICR(i2c)), readl(_IBMR(i2c))); |
b652b438 RK |
909 | decode_ISR(isr); |
910 | } | |
911 | ||
7e3d7db5 | 912 | if (i2c->irqlogidx < ARRAY_SIZE(i2c->isrlog)) |
b652b438 RK |
913 | i2c->isrlog[i2c->irqlogidx++] = isr; |
914 | ||
915 | show_state(i2c); | |
916 | ||
917 | /* | |
918 | * Always clear all pending IRQs. | |
919 | */ | |
a7b4e550 | 920 | writel(isr & (ISR_SSD|ISR_ALD|ISR_ITE|ISR_IRF|ISR_SAD|ISR_BED), _ISR(i2c)); |
b652b438 RK |
921 | |
922 | if (isr & ISR_SAD) | |
923 | i2c_pxa_slave_start(i2c, isr); | |
924 | if (isr & ISR_SSD) | |
925 | i2c_pxa_slave_stop(i2c); | |
926 | ||
927 | if (i2c_pxa_is_slavemode(i2c)) { | |
928 | if (isr & ISR_ITE) | |
929 | i2c_pxa_slave_txempty(i2c, isr); | |
930 | if (isr & ISR_IRF) | |
931 | i2c_pxa_slave_rxfull(i2c, isr); | |
932 | } else if (i2c->msg) { | |
933 | if (isr & ISR_ITE) | |
934 | i2c_pxa_irq_txempty(i2c, isr); | |
935 | if (isr & ISR_IRF) | |
936 | i2c_pxa_irq_rxfull(i2c, isr); | |
937 | } else { | |
938 | i2c_pxa_scream_blue_murder(i2c, "spurious irq"); | |
939 | } | |
940 | ||
941 | return IRQ_HANDLED; | |
942 | } | |
943 | ||
944 | ||
945 | static int i2c_pxa_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) | |
946 | { | |
947 | struct pxa_i2c *i2c = adap->algo_data; | |
948 | int ret, i; | |
949 | ||
950 | for (i = adap->retries; i >= 0; i--) { | |
951 | ret = i2c_pxa_do_xfer(i2c, msgs, num); | |
952 | if (ret != I2C_RETRY) | |
953 | goto out; | |
954 | ||
955 | if (i2c_debug) | |
6fd60fa9 | 956 | dev_dbg(&adap->dev, "Retrying transmission\n"); |
b652b438 RK |
957 | udelay(100); |
958 | } | |
959 | i2c_pxa_scream_blue_murder(i2c, "exhausted retries"); | |
960 | ret = -EREMOTEIO; | |
961 | out: | |
962 | i2c_pxa_set_slave(i2c, ret); | |
963 | return ret; | |
964 | } | |
965 | ||
da16e324 RK |
966 | static u32 i2c_pxa_functionality(struct i2c_adapter *adap) |
967 | { | |
968 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; | |
969 | } | |
970 | ||
8f9082c5 | 971 | static const struct i2c_algorithm i2c_pxa_algorithm = { |
b652b438 | 972 | .master_xfer = i2c_pxa_xfer, |
da16e324 | 973 | .functionality = i2c_pxa_functionality, |
b652b438 RK |
974 | }; |
975 | ||
b7a36701 MR |
976 | static const struct i2c_algorithm i2c_pxa_pio_algorithm = { |
977 | .master_xfer = i2c_pxa_pio_xfer, | |
978 | .functionality = i2c_pxa_functionality, | |
979 | }; | |
980 | ||
a7b4e550 | 981 | #define res_len(r) ((r)->end - (r)->start + 1) |
3ae5eaec | 982 | static int i2c_pxa_probe(struct platform_device *dev) |
b652b438 | 983 | { |
6776f3d2 | 984 | struct pxa_i2c *i2c; |
a7b4e550 | 985 | struct resource *res; |
3ae5eaec | 986 | struct i2c_pxa_platform_data *plat = dev->dev.platform_data; |
b652b438 | 987 | int ret; |
a7b4e550 | 988 | int irq; |
b652b438 | 989 | |
a7b4e550 GL |
990 | res = platform_get_resource(dev, IORESOURCE_MEM, 0); |
991 | irq = platform_get_irq(dev, 0); | |
992 | if (res == NULL || irq < 0) | |
993 | return -ENODEV; | |
994 | ||
995 | if (!request_mem_region(res->start, res_len(res), res->name)) | |
996 | return -ENOMEM; | |
997 | ||
6776f3d2 | 998 | i2c = kzalloc(sizeof(struct pxa_i2c), GFP_KERNEL); |
a7b4e550 GL |
999 | if (!i2c) { |
1000 | ret = -ENOMEM; | |
1001 | goto emalloc; | |
1002 | } | |
1003 | ||
6776f3d2 | 1004 | i2c->adap.owner = THIS_MODULE; |
6776f3d2 ES |
1005 | i2c->adap.retries = 5; |
1006 | ||
1007 | spin_lock_init(&i2c->lock); | |
a7b4e550 | 1008 | init_waitqueue_head(&i2c->wait); |
6776f3d2 | 1009 | |
a92b36ed WS |
1010 | /* |
1011 | * If "dev->id" is negative we consider it as zero. | |
1012 | * The reason to do so is to avoid sysfs names that only make | |
1013 | * sense when there are multiple adapters. | |
1014 | */ | |
1015 | i2c->adap.nr = dev->id != -1 ? dev->id : 0; | |
1016 | snprintf(i2c->adap.name, sizeof(i2c->adap.name), "pxa_i2c-i2c.%u", | |
1017 | i2c->adap.nr); | |
a7b4e550 | 1018 | |
e0d8b13a | 1019 | i2c->clk = clk_get(&dev->dev, NULL); |
c3cef3f3 RK |
1020 | if (IS_ERR(i2c->clk)) { |
1021 | ret = PTR_ERR(i2c->clk); | |
1022 | goto eclk; | |
1023 | } | |
1024 | ||
a7b4e550 GL |
1025 | i2c->reg_base = ioremap(res->start, res_len(res)); |
1026 | if (!i2c->reg_base) { | |
1027 | ret = -EIO; | |
1028 | goto eremap; | |
1029 | } | |
9ba63c4f | 1030 | i2c->reg_shift = (cpu_is_pxa3xx() && (dev->id == 1)) ? 0 : 1; |
a7b4e550 GL |
1031 | |
1032 | i2c->iobase = res->start; | |
1033 | i2c->iosize = res_len(res); | |
1034 | ||
1035 | i2c->irq = irq; | |
b652b438 RK |
1036 | |
1037 | i2c->slave_addr = I2C_PXA_SLAVE_ADDR; | |
1038 | ||
1039 | #ifdef CONFIG_I2C_PXA_SLAVE | |
b652b438 RK |
1040 | if (plat) { |
1041 | i2c->slave_addr = plat->slave_addr; | |
beea494d | 1042 | i2c->slave = plat->slave; |
b652b438 RK |
1043 | } |
1044 | #endif | |
1045 | ||
c3cef3f3 | 1046 | clk_enable(i2c->clk); |
a7b4e550 | 1047 | |
b7a36701 MR |
1048 | if (plat) { |
1049 | i2c->adap.class = plat->class; | |
1050 | i2c->use_pio = plat->use_pio; | |
c46c9482 | 1051 | i2c->fast_mode = plat->fast_mode; |
b7a36701 MR |
1052 | } |
1053 | ||
1054 | if (i2c->use_pio) { | |
1055 | i2c->adap.algo = &i2c_pxa_pio_algorithm; | |
1056 | } else { | |
1057 | i2c->adap.algo = &i2c_pxa_algorithm; | |
1058 | ret = request_irq(irq, i2c_pxa_handler, IRQF_DISABLED, | |
1059 | i2c->adap.name, i2c); | |
1060 | if (ret) | |
1061 | goto ereqirq; | |
1062 | } | |
a7b4e550 | 1063 | |
b652b438 RK |
1064 | i2c_pxa_reset(i2c); |
1065 | ||
1066 | i2c->adap.algo_data = i2c; | |
3ae5eaec | 1067 | i2c->adap.dev.parent = &dev->dev; |
b652b438 | 1068 | |
066af983 | 1069 | ret = i2c_add_numbered_adapter(&i2c->adap); |
b652b438 RK |
1070 | if (ret < 0) { |
1071 | printk(KERN_INFO "I2C: Failed to add bus\n"); | |
a7b4e550 | 1072 | goto eadapt; |
b652b438 RK |
1073 | } |
1074 | ||
3ae5eaec | 1075 | platform_set_drvdata(dev, i2c); |
b652b438 RK |
1076 | |
1077 | #ifdef CONFIG_I2C_PXA_SLAVE | |
1078 | printk(KERN_INFO "I2C: %s: PXA I2C adapter, slave address %d\n", | |
22e965c2 | 1079 | dev_name(&i2c->adap.dev), i2c->slave_addr); |
b652b438 RK |
1080 | #else |
1081 | printk(KERN_INFO "I2C: %s: PXA I2C adapter\n", | |
22e965c2 | 1082 | dev_name(&i2c->adap.dev)); |
b652b438 RK |
1083 | #endif |
1084 | return 0; | |
1085 | ||
a7b4e550 | 1086 | eadapt: |
b7a36701 MR |
1087 | if (!i2c->use_pio) |
1088 | free_irq(irq, i2c); | |
a7b4e550 | 1089 | ereqirq: |
c3cef3f3 | 1090 | clk_disable(i2c->clk); |
a92b36ed | 1091 | iounmap(i2c->reg_base); |
a7b4e550 | 1092 | eremap: |
c3cef3f3 RK |
1093 | clk_put(i2c->clk); |
1094 | eclk: | |
a7b4e550 GL |
1095 | kfree(i2c); |
1096 | emalloc: | |
1097 | release_mem_region(res->start, res_len(res)); | |
b652b438 RK |
1098 | return ret; |
1099 | } | |
1100 | ||
a92b36ed | 1101 | static int __exit i2c_pxa_remove(struct platform_device *dev) |
b652b438 | 1102 | { |
3ae5eaec | 1103 | struct pxa_i2c *i2c = platform_get_drvdata(dev); |
b652b438 | 1104 | |
3ae5eaec | 1105 | platform_set_drvdata(dev, NULL); |
b652b438 RK |
1106 | |
1107 | i2c_del_adapter(&i2c->adap); | |
b7a36701 MR |
1108 | if (!i2c->use_pio) |
1109 | free_irq(i2c->irq, i2c); | |
c3cef3f3 RK |
1110 | |
1111 | clk_disable(i2c->clk); | |
1112 | clk_put(i2c->clk); | |
c3cef3f3 | 1113 | |
a92b36ed | 1114 | iounmap(i2c->reg_base); |
a7b4e550 GL |
1115 | release_mem_region(i2c->iobase, i2c->iosize); |
1116 | kfree(i2c); | |
b652b438 RK |
1117 | |
1118 | return 0; | |
1119 | } | |
1120 | ||
e7d48fa2 RK |
1121 | #ifdef CONFIG_PM |
1122 | static int i2c_pxa_suspend_late(struct platform_device *dev, pm_message_t state) | |
1123 | { | |
1124 | struct pxa_i2c *i2c = platform_get_drvdata(dev); | |
1125 | clk_disable(i2c->clk); | |
1126 | return 0; | |
1127 | } | |
1128 | ||
1129 | static int i2c_pxa_resume_early(struct platform_device *dev) | |
1130 | { | |
1131 | struct pxa_i2c *i2c = platform_get_drvdata(dev); | |
1132 | ||
1133 | clk_enable(i2c->clk); | |
1134 | i2c_pxa_reset(i2c); | |
1135 | ||
1136 | return 0; | |
1137 | } | |
1138 | #else | |
1139 | #define i2c_pxa_suspend_late NULL | |
1140 | #define i2c_pxa_resume_early NULL | |
1141 | #endif | |
1142 | ||
3ae5eaec | 1143 | static struct platform_driver i2c_pxa_driver = { |
b652b438 | 1144 | .probe = i2c_pxa_probe, |
a92b36ed | 1145 | .remove = __exit_p(i2c_pxa_remove), |
e7d48fa2 RK |
1146 | .suspend_late = i2c_pxa_suspend_late, |
1147 | .resume_early = i2c_pxa_resume_early, | |
3ae5eaec RK |
1148 | .driver = { |
1149 | .name = "pxa2xx-i2c", | |
a92b36ed | 1150 | .owner = THIS_MODULE, |
3ae5eaec | 1151 | }, |
b652b438 RK |
1152 | }; |
1153 | ||
1154 | static int __init i2c_adap_pxa_init(void) | |
1155 | { | |
3ae5eaec | 1156 | return platform_driver_register(&i2c_pxa_driver); |
b652b438 RK |
1157 | } |
1158 | ||
a92b36ed | 1159 | static void __exit i2c_adap_pxa_exit(void) |
b652b438 | 1160 | { |
d6a7b5f8 | 1161 | platform_driver_unregister(&i2c_pxa_driver); |
b652b438 RK |
1162 | } |
1163 | ||
ece5f7b3 | 1164 | MODULE_LICENSE("GPL"); |
add8eda7 | 1165 | MODULE_ALIAS("platform:pxa2xx-i2c"); |
ece5f7b3 | 1166 | |
47a9b137 | 1167 | subsys_initcall(i2c_adap_pxa_init); |
b652b438 | 1168 | module_exit(i2c_adap_pxa_exit); |