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[ARM] Move processor_modes[] to .../process.c
[linux-block.git] / drivers / i2c / busses / i2c-pxa.c
CommitLineData
b652b438
RK		 1/*
2 * i2c_adap_pxa.c
3 *
4 * I2C adapter for the PXA I2C bus access.
5 *
6 * Copyright (C) 2002 Intrinsyc Software Inc.
7 * Copyright (C) 2004-2005 Deep Blue Solutions Ltd.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * History:
14 * Apr 2002: Initial version [CS]
15 * Jun 2002: Properly seperated algo/adap [FB]
16 * Jan 2003: Fixed several bugs concerning interrupt handling [Kai-Uwe Bloem]
17 * Jan 2003: added limited signal handling [Kai-Uwe Bloem]
18 * Sep 2004: Major rework to ensure efficient bus handling [RMK]
19 * Dec 2004: Added support for PXA27x and slave device probing [Liam Girdwood]
20 * Feb 2005: Rework slave mode handling [RMK]
21 */
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/i2c.h>
25#include <linux/i2c-id.h>
26#include <linux/init.h>
27#include <linux/time.h>
28#include <linux/sched.h>
29#include <linux/delay.h>
30#include <linux/errno.h>
31#include <linux/interrupt.h>
32#include <linux/i2c-pxa.h>
d052d1be 33#include <linux/platform_device.h>
b652b438
RK		 34
35#include <asm/hardware.h>
36#include <asm/irq.h>
37#include <asm/arch/i2c.h>
38#include <asm/arch/pxa-regs.h>
39
40struct pxa_i2c {
41 spinlock_t lock;
42 wait_queue_head_t wait;
43 struct i2c_msg *msg;
44 unsigned int msg_num;
45 unsigned int msg_idx;
46 unsigned int msg_ptr;
47 unsigned int slave_addr;
48
49 struct i2c_adapter adap;
50#ifdef CONFIG_I2C_PXA_SLAVE
51 struct i2c_slave_client *slave;
52#endif
53
54 unsigned int irqlogidx;
55 u32 isrlog[32];
56 u32 icrlog[32];
57};
58
59/*
60 * I2C Slave mode address
61 */
62#define I2C_PXA_SLAVE_ADDR 0x1
63
b652b438
RK		 64#ifdef DEBUG
65
66struct bits {
67 u32 mask;
68 const char *set;
69 const char *unset;
70};
71#define BIT(m, s, u) { .mask = m, .set = s, .unset = u }
72
73static inline void
74decode_bits(const char *prefix, const struct bits *bits, int num, u32 val)
75{
76 printk("%s %08x: ", prefix, val);
77 while (num--) {
78 const char *str = val & bits->mask ? bits->set : bits->unset;
79 if (str)
80 printk("%s ", str);
81 bits++;
82 }
83}
84
85static const struct bits isr_bits[] = {
86 BIT(ISR_RWM, "RX", "TX"),
87 BIT(ISR_ACKNAK, "NAK", "ACK"),
88 BIT(ISR_UB, "Bsy", "Rdy"),
89 BIT(ISR_IBB, "BusBsy", "BusRdy"),
90 BIT(ISR_SSD, "SlaveStop", NULL),
91 BIT(ISR_ALD, "ALD", NULL),
92 BIT(ISR_ITE, "TxEmpty", NULL),
93 BIT(ISR_IRF, "RxFull", NULL),
94 BIT(ISR_GCAD, "GenCall", NULL),
95 BIT(ISR_SAD, "SlaveAddr", NULL),
96 BIT(ISR_BED, "BusErr", NULL),
97};
98
99static void decode_ISR(unsigned int val)
100{
6fd60fa9 101 decode_bits(KERN_DEBUG "ISR", isr_bits, ARRAY_SIZE(isr_bits), val);
b652b438
RK		 102 printk("\n");
103}
104
105static const struct bits icr_bits[] = {
106 BIT(ICR_START, "START", NULL),
107 BIT(ICR_STOP, "STOP", NULL),
108 BIT(ICR_ACKNAK, "ACKNAK", NULL),
109 BIT(ICR_TB, "TB", NULL),
110 BIT(ICR_MA, "MA", NULL),
111 BIT(ICR_SCLE, "SCLE", "scle"),
112 BIT(ICR_IUE, "IUE", "iue"),
113 BIT(ICR_GCD, "GCD", NULL),
114 BIT(ICR_ITEIE, "ITEIE", NULL),
115 BIT(ICR_IRFIE, "IRFIE", NULL),
116 BIT(ICR_BEIE, "BEIE", NULL),
117 BIT(ICR_SSDIE, "SSDIE", NULL),
118 BIT(ICR_ALDIE, "ALDIE", NULL),
119 BIT(ICR_SADIE, "SADIE", NULL),
120 BIT(ICR_UR, "UR", "ur"),
121};
122
123static void decode_ICR(unsigned int val)
124{
6fd60fa9 125 decode_bits(KERN_DEBUG "ICR", icr_bits, ARRAY_SIZE(icr_bits), val);
b652b438
RK		 126 printk("\n");
127}
128
129static unsigned int i2c_debug = DEBUG;
130
131static void i2c_pxa_show_state(struct pxa_i2c *i2c, int lno, const char *fname)
132{
6fd60fa9 133 dev_dbg(&i2c->adap.dev, "state:%s:%d: ISR=%08x, ICR=%08x, IBMR=%02x\n", fname, lno, ISR, ICR, IBMR);
b652b438
RK		 134}
135
136#define show_state(i2c) i2c_pxa_show_state(i2c, __LINE__, __FUNCTION__)
137#else
138#define i2c_debug 0
139
140#define show_state(i2c) do { } while (0)
141#define decode_ISR(val) do { } while (0)
142#define decode_ICR(val) do { } while (0)
143#endif
144
6fd60fa9 145#define eedbg(lvl, x...) do { if ((lvl) < 1) { printk(KERN_DEBUG "" x); } } while(0)
b652b438
RK		 146
147static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret);
148
149static void i2c_pxa_scream_blue_murder(struct pxa_i2c *i2c, const char *why)
150{
151 unsigned int i;
152 printk("i2c: error: %s\n", why);
153 printk("i2c: msg_num: %d msg_idx: %d msg_ptr: %d\n",
154 i2c->msg_num, i2c->msg_idx, i2c->msg_ptr);
6fd60fa9
RK		 155 printk("i2c: ICR: %08x ISR: %08x\n"
156 "i2c: log: ", ICR, ISR);
b652b438
RK		 157 for (i = 0; i < i2c->irqlogidx; i++)
158 printk("[%08x:%08x] ", i2c->isrlog[i], i2c->icrlog[i]);
159 printk("\n");
160}
161
162static inline int i2c_pxa_is_slavemode(struct pxa_i2c *i2c)
163{
164 return !(ICR & ICR_SCLE);
165}
166
167static void i2c_pxa_abort(struct pxa_i2c *i2c)
168{
169 unsigned long timeout = jiffies + HZ/4;
170
171 if (i2c_pxa_is_slavemode(i2c)) {
6fd60fa9 172 dev_dbg(&i2c->adap.dev, "%s: called in slave mode\n", __func__);
b652b438
RK		 173 return;
174 }
175
176 while (time_before(jiffies, timeout) && (IBMR & 0x1) == 0) {
177 unsigned long icr = ICR;
178
179 icr &= ~ICR_START;
180 icr |= ICR_ACKNAK | ICR_STOP | ICR_TB;
181
182 ICR = icr;
183
184 show_state(i2c);
185
186 msleep(1);
187 }
188
189 ICR &= ~(ICR_MA | ICR_START | ICR_STOP);
190}
191
192static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c *i2c)
193{
194 int timeout = DEF_TIMEOUT;
195
196 while (timeout-- && ISR & (ISR_IBB | ISR_UB)) {
197 if ((ISR & ISR_SAD) != 0)
198 timeout += 4;
199
200 msleep(2);
201 show_state(i2c);
202 }
203
204 if (timeout <= 0)
205 show_state(i2c);
206
207 return timeout <= 0 ? I2C_RETRY : 0;
208}
209
210static int i2c_pxa_wait_master(struct pxa_i2c *i2c)
211{
212 unsigned long timeout = jiffies + HZ*4;
213
214 while (time_before(jiffies, timeout)) {
215 if (i2c_debug > 1)
6fd60fa9
RK		 216 dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
217 __func__, (long)jiffies, ISR, ICR, IBMR);
b652b438
RK		 218
219 if (ISR & ISR_SAD) {
220 if (i2c_debug > 0)
6fd60fa9 221 dev_dbg(&i2c->adap.dev, "%s: Slave detected\n", __func__);
b652b438
RK		 222 goto out;
223 }
224
225 /* wait for unit and bus being not busy, and we also do a
226 * quick check of the i2c lines themselves to ensure they've
227 * gone high...
228 */
229 if ((ISR & (ISR_UB | ISR_IBB)) == 0 && IBMR == 3) {
230 if (i2c_debug > 0)
6fd60fa9 231 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
b652b438
RK		 232 return 1;
233 }
234
235 msleep(1);
236 }
237
238 if (i2c_debug > 0)
6fd60fa9 239 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
b652b438
RK		 240 out:
241 return 0;
242}
243
244static int i2c_pxa_set_master(struct pxa_i2c *i2c)
245{
246 if (i2c_debug)
6fd60fa9 247 dev_dbg(&i2c->adap.dev, "setting to bus master\n");
b652b438
RK		 248
249 if ((ISR & (ISR_UB | ISR_IBB)) != 0) {
6fd60fa9 250 dev_dbg(&i2c->adap.dev, "%s: unit is busy\n", __func__);
b652b438 251 if (!i2c_pxa_wait_master(i2c)) {
6fd60fa9 252 dev_dbg(&i2c->adap.dev, "%s: error: unit busy\n", __func__);
b652b438
RK		 253 return I2C_RETRY;
254 }
255 }
256
257 ICR |= ICR_SCLE;
258 return 0;
259}
260
261#ifdef CONFIG_I2C_PXA_SLAVE
262static int i2c_pxa_wait_slave(struct pxa_i2c *i2c)
263{
264 unsigned long timeout = jiffies + HZ*1;
265
266 /* wait for stop */
267
268 show_state(i2c);
269
270 while (time_before(jiffies, timeout)) {
271 if (i2c_debug > 1)
6fd60fa9
RK		 272 dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
273 __func__, (long)jiffies, ISR, ICR, IBMR);
b652b438 274
84b5abe6
RK		 275 if ((ISR & (ISR_UB|ISR_IBB)) == 0 ||
276 (ISR & ISR_SAD) != 0 ||
b652b438
RK		 277 (ICR & ICR_SCLE) == 0) {
278 if (i2c_debug > 1)
6fd60fa9 279 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
b652b438
RK		 280 return 1;
281 }
282
283 msleep(1);
284 }
285
286 if (i2c_debug > 0)
6fd60fa9 287 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
b652b438
RK		 288 return 0;
289}
290
291/*
292 * clear the hold on the bus, and take of anything else
293 * that has been configured
294 */
295static void i2c_pxa_set_slave(struct pxa_i2c *i2c, int errcode)
296{
297 show_state(i2c);
298
299 if (errcode < 0) {
300 udelay(100); /* simple delay */
301 } else {
302 /* we need to wait for the stop condition to end */
303
304 /* if we where in stop, then clear... */
305 if (ICR & ICR_STOP) {
306 udelay(100);
307 ICR &= ~ICR_STOP;
308 }
309
310 if (!i2c_pxa_wait_slave(i2c)) {
6fd60fa9
RK		 311 dev_err(&i2c->adap.dev, "%s: wait timedout\n",
312 __func__);
b652b438
RK		 313 return;
314 }
315 }
316
317 ICR &= ~(ICR_STOP|ICR_ACKNAK|ICR_MA);
318 ICR &= ~ICR_SCLE;
319
320 if (i2c_debug) {
6fd60fa9 321 dev_dbg(&i2c->adap.dev, "ICR now %08x, ISR %08x\n", ICR, ISR);
b652b438
RK		 322 decode_ICR(ICR);
323 }
324}
325#else
326#define i2c_pxa_set_slave(i2c, err) do { } while (0)
327#endif
328
329static void i2c_pxa_reset(struct pxa_i2c *i2c)
330{
331 pr_debug("Resetting I2C Controller Unit\n");
332
333 /* abort any transfer currently under way */
334 i2c_pxa_abort(i2c);
335
336 /* reset according to 9.8 */
337 ICR = ICR_UR;
338 ISR = I2C_ISR_INIT;
339 ICR &= ~ICR_UR;
340
341 ISAR = i2c->slave_addr;
342
343 /* set control register values */
344 ICR = I2C_ICR_INIT;
345
346#ifdef CONFIG_I2C_PXA_SLAVE
6fd60fa9 347 dev_info(&i2c->adap.dev, "Enabling slave mode\n");
b652b438
RK		 348 ICR |= ICR_SADIE | ICR_ALDIE | ICR_SSDIE;
349#endif
350
351 i2c_pxa_set_slave(i2c, 0);
352
353 /* enable unit */
354 ICR |= ICR_IUE;
355 udelay(100);
356}
357
358
359#ifdef CONFIG_I2C_PXA_SLAVE
b652b438
RK		 360/*
361 * PXA I2C Slave mode
362 */
363
364static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
365{
366 if (isr & ISR_BED) {
367 /* what should we do here? */
368 } else {
84b5abe6
RK		 369 int ret = 0;
370
371 if (i2c->slave != NULL)
372 ret = i2c->slave->read(i2c->slave->data);
b652b438
RK		 373
374 IDBR = ret;
375 ICR |= ICR_TB; /* allow next byte */
376 }
377}
378
379static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
380{
381 unsigned int byte = IDBR;
382
383 if (i2c->slave != NULL)
384 i2c->slave->write(i2c->slave->data, byte);
385
386 ICR |= ICR_TB;
387}
388
389static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
390{
391 int timeout;
392
393 if (i2c_debug > 0)
6fd60fa9 394 dev_dbg(&i2c->adap.dev, "SAD, mode is slave-%cx\n",
b652b438
RK		 395 (isr & ISR_RWM) ? 'r' : 't');
396
397 if (i2c->slave != NULL)
398 i2c->slave->event(i2c->slave->data,
399 (isr & ISR_RWM) ? I2C_SLAVE_EVENT_START_READ : I2C_SLAVE_EVENT_START_WRITE);
400
401 /*
402 * slave could interrupt in the middle of us generating a
403 * start condition... if this happens, we'd better back off
404 * and stop holding the poor thing up
405 */
406 ICR &= ~(ICR_START|ICR_STOP);
407 ICR |= ICR_TB;
408
409 timeout = 0x10000;
410
411 while (1) {
412 if ((IBMR & 2) == 2)
413 break;
414
415 timeout--;
416
417 if (timeout <= 0) {
6fd60fa9 418 dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
b652b438
RK		 419 break;
420 }
421 }
422
423 ICR &= ~ICR_SCLE;
424}
425
426static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
427{
428 if (i2c_debug > 2)
6fd60fa9 429 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop)\n");
b652b438
RK		 430
431 if (i2c->slave != NULL)
432 i2c->slave->event(i2c->slave->data, I2C_SLAVE_EVENT_STOP);
433
434 if (i2c_debug > 2)
6fd60fa9 435 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop) acked\n");
b652b438
RK		 436
437 /*
438 * If we have a master-mode message waiting,
439 * kick it off now that the slave has completed.
440 */
441 if (i2c->msg)
442 i2c_pxa_master_complete(i2c, I2C_RETRY);
443}
444#else
445static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
446{
447 if (isr & ISR_BED) {
448 /* what should we do here? */
449 } else {
450 IDBR = 0;
451 ICR |= ICR_TB;
452 }
453}
454
455static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
456{
457 ICR |= ICR_TB | ICR_ACKNAK;
458}
459
460static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
461{
462 int timeout;
463
464 /*
465 * slave could interrupt in the middle of us generating a
466 * start condition... if this happens, we'd better back off
467 * and stop holding the poor thing up
468 */
469 ICR &= ~(ICR_START|ICR_STOP);
470 ICR |= ICR_TB | ICR_ACKNAK;
471
472 timeout = 0x10000;
473
474 while (1) {
475 if ((IBMR & 2) == 2)
476 break;
477
478 timeout--;
479
480 if (timeout <= 0) {
6fd60fa9 481 dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
b652b438
RK		 482 break;
483 }
484 }
485
486 ICR &= ~ICR_SCLE;
487}
488
489static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
490{
491 if (i2c->msg)
492 i2c_pxa_master_complete(i2c, I2C_RETRY);
493}
494#endif
495
496/*
497 * PXA I2C Master mode
498 */
499
500static inline unsigned int i2c_pxa_addr_byte(struct i2c_msg *msg)
501{
502 unsigned int addr = (msg->addr & 0x7f) << 1;
503
504 if (msg->flags & I2C_M_RD)
505 addr |= 1;
506
507 return addr;
508}
509
510static inline void i2c_pxa_start_message(struct pxa_i2c *i2c)
511{
512 u32 icr;
513
514 /*
515 * Step 1: target slave address into IDBR
516 */
517 IDBR = i2c_pxa_addr_byte(i2c->msg);
518
519 /*
520 * Step 2: initiate the write.
521 */
522 icr = ICR & ~(ICR_STOP | ICR_ALDIE);
523 ICR = icr | ICR_START | ICR_TB;
524}
525
526/*
3fb9a655 527 * We are protected by the adapter bus mutex.
b652b438
RK		 528 */
529static int i2c_pxa_do_xfer(struct pxa_i2c *i2c, struct i2c_msg *msg, int num)
530{
531 long timeout;
532 int ret;
533
534 /*
535 * Wait for the bus to become free.
536 */
537 ret = i2c_pxa_wait_bus_not_busy(i2c);
538 if (ret) {
6fd60fa9 539 dev_err(&i2c->adap.dev, "i2c_pxa: timeout waiting for bus free\n");
b652b438
RK		 540 goto out;
541 }
542
543 /*
544 * Set master mode.
545 */
546 ret = i2c_pxa_set_master(i2c);
547 if (ret) {
6fd60fa9 548 dev_err(&i2c->adap.dev, "i2c_pxa_set_master: error %d\n", ret);
b652b438
RK		 549 goto out;
550 }
551
552 spin_lock_irq(&i2c->lock);
553
554 i2c->msg = msg;
555 i2c->msg_num = num;
556 i2c->msg_idx = 0;
557 i2c->msg_ptr = 0;
558 i2c->irqlogidx = 0;
559
560 i2c_pxa_start_message(i2c);
561
562 spin_unlock_irq(&i2c->lock);
563
564 /*
565 * The rest of the processing occurs in the interrupt handler.
566 */
567 timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
568
569 /*
570 * We place the return code in i2c->msg_idx.
571 */
572 ret = i2c->msg_idx;
573
574 if (timeout == 0)
575 i2c_pxa_scream_blue_murder(i2c, "timeout");
576
577 out:
578 return ret;
579}
580
581/*
582 * i2c_pxa_master_complete - complete the message and wake up.
583 */
584static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret)
585{
586 i2c->msg_ptr = 0;
587 i2c->msg = NULL;
588 i2c->msg_idx ++;
589 i2c->msg_num = 0;
590 if (ret)
591 i2c->msg_idx = ret;
592 wake_up(&i2c->wait);
593}
594
595static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr)
596{
597 u32 icr = ICR & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
598
599 again:
600 /*
601 * If ISR_ALD is set, we lost arbitration.
602 */
603 if (isr & ISR_ALD) {
604 /*
605 * Do we need to do anything here? The PXA docs
606 * are vague about what happens.
607 */
608 i2c_pxa_scream_blue_murder(i2c, "ALD set");
609
610 /*
611 * We ignore this error. We seem to see spurious ALDs
612 * for seemingly no reason. If we handle them as I think
613 * they should, we end up causing an I2C error, which
614 * is painful for some systems.
615 */
616 return; /* ignore */
617 }
618
619 if (isr & ISR_BED) {
620 int ret = BUS_ERROR;
621
622 /*
623 * I2C bus error - either the device NAK'd us, or
624 * something more serious happened. If we were NAK'd
625 * on the initial address phase, we can retry.
626 */
627 if (isr & ISR_ACKNAK) {
628 if (i2c->msg_ptr == 0 && i2c->msg_idx == 0)
629 ret = I2C_RETRY;
630 else
631 ret = XFER_NAKED;
632 }
633 i2c_pxa_master_complete(i2c, ret);
634 } else if (isr & ISR_RWM) {
635 /*
636 * Read mode. We have just sent the address byte, and
637 * now we must initiate the transfer.
638 */
639 if (i2c->msg_ptr == i2c->msg->len - 1 &&
640 i2c->msg_idx == i2c->msg_num - 1)
641 icr |= ICR_STOP | ICR_ACKNAK;
642
643 icr |= ICR_ALDIE | ICR_TB;
644 } else if (i2c->msg_ptr < i2c->msg->len) {
645 /*
646 * Write mode. Write the next data byte.
647 */
648 IDBR = i2c->msg->buf[i2c->msg_ptr++];
649
650 icr |= ICR_ALDIE | ICR_TB;
651
652 /*
653 * If this is the last byte of the last message, send
654 * a STOP.
655 */
656 if (i2c->msg_ptr == i2c->msg->len &&
657 i2c->msg_idx == i2c->msg_num - 1)
658 icr |= ICR_STOP;
659 } else if (i2c->msg_idx < i2c->msg_num - 1) {
660 /*
661 * Next segment of the message.
662 */
663 i2c->msg_ptr = 0;
664 i2c->msg_idx ++;
665 i2c->msg++;
666
667 /*
668 * If we aren't doing a repeated start and address,
669 * go back and try to send the next byte. Note that
670 * we do not support switching the R/W direction here.
671 */
672 if (i2c->msg->flags & I2C_M_NOSTART)
673 goto again;
674
675 /*
676 * Write the next address.
677 */
678 IDBR = i2c_pxa_addr_byte(i2c->msg);
679
680 /*
681 * And trigger a repeated start, and send the byte.
682 */
683 icr &= ~ICR_ALDIE;
684 icr |= ICR_START | ICR_TB;
685 } else {
686 if (i2c->msg->len == 0) {
687 /*
688 * Device probes have a message length of zero
689 * and need the bus to be reset before it can
690 * be used again.
691 */
692 i2c_pxa_reset(i2c);
693 }
694 i2c_pxa_master_complete(i2c, 0);
695 }
696
697 i2c->icrlog[i2c->irqlogidx-1] = icr;
698
699 ICR = icr;
700 show_state(i2c);
701}
702
703static void i2c_pxa_irq_rxfull(struct pxa_i2c *i2c, u32 isr)
704{
705 u32 icr = ICR & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
706
707 /*
708 * Read the byte.
709 */
710 i2c->msg->buf[i2c->msg_ptr++] = IDBR;
711
712 if (i2c->msg_ptr < i2c->msg->len) {
713 /*
714 * If this is the last byte of the last
715 * message, send a STOP.
716 */
717 if (i2c->msg_ptr == i2c->msg->len - 1)
718 icr |= ICR_STOP | ICR_ACKNAK;
719
720 icr |= ICR_ALDIE | ICR_TB;
721 } else {
722 i2c_pxa_master_complete(i2c, 0);
723 }
724
725 i2c->icrlog[i2c->irqlogidx-1] = icr;
726
727 ICR = icr;
728}
729
7d12e780 730static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id)
b652b438
RK		 731{
732 struct pxa_i2c *i2c = dev_id;
733 u32 isr = ISR;
734
735 if (i2c_debug > 2 && 0) {
6fd60fa9
RK		 736 dev_dbg(&i2c->adap.dev, "%s: ISR=%08x, ICR=%08x, IBMR=%02x\n",
737 __func__, isr, ICR, IBMR);
b652b438
RK		 738 decode_ISR(isr);
739 }
740
7e3d7db5 741 if (i2c->irqlogidx < ARRAY_SIZE(i2c->isrlog))
b652b438
RK		 742 i2c->isrlog[i2c->irqlogidx++] = isr;
743
744 show_state(i2c);
745
746 /*
747 * Always clear all pending IRQs.
748 */
749 ISR = isr & (ISR_SSD|ISR_ALD|ISR_ITE|ISR_IRF|ISR_SAD|ISR_BED);
750
751 if (isr & ISR_SAD)
752 i2c_pxa_slave_start(i2c, isr);
753 if (isr & ISR_SSD)
754 i2c_pxa_slave_stop(i2c);
755
756 if (i2c_pxa_is_slavemode(i2c)) {
757 if (isr & ISR_ITE)
758 i2c_pxa_slave_txempty(i2c, isr);
759 if (isr & ISR_IRF)
760 i2c_pxa_slave_rxfull(i2c, isr);
761 } else if (i2c->msg) {
762 if (isr & ISR_ITE)
763 i2c_pxa_irq_txempty(i2c, isr);
764 if (isr & ISR_IRF)
765 i2c_pxa_irq_rxfull(i2c, isr);
766 } else {
767 i2c_pxa_scream_blue_murder(i2c, "spurious irq");
768 }
769
770 return IRQ_HANDLED;
771}
772
773
774static int i2c_pxa_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
775{
776 struct pxa_i2c *i2c = adap->algo_data;
777 int ret, i;
778
ece5f7b3
RP		 779 /* If the I2C controller is disabled we need to reset it (probably due
780 to a suspend/resume destroying state). We do this here as we can then
781 avoid worrying about resuming the controller before its users. */
782 if (!(ICR & ICR_IUE))
783 i2c_pxa_reset(i2c);
784
b652b438
RK		 785 for (i = adap->retries; i >= 0; i--) {
786 ret = i2c_pxa_do_xfer(i2c, msgs, num);
787 if (ret != I2C_RETRY)
788 goto out;
789
790 if (i2c_debug)
6fd60fa9 791 dev_dbg(&adap->dev, "Retrying transmission\n");
b652b438
RK		 792 udelay(100);
793 }
794 i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
795 ret = -EREMOTEIO;
796 out:
797 i2c_pxa_set_slave(i2c, ret);
798 return ret;
799}
800
da16e324
RK		 801static u32 i2c_pxa_functionality(struct i2c_adapter *adap)
802{
803 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
804}
805
8f9082c5 806static const struct i2c_algorithm i2c_pxa_algorithm = {
b652b438 807 .master_xfer = i2c_pxa_xfer,
da16e324 808 .functionality = i2c_pxa_functionality,
b652b438
RK		 809};
810
811static struct pxa_i2c i2c_pxa = {
812 .lock = SPIN_LOCK_UNLOCKED,
813 .wait = __WAIT_QUEUE_HEAD_INITIALIZER(i2c_pxa.wait),
814 .adap = {
da16e324 815 .owner = THIS_MODULE,
b652b438 816 .algo = &i2c_pxa_algorithm,
da16e324 817 .name = "pxa2xx-i2c",
b652b438
RK		 818 .retries = 5,
819 },
820};
821
3ae5eaec 822static int i2c_pxa_probe(struct platform_device *dev)
b652b438
RK		 823{
824 struct pxa_i2c *i2c = &i2c_pxa;
ece5f7b3 825#ifdef CONFIG_I2C_PXA_SLAVE
3ae5eaec 826 struct i2c_pxa_platform_data *plat = dev->dev.platform_data;
ece5f7b3 827#endif
b652b438
RK		 828 int ret;
829
830#ifdef CONFIG_PXA27x
831 pxa_gpio_mode(GPIO117_I2CSCL_MD);
832 pxa_gpio_mode(GPIO118_I2CSDA_MD);
833 udelay(100);
834#endif
835
836 i2c->slave_addr = I2C_PXA_SLAVE_ADDR;
837
838#ifdef CONFIG_I2C_PXA_SLAVE
b652b438
RK		 839 if (plat) {
840 i2c->slave_addr = plat->slave_addr;
beea494d 841 i2c->slave = plat->slave;
b652b438
RK		 842 }
843#endif
844
845 pxa_set_cken(CKEN14_I2C, 1);
dace1453 846 ret = request_irq(IRQ_I2C, i2c_pxa_handler, IRQF_DISABLED,
b652b438
RK		 847 "pxa2xx-i2c", i2c);
848 if (ret)
849 goto out;
850
851 i2c_pxa_reset(i2c);
852
853 i2c->adap.algo_data = i2c;
3ae5eaec 854 i2c->adap.dev.parent = &dev->dev;
b652b438
RK		 855
856 ret = i2c_add_adapter(&i2c->adap);
857 if (ret < 0) {
858 printk(KERN_INFO "I2C: Failed to add bus\n");
859 goto err_irq;
860 }
861
3ae5eaec 862 platform_set_drvdata(dev, i2c);
b652b438
RK		 863
864#ifdef CONFIG_I2C_PXA_SLAVE
865 printk(KERN_INFO "I2C: %s: PXA I2C adapter, slave address %d\n",
866 i2c->adap.dev.bus_id, i2c->slave_addr);
867#else
868 printk(KERN_INFO "I2C: %s: PXA I2C adapter\n",
869 i2c->adap.dev.bus_id);
870#endif
871 return 0;
872
873 err_irq:
874 free_irq(IRQ_I2C, i2c);
875 out:
876 return ret;
877}
878
3ae5eaec 879static int i2c_pxa_remove(struct platform_device *dev)
b652b438 880{
3ae5eaec 881 struct pxa_i2c *i2c = platform_get_drvdata(dev);
b652b438 882
3ae5eaec 883 platform_set_drvdata(dev, NULL);
b652b438
RK		 884
885 i2c_del_adapter(&i2c->adap);
886 free_irq(IRQ_I2C, i2c);
887 pxa_set_cken(CKEN14_I2C, 0);
888
889 return 0;
890}
891
3ae5eaec 892static struct platform_driver i2c_pxa_driver = {
b652b438
RK		 893 .probe = i2c_pxa_probe,
894 .remove = i2c_pxa_remove,
3ae5eaec
RK		 895 .driver = {
896 .name = "pxa2xx-i2c",
897 },
b652b438
RK		 898};
899
900static int __init i2c_adap_pxa_init(void)
901{
3ae5eaec 902 return platform_driver_register(&i2c_pxa_driver);
b652b438
RK		 903}
904
905static void i2c_adap_pxa_exit(void)
906{
3ae5eaec 907 return platform_driver_unregister(&i2c_pxa_driver);
b652b438
RK		 908}
909
ece5f7b3
RP		 910MODULE_LICENSE("GPL");
911
b652b438
RK		 912module_init(i2c_adap_pxa_init);
913module_exit(i2c_adap_pxa_exit);
Linux 6.x block layer and io_uring tree(s)