Commit | Line | Data |
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b652b438 RK |
1 | /* |
2 | * i2c_adap_pxa.c | |
3 | * | |
4 | * I2C adapter for the PXA I2C bus access. | |
5 | * | |
6 | * Copyright (C) 2002 Intrinsyc Software Inc. | |
7 | * Copyright (C) 2004-2005 Deep Blue Solutions Ltd. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * History: | |
14 | * Apr 2002: Initial version [CS] | |
15 | * Jun 2002: Properly seperated algo/adap [FB] | |
16 | * Jan 2003: Fixed several bugs concerning interrupt handling [Kai-Uwe Bloem] | |
17 | * Jan 2003: added limited signal handling [Kai-Uwe Bloem] | |
18 | * Sep 2004: Major rework to ensure efficient bus handling [RMK] | |
19 | * Dec 2004: Added support for PXA27x and slave device probing [Liam Girdwood] | |
20 | * Feb 2005: Rework slave mode handling [RMK] | |
21 | */ | |
22 | #include <linux/kernel.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/i2c.h> | |
25 | #include <linux/i2c-id.h> | |
26 | #include <linux/init.h> | |
27 | #include <linux/time.h> | |
28 | #include <linux/sched.h> | |
29 | #include <linux/delay.h> | |
30 | #include <linux/errno.h> | |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/i2c-pxa.h> | |
d052d1be | 33 | #include <linux/platform_device.h> |
c3cef3f3 RK |
34 | #include <linux/err.h> |
35 | #include <linux/clk.h> | |
b652b438 RK |
36 | |
37 | #include <asm/hardware.h> | |
38 | #include <asm/irq.h> | |
a7b4e550 | 39 | #include <asm/io.h> |
b652b438 RK |
40 | #include <asm/arch/i2c.h> |
41 | #include <asm/arch/pxa-regs.h> | |
42 | ||
43 | struct pxa_i2c { | |
44 | spinlock_t lock; | |
45 | wait_queue_head_t wait; | |
46 | struct i2c_msg *msg; | |
47 | unsigned int msg_num; | |
48 | unsigned int msg_idx; | |
49 | unsigned int msg_ptr; | |
50 | unsigned int slave_addr; | |
51 | ||
52 | struct i2c_adapter adap; | |
c3cef3f3 | 53 | struct clk *clk; |
b652b438 RK |
54 | #ifdef CONFIG_I2C_PXA_SLAVE |
55 | struct i2c_slave_client *slave; | |
56 | #endif | |
57 | ||
58 | unsigned int irqlogidx; | |
59 | u32 isrlog[32]; | |
60 | u32 icrlog[32]; | |
a7b4e550 GL |
61 | |
62 | void __iomem *reg_base; | |
63 | ||
64 | unsigned long iobase; | |
65 | unsigned long iosize; | |
66 | ||
67 | int irq; | |
b7a36701 | 68 | int use_pio; |
b652b438 RK |
69 | }; |
70 | ||
a7b4e550 GL |
71 | #define _IBMR(i2c) ((i2c)->reg_base + 0) |
72 | #define _IDBR(i2c) ((i2c)->reg_base + 8) | |
73 | #define _ICR(i2c) ((i2c)->reg_base + 0x10) | |
74 | #define _ISR(i2c) ((i2c)->reg_base + 0x18) | |
75 | #define _ISAR(i2c) ((i2c)->reg_base + 0x20) | |
76 | ||
b652b438 RK |
77 | /* |
78 | * I2C Slave mode address | |
79 | */ | |
80 | #define I2C_PXA_SLAVE_ADDR 0x1 | |
81 | ||
b652b438 RK |
82 | #ifdef DEBUG |
83 | ||
84 | struct bits { | |
85 | u32 mask; | |
86 | const char *set; | |
87 | const char *unset; | |
88 | }; | |
ed11399d | 89 | #define PXA_BIT(m, s, u) { .mask = m, .set = s, .unset = u } |
b652b438 RK |
90 | |
91 | static inline void | |
92 | decode_bits(const char *prefix, const struct bits *bits, int num, u32 val) | |
93 | { | |
94 | printk("%s %08x: ", prefix, val); | |
95 | while (num--) { | |
96 | const char *str = val & bits->mask ? bits->set : bits->unset; | |
97 | if (str) | |
98 | printk("%s ", str); | |
99 | bits++; | |
100 | } | |
101 | } | |
102 | ||
103 | static const struct bits isr_bits[] = { | |
ed11399d JS |
104 | PXA_BIT(ISR_RWM, "RX", "TX"), |
105 | PXA_BIT(ISR_ACKNAK, "NAK", "ACK"), | |
106 | PXA_BIT(ISR_UB, "Bsy", "Rdy"), | |
107 | PXA_BIT(ISR_IBB, "BusBsy", "BusRdy"), | |
108 | PXA_BIT(ISR_SSD, "SlaveStop", NULL), | |
109 | PXA_BIT(ISR_ALD, "ALD", NULL), | |
110 | PXA_BIT(ISR_ITE, "TxEmpty", NULL), | |
111 | PXA_BIT(ISR_IRF, "RxFull", NULL), | |
112 | PXA_BIT(ISR_GCAD, "GenCall", NULL), | |
113 | PXA_BIT(ISR_SAD, "SlaveAddr", NULL), | |
114 | PXA_BIT(ISR_BED, "BusErr", NULL), | |
b652b438 RK |
115 | }; |
116 | ||
117 | static void decode_ISR(unsigned int val) | |
118 | { | |
6fd60fa9 | 119 | decode_bits(KERN_DEBUG "ISR", isr_bits, ARRAY_SIZE(isr_bits), val); |
b652b438 RK |
120 | printk("\n"); |
121 | } | |
122 | ||
123 | static const struct bits icr_bits[] = { | |
ed11399d JS |
124 | PXA_BIT(ICR_START, "START", NULL), |
125 | PXA_BIT(ICR_STOP, "STOP", NULL), | |
126 | PXA_BIT(ICR_ACKNAK, "ACKNAK", NULL), | |
127 | PXA_BIT(ICR_TB, "TB", NULL), | |
128 | PXA_BIT(ICR_MA, "MA", NULL), | |
129 | PXA_BIT(ICR_SCLE, "SCLE", "scle"), | |
130 | PXA_BIT(ICR_IUE, "IUE", "iue"), | |
131 | PXA_BIT(ICR_GCD, "GCD", NULL), | |
132 | PXA_BIT(ICR_ITEIE, "ITEIE", NULL), | |
133 | PXA_BIT(ICR_IRFIE, "IRFIE", NULL), | |
134 | PXA_BIT(ICR_BEIE, "BEIE", NULL), | |
135 | PXA_BIT(ICR_SSDIE, "SSDIE", NULL), | |
136 | PXA_BIT(ICR_ALDIE, "ALDIE", NULL), | |
137 | PXA_BIT(ICR_SADIE, "SADIE", NULL), | |
138 | PXA_BIT(ICR_UR, "UR", "ur"), | |
b652b438 RK |
139 | }; |
140 | ||
141 | static void decode_ICR(unsigned int val) | |
142 | { | |
6fd60fa9 | 143 | decode_bits(KERN_DEBUG "ICR", icr_bits, ARRAY_SIZE(icr_bits), val); |
b652b438 RK |
144 | printk("\n"); |
145 | } | |
146 | ||
147 | static unsigned int i2c_debug = DEBUG; | |
148 | ||
149 | static void i2c_pxa_show_state(struct pxa_i2c *i2c, int lno, const char *fname) | |
150 | { | |
a7b4e550 GL |
151 | dev_dbg(&i2c->adap.dev, "state:%s:%d: ISR=%08x, ICR=%08x, IBMR=%02x\n", fname, lno, |
152 | readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c))); | |
b652b438 RK |
153 | } |
154 | ||
155 | #define show_state(i2c) i2c_pxa_show_state(i2c, __LINE__, __FUNCTION__) | |
156 | #else | |
157 | #define i2c_debug 0 | |
158 | ||
159 | #define show_state(i2c) do { } while (0) | |
160 | #define decode_ISR(val) do { } while (0) | |
161 | #define decode_ICR(val) do { } while (0) | |
162 | #endif | |
163 | ||
6fd60fa9 | 164 | #define eedbg(lvl, x...) do { if ((lvl) < 1) { printk(KERN_DEBUG "" x); } } while(0) |
b652b438 RK |
165 | |
166 | static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret); | |
b7a36701 | 167 | static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id); |
b652b438 RK |
168 | |
169 | static void i2c_pxa_scream_blue_murder(struct pxa_i2c *i2c, const char *why) | |
170 | { | |
171 | unsigned int i; | |
172 | printk("i2c: error: %s\n", why); | |
173 | printk("i2c: msg_num: %d msg_idx: %d msg_ptr: %d\n", | |
174 | i2c->msg_num, i2c->msg_idx, i2c->msg_ptr); | |
6fd60fa9 | 175 | printk("i2c: ICR: %08x ISR: %08x\n" |
a7b4e550 | 176 | "i2c: log: ", readl(_ICR(i2c)), readl(_ISR(i2c))); |
b652b438 RK |
177 | for (i = 0; i < i2c->irqlogidx; i++) |
178 | printk("[%08x:%08x] ", i2c->isrlog[i], i2c->icrlog[i]); | |
179 | printk("\n"); | |
180 | } | |
181 | ||
182 | static inline int i2c_pxa_is_slavemode(struct pxa_i2c *i2c) | |
183 | { | |
a7b4e550 | 184 | return !(readl(_ICR(i2c)) & ICR_SCLE); |
b652b438 RK |
185 | } |
186 | ||
187 | static void i2c_pxa_abort(struct pxa_i2c *i2c) | |
188 | { | |
189 | unsigned long timeout = jiffies + HZ/4; | |
190 | ||
191 | if (i2c_pxa_is_slavemode(i2c)) { | |
6fd60fa9 | 192 | dev_dbg(&i2c->adap.dev, "%s: called in slave mode\n", __func__); |
b652b438 RK |
193 | return; |
194 | } | |
195 | ||
a7b4e550 GL |
196 | while (time_before(jiffies, timeout) && (readl(_IBMR(i2c)) & 0x1) == 0) { |
197 | unsigned long icr = readl(_ICR(i2c)); | |
b652b438 RK |
198 | |
199 | icr &= ~ICR_START; | |
200 | icr |= ICR_ACKNAK | ICR_STOP | ICR_TB; | |
201 | ||
a7b4e550 | 202 | writel(icr, _ICR(i2c)); |
b652b438 RK |
203 | |
204 | show_state(i2c); | |
205 | ||
206 | msleep(1); | |
207 | } | |
208 | ||
a7b4e550 GL |
209 | writel(readl(_ICR(i2c)) & ~(ICR_MA | ICR_START | ICR_STOP), |
210 | _ICR(i2c)); | |
b652b438 RK |
211 | } |
212 | ||
213 | static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c *i2c) | |
214 | { | |
215 | int timeout = DEF_TIMEOUT; | |
216 | ||
a7b4e550 GL |
217 | while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) { |
218 | if ((readl(_ISR(i2c)) & ISR_SAD) != 0) | |
b652b438 RK |
219 | timeout += 4; |
220 | ||
221 | msleep(2); | |
222 | show_state(i2c); | |
223 | } | |
224 | ||
225 | if (timeout <= 0) | |
226 | show_state(i2c); | |
227 | ||
228 | return timeout <= 0 ? I2C_RETRY : 0; | |
229 | } | |
230 | ||
231 | static int i2c_pxa_wait_master(struct pxa_i2c *i2c) | |
232 | { | |
233 | unsigned long timeout = jiffies + HZ*4; | |
234 | ||
235 | while (time_before(jiffies, timeout)) { | |
236 | if (i2c_debug > 1) | |
6fd60fa9 | 237 | dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n", |
a7b4e550 | 238 | __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c))); |
b652b438 | 239 | |
a7b4e550 | 240 | if (readl(_ISR(i2c)) & ISR_SAD) { |
b652b438 | 241 | if (i2c_debug > 0) |
6fd60fa9 | 242 | dev_dbg(&i2c->adap.dev, "%s: Slave detected\n", __func__); |
b652b438 RK |
243 | goto out; |
244 | } | |
245 | ||
246 | /* wait for unit and bus being not busy, and we also do a | |
247 | * quick check of the i2c lines themselves to ensure they've | |
248 | * gone high... | |
249 | */ | |
a7b4e550 | 250 | if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) == 0 && readl(_IBMR(i2c)) == 3) { |
b652b438 | 251 | if (i2c_debug > 0) |
6fd60fa9 | 252 | dev_dbg(&i2c->adap.dev, "%s: done\n", __func__); |
b652b438 RK |
253 | return 1; |
254 | } | |
255 | ||
256 | msleep(1); | |
257 | } | |
258 | ||
259 | if (i2c_debug > 0) | |
6fd60fa9 | 260 | dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__); |
b652b438 RK |
261 | out: |
262 | return 0; | |
263 | } | |
264 | ||
265 | static int i2c_pxa_set_master(struct pxa_i2c *i2c) | |
266 | { | |
267 | if (i2c_debug) | |
6fd60fa9 | 268 | dev_dbg(&i2c->adap.dev, "setting to bus master\n"); |
b652b438 | 269 | |
a7b4e550 | 270 | if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) != 0) { |
6fd60fa9 | 271 | dev_dbg(&i2c->adap.dev, "%s: unit is busy\n", __func__); |
b652b438 | 272 | if (!i2c_pxa_wait_master(i2c)) { |
6fd60fa9 | 273 | dev_dbg(&i2c->adap.dev, "%s: error: unit busy\n", __func__); |
b652b438 RK |
274 | return I2C_RETRY; |
275 | } | |
276 | } | |
277 | ||
a7b4e550 | 278 | writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c)); |
b652b438 RK |
279 | return 0; |
280 | } | |
281 | ||
282 | #ifdef CONFIG_I2C_PXA_SLAVE | |
283 | static int i2c_pxa_wait_slave(struct pxa_i2c *i2c) | |
284 | { | |
285 | unsigned long timeout = jiffies + HZ*1; | |
286 | ||
287 | /* wait for stop */ | |
288 | ||
289 | show_state(i2c); | |
290 | ||
291 | while (time_before(jiffies, timeout)) { | |
292 | if (i2c_debug > 1) | |
6fd60fa9 | 293 | dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n", |
a7b4e550 | 294 | __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c))); |
b652b438 | 295 | |
a7b4e550 GL |
296 | if ((readl(_ISR(i2c)) & (ISR_UB|ISR_IBB)) == 0 || |
297 | (readl(_ISR(i2c)) & ISR_SAD) != 0 || | |
298 | (readl(_ICR(i2c)) & ICR_SCLE) == 0) { | |
b652b438 | 299 | if (i2c_debug > 1) |
6fd60fa9 | 300 | dev_dbg(&i2c->adap.dev, "%s: done\n", __func__); |
b652b438 RK |
301 | return 1; |
302 | } | |
303 | ||
304 | msleep(1); | |
305 | } | |
306 | ||
307 | if (i2c_debug > 0) | |
6fd60fa9 | 308 | dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__); |
b652b438 RK |
309 | return 0; |
310 | } | |
311 | ||
312 | /* | |
313 | * clear the hold on the bus, and take of anything else | |
314 | * that has been configured | |
315 | */ | |
316 | static void i2c_pxa_set_slave(struct pxa_i2c *i2c, int errcode) | |
317 | { | |
318 | show_state(i2c); | |
319 | ||
320 | if (errcode < 0) { | |
321 | udelay(100); /* simple delay */ | |
322 | } else { | |
323 | /* we need to wait for the stop condition to end */ | |
324 | ||
325 | /* if we where in stop, then clear... */ | |
a7b4e550 | 326 | if (readl(_ICR(i2c)) & ICR_STOP) { |
b652b438 | 327 | udelay(100); |
a7b4e550 | 328 | writel(readl(_ICR(i2c)) & ~ICR_STOP, _ICR(i2c)); |
b652b438 RK |
329 | } |
330 | ||
331 | if (!i2c_pxa_wait_slave(i2c)) { | |
6fd60fa9 RK |
332 | dev_err(&i2c->adap.dev, "%s: wait timedout\n", |
333 | __func__); | |
b652b438 RK |
334 | return; |
335 | } | |
336 | } | |
337 | ||
a7b4e550 GL |
338 | writel(readl(_ICR(i2c)) & ~(ICR_STOP|ICR_ACKNAK|ICR_MA), _ICR(i2c)); |
339 | writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c)); | |
b652b438 RK |
340 | |
341 | if (i2c_debug) { | |
a7b4e550 GL |
342 | dev_dbg(&i2c->adap.dev, "ICR now %08x, ISR %08x\n", readl(_ICR(i2c)), readl(_ISR(i2c))); |
343 | decode_ICR(readl(_ICR(i2c))); | |
b652b438 RK |
344 | } |
345 | } | |
346 | #else | |
347 | #define i2c_pxa_set_slave(i2c, err) do { } while (0) | |
348 | #endif | |
349 | ||
350 | static void i2c_pxa_reset(struct pxa_i2c *i2c) | |
351 | { | |
352 | pr_debug("Resetting I2C Controller Unit\n"); | |
353 | ||
354 | /* abort any transfer currently under way */ | |
355 | i2c_pxa_abort(i2c); | |
356 | ||
357 | /* reset according to 9.8 */ | |
a7b4e550 GL |
358 | writel(ICR_UR, _ICR(i2c)); |
359 | writel(I2C_ISR_INIT, _ISR(i2c)); | |
360 | writel(readl(_ICR(i2c)) & ~ICR_UR, _ICR(i2c)); | |
b652b438 | 361 | |
a7b4e550 | 362 | writel(i2c->slave_addr, _ISAR(i2c)); |
b652b438 RK |
363 | |
364 | /* set control register values */ | |
a7b4e550 | 365 | writel(I2C_ICR_INIT, _ICR(i2c)); |
b652b438 RK |
366 | |
367 | #ifdef CONFIG_I2C_PXA_SLAVE | |
6fd60fa9 | 368 | dev_info(&i2c->adap.dev, "Enabling slave mode\n"); |
a7b4e550 | 369 | writel(readl(_ICR(i2c)) | ICR_SADIE | ICR_ALDIE | ICR_SSDIE, _ICR(i2c)); |
b652b438 RK |
370 | #endif |
371 | ||
372 | i2c_pxa_set_slave(i2c, 0); | |
373 | ||
374 | /* enable unit */ | |
a7b4e550 | 375 | writel(readl(_ICR(i2c)) | ICR_IUE, _ICR(i2c)); |
b652b438 RK |
376 | udelay(100); |
377 | } | |
378 | ||
379 | ||
380 | #ifdef CONFIG_I2C_PXA_SLAVE | |
b652b438 RK |
381 | /* |
382 | * PXA I2C Slave mode | |
383 | */ | |
384 | ||
385 | static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr) | |
386 | { | |
387 | if (isr & ISR_BED) { | |
388 | /* what should we do here? */ | |
389 | } else { | |
84b5abe6 RK |
390 | int ret = 0; |
391 | ||
392 | if (i2c->slave != NULL) | |
393 | ret = i2c->slave->read(i2c->slave->data); | |
b652b438 | 394 | |
a7b4e550 GL |
395 | writel(ret, _IDBR(i2c)); |
396 | writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); /* allow next byte */ | |
b652b438 RK |
397 | } |
398 | } | |
399 | ||
400 | static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr) | |
401 | { | |
a7b4e550 | 402 | unsigned int byte = readl(_IDBR(i2c)); |
b652b438 RK |
403 | |
404 | if (i2c->slave != NULL) | |
405 | i2c->slave->write(i2c->slave->data, byte); | |
406 | ||
a7b4e550 | 407 | writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); |
b652b438 RK |
408 | } |
409 | ||
410 | static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr) | |
411 | { | |
412 | int timeout; | |
413 | ||
414 | if (i2c_debug > 0) | |
6fd60fa9 | 415 | dev_dbg(&i2c->adap.dev, "SAD, mode is slave-%cx\n", |
b652b438 RK |
416 | (isr & ISR_RWM) ? 'r' : 't'); |
417 | ||
418 | if (i2c->slave != NULL) | |
419 | i2c->slave->event(i2c->slave->data, | |
420 | (isr & ISR_RWM) ? I2C_SLAVE_EVENT_START_READ : I2C_SLAVE_EVENT_START_WRITE); | |
421 | ||
422 | /* | |
423 | * slave could interrupt in the middle of us generating a | |
424 | * start condition... if this happens, we'd better back off | |
425 | * and stop holding the poor thing up | |
426 | */ | |
a7b4e550 GL |
427 | writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c)); |
428 | writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); | |
b652b438 RK |
429 | |
430 | timeout = 0x10000; | |
431 | ||
432 | while (1) { | |
a7b4e550 | 433 | if ((readl(_IBMR(i2c)) & 2) == 2) |
b652b438 RK |
434 | break; |
435 | ||
436 | timeout--; | |
437 | ||
438 | if (timeout <= 0) { | |
6fd60fa9 | 439 | dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n"); |
b652b438 RK |
440 | break; |
441 | } | |
442 | } | |
443 | ||
a7b4e550 | 444 | writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c)); |
b652b438 RK |
445 | } |
446 | ||
447 | static void i2c_pxa_slave_stop(struct pxa_i2c *i2c) | |
448 | { | |
449 | if (i2c_debug > 2) | |
6fd60fa9 | 450 | dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop)\n"); |
b652b438 RK |
451 | |
452 | if (i2c->slave != NULL) | |
453 | i2c->slave->event(i2c->slave->data, I2C_SLAVE_EVENT_STOP); | |
454 | ||
455 | if (i2c_debug > 2) | |
6fd60fa9 | 456 | dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop) acked\n"); |
b652b438 RK |
457 | |
458 | /* | |
459 | * If we have a master-mode message waiting, | |
460 | * kick it off now that the slave has completed. | |
461 | */ | |
462 | if (i2c->msg) | |
463 | i2c_pxa_master_complete(i2c, I2C_RETRY); | |
464 | } | |
465 | #else | |
466 | static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr) | |
467 | { | |
468 | if (isr & ISR_BED) { | |
469 | /* what should we do here? */ | |
470 | } else { | |
a7b4e550 GL |
471 | writel(0, _IDBR(i2c)); |
472 | writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); | |
b652b438 RK |
473 | } |
474 | } | |
475 | ||
476 | static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr) | |
477 | { | |
a7b4e550 | 478 | writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c)); |
b652b438 RK |
479 | } |
480 | ||
481 | static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr) | |
482 | { | |
483 | int timeout; | |
484 | ||
485 | /* | |
486 | * slave could interrupt in the middle of us generating a | |
487 | * start condition... if this happens, we'd better back off | |
488 | * and stop holding the poor thing up | |
489 | */ | |
a7b4e550 GL |
490 | writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c)); |
491 | writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c)); | |
b652b438 RK |
492 | |
493 | timeout = 0x10000; | |
494 | ||
495 | while (1) { | |
a7b4e550 | 496 | if ((readl(_IBMR(i2c)) & 2) == 2) |
b652b438 RK |
497 | break; |
498 | ||
499 | timeout--; | |
500 | ||
501 | if (timeout <= 0) { | |
6fd60fa9 | 502 | dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n"); |
b652b438 RK |
503 | break; |
504 | } | |
505 | } | |
506 | ||
a7b4e550 | 507 | writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c)); |
b652b438 RK |
508 | } |
509 | ||
510 | static void i2c_pxa_slave_stop(struct pxa_i2c *i2c) | |
511 | { | |
512 | if (i2c->msg) | |
513 | i2c_pxa_master_complete(i2c, I2C_RETRY); | |
514 | } | |
515 | #endif | |
516 | ||
517 | /* | |
518 | * PXA I2C Master mode | |
519 | */ | |
520 | ||
521 | static inline unsigned int i2c_pxa_addr_byte(struct i2c_msg *msg) | |
522 | { | |
523 | unsigned int addr = (msg->addr & 0x7f) << 1; | |
524 | ||
525 | if (msg->flags & I2C_M_RD) | |
526 | addr |= 1; | |
527 | ||
528 | return addr; | |
529 | } | |
530 | ||
531 | static inline void i2c_pxa_start_message(struct pxa_i2c *i2c) | |
532 | { | |
533 | u32 icr; | |
534 | ||
535 | /* | |
536 | * Step 1: target slave address into IDBR | |
537 | */ | |
a7b4e550 | 538 | writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c)); |
b652b438 RK |
539 | |
540 | /* | |
541 | * Step 2: initiate the write. | |
542 | */ | |
a7b4e550 GL |
543 | icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE); |
544 | writel(icr | ICR_START | ICR_TB, _ICR(i2c)); | |
b652b438 RK |
545 | } |
546 | ||
7d054817 JD |
547 | static inline void i2c_pxa_stop_message(struct pxa_i2c *i2c) |
548 | { | |
549 | u32 icr; | |
550 | ||
551 | /* | |
552 | * Clear the STOP and ACK flags | |
553 | */ | |
554 | icr = readl(_ICR(i2c)); | |
555 | icr &= ~(ICR_STOP | ICR_ACKNAK); | |
0cfe61e1 | 556 | writel(icr, _ICR(i2c)); |
7d054817 JD |
557 | } |
558 | ||
b7a36701 MR |
559 | static int i2c_pxa_pio_set_master(struct pxa_i2c *i2c) |
560 | { | |
561 | /* make timeout the same as for interrupt based functions */ | |
562 | long timeout = 2 * DEF_TIMEOUT; | |
563 | ||
564 | /* | |
565 | * Wait for the bus to become free. | |
566 | */ | |
567 | while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) { | |
568 | udelay(1000); | |
569 | show_state(i2c); | |
570 | } | |
571 | ||
572 | if (timeout <= 0) { | |
573 | show_state(i2c); | |
574 | dev_err(&i2c->adap.dev, | |
575 | "i2c_pxa: timeout waiting for bus free\n"); | |
576 | return I2C_RETRY; | |
577 | } | |
578 | ||
579 | /* | |
580 | * Set master mode. | |
581 | */ | |
582 | writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c)); | |
583 | ||
584 | return 0; | |
585 | } | |
586 | ||
587 | static int i2c_pxa_do_pio_xfer(struct pxa_i2c *i2c, | |
588 | struct i2c_msg *msg, int num) | |
589 | { | |
590 | unsigned long timeout = 500000; /* 5 seconds */ | |
591 | int ret = 0; | |
592 | ||
593 | ret = i2c_pxa_pio_set_master(i2c); | |
594 | if (ret) | |
595 | goto out; | |
596 | ||
597 | i2c->msg = msg; | |
598 | i2c->msg_num = num; | |
599 | i2c->msg_idx = 0; | |
600 | i2c->msg_ptr = 0; | |
601 | i2c->irqlogidx = 0; | |
602 | ||
603 | i2c_pxa_start_message(i2c); | |
604 | ||
605 | while (timeout-- && i2c->msg_num > 0) { | |
606 | i2c_pxa_handler(0, i2c); | |
607 | udelay(10); | |
608 | } | |
609 | ||
610 | i2c_pxa_stop_message(i2c); | |
611 | ||
612 | /* | |
613 | * We place the return code in i2c->msg_idx. | |
614 | */ | |
615 | ret = i2c->msg_idx; | |
616 | ||
617 | out: | |
618 | if (timeout == 0) | |
619 | i2c_pxa_scream_blue_murder(i2c, "timeout"); | |
620 | ||
621 | return ret; | |
622 | } | |
623 | ||
b652b438 | 624 | /* |
3fb9a655 | 625 | * We are protected by the adapter bus mutex. |
b652b438 RK |
626 | */ |
627 | static int i2c_pxa_do_xfer(struct pxa_i2c *i2c, struct i2c_msg *msg, int num) | |
628 | { | |
629 | long timeout; | |
630 | int ret; | |
631 | ||
632 | /* | |
633 | * Wait for the bus to become free. | |
634 | */ | |
635 | ret = i2c_pxa_wait_bus_not_busy(i2c); | |
636 | if (ret) { | |
6fd60fa9 | 637 | dev_err(&i2c->adap.dev, "i2c_pxa: timeout waiting for bus free\n"); |
b652b438 RK |
638 | goto out; |
639 | } | |
640 | ||
641 | /* | |
642 | * Set master mode. | |
643 | */ | |
644 | ret = i2c_pxa_set_master(i2c); | |
645 | if (ret) { | |
6fd60fa9 | 646 | dev_err(&i2c->adap.dev, "i2c_pxa_set_master: error %d\n", ret); |
b652b438 RK |
647 | goto out; |
648 | } | |
649 | ||
650 | spin_lock_irq(&i2c->lock); | |
651 | ||
652 | i2c->msg = msg; | |
653 | i2c->msg_num = num; | |
654 | i2c->msg_idx = 0; | |
655 | i2c->msg_ptr = 0; | |
656 | i2c->irqlogidx = 0; | |
657 | ||
658 | i2c_pxa_start_message(i2c); | |
659 | ||
660 | spin_unlock_irq(&i2c->lock); | |
661 | ||
662 | /* | |
663 | * The rest of the processing occurs in the interrupt handler. | |
664 | */ | |
665 | timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5); | |
7d054817 | 666 | i2c_pxa_stop_message(i2c); |
b652b438 RK |
667 | |
668 | /* | |
669 | * We place the return code in i2c->msg_idx. | |
670 | */ | |
671 | ret = i2c->msg_idx; | |
672 | ||
673 | if (timeout == 0) | |
674 | i2c_pxa_scream_blue_murder(i2c, "timeout"); | |
675 | ||
676 | out: | |
677 | return ret; | |
678 | } | |
679 | ||
b7a36701 MR |
680 | static int i2c_pxa_pio_xfer(struct i2c_adapter *adap, |
681 | struct i2c_msg msgs[], int num) | |
682 | { | |
683 | struct pxa_i2c *i2c = adap->algo_data; | |
684 | int ret, i; | |
685 | ||
686 | /* If the I2C controller is disabled we need to reset it | |
687 | (probably due to a suspend/resume destroying state). We do | |
688 | this here as we can then avoid worrying about resuming the | |
689 | controller before its users. */ | |
690 | if (!(readl(_ICR(i2c)) & ICR_IUE)) | |
691 | i2c_pxa_reset(i2c); | |
692 | ||
693 | for (i = adap->retries; i >= 0; i--) { | |
694 | ret = i2c_pxa_do_pio_xfer(i2c, msgs, num); | |
695 | if (ret != I2C_RETRY) | |
696 | goto out; | |
697 | ||
698 | if (i2c_debug) | |
699 | dev_dbg(&adap->dev, "Retrying transmission\n"); | |
700 | udelay(100); | |
701 | } | |
702 | i2c_pxa_scream_blue_murder(i2c, "exhausted retries"); | |
703 | ret = -EREMOTEIO; | |
704 | out: | |
705 | i2c_pxa_set_slave(i2c, ret); | |
706 | return ret; | |
707 | } | |
708 | ||
b652b438 RK |
709 | /* |
710 | * i2c_pxa_master_complete - complete the message and wake up. | |
711 | */ | |
712 | static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret) | |
713 | { | |
714 | i2c->msg_ptr = 0; | |
715 | i2c->msg = NULL; | |
716 | i2c->msg_idx ++; | |
717 | i2c->msg_num = 0; | |
718 | if (ret) | |
719 | i2c->msg_idx = ret; | |
b7a36701 MR |
720 | if (!i2c->use_pio) |
721 | wake_up(&i2c->wait); | |
b652b438 RK |
722 | } |
723 | ||
724 | static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr) | |
725 | { | |
a7b4e550 | 726 | u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB); |
b652b438 RK |
727 | |
728 | again: | |
729 | /* | |
730 | * If ISR_ALD is set, we lost arbitration. | |
731 | */ | |
732 | if (isr & ISR_ALD) { | |
733 | /* | |
734 | * Do we need to do anything here? The PXA docs | |
735 | * are vague about what happens. | |
736 | */ | |
737 | i2c_pxa_scream_blue_murder(i2c, "ALD set"); | |
738 | ||
739 | /* | |
740 | * We ignore this error. We seem to see spurious ALDs | |
741 | * for seemingly no reason. If we handle them as I think | |
742 | * they should, we end up causing an I2C error, which | |
743 | * is painful for some systems. | |
744 | */ | |
745 | return; /* ignore */ | |
746 | } | |
747 | ||
748 | if (isr & ISR_BED) { | |
749 | int ret = BUS_ERROR; | |
750 | ||
751 | /* | |
752 | * I2C bus error - either the device NAK'd us, or | |
753 | * something more serious happened. If we were NAK'd | |
754 | * on the initial address phase, we can retry. | |
755 | */ | |
756 | if (isr & ISR_ACKNAK) { | |
757 | if (i2c->msg_ptr == 0 && i2c->msg_idx == 0) | |
758 | ret = I2C_RETRY; | |
759 | else | |
760 | ret = XFER_NAKED; | |
761 | } | |
762 | i2c_pxa_master_complete(i2c, ret); | |
763 | } else if (isr & ISR_RWM) { | |
764 | /* | |
765 | * Read mode. We have just sent the address byte, and | |
766 | * now we must initiate the transfer. | |
767 | */ | |
768 | if (i2c->msg_ptr == i2c->msg->len - 1 && | |
769 | i2c->msg_idx == i2c->msg_num - 1) | |
770 | icr |= ICR_STOP | ICR_ACKNAK; | |
771 | ||
772 | icr |= ICR_ALDIE | ICR_TB; | |
773 | } else if (i2c->msg_ptr < i2c->msg->len) { | |
774 | /* | |
775 | * Write mode. Write the next data byte. | |
776 | */ | |
a7b4e550 | 777 | writel(i2c->msg->buf[i2c->msg_ptr++], _IDBR(i2c)); |
b652b438 RK |
778 | |
779 | icr |= ICR_ALDIE | ICR_TB; | |
780 | ||
781 | /* | |
782 | * If this is the last byte of the last message, send | |
783 | * a STOP. | |
784 | */ | |
785 | if (i2c->msg_ptr == i2c->msg->len && | |
786 | i2c->msg_idx == i2c->msg_num - 1) | |
787 | icr |= ICR_STOP; | |
788 | } else if (i2c->msg_idx < i2c->msg_num - 1) { | |
789 | /* | |
790 | * Next segment of the message. | |
791 | */ | |
792 | i2c->msg_ptr = 0; | |
793 | i2c->msg_idx ++; | |
794 | i2c->msg++; | |
795 | ||
796 | /* | |
797 | * If we aren't doing a repeated start and address, | |
798 | * go back and try to send the next byte. Note that | |
799 | * we do not support switching the R/W direction here. | |
800 | */ | |
801 | if (i2c->msg->flags & I2C_M_NOSTART) | |
802 | goto again; | |
803 | ||
804 | /* | |
805 | * Write the next address. | |
806 | */ | |
a7b4e550 | 807 | writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c)); |
b652b438 RK |
808 | |
809 | /* | |
810 | * And trigger a repeated start, and send the byte. | |
811 | */ | |
812 | icr &= ~ICR_ALDIE; | |
813 | icr |= ICR_START | ICR_TB; | |
814 | } else { | |
815 | if (i2c->msg->len == 0) { | |
816 | /* | |
817 | * Device probes have a message length of zero | |
818 | * and need the bus to be reset before it can | |
819 | * be used again. | |
820 | */ | |
821 | i2c_pxa_reset(i2c); | |
822 | } | |
823 | i2c_pxa_master_complete(i2c, 0); | |
824 | } | |
825 | ||
826 | i2c->icrlog[i2c->irqlogidx-1] = icr; | |
827 | ||
a7b4e550 | 828 | writel(icr, _ICR(i2c)); |
b652b438 RK |
829 | show_state(i2c); |
830 | } | |
831 | ||
832 | static void i2c_pxa_irq_rxfull(struct pxa_i2c *i2c, u32 isr) | |
833 | { | |
a7b4e550 | 834 | u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB); |
b652b438 RK |
835 | |
836 | /* | |
837 | * Read the byte. | |
838 | */ | |
a7b4e550 | 839 | i2c->msg->buf[i2c->msg_ptr++] = readl(_IDBR(i2c)); |
b652b438 RK |
840 | |
841 | if (i2c->msg_ptr < i2c->msg->len) { | |
842 | /* | |
843 | * If this is the last byte of the last | |
844 | * message, send a STOP. | |
845 | */ | |
846 | if (i2c->msg_ptr == i2c->msg->len - 1) | |
847 | icr |= ICR_STOP | ICR_ACKNAK; | |
848 | ||
849 | icr |= ICR_ALDIE | ICR_TB; | |
850 | } else { | |
851 | i2c_pxa_master_complete(i2c, 0); | |
852 | } | |
853 | ||
854 | i2c->icrlog[i2c->irqlogidx-1] = icr; | |
855 | ||
a7b4e550 | 856 | writel(icr, _ICR(i2c)); |
b652b438 RK |
857 | } |
858 | ||
7d12e780 | 859 | static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id) |
b652b438 RK |
860 | { |
861 | struct pxa_i2c *i2c = dev_id; | |
a7b4e550 | 862 | u32 isr = readl(_ISR(i2c)); |
b652b438 RK |
863 | |
864 | if (i2c_debug > 2 && 0) { | |
6fd60fa9 | 865 | dev_dbg(&i2c->adap.dev, "%s: ISR=%08x, ICR=%08x, IBMR=%02x\n", |
a7b4e550 | 866 | __func__, isr, readl(_ICR(i2c)), readl(_IBMR(i2c))); |
b652b438 RK |
867 | decode_ISR(isr); |
868 | } | |
869 | ||
7e3d7db5 | 870 | if (i2c->irqlogidx < ARRAY_SIZE(i2c->isrlog)) |
b652b438 RK |
871 | i2c->isrlog[i2c->irqlogidx++] = isr; |
872 | ||
873 | show_state(i2c); | |
874 | ||
875 | /* | |
876 | * Always clear all pending IRQs. | |
877 | */ | |
a7b4e550 | 878 | writel(isr & (ISR_SSD|ISR_ALD|ISR_ITE|ISR_IRF|ISR_SAD|ISR_BED), _ISR(i2c)); |
b652b438 RK |
879 | |
880 | if (isr & ISR_SAD) | |
881 | i2c_pxa_slave_start(i2c, isr); | |
882 | if (isr & ISR_SSD) | |
883 | i2c_pxa_slave_stop(i2c); | |
884 | ||
885 | if (i2c_pxa_is_slavemode(i2c)) { | |
886 | if (isr & ISR_ITE) | |
887 | i2c_pxa_slave_txempty(i2c, isr); | |
888 | if (isr & ISR_IRF) | |
889 | i2c_pxa_slave_rxfull(i2c, isr); | |
890 | } else if (i2c->msg) { | |
891 | if (isr & ISR_ITE) | |
892 | i2c_pxa_irq_txempty(i2c, isr); | |
893 | if (isr & ISR_IRF) | |
894 | i2c_pxa_irq_rxfull(i2c, isr); | |
895 | } else { | |
896 | i2c_pxa_scream_blue_murder(i2c, "spurious irq"); | |
897 | } | |
898 | ||
899 | return IRQ_HANDLED; | |
900 | } | |
901 | ||
902 | ||
903 | static int i2c_pxa_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) | |
904 | { | |
905 | struct pxa_i2c *i2c = adap->algo_data; | |
906 | int ret, i; | |
907 | ||
ece5f7b3 RP |
908 | /* If the I2C controller is disabled we need to reset it (probably due |
909 | to a suspend/resume destroying state). We do this here as we can then | |
910 | avoid worrying about resuming the controller before its users. */ | |
a7b4e550 | 911 | if (!(readl(_ICR(i2c)) & ICR_IUE)) |
ece5f7b3 RP |
912 | i2c_pxa_reset(i2c); |
913 | ||
b652b438 RK |
914 | for (i = adap->retries; i >= 0; i--) { |
915 | ret = i2c_pxa_do_xfer(i2c, msgs, num); | |
916 | if (ret != I2C_RETRY) | |
917 | goto out; | |
918 | ||
919 | if (i2c_debug) | |
6fd60fa9 | 920 | dev_dbg(&adap->dev, "Retrying transmission\n"); |
b652b438 RK |
921 | udelay(100); |
922 | } | |
923 | i2c_pxa_scream_blue_murder(i2c, "exhausted retries"); | |
924 | ret = -EREMOTEIO; | |
925 | out: | |
926 | i2c_pxa_set_slave(i2c, ret); | |
927 | return ret; | |
928 | } | |
929 | ||
da16e324 RK |
930 | static u32 i2c_pxa_functionality(struct i2c_adapter *adap) |
931 | { | |
932 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; | |
933 | } | |
934 | ||
8f9082c5 | 935 | static const struct i2c_algorithm i2c_pxa_algorithm = { |
b652b438 | 936 | .master_xfer = i2c_pxa_xfer, |
da16e324 | 937 | .functionality = i2c_pxa_functionality, |
b652b438 RK |
938 | }; |
939 | ||
b7a36701 MR |
940 | static const struct i2c_algorithm i2c_pxa_pio_algorithm = { |
941 | .master_xfer = i2c_pxa_pio_xfer, | |
942 | .functionality = i2c_pxa_functionality, | |
943 | }; | |
944 | ||
59d70df0 | 945 | static void i2c_pxa_enable(struct platform_device *dev) |
946 | { | |
947 | if (cpu_is_pxa27x()) { | |
948 | switch (dev->id) { | |
949 | case 0: | |
950 | pxa_gpio_mode(GPIO117_I2CSCL_MD); | |
951 | pxa_gpio_mode(GPIO118_I2CSDA_MD); | |
952 | break; | |
953 | case 1: | |
954 | local_irq_disable(); | |
955 | PCFR |= PCFR_PI2CEN; | |
956 | local_irq_enable(); | |
957 | break; | |
958 | } | |
959 | } | |
960 | } | |
961 | ||
962 | static void i2c_pxa_disable(struct platform_device *dev) | |
963 | { | |
964 | if (cpu_is_pxa27x() && dev->id == 1) { | |
965 | local_irq_disable(); | |
966 | PCFR &= ~PCFR_PI2CEN; | |
967 | local_irq_enable(); | |
968 | } | |
969 | } | |
970 | ||
a7b4e550 | 971 | #define res_len(r) ((r)->end - (r)->start + 1) |
3ae5eaec | 972 | static int i2c_pxa_probe(struct platform_device *dev) |
b652b438 | 973 | { |
6776f3d2 | 974 | struct pxa_i2c *i2c; |
a7b4e550 | 975 | struct resource *res; |
3ae5eaec | 976 | struct i2c_pxa_platform_data *plat = dev->dev.platform_data; |
b652b438 | 977 | int ret; |
a7b4e550 | 978 | int irq; |
b652b438 | 979 | |
a7b4e550 GL |
980 | res = platform_get_resource(dev, IORESOURCE_MEM, 0); |
981 | irq = platform_get_irq(dev, 0); | |
982 | if (res == NULL || irq < 0) | |
983 | return -ENODEV; | |
984 | ||
985 | if (!request_mem_region(res->start, res_len(res), res->name)) | |
986 | return -ENOMEM; | |
987 | ||
6776f3d2 | 988 | i2c = kzalloc(sizeof(struct pxa_i2c), GFP_KERNEL); |
a7b4e550 GL |
989 | if (!i2c) { |
990 | ret = -ENOMEM; | |
991 | goto emalloc; | |
992 | } | |
993 | ||
6776f3d2 | 994 | i2c->adap.owner = THIS_MODULE; |
6776f3d2 ES |
995 | i2c->adap.retries = 5; |
996 | ||
997 | spin_lock_init(&i2c->lock); | |
a7b4e550 | 998 | init_waitqueue_head(&i2c->wait); |
6776f3d2 ES |
999 | |
1000 | sprintf(i2c->adap.name, "pxa_i2c-i2c.%u", dev->id); | |
a7b4e550 | 1001 | |
c3cef3f3 RK |
1002 | i2c->clk = clk_get(&dev->dev, "I2CCLK"); |
1003 | if (IS_ERR(i2c->clk)) { | |
1004 | ret = PTR_ERR(i2c->clk); | |
1005 | goto eclk; | |
1006 | } | |
1007 | ||
a7b4e550 GL |
1008 | i2c->reg_base = ioremap(res->start, res_len(res)); |
1009 | if (!i2c->reg_base) { | |
1010 | ret = -EIO; | |
1011 | goto eremap; | |
1012 | } | |
1013 | ||
1014 | i2c->iobase = res->start; | |
1015 | i2c->iosize = res_len(res); | |
1016 | ||
1017 | i2c->irq = irq; | |
b652b438 RK |
1018 | |
1019 | i2c->slave_addr = I2C_PXA_SLAVE_ADDR; | |
1020 | ||
1021 | #ifdef CONFIG_I2C_PXA_SLAVE | |
b652b438 RK |
1022 | if (plat) { |
1023 | i2c->slave_addr = plat->slave_addr; | |
beea494d | 1024 | i2c->slave = plat->slave; |
b652b438 RK |
1025 | } |
1026 | #endif | |
1027 | ||
c3cef3f3 | 1028 | clk_enable(i2c->clk); |
59d70df0 | 1029 | i2c_pxa_enable(dev); |
a7b4e550 | 1030 | |
b7a36701 MR |
1031 | if (plat) { |
1032 | i2c->adap.class = plat->class; | |
1033 | i2c->use_pio = plat->use_pio; | |
1034 | } | |
1035 | ||
1036 | if (i2c->use_pio) { | |
1037 | i2c->adap.algo = &i2c_pxa_pio_algorithm; | |
1038 | } else { | |
1039 | i2c->adap.algo = &i2c_pxa_algorithm; | |
1040 | ret = request_irq(irq, i2c_pxa_handler, IRQF_DISABLED, | |
1041 | i2c->adap.name, i2c); | |
1042 | if (ret) | |
1043 | goto ereqirq; | |
1044 | } | |
a7b4e550 | 1045 | |
b652b438 RK |
1046 | i2c_pxa_reset(i2c); |
1047 | ||
1048 | i2c->adap.algo_data = i2c; | |
3ae5eaec | 1049 | i2c->adap.dev.parent = &dev->dev; |
b652b438 | 1050 | |
066af983 RG |
1051 | /* |
1052 | * If "dev->id" is negative we consider it as zero. | |
1053 | * The reason to do so is to avoid sysfs names that only make | |
1054 | * sense when there are multiple adapters. | |
1055 | */ | |
51e5709a | 1056 | i2c->adap.nr = dev->id != -1 ? dev->id : 0; |
066af983 RG |
1057 | |
1058 | ret = i2c_add_numbered_adapter(&i2c->adap); | |
b652b438 RK |
1059 | if (ret < 0) { |
1060 | printk(KERN_INFO "I2C: Failed to add bus\n"); | |
a7b4e550 | 1061 | goto eadapt; |
b652b438 RK |
1062 | } |
1063 | ||
3ae5eaec | 1064 | platform_set_drvdata(dev, i2c); |
b652b438 RK |
1065 | |
1066 | #ifdef CONFIG_I2C_PXA_SLAVE | |
1067 | printk(KERN_INFO "I2C: %s: PXA I2C adapter, slave address %d\n", | |
1068 | i2c->adap.dev.bus_id, i2c->slave_addr); | |
1069 | #else | |
1070 | printk(KERN_INFO "I2C: %s: PXA I2C adapter\n", | |
1071 | i2c->adap.dev.bus_id); | |
1072 | #endif | |
1073 | return 0; | |
1074 | ||
a7b4e550 | 1075 | eadapt: |
b7a36701 MR |
1076 | if (!i2c->use_pio) |
1077 | free_irq(irq, i2c); | |
a7b4e550 | 1078 | ereqirq: |
c3cef3f3 | 1079 | clk_disable(i2c->clk); |
59d70df0 | 1080 | i2c_pxa_disable(dev); |
a7b4e550 | 1081 | eremap: |
c3cef3f3 RK |
1082 | clk_put(i2c->clk); |
1083 | eclk: | |
a7b4e550 GL |
1084 | kfree(i2c); |
1085 | emalloc: | |
1086 | release_mem_region(res->start, res_len(res)); | |
b652b438 RK |
1087 | return ret; |
1088 | } | |
1089 | ||
3ae5eaec | 1090 | static int i2c_pxa_remove(struct platform_device *dev) |
b652b438 | 1091 | { |
3ae5eaec | 1092 | struct pxa_i2c *i2c = platform_get_drvdata(dev); |
b652b438 | 1093 | |
3ae5eaec | 1094 | platform_set_drvdata(dev, NULL); |
b652b438 RK |
1095 | |
1096 | i2c_del_adapter(&i2c->adap); | |
b7a36701 MR |
1097 | if (!i2c->use_pio) |
1098 | free_irq(i2c->irq, i2c); | |
c3cef3f3 RK |
1099 | |
1100 | clk_disable(i2c->clk); | |
1101 | clk_put(i2c->clk); | |
59d70df0 | 1102 | i2c_pxa_disable(dev); |
c3cef3f3 | 1103 | |
a7b4e550 GL |
1104 | release_mem_region(i2c->iobase, i2c->iosize); |
1105 | kfree(i2c); | |
b652b438 RK |
1106 | |
1107 | return 0; | |
1108 | } | |
1109 | ||
3ae5eaec | 1110 | static struct platform_driver i2c_pxa_driver = { |
b652b438 RK |
1111 | .probe = i2c_pxa_probe, |
1112 | .remove = i2c_pxa_remove, | |
3ae5eaec RK |
1113 | .driver = { |
1114 | .name = "pxa2xx-i2c", | |
1115 | }, | |
b652b438 RK |
1116 | }; |
1117 | ||
1118 | static int __init i2c_adap_pxa_init(void) | |
1119 | { | |
3ae5eaec | 1120 | return platform_driver_register(&i2c_pxa_driver); |
b652b438 RK |
1121 | } |
1122 | ||
1123 | static void i2c_adap_pxa_exit(void) | |
1124 | { | |
3ae5eaec | 1125 | return platform_driver_unregister(&i2c_pxa_driver); |
b652b438 RK |
1126 | } |
1127 | ||
ece5f7b3 RP |
1128 | MODULE_LICENSE("GPL"); |
1129 | ||
b652b438 RK |
1130 | module_init(i2c_adap_pxa_init); |
1131 | module_exit(i2c_adap_pxa_exit); |