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41561f28 VW |
1 | /* |
2 | * Provides I2C support for Philips PNX010x/PNX4008 boards. | |
3 | * | |
4 | * Authors: Dennis Kovalev <dkovalev@ru.mvista.com> | |
5 | * Vitaly Wool <vwool@ru.mvista.com> | |
6 | * | |
7 | * 2004-2006 (c) MontaVista Software, Inc. This file is licensed under | |
8 | * the terms of the GNU General Public License version 2. This program | |
9 | * is licensed "as is" without any warranty of any kind, whether express | |
10 | * or implied. | |
11 | */ | |
12 | ||
13 | #include <linux/module.h> | |
14 | #include <linux/interrupt.h> | |
15 | #include <linux/ioport.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/i2c.h> | |
18 | #include <linux/timer.h> | |
19 | #include <linux/completion.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/i2c-pnx.h> | |
a7d73d8c | 22 | #include <linux/io.h> |
0321cb83 RK |
23 | #include <linux/err.h> |
24 | #include <linux/clk.h> | |
5a0e3ad6 | 25 | #include <linux/slab.h> |
0321cb83 | 26 | |
a09e64fb | 27 | #include <mach/hardware.h> |
a7d73d8c | 28 | #include <mach/i2c.h> |
41561f28 VW |
29 | |
30 | #define I2C_PNX_TIMEOUT 10 /* msec */ | |
31 | #define I2C_PNX_SPEED_KHZ 100 | |
32 | #define I2C_PNX_REGION_SIZE 0x100 | |
41561f28 VW |
33 | |
34 | static inline int wait_timeout(long timeout, struct i2c_pnx_algo_data *data) | |
35 | { | |
36 | while (timeout > 0 && | |
37 | (ioread32(I2C_REG_STS(data)) & mstatus_active)) { | |
38 | mdelay(1); | |
39 | timeout--; | |
40 | } | |
41 | return (timeout <= 0); | |
42 | } | |
43 | ||
44 | static inline int wait_reset(long timeout, struct i2c_pnx_algo_data *data) | |
45 | { | |
46 | while (timeout > 0 && | |
47 | (ioread32(I2C_REG_CTL(data)) & mcntrl_reset)) { | |
48 | mdelay(1); | |
49 | timeout--; | |
50 | } | |
51 | return (timeout <= 0); | |
52 | } | |
53 | ||
81d6724a | 54 | static inline void i2c_pnx_arm_timer(struct i2c_pnx_algo_data *alg_data) |
41561f28 | 55 | { |
81d6724a | 56 | struct timer_list *timer = &alg_data->mif.timer; |
eed18b5f | 57 | unsigned long expires = msecs_to_jiffies(I2C_PNX_TIMEOUT); |
41561f28 | 58 | |
b2f125bc KW |
59 | if (expires <= 1) |
60 | expires = 2; | |
61 | ||
41561f28 VW |
62 | del_timer_sync(timer); |
63 | ||
eed18b5f | 64 | dev_dbg(&alg_data->adapter.dev, "Timer armed at %lu plus %lu jiffies.\n", |
41561f28 VW |
65 | jiffies, expires); |
66 | ||
67 | timer->expires = jiffies + expires; | |
81d6724a | 68 | timer->data = (unsigned long)&alg_data; |
41561f28 VW |
69 | |
70 | add_timer(timer); | |
71 | } | |
72 | ||
73 | /** | |
74 | * i2c_pnx_start - start a device | |
75 | * @slave_addr: slave address | |
76 | * @adap: pointer to adapter structure | |
77 | * | |
78 | * Generate a START signal in the desired mode. | |
79 | */ | |
81d6724a RK |
80 | static int i2c_pnx_start(unsigned char slave_addr, |
81 | struct i2c_pnx_algo_data *alg_data) | |
41561f28 | 82 | { |
81d6724a | 83 | dev_dbg(&alg_data->adapter.dev, "%s(): addr 0x%x mode %d\n", __func__, |
41561f28 VW |
84 | slave_addr, alg_data->mif.mode); |
85 | ||
86 | /* Check for 7 bit slave addresses only */ | |
87 | if (slave_addr & ~0x7f) { | |
4be53dbe RK |
88 | dev_err(&alg_data->adapter.dev, |
89 | "%s: Invalid slave address %x. Only 7-bit addresses are supported\n", | |
90 | alg_data->adapter.name, slave_addr); | |
41561f28 VW |
91 | return -EINVAL; |
92 | } | |
93 | ||
94 | /* First, make sure bus is idle */ | |
95 | if (wait_timeout(I2C_PNX_TIMEOUT, alg_data)) { | |
96 | /* Somebody else is monopolizing the bus */ | |
4be53dbe RK |
97 | dev_err(&alg_data->adapter.dev, |
98 | "%s: Bus busy. Slave addr = %02x, cntrl = %x, stat = %x\n", | |
99 | alg_data->adapter.name, slave_addr, | |
100 | ioread32(I2C_REG_CTL(alg_data)), | |
101 | ioread32(I2C_REG_STS(alg_data))); | |
41561f28 VW |
102 | return -EBUSY; |
103 | } else if (ioread32(I2C_REG_STS(alg_data)) & mstatus_afi) { | |
104 | /* Sorry, we lost the bus */ | |
4be53dbe RK |
105 | dev_err(&alg_data->adapter.dev, |
106 | "%s: Arbitration failure. Slave addr = %02x\n", | |
107 | alg_data->adapter.name, slave_addr); | |
41561f28 VW |
108 | return -EIO; |
109 | } | |
110 | ||
111 | /* | |
112 | * OK, I2C is enabled and we have the bus. | |
113 | * Clear the current TDI and AFI status flags. | |
114 | */ | |
115 | iowrite32(ioread32(I2C_REG_STS(alg_data)) | mstatus_tdi | mstatus_afi, | |
116 | I2C_REG_STS(alg_data)); | |
117 | ||
81d6724a | 118 | dev_dbg(&alg_data->adapter.dev, "%s(): sending %#x\n", __func__, |
41561f28 VW |
119 | (slave_addr << 1) | start_bit | alg_data->mif.mode); |
120 | ||
121 | /* Write the slave address, START bit and R/W bit */ | |
122 | iowrite32((slave_addr << 1) | start_bit | alg_data->mif.mode, | |
123 | I2C_REG_TX(alg_data)); | |
124 | ||
81d6724a | 125 | dev_dbg(&alg_data->adapter.dev, "%s(): exit\n", __func__); |
41561f28 VW |
126 | |
127 | return 0; | |
128 | } | |
129 | ||
130 | /** | |
131 | * i2c_pnx_stop - stop a device | |
132 | * @adap: pointer to I2C adapter structure | |
133 | * | |
134 | * Generate a STOP signal to terminate the master transaction. | |
135 | */ | |
81d6724a | 136 | static void i2c_pnx_stop(struct i2c_pnx_algo_data *alg_data) |
41561f28 | 137 | { |
41561f28 VW |
138 | /* Only 1 msec max timeout due to interrupt context */ |
139 | long timeout = 1000; | |
140 | ||
81d6724a | 141 | dev_dbg(&alg_data->adapter.dev, "%s(): entering: stat = %04x.\n", |
08882d20 | 142 | __func__, ioread32(I2C_REG_STS(alg_data))); |
41561f28 VW |
143 | |
144 | /* Write a STOP bit to TX FIFO */ | |
145 | iowrite32(0xff | stop_bit, I2C_REG_TX(alg_data)); | |
146 | ||
147 | /* Wait until the STOP is seen. */ | |
148 | while (timeout > 0 && | |
149 | (ioread32(I2C_REG_STS(alg_data)) & mstatus_active)) { | |
150 | /* may be called from interrupt context */ | |
151 | udelay(1); | |
152 | timeout--; | |
153 | } | |
154 | ||
81d6724a | 155 | dev_dbg(&alg_data->adapter.dev, "%s(): exiting: stat = %04x.\n", |
08882d20 | 156 | __func__, ioread32(I2C_REG_STS(alg_data))); |
41561f28 VW |
157 | } |
158 | ||
159 | /** | |
160 | * i2c_pnx_master_xmit - transmit data to slave | |
161 | * @adap: pointer to I2C adapter structure | |
162 | * | |
163 | * Sends one byte of data to the slave | |
164 | */ | |
81d6724a | 165 | static int i2c_pnx_master_xmit(struct i2c_pnx_algo_data *alg_data) |
41561f28 | 166 | { |
41561f28 VW |
167 | u32 val; |
168 | ||
81d6724a | 169 | dev_dbg(&alg_data->adapter.dev, "%s(): entering: stat = %04x.\n", |
08882d20 | 170 | __func__, ioread32(I2C_REG_STS(alg_data))); |
41561f28 VW |
171 | |
172 | if (alg_data->mif.len > 0) { | |
173 | /* We still have something to talk about... */ | |
174 | val = *alg_data->mif.buf++; | |
175 | ||
28ad3321 KW |
176 | if (alg_data->mif.len == 1) |
177 | val |= stop_bit; | |
178 | ||
41561f28 VW |
179 | alg_data->mif.len--; |
180 | iowrite32(val, I2C_REG_TX(alg_data)); | |
181 | ||
4be53dbe RK |
182 | dev_dbg(&alg_data->adapter.dev, "%s(): xmit %#x [%d]\n", |
183 | __func__, val, alg_data->mif.len + 1); | |
41561f28 VW |
184 | |
185 | if (alg_data->mif.len == 0) { | |
186 | if (alg_data->last) { | |
187 | /* Wait until the STOP is seen. */ | |
188 | if (wait_timeout(I2C_PNX_TIMEOUT, alg_data)) | |
4be53dbe RK |
189 | dev_err(&alg_data->adapter.dev, |
190 | "The bus is still active after timeout\n"); | |
41561f28 VW |
191 | } |
192 | /* Disable master interrupts */ | |
193 | iowrite32(ioread32(I2C_REG_CTL(alg_data)) & | |
194 | ~(mcntrl_afie | mcntrl_naie | mcntrl_drmie), | |
195 | I2C_REG_CTL(alg_data)); | |
196 | ||
197 | del_timer_sync(&alg_data->mif.timer); | |
198 | ||
4be53dbe RK |
199 | dev_dbg(&alg_data->adapter.dev, |
200 | "%s(): Waking up xfer routine.\n", | |
08882d20 | 201 | __func__); |
41561f28 VW |
202 | |
203 | complete(&alg_data->mif.complete); | |
204 | } | |
205 | } else if (alg_data->mif.len == 0) { | |
206 | /* zero-sized transfer */ | |
81d6724a | 207 | i2c_pnx_stop(alg_data); |
41561f28 VW |
208 | |
209 | /* Disable master interrupts. */ | |
210 | iowrite32(ioread32(I2C_REG_CTL(alg_data)) & | |
211 | ~(mcntrl_afie | mcntrl_naie | mcntrl_drmie), | |
212 | I2C_REG_CTL(alg_data)); | |
213 | ||
214 | /* Stop timer. */ | |
215 | del_timer_sync(&alg_data->mif.timer); | |
4be53dbe RK |
216 | dev_dbg(&alg_data->adapter.dev, |
217 | "%s(): Waking up xfer routine after zero-xfer.\n", | |
218 | __func__); | |
41561f28 VW |
219 | |
220 | complete(&alg_data->mif.complete); | |
221 | } | |
222 | ||
81d6724a | 223 | dev_dbg(&alg_data->adapter.dev, "%s(): exiting: stat = %04x.\n", |
08882d20 | 224 | __func__, ioread32(I2C_REG_STS(alg_data))); |
41561f28 VW |
225 | |
226 | return 0; | |
227 | } | |
228 | ||
229 | /** | |
230 | * i2c_pnx_master_rcv - receive data from slave | |
231 | * @adap: pointer to I2C adapter structure | |
232 | * | |
233 | * Reads one byte data from the slave | |
234 | */ | |
81d6724a | 235 | static int i2c_pnx_master_rcv(struct i2c_pnx_algo_data *alg_data) |
41561f28 | 236 | { |
41561f28 VW |
237 | unsigned int val = 0; |
238 | u32 ctl = 0; | |
239 | ||
81d6724a | 240 | dev_dbg(&alg_data->adapter.dev, "%s(): entering: stat = %04x.\n", |
08882d20 | 241 | __func__, ioread32(I2C_REG_STS(alg_data))); |
41561f28 VW |
242 | |
243 | /* Check, whether there is already data, | |
244 | * or we didn't 'ask' for it yet. | |
245 | */ | |
246 | if (ioread32(I2C_REG_STS(alg_data)) & mstatus_rfe) { | |
4be53dbe RK |
247 | dev_dbg(&alg_data->adapter.dev, |
248 | "%s(): Write dummy data to fill Rx-fifo...\n", | |
249 | __func__); | |
41561f28 VW |
250 | |
251 | if (alg_data->mif.len == 1) { | |
28ad3321 KW |
252 | /* Last byte, do not acknowledge next rcv. */ |
253 | val |= stop_bit; | |
254 | ||
41561f28 VW |
255 | /* |
256 | * Enable interrupt RFDAIE (data in Rx fifo), | |
257 | * and disable DRMIE (need data for Tx) | |
258 | */ | |
259 | ctl = ioread32(I2C_REG_CTL(alg_data)); | |
260 | ctl |= mcntrl_rffie | mcntrl_daie; | |
261 | ctl &= ~mcntrl_drmie; | |
262 | iowrite32(ctl, I2C_REG_CTL(alg_data)); | |
263 | } | |
264 | ||
265 | /* | |
266 | * Now we'll 'ask' for data: | |
267 | * For each byte we want to receive, we must | |
268 | * write a (dummy) byte to the Tx-FIFO. | |
269 | */ | |
270 | iowrite32(val, I2C_REG_TX(alg_data)); | |
271 | ||
272 | return 0; | |
273 | } | |
274 | ||
275 | /* Handle data. */ | |
276 | if (alg_data->mif.len > 0) { | |
277 | val = ioread32(I2C_REG_RX(alg_data)); | |
278 | *alg_data->mif.buf++ = (u8) (val & 0xff); | |
4be53dbe RK |
279 | dev_dbg(&alg_data->adapter.dev, "%s(): rcv 0x%x [%d]\n", |
280 | __func__, val, alg_data->mif.len); | |
41561f28 VW |
281 | |
282 | alg_data->mif.len--; | |
283 | if (alg_data->mif.len == 0) { | |
284 | if (alg_data->last) | |
285 | /* Wait until the STOP is seen. */ | |
286 | if (wait_timeout(I2C_PNX_TIMEOUT, alg_data)) | |
4be53dbe RK |
287 | dev_err(&alg_data->adapter.dev, |
288 | "The bus is still active after timeout\n"); | |
41561f28 VW |
289 | |
290 | /* Disable master interrupts */ | |
291 | ctl = ioread32(I2C_REG_CTL(alg_data)); | |
292 | ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie | | |
293 | mcntrl_drmie | mcntrl_daie); | |
294 | iowrite32(ctl, I2C_REG_CTL(alg_data)); | |
295 | ||
296 | /* Kill timer. */ | |
297 | del_timer_sync(&alg_data->mif.timer); | |
298 | complete(&alg_data->mif.complete); | |
299 | } | |
300 | } | |
301 | ||
81d6724a | 302 | dev_dbg(&alg_data->adapter.dev, "%s(): exiting: stat = %04x.\n", |
08882d20 | 303 | __func__, ioread32(I2C_REG_STS(alg_data))); |
41561f28 VW |
304 | |
305 | return 0; | |
306 | } | |
307 | ||
6c566fb7 | 308 | static irqreturn_t i2c_pnx_interrupt(int irq, void *dev_id) |
41561f28 | 309 | { |
81d6724a | 310 | struct i2c_pnx_algo_data *alg_data = dev_id; |
41561f28 | 311 | u32 stat, ctl; |
41561f28 | 312 | |
4be53dbe RK |
313 | dev_dbg(&alg_data->adapter.dev, |
314 | "%s(): mstat = %x mctrl = %x, mode = %d\n", | |
08882d20 | 315 | __func__, |
41561f28 VW |
316 | ioread32(I2C_REG_STS(alg_data)), |
317 | ioread32(I2C_REG_CTL(alg_data)), | |
318 | alg_data->mif.mode); | |
319 | stat = ioread32(I2C_REG_STS(alg_data)); | |
320 | ||
321 | /* let's see what kind of event this is */ | |
322 | if (stat & mstatus_afi) { | |
323 | /* We lost arbitration in the midst of a transfer */ | |
324 | alg_data->mif.ret = -EIO; | |
325 | ||
326 | /* Disable master interrupts. */ | |
327 | ctl = ioread32(I2C_REG_CTL(alg_data)); | |
328 | ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie | | |
329 | mcntrl_drmie); | |
330 | iowrite32(ctl, I2C_REG_CTL(alg_data)); | |
331 | ||
332 | /* Stop timer, to prevent timeout. */ | |
333 | del_timer_sync(&alg_data->mif.timer); | |
334 | complete(&alg_data->mif.complete); | |
335 | } else if (stat & mstatus_nai) { | |
336 | /* Slave did not acknowledge, generate a STOP */ | |
4be53dbe RK |
337 | dev_dbg(&alg_data->adapter.dev, |
338 | "%s(): Slave did not acknowledge, generating a STOP.\n", | |
08882d20 | 339 | __func__); |
81d6724a | 340 | i2c_pnx_stop(alg_data); |
41561f28 VW |
341 | |
342 | /* Disable master interrupts. */ | |
343 | ctl = ioread32(I2C_REG_CTL(alg_data)); | |
344 | ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie | | |
345 | mcntrl_drmie); | |
346 | iowrite32(ctl, I2C_REG_CTL(alg_data)); | |
347 | ||
348 | /* Our return value. */ | |
349 | alg_data->mif.ret = -EIO; | |
350 | ||
351 | /* Stop timer, to prevent timeout. */ | |
352 | del_timer_sync(&alg_data->mif.timer); | |
353 | complete(&alg_data->mif.complete); | |
354 | } else { | |
355 | /* | |
356 | * Two options: | |
357 | * - Master Tx needs data. | |
358 | * - There is data in the Rx-fifo | |
359 | * The latter is only the case if we have requested for data, | |
360 | * via a dummy write. (See 'i2c_pnx_master_rcv'.) | |
361 | * We therefore check, as a sanity check, whether that interrupt | |
362 | * has been enabled. | |
363 | */ | |
364 | if ((stat & mstatus_drmi) || !(stat & mstatus_rfe)) { | |
365 | if (alg_data->mif.mode == I2C_SMBUS_WRITE) { | |
81d6724a | 366 | i2c_pnx_master_xmit(alg_data); |
41561f28 | 367 | } else if (alg_data->mif.mode == I2C_SMBUS_READ) { |
81d6724a | 368 | i2c_pnx_master_rcv(alg_data); |
41561f28 VW |
369 | } |
370 | } | |
371 | } | |
372 | ||
373 | /* Clear TDI and AFI bits */ | |
374 | stat = ioread32(I2C_REG_STS(alg_data)); | |
375 | iowrite32(stat | mstatus_tdi | mstatus_afi, I2C_REG_STS(alg_data)); | |
376 | ||
4be53dbe RK |
377 | dev_dbg(&alg_data->adapter.dev, |
378 | "%s(): exiting, stat = %x ctrl = %x.\n", | |
08882d20 | 379 | __func__, ioread32(I2C_REG_STS(alg_data)), |
41561f28 VW |
380 | ioread32(I2C_REG_CTL(alg_data))); |
381 | ||
382 | return IRQ_HANDLED; | |
383 | } | |
384 | ||
385 | static void i2c_pnx_timeout(unsigned long data) | |
386 | { | |
81d6724a | 387 | struct i2c_pnx_algo_data *alg_data = (struct i2c_pnx_algo_data *)data; |
41561f28 VW |
388 | u32 ctl; |
389 | ||
4be53dbe RK |
390 | dev_err(&alg_data->adapter.dev, |
391 | "Master timed out. stat = %04x, cntrl = %04x. Resetting master...\n", | |
392 | ioread32(I2C_REG_STS(alg_data)), | |
393 | ioread32(I2C_REG_CTL(alg_data))); | |
41561f28 VW |
394 | |
395 | /* Reset master and disable interrupts */ | |
396 | ctl = ioread32(I2C_REG_CTL(alg_data)); | |
397 | ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie | mcntrl_drmie); | |
398 | iowrite32(ctl, I2C_REG_CTL(alg_data)); | |
399 | ||
400 | ctl |= mcntrl_reset; | |
401 | iowrite32(ctl, I2C_REG_CTL(alg_data)); | |
402 | wait_reset(I2C_PNX_TIMEOUT, alg_data); | |
403 | alg_data->mif.ret = -EIO; | |
404 | complete(&alg_data->mif.complete); | |
405 | } | |
406 | ||
81d6724a | 407 | static inline void bus_reset_if_active(struct i2c_pnx_algo_data *alg_data) |
41561f28 | 408 | { |
41561f28 VW |
409 | u32 stat; |
410 | ||
411 | if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_active) { | |
81d6724a | 412 | dev_err(&alg_data->adapter.dev, |
41561f28 | 413 | "%s: Bus is still active after xfer. Reset it...\n", |
4be53dbe | 414 | alg_data->adapter.name); |
41561f28 VW |
415 | iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset, |
416 | I2C_REG_CTL(alg_data)); | |
417 | wait_reset(I2C_PNX_TIMEOUT, alg_data); | |
418 | } else if (!(stat & mstatus_rfe) || !(stat & mstatus_tfe)) { | |
419 | /* If there is data in the fifo's after transfer, | |
420 | * flush fifo's by reset. | |
421 | */ | |
422 | iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset, | |
423 | I2C_REG_CTL(alg_data)); | |
424 | wait_reset(I2C_PNX_TIMEOUT, alg_data); | |
425 | } else if (stat & mstatus_nai) { | |
426 | iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset, | |
427 | I2C_REG_CTL(alg_data)); | |
428 | wait_reset(I2C_PNX_TIMEOUT, alg_data); | |
429 | } | |
430 | } | |
431 | ||
432 | /** | |
433 | * i2c_pnx_xfer - generic transfer entry point | |
434 | * @adap: pointer to I2C adapter structure | |
435 | * @msgs: array of messages | |
436 | * @num: number of messages | |
437 | * | |
438 | * Initiates the transfer | |
439 | */ | |
440 | static int | |
441 | i2c_pnx_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) | |
442 | { | |
443 | struct i2c_msg *pmsg; | |
444 | int rc = 0, completed = 0, i; | |
445 | struct i2c_pnx_algo_data *alg_data = adap->algo_data; | |
446 | u32 stat = ioread32(I2C_REG_STS(alg_data)); | |
447 | ||
4be53dbe RK |
448 | dev_dbg(&alg_data->adapter.dev, |
449 | "%s(): entering: %d messages, stat = %04x.\n", | |
08882d20 | 450 | __func__, num, ioread32(I2C_REG_STS(alg_data))); |
41561f28 | 451 | |
81d6724a | 452 | bus_reset_if_active(alg_data); |
41561f28 VW |
453 | |
454 | /* Process transactions in a loop. */ | |
455 | for (i = 0; rc >= 0 && i < num; i++) { | |
456 | u8 addr; | |
457 | ||
458 | pmsg = &msgs[i]; | |
459 | addr = pmsg->addr; | |
460 | ||
461 | if (pmsg->flags & I2C_M_TEN) { | |
81d6724a | 462 | dev_err(&alg_data->adapter.dev, |
41561f28 | 463 | "%s: 10 bits addr not supported!\n", |
81d6724a | 464 | alg_data->adapter.name); |
41561f28 VW |
465 | rc = -EINVAL; |
466 | break; | |
467 | } | |
468 | ||
469 | alg_data->mif.buf = pmsg->buf; | |
470 | alg_data->mif.len = pmsg->len; | |
471 | alg_data->mif.mode = (pmsg->flags & I2C_M_RD) ? | |
472 | I2C_SMBUS_READ : I2C_SMBUS_WRITE; | |
473 | alg_data->mif.ret = 0; | |
474 | alg_data->last = (i == num - 1); | |
475 | ||
4be53dbe RK |
476 | dev_dbg(&alg_data->adapter.dev, "%s(): mode %d, %d bytes\n", |
477 | __func__, alg_data->mif.mode, alg_data->mif.len); | |
41561f28 | 478 | |
81d6724a | 479 | i2c_pnx_arm_timer(alg_data); |
41561f28 VW |
480 | |
481 | /* initialize the completion var */ | |
482 | init_completion(&alg_data->mif.complete); | |
483 | ||
484 | /* Enable master interrupt */ | |
485 | iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_afie | | |
486 | mcntrl_naie | mcntrl_drmie, | |
487 | I2C_REG_CTL(alg_data)); | |
488 | ||
489 | /* Put start-code and slave-address on the bus. */ | |
81d6724a | 490 | rc = i2c_pnx_start(addr, alg_data); |
41561f28 VW |
491 | if (rc < 0) |
492 | break; | |
493 | ||
494 | /* Wait for completion */ | |
495 | wait_for_completion(&alg_data->mif.complete); | |
496 | ||
497 | if (!(rc = alg_data->mif.ret)) | |
498 | completed++; | |
4be53dbe RK |
499 | dev_dbg(&alg_data->adapter.dev, |
500 | "%s(): Complete, return code = %d.\n", | |
08882d20 | 501 | __func__, rc); |
41561f28 VW |
502 | |
503 | /* Clear TDI and AFI bits in case they are set. */ | |
504 | if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_tdi) { | |
81d6724a | 505 | dev_dbg(&alg_data->adapter.dev, |
41561f28 | 506 | "%s: TDI still set... clearing now.\n", |
81d6724a | 507 | alg_data->adapter.name); |
41561f28 VW |
508 | iowrite32(stat, I2C_REG_STS(alg_data)); |
509 | } | |
510 | if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_afi) { | |
81d6724a | 511 | dev_dbg(&alg_data->adapter.dev, |
41561f28 | 512 | "%s: AFI still set... clearing now.\n", |
81d6724a | 513 | alg_data->adapter.name); |
41561f28 VW |
514 | iowrite32(stat, I2C_REG_STS(alg_data)); |
515 | } | |
516 | } | |
517 | ||
81d6724a | 518 | bus_reset_if_active(alg_data); |
41561f28 VW |
519 | |
520 | /* Cleanup to be sure... */ | |
521 | alg_data->mif.buf = NULL; | |
522 | alg_data->mif.len = 0; | |
523 | ||
81d6724a | 524 | dev_dbg(&alg_data->adapter.dev, "%s(): exiting, stat = %x\n", |
08882d20 | 525 | __func__, ioread32(I2C_REG_STS(alg_data))); |
41561f28 VW |
526 | |
527 | if (completed != num) | |
528 | return ((rc < 0) ? rc : -EREMOTEIO); | |
529 | ||
530 | return num; | |
531 | } | |
532 | ||
533 | static u32 i2c_pnx_func(struct i2c_adapter *adapter) | |
534 | { | |
535 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; | |
536 | } | |
537 | ||
538 | static struct i2c_algorithm pnx_algorithm = { | |
539 | .master_xfer = i2c_pnx_xfer, | |
540 | .functionality = i2c_pnx_func, | |
541 | }; | |
542 | ||
a0dcf19f | 543 | #ifdef CONFIG_PM |
41561f28 VW |
544 | static int i2c_pnx_controller_suspend(struct platform_device *pdev, |
545 | pm_message_t state) | |
546 | { | |
9d7f7363 | 547 | struct i2c_pnx_algo_data *alg_data = platform_get_drvdata(pdev); |
0321cb83 | 548 | |
ebdbbf20 RK |
549 | /* FIXME: shouldn't this be clk_disable? */ |
550 | clk_enable(alg_data->clk); | |
0321cb83 RK |
551 | |
552 | return 0; | |
41561f28 VW |
553 | } |
554 | ||
555 | static int i2c_pnx_controller_resume(struct platform_device *pdev) | |
556 | { | |
9d7f7363 | 557 | struct i2c_pnx_algo_data *alg_data = platform_get_drvdata(pdev); |
0321cb83 | 558 | |
ebdbbf20 | 559 | return clk_enable(alg_data->clk); |
41561f28 | 560 | } |
a0dcf19f RK |
561 | #else |
562 | #define i2c_pnx_controller_suspend NULL | |
563 | #define i2c_pnx_controller_resume NULL | |
564 | #endif | |
41561f28 VW |
565 | |
566 | static int __devinit i2c_pnx_probe(struct platform_device *pdev) | |
567 | { | |
568 | unsigned long tmp; | |
569 | int ret = 0; | |
570 | struct i2c_pnx_algo_data *alg_data; | |
6fff3da9 | 571 | unsigned long freq; |
41561f28 VW |
572 | struct i2c_pnx_data *i2c_pnx = pdev->dev.platform_data; |
573 | ||
9d7f7363 | 574 | if (!i2c_pnx || !i2c_pnx->name) { |
41561f28 | 575 | dev_err(&pdev->dev, "%s: no platform data supplied\n", |
08882d20 | 576 | __func__); |
41561f28 VW |
577 | ret = -EINVAL; |
578 | goto out; | |
579 | } | |
580 | ||
44c5d739 RK |
581 | alg_data = kzalloc(sizeof(*alg_data), GFP_KERNEL); |
582 | if (!alg_data) { | |
583 | ret = -ENOMEM; | |
584 | goto err_kzalloc; | |
585 | } | |
586 | ||
9d7f7363 | 587 | platform_set_drvdata(pdev, alg_data); |
41561f28 | 588 | |
9d7f7363 RK |
589 | strlcpy(alg_data->adapter.name, i2c_pnx->name, |
590 | sizeof(alg_data->adapter.name)); | |
591 | alg_data->adapter.dev.parent = &pdev->dev; | |
592 | alg_data->adapter.algo = &pnx_algorithm; | |
593 | alg_data->adapter.algo_data = alg_data; | |
594 | alg_data->adapter.nr = pdev->id; | |
595 | alg_data->i2c_pnx = i2c_pnx; | |
0321cb83 RK |
596 | |
597 | alg_data->clk = clk_get(&pdev->dev, NULL); | |
598 | if (IS_ERR(alg_data->clk)) { | |
599 | ret = PTR_ERR(alg_data->clk); | |
600 | goto out_drvdata; | |
601 | } | |
602 | ||
41561f28 VW |
603 | init_timer(&alg_data->mif.timer); |
604 | alg_data->mif.timer.function = i2c_pnx_timeout; | |
81d6724a | 605 | alg_data->mif.timer.data = (unsigned long)alg_data; |
41561f28 VW |
606 | |
607 | /* Register I/O resource */ | |
44c5d739 | 608 | if (!request_mem_region(i2c_pnx->base, I2C_PNX_REGION_SIZE, |
449d2c75 | 609 | pdev->name)) { |
41561f28 VW |
610 | dev_err(&pdev->dev, |
611 | "I/O region 0x%08x for I2C already in use.\n", | |
44c5d739 | 612 | i2c_pnx->base); |
41561f28 | 613 | ret = -ENODEV; |
0321cb83 | 614 | goto out_clkget; |
41561f28 VW |
615 | } |
616 | ||
44c5d739 | 617 | alg_data->ioaddr = ioremap(i2c_pnx->base, I2C_PNX_REGION_SIZE); |
88d968b2 | 618 | if (!alg_data->ioaddr) { |
41561f28 VW |
619 | dev_err(&pdev->dev, "Couldn't ioremap I2C I/O region\n"); |
620 | ret = -ENOMEM; | |
621 | goto out_release; | |
622 | } | |
623 | ||
ebdbbf20 RK |
624 | ret = clk_enable(alg_data->clk); |
625 | if (ret) | |
626 | goto out_unmap; | |
41561f28 | 627 | |
6fff3da9 RK |
628 | freq = clk_get_rate(alg_data->clk); |
629 | ||
41561f28 VW |
630 | /* |
631 | * Clock Divisor High This value is the number of system clocks | |
632 | * the serial clock (SCL) will be high. | |
633 | * For example, if the system clock period is 50 ns and the maximum | |
634 | * desired serial period is 10000 ns (100 kHz), then CLKHI would be | |
635 | * set to 0.5*(f_sys/f_i2c)-2=0.5*(20e6/100e3)-2=98. The actual value | |
636 | * programmed into CLKHI will vary from this slightly due to | |
637 | * variations in the output pad's rise and fall times as well as | |
638 | * the deglitching filter length. | |
639 | */ | |
640 | ||
6fff3da9 | 641 | tmp = ((freq / 1000) / I2C_PNX_SPEED_KHZ) / 2 - 2; |
be80dbaa KW |
642 | if (tmp > 0x3FF) |
643 | tmp = 0x3FF; | |
41561f28 VW |
644 | iowrite32(tmp, I2C_REG_CKH(alg_data)); |
645 | iowrite32(tmp, I2C_REG_CKL(alg_data)); | |
646 | ||
647 | iowrite32(mcntrl_reset, I2C_REG_CTL(alg_data)); | |
648 | if (wait_reset(I2C_PNX_TIMEOUT, alg_data)) { | |
649 | ret = -ENODEV; | |
ebdbbf20 | 650 | goto out_clock; |
41561f28 VW |
651 | } |
652 | init_completion(&alg_data->mif.complete); | |
653 | ||
44c5d739 | 654 | ret = request_irq(i2c_pnx->irq, i2c_pnx_interrupt, |
81d6724a | 655 | 0, pdev->name, alg_data); |
41561f28 VW |
656 | if (ret) |
657 | goto out_clock; | |
658 | ||
659 | /* Register this adapter with the I2C subsystem */ | |
9d7f7363 | 660 | ret = i2c_add_numbered_adapter(&alg_data->adapter); |
41561f28 VW |
661 | if (ret < 0) { |
662 | dev_err(&pdev->dev, "I2C: Failed to add bus\n"); | |
663 | goto out_irq; | |
664 | } | |
665 | ||
666 | dev_dbg(&pdev->dev, "%s: Master at %#8x, irq %d.\n", | |
9d7f7363 | 667 | alg_data->adapter.name, i2c_pnx->base, i2c_pnx->irq); |
41561f28 VW |
668 | |
669 | return 0; | |
670 | ||
671 | out_irq: | |
81d6724a | 672 | free_irq(i2c_pnx->irq, alg_data); |
41561f28 | 673 | out_clock: |
ebdbbf20 | 674 | clk_disable(alg_data->clk); |
41561f28 | 675 | out_unmap: |
88d968b2 | 676 | iounmap(alg_data->ioaddr); |
41561f28 | 677 | out_release: |
44c5d739 | 678 | release_mem_region(i2c_pnx->base, I2C_PNX_REGION_SIZE); |
0321cb83 RK |
679 | out_clkget: |
680 | clk_put(alg_data->clk); | |
41561f28 | 681 | out_drvdata: |
44c5d739 RK |
682 | kfree(alg_data); |
683 | err_kzalloc: | |
41561f28 VW |
684 | platform_set_drvdata(pdev, NULL); |
685 | out: | |
686 | return ret; | |
687 | } | |
688 | ||
689 | static int __devexit i2c_pnx_remove(struct platform_device *pdev) | |
690 | { | |
9d7f7363 RK |
691 | struct i2c_pnx_algo_data *alg_data = platform_get_drvdata(pdev); |
692 | struct i2c_pnx_data *i2c_pnx = alg_data->i2c_pnx; | |
41561f28 | 693 | |
81d6724a | 694 | free_irq(i2c_pnx->irq, alg_data); |
9d7f7363 | 695 | i2c_del_adapter(&alg_data->adapter); |
ebdbbf20 | 696 | clk_disable(alg_data->clk); |
88d968b2 | 697 | iounmap(alg_data->ioaddr); |
44c5d739 | 698 | release_mem_region(i2c_pnx->base, I2C_PNX_REGION_SIZE); |
0321cb83 | 699 | clk_put(alg_data->clk); |
44c5d739 | 700 | kfree(alg_data); |
41561f28 VW |
701 | platform_set_drvdata(pdev, NULL); |
702 | ||
703 | return 0; | |
704 | } | |
705 | ||
706 | static struct platform_driver i2c_pnx_driver = { | |
707 | .driver = { | |
708 | .name = "pnx-i2c", | |
709 | .owner = THIS_MODULE, | |
710 | }, | |
711 | .probe = i2c_pnx_probe, | |
712 | .remove = __devexit_p(i2c_pnx_remove), | |
713 | .suspend = i2c_pnx_controller_suspend, | |
714 | .resume = i2c_pnx_controller_resume, | |
715 | }; | |
716 | ||
717 | static int __init i2c_adap_pnx_init(void) | |
718 | { | |
719 | return platform_driver_register(&i2c_pnx_driver); | |
720 | } | |
721 | ||
722 | static void __exit i2c_adap_pnx_exit(void) | |
723 | { | |
724 | platform_driver_unregister(&i2c_pnx_driver); | |
725 | } | |
726 | ||
727 | MODULE_AUTHOR("Vitaly Wool, Dennis Kovalev <source@mvista.com>"); | |
728 | MODULE_DESCRIPTION("I2C driver for Philips IP3204-based I2C busses"); | |
729 | MODULE_LICENSE("GPL"); | |
add8eda7 | 730 | MODULE_ALIAS("platform:pnx-i2c"); |
41561f28 | 731 | |
41561f28 VW |
732 | /* We need to make sure I2C is initialized before USB */ |
733 | subsys_initcall(i2c_adap_pnx_init); | |
41561f28 | 734 | module_exit(i2c_adap_pnx_exit); |