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x86: move hp-wmi's probe function to .devinit.text
[linux-2.6-block.git] / drivers / i2c / busses / i2c-omap.c
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010d442c
KS		 1/*
2 * TI OMAP I2C master mode driver
3 *
4 * Copyright (C) 2003 MontaVista Software, Inc.
010d442c 5 * Copyright (C) 2005 Nokia Corporation
c1a473bd 6 * Copyright (C) 2004 - 2007 Texas Instruments.
010d442c 7 *
c1a473bd
TL		 8 * Originally written by MontaVista Software, Inc.
9 * Additional contributions by:
10 * Tony Lindgren <tony@atomide.com>
11 * Imre Deak <imre.deak@nokia.com>
12 * Juha Yrjölä <juha.yrjola@solidboot.com>
13 * Syed Khasim <x0khasim@ti.com>
14 * Nishant Menon <nm@ti.com>
010d442c
KS		 15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30
31#include <linux/module.h>
32#include <linux/delay.h>
33#include <linux/i2c.h>
34#include <linux/err.h>
35#include <linux/interrupt.h>
36#include <linux/completion.h>
37#include <linux/platform_device.h>
38#include <linux/clk.h>
c1a473bd 39#include <linux/io.h>
010d442c 40
9c76b878
PW		 41/* I2C controller revisions */
42#define OMAP_I2C_REV_2 0x20
43
44/* I2C controller revisions present on specific hardware */
45#define OMAP_I2C_REV_ON_2430 0x36
46#define OMAP_I2C_REV_ON_3430 0x3C
47
010d442c
KS		 48/* timeout waiting for the controller to respond */
49#define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
50
51#define OMAP_I2C_REV_REG 0x00
d84d3ea3
CM		 52#define OMAP_I2C_IE_REG 0x01
53#define OMAP_I2C_STAT_REG 0x02
54#define OMAP_I2C_IV_REG 0x03
5043e9e7 55/* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
d84d3ea3
CM		 56#define OMAP_I2C_WE_REG 0x03
57#define OMAP_I2C_SYSS_REG 0x04
58#define OMAP_I2C_BUF_REG 0x05
59#define OMAP_I2C_CNT_REG 0x06
60#define OMAP_I2C_DATA_REG 0x07
61#define OMAP_I2C_SYSC_REG 0x08
62#define OMAP_I2C_CON_REG 0x09
63#define OMAP_I2C_OA_REG 0x0a
64#define OMAP_I2C_SA_REG 0x0b
65#define OMAP_I2C_PSC_REG 0x0c
66#define OMAP_I2C_SCLL_REG 0x0d
67#define OMAP_I2C_SCLH_REG 0x0e
68#define OMAP_I2C_SYSTEST_REG 0x0f
69#define OMAP_I2C_BUFSTAT_REG 0x10
010d442c
KS		 70
71/* I2C Interrupt Enable Register (OMAP_I2C_IE): */
b6ee52c3
NM		 72#define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */
73#define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */
010d442c
KS		 74#define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */
75#define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */
76#define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */
77#define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */
78#define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */
79
80/* I2C Status Register (OMAP_I2C_STAT): */
b6ee52c3
NM		 81#define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */
82#define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */
010d442c
KS		 83#define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */
84#define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */
85#define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
86#define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */
87#define OMAP_I2C_STAT_AD0 (1 << 8) /* Address zero */
88#define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
89#define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */
90#define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */
91#define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */
92#define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */
93
5043e9e7
KJ		 94/* I2C WE wakeup enable register */
95#define OMAP_I2C_WE_XDR_WE (1 << 14) /* TX drain wakup */
96#define OMAP_I2C_WE_RDR_WE (1 << 13) /* RX drain wakeup */
97#define OMAP_I2C_WE_AAS_WE (1 << 9) /* Address as slave wakeup*/
98#define OMAP_I2C_WE_BF_WE (1 << 8) /* Bus free wakeup */
99#define OMAP_I2C_WE_STC_WE (1 << 6) /* Start condition wakeup */
100#define OMAP_I2C_WE_GC_WE (1 << 5) /* General call wakeup */
101#define OMAP_I2C_WE_DRDY_WE (1 << 3) /* TX/RX data ready wakeup */
102#define OMAP_I2C_WE_ARDY_WE (1 << 2) /* Reg access ready wakeup */
103#define OMAP_I2C_WE_NACK_WE (1 << 1) /* No acknowledgment wakeup */
104#define OMAP_I2C_WE_AL_WE (1 << 0) /* Arbitration lost wakeup */
105
106#define OMAP_I2C_WE_ALL (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \
107 OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \
108 OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \
109 OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \
110 OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE)
111
010d442c
KS		 112/* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
113#define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */
b6ee52c3 114#define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */
010d442c 115#define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */
b6ee52c3 116#define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */
010d442c
KS		 117
118/* I2C Configuration Register (OMAP_I2C_CON): */
119#define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */
120#define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */
b6ee52c3 121#define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */
010d442c
KS		 122#define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */
123#define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */
124#define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */
125#define OMAP_I2C_CON_XA (1 << 8) /* Expand address */
126#define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */
127#define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */
128#define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */
129
4574eb68
SMK		 130/* I2C SCL time value when Master */
131#define OMAP_I2C_SCLL_HSSCLL 8
132#define OMAP_I2C_SCLH_HSSCLH 8
133
010d442c
KS		 134/* I2C System Test Register (OMAP_I2C_SYSTEST): */
135#ifdef DEBUG
136#define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
137#define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */
138#define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
139#define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
140#define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */
141#define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */
142#define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */
143#define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */
144#endif
145
fdd07fe6
PW		 146/* OCP_SYSSTATUS bit definitions */
147#define SYSS_RESETDONE_MASK (1 << 0)
148
149/* OCP_SYSCONFIG bit definitions */
150#define SYSC_CLOCKACTIVITY_MASK (0x3 << 8)
151#define SYSC_SIDLEMODE_MASK (0x3 << 3)
152#define SYSC_ENAWAKEUP_MASK (1 << 2)
153#define SYSC_SOFTRESET_MASK (1 << 1)
154#define SYSC_AUTOIDLE_MASK (1 << 0)
155
156#define SYSC_IDLEMODE_SMART 0x2
157#define SYSC_CLOCKACTIVITY_FCLK 0x2
010d442c 158
010d442c 159
010d442c
KS		 160struct omap_i2c_dev {
161 struct device *dev;
162 void __iomem *base; /* virtual */
163 int irq;
d84d3ea3 164 int reg_shift; /* bit shift for I2C register addresses */
010d442c
KS		 165 struct clk *iclk; /* Interface clock */
166 struct clk *fclk; /* Functional clock */
167 struct completion cmd_complete;
168 struct resource *ioarea;
4574eb68 169 u32 speed; /* Speed of bus in Khz */
010d442c
KS		 170 u16 cmd_err;
171 u8 *buf;
172 size_t buf_len;
173 struct i2c_adapter adapter;
b6ee52c3
NM		 174 u8 fifo_size; /* use as flag and value
175 * fifo_size==0 implies no fifo
176 * if set, should be trsh+1
177 */
9c76b878 178 u8 rev;
b6ee52c3 179 unsigned b_hw:1; /* bad h/w fixes */
f08ac4e7
TL		 180 unsigned idle:1;
181 u16 iestate; /* Saved interrupt register */
ef871432
RN		 182 u16 pscstate;
183 u16 scllstate;
184 u16 sclhstate;
185 u16 bufstate;
186 u16 syscstate;
187 u16 westate;
010d442c
KS		 188};
189
190static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
191 int reg, u16 val)
192{
d84d3ea3 193 __raw_writew(val, i2c_dev->base + (reg << i2c_dev->reg_shift));
010d442c
KS		 194}
195
196static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
197{
d84d3ea3 198 return __raw_readw(i2c_dev->base + (reg << i2c_dev->reg_shift));
010d442c
KS		 199}
200
510be9c9 201static int __init omap_i2c_get_clocks(struct omap_i2c_dev *dev)
010d442c 202{
5fe23380
RK		 203 int ret;
204
205 dev->iclk = clk_get(dev->dev, "ick");
206 if (IS_ERR(dev->iclk)) {
207 ret = PTR_ERR(dev->iclk);
208 dev->iclk = NULL;
209 return ret;
010d442c
KS		 210 }
211
1d14de08 212 dev->fclk = clk_get(dev->dev, "fck");
010d442c 213 if (IS_ERR(dev->fclk)) {
5fe23380 214 ret = PTR_ERR(dev->fclk);
010d442c
KS		 215 if (dev->iclk != NULL) {
216 clk_put(dev->iclk);
217 dev->iclk = NULL;
218 }
219 dev->fclk = NULL;
5fe23380 220 return ret;
010d442c
KS		 221 }
222
223 return 0;
224}
225
226static void omap_i2c_put_clocks(struct omap_i2c_dev *dev)
227{
228 clk_put(dev->fclk);
229 dev->fclk = NULL;
5fe23380
RK		 230 clk_put(dev->iclk);
231 dev->iclk = NULL;
010d442c
KS		 232}
233
f08ac4e7 234static void omap_i2c_unidle(struct omap_i2c_dev *dev)
010d442c 235{
3831f154
PW		 236 WARN_ON(!dev->idle);
237
5fe23380 238 clk_enable(dev->iclk);
010d442c 239 clk_enable(dev->fclk);
ef871432
RN		 240 if (cpu_is_omap34xx()) {
241 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
242 omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, dev->pscstate);
243 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, dev->scllstate);
244 omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, dev->sclhstate);
245 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, dev->bufstate);
246 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, dev->syscstate);
247 omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate);
248 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
249 }
0cbbcffd 250 dev->idle = 0;
07ac31f6
CM		 251
252 /*
253 * Don't write to this register if the IE state is 0 as it can
254 * cause deadlock.
255 */
256 if (dev->iestate)
257 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
010d442c
KS		 258}
259
f08ac4e7 260static void omap_i2c_idle(struct omap_i2c_dev *dev)
010d442c 261{
f08ac4e7
TL		 262 u16 iv;
263
3831f154
PW		 264 WARN_ON(dev->idle);
265
f08ac4e7
TL		 266 dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
267 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0);
9c76b878 268 if (dev->rev < OMAP_I2C_REV_2) {
c1a473bd 269 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); /* Read clears */
0cbbcffd 270 } else {
f08ac4e7 271 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, dev->iestate);
0cbbcffd
PW		 272
273 /* Flush posted write before the dev->idle store occurs */
274 omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
275 }
276 dev->idle = 1;
f08ac4e7 277 clk_disable(dev->fclk);
5fe23380 278 clk_disable(dev->iclk);
010d442c
KS		 279}
280
281static int omap_i2c_init(struct omap_i2c_dev *dev)
282{
ef871432 283 u16 psc = 0, scll = 0, sclh = 0, buf = 0;
4574eb68 284 u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
010d442c
KS		 285 unsigned long fclk_rate = 12000000;
286 unsigned long timeout;
4574eb68 287 unsigned long internal_clk = 0;
010d442c 288
9c76b878 289 if (dev->rev >= OMAP_I2C_REV_2) {
57eb81b1
MG		 290 /* Disable I2C controller before soft reset */
291 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
292 omap_i2c_read_reg(dev, OMAP_I2C_CON_REG) &
293 ~(OMAP_I2C_CON_EN));
294
fdd07fe6 295 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK);
010d442c
KS		 296 /* For some reason we need to set the EN bit before the
297 * reset done bit gets set. */
298 timeout = jiffies + OMAP_I2C_TIMEOUT;
299 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
300 while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
fdd07fe6 301 SYSS_RESETDONE_MASK)) {
010d442c 302 if (time_after(jiffies, timeout)) {
fce3ff03 303 dev_warn(dev->dev, "timeout waiting "
010d442c
KS		 304 "for controller reset\n");
305 return -ETIMEDOUT;
306 }
307 msleep(1);
308 }
fdd07fe6
PW		 309
310 /* SYSC register is cleared by the reset; rewrite it */
311 if (dev->rev == OMAP_I2C_REV_ON_2430) {
312
313 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
314 SYSC_AUTOIDLE_MASK);
315
316 } else if (dev->rev >= OMAP_I2C_REV_ON_3430) {
ef871432
RN		 317 dev->syscstate = SYSC_AUTOIDLE_MASK;
318 dev->syscstate |= SYSC_ENAWAKEUP_MASK;
319 dev->syscstate |= (SYSC_IDLEMODE_SMART <<
fdd07fe6 320 __ffs(SYSC_SIDLEMODE_MASK));
ef871432 321 dev->syscstate |= (SYSC_CLOCKACTIVITY_FCLK <<
fdd07fe6
PW		 322 __ffs(SYSC_CLOCKACTIVITY_MASK));
323
ef871432
RN		 324 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
325 dev->syscstate);
5043e9e7
KJ		 326 /*
327 * Enabling all wakup sources to stop I2C freezing on
328 * WFI instruction.
329 * REVISIT: Some wkup sources might not be needed.
330 */
ef871432
RN		 331 dev->westate = OMAP_I2C_WE_ALL;
332 omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate);
fdd07fe6 333 }
010d442c
KS		 334 }
335 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
336
337 if (cpu_class_is_omap1()) {
0e9ae109
RK		 338 /*
339 * The I2C functional clock is the armxor_ck, so there's
340 * no need to get "armxor_ck" separately. Now, if OMAP2420
341 * always returns 12MHz for the functional clock, we can
342 * do this bit unconditionally.
343 */
344 fclk_rate = clk_get_rate(dev->fclk);
345
010d442c
KS		 346 /* TRM for 5912 says the I2C clock must be prescaled to be
347 * between 7 - 12 MHz. The XOR input clock is typically
348 * 12, 13 or 19.2 MHz. So we should have code that produces:
349 *
350 * XOR MHz Divider Prescaler
351 * 12 1 0
352 * 13 2 1
353 * 19.2 2 1
354 */
d7aef138
JD		 355 if (fclk_rate > 12000000)
356 psc = fclk_rate / 12000000;
010d442c
KS		 357 }
358
3d522fb4 359 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
4574eb68 360
84bf2c86
AK		 361 /*
362 * HSI2C controller internal clk rate should be 19.2 Mhz for
363 * HS and for all modes on 2430. On 34xx we can use lower rate
364 * to get longer filter period for better noise suppression.
365 * The filter is iclk (fclk for HS) period.
366 */
ff0f2426 367 if (dev->speed > 400 || cpu_is_omap2430())
84bf2c86
AK		 368 internal_clk = 19200;
369 else if (dev->speed > 100)
370 internal_clk = 9600;
371 else
372 internal_clk = 4000;
4574eb68
SMK		 373 fclk_rate = clk_get_rate(dev->fclk) / 1000;
374
375 /* Compute prescaler divisor */
376 psc = fclk_rate / internal_clk;
377 psc = psc - 1;
378
379 /* If configured for High Speed */
380 if (dev->speed > 400) {
baf46b4e
AK		 381 unsigned long scl;
382
4574eb68 383 /* For first phase of HS mode */
baf46b4e
AK		 384 scl = internal_clk / 400;
385 fsscll = scl - (scl / 3) - 7;
386 fssclh = (scl / 3) - 5;
4574eb68
SMK		 387
388 /* For second phase of HS mode */
baf46b4e
AK		 389 scl = fclk_rate / dev->speed;
390 hsscll = scl - (scl / 3) - 7;
391 hssclh = (scl / 3) - 5;
392 } else if (dev->speed > 100) {
393 unsigned long scl;
394
395 /* Fast mode */
396 scl = internal_clk / dev->speed;
397 fsscll = scl - (scl / 3) - 7;
398 fssclh = (scl / 3) - 5;
4574eb68 399 } else {
baf46b4e
AK		 400 /* Standard mode */
401 fsscll = internal_clk / (dev->speed * 2) - 7;
402 fssclh = internal_clk / (dev->speed * 2) - 5;
4574eb68
SMK		 403 }
404 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
405 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
406 } else {
407 /* Program desired operating rate */
408 fclk_rate /= (psc + 1) * 1000;
409 if (psc > 2)
410 psc = 2;
411 scll = fclk_rate / (dev->speed * 2) - 7 + psc;
412 sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
413 }
414
010d442c
KS		 415 /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
416 omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);
417
4574eb68
SMK		 418 /* SCL low and high time values */
419 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll);
420 omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh);
010d442c 421
ef871432
RN		 422 if (dev->fifo_size) {
423 /* Note: setup required fifo size - 1. RTRSH and XTRSH */
424 buf = (dev->fifo_size - 1) << 8 | OMAP_I2C_BUF_RXFIF_CLR |
425 (dev->fifo_size - 1) | OMAP_I2C_BUF_TXFIF_CLR;
426 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, buf);
427 }
b6ee52c3 428
010d442c
KS		 429 /* Take the I2C module out of reset: */
430 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
431
432 /* Enable interrupts */
ef871432 433 dev->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
c1a473bd
TL		 434 OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
435 OMAP_I2C_IE_AL) | ((dev->fifo_size) ?
ef871432
RN		 436 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0);
437 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
438 if (cpu_is_omap34xx()) {
439 dev->pscstate = psc;
440 dev->scllstate = scll;
441 dev->sclhstate = sclh;
442 dev->bufstate = buf;
443 }
010d442c
KS		 444 return 0;
445}
446
447/*
448 * Waiting on Bus Busy
449 */
450static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
451{
452 unsigned long timeout;
453
454 timeout = jiffies + OMAP_I2C_TIMEOUT;
455 while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
456 if (time_after(jiffies, timeout)) {
457 dev_warn(dev->dev, "timeout waiting for bus ready\n");
458 return -ETIMEDOUT;
459 }
460 msleep(1);
461 }
462
463 return 0;
464}
465
466/*
467 * Low level master read/write transaction.
468 */
469static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
470 struct i2c_msg *msg, int stop)
471{
472 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
473 int r;
474 u16 w;
475
476 dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
477 msg->addr, msg->len, msg->flags, stop);
478
479 if (msg->len == 0)
480 return -EINVAL;
481
482 omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
483
484 /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
485 dev->buf = msg->buf;
486 dev->buf_len = msg->len;
487
488 omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
489
b6ee52c3
NM		 490 /* Clear the FIFO Buffers */
491 w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
492 w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
493 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w);
494
010d442c
KS		 495 init_completion(&dev->cmd_complete);
496 dev->cmd_err = 0;
497
498 w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
4574eb68
SMK		 499
500 /* High speed configuration */
501 if (dev->speed > 400)
b6ee52c3 502 w |= OMAP_I2C_CON_OPMODE_HS;
4574eb68 503
010d442c
KS		 504 if (msg->flags & I2C_M_TEN)
505 w |= OMAP_I2C_CON_XA;
506 if (!(msg->flags & I2C_M_RD))
507 w |= OMAP_I2C_CON_TRX;
c1a473bd 508
b6ee52c3 509 if (!dev->b_hw && stop)
010d442c 510 w |= OMAP_I2C_CON_STP;
c1a473bd 511
010d442c
KS		 512 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
513
b6ee52c3
NM		 514 /*
515 * Don't write stt and stp together on some hardware.
516 */
517 if (dev->b_hw && stop) {
518 unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
519 u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
520 while (con & OMAP_I2C_CON_STT) {
521 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
522
523 /* Let the user know if i2c is in a bad state */
524 if (time_after(jiffies, delay)) {
525 dev_err(dev->dev, "controller timed out "
526 "waiting for start condition to finish\n");
527 return -ETIMEDOUT;
528 }
529 cpu_relax();
530 }
531
532 w |= OMAP_I2C_CON_STP;
533 w &= ~OMAP_I2C_CON_STT;
534 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
535 }
536
b7af349b
JN		 537 /*
538 * REVISIT: We should abort the transfer on signals, but the bus goes
539 * into arbitration and we're currently unable to recover from it.
540 */
541 r = wait_for_completion_timeout(&dev->cmd_complete,
542 OMAP_I2C_TIMEOUT);
010d442c
KS		 543 dev->buf_len = 0;
544 if (r < 0)
545 return r;
546 if (r == 0) {
547 dev_err(dev->dev, "controller timed out\n");
548 omap_i2c_init(dev);
549 return -ETIMEDOUT;
550 }
551
552 if (likely(!dev->cmd_err))
553 return 0;
554
555 /* We have an error */
556 if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
557 OMAP_I2C_STAT_XUDF)) {
558 omap_i2c_init(dev);
559 return -EIO;
560 }
561
562 if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
563 if (msg->flags & I2C_M_IGNORE_NAK)
564 return 0;
565 if (stop) {
566 w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
567 w |= OMAP_I2C_CON_STP;
568 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
569 }
570 return -EREMOTEIO;
571 }
572 return -EIO;
573}
574
575
576/*
577 * Prepare controller for a transaction and call omap_i2c_xfer_msg
578 * to do the work during IRQ processing.
579 */
580static int
581omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
582{
583 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
584 int i;
585 int r;
586
f08ac4e7 587 omap_i2c_unidle(dev);
010d442c 588
c1a473bd
TL		 589 r = omap_i2c_wait_for_bb(dev);
590 if (r < 0)
010d442c
KS		 591 goto out;
592
593 for (i = 0; i < num; i++) {
594 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
595 if (r != 0)
596 break;
597 }
598
599 if (r == 0)
600 r = num;
601out:
f08ac4e7 602 omap_i2c_idle(dev);
010d442c
KS		 603 return r;
604}
605
606static u32
607omap_i2c_func(struct i2c_adapter *adap)
608{
609 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
610}
611
612static inline void
613omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)
614{
615 dev->cmd_err |= err;
616 complete(&dev->cmd_complete);
617}
618
619static inline void
620omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
621{
622 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
623}
624
43469d8e
PW		 625/* rev1 devices are apparently only on some 15xx */
626#ifdef CONFIG_ARCH_OMAP15XX
627
010d442c 628static irqreturn_t
7d12e780 629omap_i2c_rev1_isr(int this_irq, void *dev_id)
010d442c
KS		 630{
631 struct omap_i2c_dev *dev = dev_id;
632 u16 iv, w;
633
f08ac4e7
TL		 634 if (dev->idle)
635 return IRQ_NONE;
636
010d442c
KS		 637 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
638 switch (iv) {
639 case 0x00: /* None */
640 break;
641 case 0x01: /* Arbitration lost */
642 dev_err(dev->dev, "Arbitration lost\n");
643 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
644 break;
645 case 0x02: /* No acknowledgement */
646 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
647 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
648 break;
649 case 0x03: /* Register access ready */
650 omap_i2c_complete_cmd(dev, 0);
651 break;
652 case 0x04: /* Receive data ready */
653 if (dev->buf_len) {
654 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
655 *dev->buf++ = w;
656 dev->buf_len--;
657 if (dev->buf_len) {
658 *dev->buf++ = w >> 8;
659 dev->buf_len--;
660 }
661 } else
662 dev_err(dev->dev, "RRDY IRQ while no data requested\n");
663 break;
664 case 0x05: /* Transmit data ready */
665 if (dev->buf_len) {
666 w = *dev->buf++;
667 dev->buf_len--;
668 if (dev->buf_len) {
669 w |= *dev->buf++ << 8;
670 dev->buf_len--;
671 }
672 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
673 } else
674 dev_err(dev->dev, "XRDY IRQ while no data to send\n");
675 break;
676 default:
677 return IRQ_NONE;
678 }
679
680 return IRQ_HANDLED;
681}
43469d8e 682#else
c1a473bd 683#define omap_i2c_rev1_isr NULL
43469d8e 684#endif
010d442c
KS		 685
686static irqreturn_t
7d12e780 687omap_i2c_isr(int this_irq, void *dev_id)
010d442c
KS		 688{
689 struct omap_i2c_dev *dev = dev_id;
690 u16 bits;
691 u16 stat, w;
b6ee52c3 692 int err, count = 0;
010d442c 693
f08ac4e7
TL		 694 if (dev->idle)
695 return IRQ_NONE;
696
010d442c
KS		 697 bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
698 while ((stat = (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG))) & bits) {
699 dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
700 if (count++ == 100) {
701 dev_warn(dev->dev, "Too much work in one IRQ\n");
702 break;
703 }
704
cd086d3a
SM		 705 err = 0;
706complete:
dcc4ec26
NM		 707 /*
708 * Ack the stat in one go, but [R/X]DR and [R/X]RDY should be
709 * acked after the data operation is complete.
710 * Ref: TRM SWPU114Q Figure 18-31
711 */
712 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat &
713 ~(OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR |
714 OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
010d442c 715
b6ee52c3
NM		 716 if (stat & OMAP_I2C_STAT_NACK) {
717 err |= OMAP_I2C_STAT_NACK;
718 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
719 OMAP_I2C_CON_STP);
010d442c 720 }
b6ee52c3
NM		 721 if (stat & OMAP_I2C_STAT_AL) {
722 dev_err(dev->dev, "Arbitration lost\n");
723 err |= OMAP_I2C_STAT_AL;
724 }
725 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
04c688dd 726 OMAP_I2C_STAT_AL)) {
dd11976a
MS		 727 omap_i2c_ack_stat(dev, stat &
728 (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR |
729 OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
b6ee52c3 730 omap_i2c_complete_cmd(dev, err);
04c688dd
SM		 731 return IRQ_HANDLED;
732 }
b6ee52c3
NM		 733 if (stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR)) {
734 u8 num_bytes = 1;
735 if (dev->fifo_size) {
736 if (stat & OMAP_I2C_STAT_RRDY)
737 num_bytes = dev->fifo_size;
bfb6b658
SM		 738 else /* read RXSTAT on RDR interrupt */
739 num_bytes = (omap_i2c_read_reg(dev,
740 OMAP_I2C_BUFSTAT_REG)
741 >> 8) & 0x3F;
b6ee52c3
NM		 742 }
743 while (num_bytes) {
744 num_bytes--;
745 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
010d442c 746 if (dev->buf_len) {
b6ee52c3 747 *dev->buf++ = w;
010d442c 748 dev->buf_len--;
b6ee52c3 749 /* Data reg from 2430 is 8 bit wide */
3d522fb4
C		 750 if (!cpu_is_omap2430() &&
751 !cpu_is_omap34xx()) {
b6ee52c3
NM		 752 if (dev->buf_len) {
753 *dev->buf++ = w >> 8;
754 dev->buf_len--;
755 }
756 }
757 } else {
758 if (stat & OMAP_I2C_STAT_RRDY)
759 dev_err(dev->dev,
760 "RRDY IRQ while no data"
761 " requested\n");
762 if (stat & OMAP_I2C_STAT_RDR)
763 dev_err(dev->dev,
764 "RDR IRQ while no data"
765 " requested\n");
766 break;
010d442c 767 }
b6ee52c3
NM		 768 }
769 omap_i2c_ack_stat(dev,
770 stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR));
010d442c
KS		 771 continue;
772 }
b6ee52c3
NM		 773 if (stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)) {
774 u8 num_bytes = 1;
775 if (dev->fifo_size) {
776 if (stat & OMAP_I2C_STAT_XRDY)
777 num_bytes = dev->fifo_size;
bfb6b658 778 else /* read TXSTAT on XDR interrupt */
b6ee52c3 779 num_bytes = omap_i2c_read_reg(dev,
bfb6b658
SM		 780 OMAP_I2C_BUFSTAT_REG)
781 & 0x3F;
b6ee52c3
NM		 782 }
783 while (num_bytes) {
784 num_bytes--;
785 w = 0;
010d442c 786 if (dev->buf_len) {
b6ee52c3 787 w = *dev->buf++;
010d442c 788 dev->buf_len--;
b6ee52c3 789 /* Data reg from 2430 is 8 bit wide */
3d522fb4
C		 790 if (!cpu_is_omap2430() &&
791 !cpu_is_omap34xx()) {
b6ee52c3
NM		 792 if (dev->buf_len) {
793 w |= *dev->buf++ << 8;
794 dev->buf_len--;
795 }
796 }
797 } else {
798 if (stat & OMAP_I2C_STAT_XRDY)
799 dev_err(dev->dev,
800 "XRDY IRQ while no "
801 "data to send\n");
802 if (stat & OMAP_I2C_STAT_XDR)
803 dev_err(dev->dev,
804 "XDR IRQ while no "
805 "data to send\n");
806 break;
010d442c 807 }
cd086d3a
SM		 808
809 /*
810 * OMAP3430 Errata 1.153: When an XRDY/XDR
811 * is hit, wait for XUDF before writing data
812 * to DATA_REG. Otherwise some data bytes can
813 * be lost while transferring them from the
814 * memory to the I2C interface.
815 */
816
61149787 817 if (dev->rev <= OMAP_I2C_REV_ON_3430) {
cd086d3a
SM		 818 while (!(stat & OMAP_I2C_STAT_XUDF)) {
819 if (stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
820 omap_i2c_ack_stat(dev, stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
821 err |= OMAP_I2C_STAT_XUDF;
822 goto complete;
823 }
824 cpu_relax();
825 stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
826 }
827 }
828
b6ee52c3
NM		 829 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
830 }
831 omap_i2c_ack_stat(dev,
832 stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
010d442c
KS		 833 continue;
834 }
835 if (stat & OMAP_I2C_STAT_ROVR) {
836 dev_err(dev->dev, "Receive overrun\n");
837 dev->cmd_err |= OMAP_I2C_STAT_ROVR;
838 }
839 if (stat & OMAP_I2C_STAT_XUDF) {
b6ee52c3 840 dev_err(dev->dev, "Transmit underflow\n");
010d442c
KS		 841 dev->cmd_err |= OMAP_I2C_STAT_XUDF;
842 }
010d442c
KS		 843 }
844
845 return count ? IRQ_HANDLED : IRQ_NONE;
846}
847
8f9082c5 848static const struct i2c_algorithm omap_i2c_algo = {
010d442c
KS		 849 .master_xfer = omap_i2c_xfer,
850 .functionality = omap_i2c_func,
851};
852
510be9c9 853static int __init
010d442c
KS		 854omap_i2c_probe(struct platform_device *pdev)
855{
856 struct omap_i2c_dev *dev;
857 struct i2c_adapter *adap;
858 struct resource *mem, *irq, *ioarea;
e355204e 859 irq_handler_t isr;
010d442c 860 int r;
3d522fb4 861 u32 speed = 0;
010d442c
KS		 862
863 /* NOTE: driver uses the static register mapping */
864 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
865 if (!mem) {
866 dev_err(&pdev->dev, "no mem resource?\n");
867 return -ENODEV;
868 }
869 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
870 if (!irq) {
871 dev_err(&pdev->dev, "no irq resource?\n");
872 return -ENODEV;
873 }
874
59330825 875 ioarea = request_mem_region(mem->start, resource_size(mem),
010d442c
KS		 876 pdev->name);
877 if (!ioarea) {
878 dev_err(&pdev->dev, "I2C region already claimed\n");
879 return -EBUSY;
880 }
881
010d442c
KS		 882 dev = kzalloc(sizeof(struct omap_i2c_dev), GFP_KERNEL);
883 if (!dev) {
884 r = -ENOMEM;
885 goto err_release_region;
886 }
887
4574eb68 888 if (pdev->dev.platform_data != NULL)
3d522fb4 889 speed = *(u32 *)pdev->dev.platform_data;
4574eb68 890 else
3d522fb4 891 speed = 100; /* Defualt speed */
4574eb68 892
3d522fb4 893 dev->speed = speed;
3831f154 894 dev->idle = 1;
010d442c
KS		 895 dev->dev = &pdev->dev;
896 dev->irq = irq->start;
c6ffddea 897 dev->base = ioremap(mem->start, resource_size(mem));
55c381e4
RK		 898 if (!dev->base) {
899 r = -ENOMEM;
900 goto err_free_mem;
901 }
902
010d442c
KS		 903 platform_set_drvdata(pdev, dev);
904
905 if ((r = omap_i2c_get_clocks(dev)) != 0)
55c381e4 906 goto err_iounmap;
010d442c 907
f08ac4e7 908 omap_i2c_unidle(dev);
010d442c 909
9c76b878 910 dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
010d442c 911
3d522fb4 912 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
b6ee52c3
NM		 913 u16 s;
914
915 /* Set up the fifo size - Get total size */
916 s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
917 dev->fifo_size = 0x8 << s;
918
919 /*
920 * Set up notification threshold as half the total available
921 * size. This is to ensure that we can handle the status on int
922 * call back latencies.
923 */
924 dev->fifo_size = (dev->fifo_size / 2);
925 dev->b_hw = 1; /* Enable hardware fixes */
926 }
927
d84d3ea3
CM		 928 if (cpu_is_omap7xx())
929 dev->reg_shift = 1;
930 else
931 dev->reg_shift = 2;
932
010d442c
KS		 933 /* reset ASAP, clearing any IRQs */
934 omap_i2c_init(dev);
935
9c76b878
PW		 936 isr = (dev->rev < OMAP_I2C_REV_2) ? omap_i2c_rev1_isr : omap_i2c_isr;
937 r = request_irq(dev->irq, isr, 0, pdev->name, dev);
010d442c
KS		 938
939 if (r) {
940 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
941 goto err_unuse_clocks;
942 }
9c76b878 943
010d442c 944 dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n",
9c76b878 945 pdev->id, dev->rev >> 4, dev->rev & 0xf, dev->speed);
010d442c 946
3831f154
PW		 947 omap_i2c_idle(dev);
948
010d442c
KS		 949 adap = &dev->adapter;
950 i2c_set_adapdata(adap, dev);
951 adap->owner = THIS_MODULE;
952 adap->class = I2C_CLASS_HWMON;
783fd6fa 953 strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
010d442c
KS		 954 adap->algo = &omap_i2c_algo;
955 adap->dev.parent = &pdev->dev;
956
957 /* i2c device drivers may be active on return from add_adapter() */
7c175499
DB		 958 adap->nr = pdev->id;
959 r = i2c_add_numbered_adapter(adap);
010d442c
KS		 960 if (r) {
961 dev_err(dev->dev, "failure adding adapter\n");
962 goto err_free_irq;
963 }
964
010d442c
KS		 965 return 0;
966
967err_free_irq:
968 free_irq(dev->irq, dev);
969err_unuse_clocks:
3e39752d 970 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
f08ac4e7 971 omap_i2c_idle(dev);
010d442c 972 omap_i2c_put_clocks(dev);
55c381e4
RK		 973err_iounmap:
974 iounmap(dev->base);
010d442c
KS		 975err_free_mem:
976 platform_set_drvdata(pdev, NULL);
977 kfree(dev);
978err_release_region:
59330825 979 release_mem_region(mem->start, resource_size(mem));
010d442c
KS		 980
981 return r;
982}
983
984static int
985omap_i2c_remove(struct platform_device *pdev)
986{
987 struct omap_i2c_dev *dev = platform_get_drvdata(pdev);
988 struct resource *mem;
989
990 platform_set_drvdata(pdev, NULL);
991
992 free_irq(dev->irq, dev);
993 i2c_del_adapter(&dev->adapter);
994 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
995 omap_i2c_put_clocks(dev);
55c381e4 996 iounmap(dev->base);
010d442c
KS		 997 kfree(dev);
998 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
59330825 999 release_mem_region(mem->start, resource_size(mem));
010d442c
KS		 1000 return 0;
1001}
1002
1003static struct platform_driver omap_i2c_driver = {
1004 .probe = omap_i2c_probe,
1005 .remove = omap_i2c_remove,
1006 .driver = {
1007 .name = "i2c_omap",
1008 .owner = THIS_MODULE,
1009 },
1010};
1011
1012/* I2C may be needed to bring up other drivers */
1013static int __init
1014omap_i2c_init_driver(void)
1015{
1016 return platform_driver_register(&omap_i2c_driver);
1017}
1018subsys_initcall(omap_i2c_init_driver);
1019
1020static void __exit omap_i2c_exit_driver(void)
1021{
1022 platform_driver_unregister(&omap_i2c_driver);
1023}
1024module_exit(omap_i2c_exit_driver);
1025
1026MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
1027MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
1028MODULE_LICENSE("GPL");
add8eda7 1029MODULE_ALIAS("platform:i2c_omap");
Linux 6.x block layer and io_uring tree(s)