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i2c-omap: Clean-up i2c-omap
[linux-2.6-block.git] / drivers / i2c / busses / i2c-omap.c
CommitLineData
010d442c
KS		 1/*
2 * TI OMAP I2C master mode driver
3 *
4 * Copyright (C) 2003 MontaVista Software, Inc.
010d442c 5 * Copyright (C) 2005 Nokia Corporation
c1a473bd 6 * Copyright (C) 2004 - 2007 Texas Instruments.
010d442c 7 *
c1a473bd
TL		 8 * Originally written by MontaVista Software, Inc.
9 * Additional contributions by:
10 * Tony Lindgren <tony@atomide.com>
11 * Imre Deak <imre.deak@nokia.com>
12 * Juha Yrjölä <juha.yrjola@solidboot.com>
13 * Syed Khasim <x0khasim@ti.com>
14 * Nishant Menon <nm@ti.com>
010d442c
KS		 15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30
31#include <linux/module.h>
32#include <linux/delay.h>
33#include <linux/i2c.h>
34#include <linux/err.h>
35#include <linux/interrupt.h>
36#include <linux/completion.h>
37#include <linux/platform_device.h>
38#include <linux/clk.h>
c1a473bd 39#include <linux/io.h>
010d442c
KS		 40
41/* timeout waiting for the controller to respond */
42#define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
43
44#define OMAP_I2C_REV_REG 0x00
45#define OMAP_I2C_IE_REG 0x04
46#define OMAP_I2C_STAT_REG 0x08
47#define OMAP_I2C_IV_REG 0x0c
48#define OMAP_I2C_SYSS_REG 0x10
49#define OMAP_I2C_BUF_REG 0x14
50#define OMAP_I2C_CNT_REG 0x18
51#define OMAP_I2C_DATA_REG 0x1c
52#define OMAP_I2C_SYSC_REG 0x20
53#define OMAP_I2C_CON_REG 0x24
54#define OMAP_I2C_OA_REG 0x28
55#define OMAP_I2C_SA_REG 0x2c
56#define OMAP_I2C_PSC_REG 0x30
57#define OMAP_I2C_SCLL_REG 0x34
58#define OMAP_I2C_SCLH_REG 0x38
59#define OMAP_I2C_SYSTEST_REG 0x3c
b6ee52c3 60#define OMAP_I2C_BUFSTAT_REG 0x40
010d442c
KS		 61
62/* I2C Interrupt Enable Register (OMAP_I2C_IE): */
b6ee52c3
NM		 63#define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */
64#define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */
010d442c
KS		 65#define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */
66#define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */
67#define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */
68#define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */
69#define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */
70
71/* I2C Status Register (OMAP_I2C_STAT): */
b6ee52c3
NM		 72#define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */
73#define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */
010d442c
KS		 74#define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */
75#define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */
76#define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
77#define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */
78#define OMAP_I2C_STAT_AD0 (1 << 8) /* Address zero */
79#define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
80#define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */
81#define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */
82#define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */
83#define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */
84
85/* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
86#define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */
b6ee52c3 87#define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */
010d442c 88#define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */
b6ee52c3 89#define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */
010d442c
KS		 90
91/* I2C Configuration Register (OMAP_I2C_CON): */
92#define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */
93#define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */
b6ee52c3 94#define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */
010d442c
KS		 95#define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */
96#define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */
97#define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */
98#define OMAP_I2C_CON_XA (1 << 8) /* Expand address */
99#define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */
100#define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */
101#define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */
102
4574eb68
SMK		 103/* I2C SCL time value when Master */
104#define OMAP_I2C_SCLL_HSSCLL 8
105#define OMAP_I2C_SCLH_HSSCLH 8
106
010d442c
KS		 107/* I2C System Test Register (OMAP_I2C_SYSTEST): */
108#ifdef DEBUG
109#define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
110#define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */
111#define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
112#define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
113#define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */
114#define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */
115#define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */
116#define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */
117#endif
118
119/* I2C System Status register (OMAP_I2C_SYSS): */
120#define OMAP_I2C_SYSS_RDONE (1 << 0) /* Reset Done */
121
122/* I2C System Configuration Register (OMAP_I2C_SYSC): */
123#define OMAP_I2C_SYSC_SRST (1 << 1) /* Soft Reset */
124
010d442c
KS		 125struct omap_i2c_dev {
126 struct device *dev;
127 void __iomem *base; /* virtual */
128 int irq;
129 struct clk *iclk; /* Interface clock */
130 struct clk *fclk; /* Functional clock */
131 struct completion cmd_complete;
132 struct resource *ioarea;
4574eb68 133 u32 speed; /* Speed of bus in Khz */
010d442c
KS		 134 u16 cmd_err;
135 u8 *buf;
136 size_t buf_len;
137 struct i2c_adapter adapter;
b6ee52c3
NM		 138 u8 fifo_size; /* use as flag and value
139 * fifo_size==0 implies no fifo
140 * if set, should be trsh+1
141 */
010d442c 142 unsigned rev1:1;
b6ee52c3 143 unsigned b_hw:1; /* bad h/w fixes */
f08ac4e7
TL		 144 unsigned idle:1;
145 u16 iestate; /* Saved interrupt register */
010d442c
KS		 146};
147
148static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
149 int reg, u16 val)
150{
151 __raw_writew(val, i2c_dev->base + reg);
152}
153
154static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
155{
156 return __raw_readw(i2c_dev->base + reg);
157}
158
510be9c9 159static int __init omap_i2c_get_clocks(struct omap_i2c_dev *dev)
010d442c 160{
3d522fb4 161 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
010d442c
KS		 162 dev->iclk = clk_get(dev->dev, "i2c_ick");
163 if (IS_ERR(dev->iclk)) {
164 dev->iclk = NULL;
165 return -ENODEV;
166 }
167 }
168
169 dev->fclk = clk_get(dev->dev, "i2c_fck");
170 if (IS_ERR(dev->fclk)) {
171 if (dev->iclk != NULL) {
172 clk_put(dev->iclk);
173 dev->iclk = NULL;
174 }
175 dev->fclk = NULL;
176 return -ENODEV;
177 }
178
179 return 0;
180}
181
182static void omap_i2c_put_clocks(struct omap_i2c_dev *dev)
183{
184 clk_put(dev->fclk);
185 dev->fclk = NULL;
186 if (dev->iclk != NULL) {
187 clk_put(dev->iclk);
188 dev->iclk = NULL;
189 }
190}
191
f08ac4e7 192static void omap_i2c_unidle(struct omap_i2c_dev *dev)
010d442c
KS		 193{
194 if (dev->iclk != NULL)
195 clk_enable(dev->iclk);
196 clk_enable(dev->fclk);
0cbbcffd 197 dev->idle = 0;
f08ac4e7
TL		 198 if (dev->iestate)
199 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
010d442c
KS		 200}
201
f08ac4e7 202static void omap_i2c_idle(struct omap_i2c_dev *dev)
010d442c 203{
f08ac4e7
TL		 204 u16 iv;
205
f08ac4e7
TL		 206 dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
207 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0);
0cbbcffd 208 if (dev->rev1) {
c1a473bd 209 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); /* Read clears */
0cbbcffd 210 } else {
f08ac4e7 211 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, dev->iestate);
0cbbcffd
PW		 212
213 /* Flush posted write before the dev->idle store occurs */
214 omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
215 }
216 dev->idle = 1;
f08ac4e7 217 clk_disable(dev->fclk);
010d442c
KS		 218 if (dev->iclk != NULL)
219 clk_disable(dev->iclk);
010d442c
KS		 220}
221
222static int omap_i2c_init(struct omap_i2c_dev *dev)
223{
4574eb68
SMK		 224 u16 psc = 0, scll = 0, sclh = 0;
225 u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
010d442c
KS		 226 unsigned long fclk_rate = 12000000;
227 unsigned long timeout;
4574eb68 228 unsigned long internal_clk = 0;
010d442c
KS		 229
230 if (!dev->rev1) {
231 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, OMAP_I2C_SYSC_SRST);
232 /* For some reason we need to set the EN bit before the
233 * reset done bit gets set. */
234 timeout = jiffies + OMAP_I2C_TIMEOUT;
235 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
236 while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
237 OMAP_I2C_SYSS_RDONE)) {
238 if (time_after(jiffies, timeout)) {
fce3ff03 239 dev_warn(dev->dev, "timeout waiting "
010d442c
KS		 240 "for controller reset\n");
241 return -ETIMEDOUT;
242 }
243 msleep(1);
244 }
245 }
246 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
247
248 if (cpu_class_is_omap1()) {
249 struct clk *armxor_ck;
250
251 armxor_ck = clk_get(NULL, "armxor_ck");
252 if (IS_ERR(armxor_ck))
253 dev_warn(dev->dev, "Could not get armxor_ck\n");
254 else {
255 fclk_rate = clk_get_rate(armxor_ck);
256 clk_put(armxor_ck);
257 }
258 /* TRM for 5912 says the I2C clock must be prescaled to be
259 * between 7 - 12 MHz. The XOR input clock is typically
260 * 12, 13 or 19.2 MHz. So we should have code that produces:
261 *
262 * XOR MHz Divider Prescaler
263 * 12 1 0
264 * 13 2 1
265 * 19.2 2 1
266 */
d7aef138
JD		 267 if (fclk_rate > 12000000)
268 psc = fclk_rate / 12000000;
010d442c
KS		 269 }
270
3d522fb4 271 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
4574eb68
SMK		 272
273 /* HSI2C controller internal clk rate should be 19.2 Mhz */
274 internal_clk = 19200;
275 fclk_rate = clk_get_rate(dev->fclk) / 1000;
276
277 /* Compute prescaler divisor */
278 psc = fclk_rate / internal_clk;
279 psc = psc - 1;
280
281 /* If configured for High Speed */
282 if (dev->speed > 400) {
283 /* For first phase of HS mode */
284 fsscll = internal_clk / (400 * 2) - 6;
285 fssclh = internal_clk / (400 * 2) - 6;
286
287 /* For second phase of HS mode */
288 hsscll = fclk_rate / (dev->speed * 2) - 6;
289 hssclh = fclk_rate / (dev->speed * 2) - 6;
290 } else {
291 /* To handle F/S modes */
292 fsscll = internal_clk / (dev->speed * 2) - 6;
293 fssclh = internal_clk / (dev->speed * 2) - 6;
294 }
295 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
296 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
297 } else {
298 /* Program desired operating rate */
299 fclk_rate /= (psc + 1) * 1000;
300 if (psc > 2)
301 psc = 2;
302 scll = fclk_rate / (dev->speed * 2) - 7 + psc;
303 sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
304 }
305
010d442c
KS		 306 /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
307 omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);
308
4574eb68
SMK		 309 /* SCL low and high time values */
310 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll);
311 omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh);
010d442c 312
b6ee52c3
NM		 313 if (dev->fifo_size)
314 /* Note: setup required fifo size - 1 */
315 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG,
316 (dev->fifo_size - 1) << 8 | /* RTRSH */
317 OMAP_I2C_BUF_RXFIF_CLR |
318 (dev->fifo_size - 1) | /* XTRSH */
319 OMAP_I2C_BUF_TXFIF_CLR);
320
010d442c
KS		 321 /* Take the I2C module out of reset: */
322 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
323
324 /* Enable interrupts */
325 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG,
c1a473bd
TL		 326 (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
327 OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
328 OMAP_I2C_IE_AL) | ((dev->fifo_size) ?
b6ee52c3 329 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0));
010d442c
KS		 330 return 0;
331}
332
333/*
334 * Waiting on Bus Busy
335 */
336static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
337{
338 unsigned long timeout;
339
340 timeout = jiffies + OMAP_I2C_TIMEOUT;
341 while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
342 if (time_after(jiffies, timeout)) {
343 dev_warn(dev->dev, "timeout waiting for bus ready\n");
344 return -ETIMEDOUT;
345 }
346 msleep(1);
347 }
348
349 return 0;
350}
351
352/*
353 * Low level master read/write transaction.
354 */
355static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
356 struct i2c_msg *msg, int stop)
357{
358 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
359 int r;
360 u16 w;
361
362 dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
363 msg->addr, msg->len, msg->flags, stop);
364
365 if (msg->len == 0)
366 return -EINVAL;
367
368 omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
369
370 /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
371 dev->buf = msg->buf;
372 dev->buf_len = msg->len;
373
374 omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
375
b6ee52c3
NM		 376 /* Clear the FIFO Buffers */
377 w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
378 w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
379 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w);
380
010d442c
KS		 381 init_completion(&dev->cmd_complete);
382 dev->cmd_err = 0;
383
384 w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
4574eb68
SMK		 385
386 /* High speed configuration */
387 if (dev->speed > 400)
b6ee52c3 388 w |= OMAP_I2C_CON_OPMODE_HS;
4574eb68 389
010d442c
KS		 390 if (msg->flags & I2C_M_TEN)
391 w |= OMAP_I2C_CON_XA;
392 if (!(msg->flags & I2C_M_RD))
393 w |= OMAP_I2C_CON_TRX;
c1a473bd 394
b6ee52c3 395 if (!dev->b_hw && stop)
010d442c 396 w |= OMAP_I2C_CON_STP;
c1a473bd 397
010d442c
KS		 398 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
399
b6ee52c3
NM		 400 /*
401 * Don't write stt and stp together on some hardware.
402 */
403 if (dev->b_hw && stop) {
404 unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
405 u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
406 while (con & OMAP_I2C_CON_STT) {
407 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
408
409 /* Let the user know if i2c is in a bad state */
410 if (time_after(jiffies, delay)) {
411 dev_err(dev->dev, "controller timed out "
412 "waiting for start condition to finish\n");
413 return -ETIMEDOUT;
414 }
415 cpu_relax();
416 }
417
418 w |= OMAP_I2C_CON_STP;
419 w &= ~OMAP_I2C_CON_STT;
420 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
421 }
422
b7af349b
JN		 423 /*
424 * REVISIT: We should abort the transfer on signals, but the bus goes
425 * into arbitration and we're currently unable to recover from it.
426 */
427 r = wait_for_completion_timeout(&dev->cmd_complete,
428 OMAP_I2C_TIMEOUT);
010d442c
KS		 429 dev->buf_len = 0;
430 if (r < 0)
431 return r;
432 if (r == 0) {
433 dev_err(dev->dev, "controller timed out\n");
434 omap_i2c_init(dev);
435 return -ETIMEDOUT;
436 }
437
438 if (likely(!dev->cmd_err))
439 return 0;
440
441 /* We have an error */
442 if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
443 OMAP_I2C_STAT_XUDF)) {
444 omap_i2c_init(dev);
445 return -EIO;
446 }
447
448 if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
449 if (msg->flags & I2C_M_IGNORE_NAK)
450 return 0;
451 if (stop) {
452 w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
453 w |= OMAP_I2C_CON_STP;
454 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
455 }
456 return -EREMOTEIO;
457 }
458 return -EIO;
459}
460
461
462/*
463 * Prepare controller for a transaction and call omap_i2c_xfer_msg
464 * to do the work during IRQ processing.
465 */
466static int
467omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
468{
469 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
470 int i;
471 int r;
472
f08ac4e7 473 omap_i2c_unidle(dev);
010d442c 474
c1a473bd
TL		 475 r = omap_i2c_wait_for_bb(dev);
476 if (r < 0)
010d442c
KS		 477 goto out;
478
479 for (i = 0; i < num; i++) {
480 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
481 if (r != 0)
482 break;
483 }
484
485 if (r == 0)
486 r = num;
487out:
f08ac4e7 488 omap_i2c_idle(dev);
010d442c
KS		 489 return r;
490}
491
492static u32
493omap_i2c_func(struct i2c_adapter *adap)
494{
495 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
496}
497
498static inline void
499omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)
500{
501 dev->cmd_err |= err;
502 complete(&dev->cmd_complete);
503}
504
505static inline void
506omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
507{
508 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
509}
510
43469d8e
PW		 511/* rev1 devices are apparently only on some 15xx */
512#ifdef CONFIG_ARCH_OMAP15XX
513
010d442c 514static irqreturn_t
7d12e780 515omap_i2c_rev1_isr(int this_irq, void *dev_id)
010d442c
KS		 516{
517 struct omap_i2c_dev *dev = dev_id;
518 u16 iv, w;
519
f08ac4e7
TL		 520 if (dev->idle)
521 return IRQ_NONE;
522
010d442c
KS		 523 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
524 switch (iv) {
525 case 0x00: /* None */
526 break;
527 case 0x01: /* Arbitration lost */
528 dev_err(dev->dev, "Arbitration lost\n");
529 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
530 break;
531 case 0x02: /* No acknowledgement */
532 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
533 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
534 break;
535 case 0x03: /* Register access ready */
536 omap_i2c_complete_cmd(dev, 0);
537 break;
538 case 0x04: /* Receive data ready */
539 if (dev->buf_len) {
540 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
541 *dev->buf++ = w;
542 dev->buf_len--;
543 if (dev->buf_len) {
544 *dev->buf++ = w >> 8;
545 dev->buf_len--;
546 }
547 } else
548 dev_err(dev->dev, "RRDY IRQ while no data requested\n");
549 break;
550 case 0x05: /* Transmit data ready */
551 if (dev->buf_len) {
552 w = *dev->buf++;
553 dev->buf_len--;
554 if (dev->buf_len) {
555 w |= *dev->buf++ << 8;
556 dev->buf_len--;
557 }
558 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
559 } else
560 dev_err(dev->dev, "XRDY IRQ while no data to send\n");
561 break;
562 default:
563 return IRQ_NONE;
564 }
565
566 return IRQ_HANDLED;
567}
43469d8e 568#else
c1a473bd 569#define omap_i2c_rev1_isr NULL
43469d8e 570#endif
010d442c
KS		 571
572static irqreturn_t
7d12e780 573omap_i2c_isr(int this_irq, void *dev_id)
010d442c
KS		 574{
575 struct omap_i2c_dev *dev = dev_id;
576 u16 bits;
577 u16 stat, w;
b6ee52c3 578 int err, count = 0;
010d442c 579
f08ac4e7
TL		 580 if (dev->idle)
581 return IRQ_NONE;
582
010d442c
KS		 583 bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
584 while ((stat = (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG))) & bits) {
585 dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
586 if (count++ == 100) {
587 dev_warn(dev->dev, "Too much work in one IRQ\n");
588 break;
589 }
590
591 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
592
b6ee52c3
NM		 593 err = 0;
594 if (stat & OMAP_I2C_STAT_NACK) {
595 err |= OMAP_I2C_STAT_NACK;
596 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
597 OMAP_I2C_CON_STP);
010d442c 598 }
b6ee52c3
NM		 599 if (stat & OMAP_I2C_STAT_AL) {
600 dev_err(dev->dev, "Arbitration lost\n");
601 err |= OMAP_I2C_STAT_AL;
602 }
603 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
604 OMAP_I2C_STAT_AL))
605 omap_i2c_complete_cmd(dev, err);
606 if (stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR)) {
607 u8 num_bytes = 1;
608 if (dev->fifo_size) {
609 if (stat & OMAP_I2C_STAT_RRDY)
610 num_bytes = dev->fifo_size;
611 else
612 num_bytes = omap_i2c_read_reg(dev,
613 OMAP_I2C_BUFSTAT_REG);
614 }
615 while (num_bytes) {
616 num_bytes--;
617 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
010d442c 618 if (dev->buf_len) {
b6ee52c3 619 *dev->buf++ = w;
010d442c 620 dev->buf_len--;
b6ee52c3 621 /* Data reg from 2430 is 8 bit wide */
3d522fb4
C		 622 if (!cpu_is_omap2430() &&
623 !cpu_is_omap34xx()) {
b6ee52c3
NM		 624 if (dev->buf_len) {
625 *dev->buf++ = w >> 8;
626 dev->buf_len--;
627 }
628 }
629 } else {
630 if (stat & OMAP_I2C_STAT_RRDY)
631 dev_err(dev->dev,
632 "RRDY IRQ while no data"
633 " requested\n");
634 if (stat & OMAP_I2C_STAT_RDR)
635 dev_err(dev->dev,
636 "RDR IRQ while no data"
637 " requested\n");
638 break;
010d442c 639 }
b6ee52c3
NM		 640 }
641 omap_i2c_ack_stat(dev,
642 stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR));
010d442c
KS		 643 continue;
644 }
b6ee52c3
NM		 645 if (stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)) {
646 u8 num_bytes = 1;
647 if (dev->fifo_size) {
648 if (stat & OMAP_I2C_STAT_XRDY)
649 num_bytes = dev->fifo_size;
650 else
651 num_bytes = omap_i2c_read_reg(dev,
652 OMAP_I2C_BUFSTAT_REG);
653 }
654 while (num_bytes) {
655 num_bytes--;
656 w = 0;
010d442c 657 if (dev->buf_len) {
b6ee52c3 658 w = *dev->buf++;
010d442c 659 dev->buf_len--;
b6ee52c3 660 /* Data reg from 2430 is 8 bit wide */
3d522fb4
C		 661 if (!cpu_is_omap2430() &&
662 !cpu_is_omap34xx()) {
b6ee52c3
NM		 663 if (dev->buf_len) {
664 w |= *dev->buf++ << 8;
665 dev->buf_len--;
666 }
667 }
668 } else {
669 if (stat & OMAP_I2C_STAT_XRDY)
670 dev_err(dev->dev,
671 "XRDY IRQ while no "
672 "data to send\n");
673 if (stat & OMAP_I2C_STAT_XDR)
674 dev_err(dev->dev,
675 "XDR IRQ while no "
676 "data to send\n");
677 break;
010d442c 678 }
b6ee52c3
NM		 679 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
680 }
681 omap_i2c_ack_stat(dev,
682 stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
010d442c
KS		 683 continue;
684 }
685 if (stat & OMAP_I2C_STAT_ROVR) {
686 dev_err(dev->dev, "Receive overrun\n");
687 dev->cmd_err |= OMAP_I2C_STAT_ROVR;
688 }
689 if (stat & OMAP_I2C_STAT_XUDF) {
b6ee52c3 690 dev_err(dev->dev, "Transmit underflow\n");
010d442c
KS		 691 dev->cmd_err |= OMAP_I2C_STAT_XUDF;
692 }
010d442c
KS		 693 }
694
695 return count ? IRQ_HANDLED : IRQ_NONE;
696}
697
8f9082c5 698static const struct i2c_algorithm omap_i2c_algo = {
010d442c
KS		 699 .master_xfer = omap_i2c_xfer,
700 .functionality = omap_i2c_func,
701};
702
510be9c9 703static int __init
010d442c
KS		 704omap_i2c_probe(struct platform_device *pdev)
705{
706 struct omap_i2c_dev *dev;
707 struct i2c_adapter *adap;
708 struct resource *mem, *irq, *ioarea;
709 int r;
3d522fb4 710 u32 speed = 0;
010d442c
KS		 711
712 /* NOTE: driver uses the static register mapping */
713 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
714 if (!mem) {
715 dev_err(&pdev->dev, "no mem resource?\n");
716 return -ENODEV;
717 }
718 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
719 if (!irq) {
720 dev_err(&pdev->dev, "no irq resource?\n");
721 return -ENODEV;
722 }
723
724 ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1,
725 pdev->name);
726 if (!ioarea) {
727 dev_err(&pdev->dev, "I2C region already claimed\n");
728 return -EBUSY;
729 }
730
010d442c
KS		 731 dev = kzalloc(sizeof(struct omap_i2c_dev), GFP_KERNEL);
732 if (!dev) {
733 r = -ENOMEM;
734 goto err_release_region;
735 }
736
4574eb68 737 if (pdev->dev.platform_data != NULL)
3d522fb4 738 speed = *(u32 *)pdev->dev.platform_data;
4574eb68 739 else
3d522fb4 740 speed = 100; /* Defualt speed */
4574eb68 741
3d522fb4 742 dev->speed = speed;
010d442c
KS		 743 dev->dev = &pdev->dev;
744 dev->irq = irq->start;
55c381e4
RK		 745 dev->base = ioremap(mem->start, mem->end - mem->start + 1);
746 if (!dev->base) {
747 r = -ENOMEM;
748 goto err_free_mem;
749 }
750
010d442c
KS		 751 platform_set_drvdata(pdev, dev);
752
753 if ((r = omap_i2c_get_clocks(dev)) != 0)
55c381e4 754 goto err_iounmap;
010d442c 755
f08ac4e7 756 omap_i2c_unidle(dev);
010d442c
KS		 757
758 if (cpu_is_omap15xx())
759 dev->rev1 = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) < 0x20;
760
3d522fb4 761 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
b6ee52c3
NM		 762 u16 s;
763
764 /* Set up the fifo size - Get total size */
765 s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
766 dev->fifo_size = 0x8 << s;
767
768 /*
769 * Set up notification threshold as half the total available
770 * size. This is to ensure that we can handle the status on int
771 * call back latencies.
772 */
773 dev->fifo_size = (dev->fifo_size / 2);
774 dev->b_hw = 1; /* Enable hardware fixes */
775 }
776
010d442c
KS		 777 /* reset ASAP, clearing any IRQs */
778 omap_i2c_init(dev);
779
780 r = request_irq(dev->irq, dev->rev1 ? omap_i2c_rev1_isr : omap_i2c_isr,
781 0, pdev->name, dev);
782
783 if (r) {
784 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
785 goto err_unuse_clocks;
786 }
787 r = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
788 dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n",
4574eb68 789 pdev->id, r >> 4, r & 0xf, dev->speed);
010d442c
KS		 790
791 adap = &dev->adapter;
792 i2c_set_adapdata(adap, dev);
793 adap->owner = THIS_MODULE;
794 adap->class = I2C_CLASS_HWMON;
795 strncpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
796 adap->algo = &omap_i2c_algo;
797 adap->dev.parent = &pdev->dev;
798
799 /* i2c device drivers may be active on return from add_adapter() */
7c175499
DB		 800 adap->nr = pdev->id;
801 r = i2c_add_numbered_adapter(adap);
010d442c
KS		 802 if (r) {
803 dev_err(dev->dev, "failure adding adapter\n");
804 goto err_free_irq;
805 }
806
f08ac4e7 807 omap_i2c_idle(dev);
010d442c
KS		 808
809 return 0;
810
811err_free_irq:
812 free_irq(dev->irq, dev);
813err_unuse_clocks:
3e39752d 814 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
f08ac4e7 815 omap_i2c_idle(dev);
010d442c 816 omap_i2c_put_clocks(dev);
55c381e4
RK		 817err_iounmap:
818 iounmap(dev->base);
010d442c
KS		 819err_free_mem:
820 platform_set_drvdata(pdev, NULL);
821 kfree(dev);
822err_release_region:
010d442c
KS		 823 release_mem_region(mem->start, (mem->end - mem->start) + 1);
824
825 return r;
826}
827
828static int
829omap_i2c_remove(struct platform_device *pdev)
830{
831 struct omap_i2c_dev *dev = platform_get_drvdata(pdev);
832 struct resource *mem;
833
834 platform_set_drvdata(pdev, NULL);
835
836 free_irq(dev->irq, dev);
837 i2c_del_adapter(&dev->adapter);
838 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
839 omap_i2c_put_clocks(dev);
55c381e4 840 iounmap(dev->base);
010d442c
KS		 841 kfree(dev);
842 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
843 release_mem_region(mem->start, (mem->end - mem->start) + 1);
844 return 0;
845}
846
847static struct platform_driver omap_i2c_driver = {
848 .probe = omap_i2c_probe,
849 .remove = omap_i2c_remove,
850 .driver = {
851 .name = "i2c_omap",
852 .owner = THIS_MODULE,
853 },
854};
855
856/* I2C may be needed to bring up other drivers */
857static int __init
858omap_i2c_init_driver(void)
859{
860 return platform_driver_register(&omap_i2c_driver);
861}
862subsys_initcall(omap_i2c_init_driver);
863
864static void __exit omap_i2c_exit_driver(void)
865{
866 platform_driver_unregister(&omap_i2c_driver);
867}
868module_exit(omap_i2c_exit_driver);
869
870MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
871MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
872MODULE_LICENSE("GPL");
add8eda7 873MODULE_ALIAS("platform:i2c_omap");
Linux 6.x block layer and io_uring tree(s)