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i2c-omap: Bug in reading the RXSTAT/TXSTAT values from the I2C_BUFFSTAT register
[linux-2.6-block.git] / drivers / i2c / busses / i2c-omap.c
CommitLineData
010d442c
KS		 1/*
2 * TI OMAP I2C master mode driver
3 *
4 * Copyright (C) 2003 MontaVista Software, Inc.
010d442c 5 * Copyright (C) 2005 Nokia Corporation
c1a473bd 6 * Copyright (C) 2004 - 2007 Texas Instruments.
010d442c 7 *
c1a473bd
TL		 8 * Originally written by MontaVista Software, Inc.
9 * Additional contributions by:
10 * Tony Lindgren <tony@atomide.com>
11 * Imre Deak <imre.deak@nokia.com>
12 * Juha Yrjölä <juha.yrjola@solidboot.com>
13 * Syed Khasim <x0khasim@ti.com>
14 * Nishant Menon <nm@ti.com>
010d442c
KS		 15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30
31#include <linux/module.h>
32#include <linux/delay.h>
33#include <linux/i2c.h>
34#include <linux/err.h>
35#include <linux/interrupt.h>
36#include <linux/completion.h>
37#include <linux/platform_device.h>
38#include <linux/clk.h>
c1a473bd 39#include <linux/io.h>
010d442c 40
9c76b878
PW		 41/* I2C controller revisions */
42#define OMAP_I2C_REV_2 0x20
43
44/* I2C controller revisions present on specific hardware */
45#define OMAP_I2C_REV_ON_2430 0x36
46#define OMAP_I2C_REV_ON_3430 0x3C
47
010d442c
KS		 48/* timeout waiting for the controller to respond */
49#define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
50
51#define OMAP_I2C_REV_REG 0x00
52#define OMAP_I2C_IE_REG 0x04
53#define OMAP_I2C_STAT_REG 0x08
54#define OMAP_I2C_IV_REG 0x0c
5043e9e7
KJ		 55/* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
56#define OMAP_I2C_WE_REG 0x0c
010d442c
KS		 57#define OMAP_I2C_SYSS_REG 0x10
58#define OMAP_I2C_BUF_REG 0x14
59#define OMAP_I2C_CNT_REG 0x18
60#define OMAP_I2C_DATA_REG 0x1c
61#define OMAP_I2C_SYSC_REG 0x20
62#define OMAP_I2C_CON_REG 0x24
63#define OMAP_I2C_OA_REG 0x28
64#define OMAP_I2C_SA_REG 0x2c
65#define OMAP_I2C_PSC_REG 0x30
66#define OMAP_I2C_SCLL_REG 0x34
67#define OMAP_I2C_SCLH_REG 0x38
68#define OMAP_I2C_SYSTEST_REG 0x3c
b6ee52c3 69#define OMAP_I2C_BUFSTAT_REG 0x40
010d442c
KS		 70
71/* I2C Interrupt Enable Register (OMAP_I2C_IE): */
b6ee52c3
NM		 72#define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */
73#define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */
010d442c
KS		 74#define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */
75#define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */
76#define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */
77#define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */
78#define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */
79
80/* I2C Status Register (OMAP_I2C_STAT): */
b6ee52c3
NM		 81#define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */
82#define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */
010d442c
KS		 83#define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */
84#define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */
85#define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
86#define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */
87#define OMAP_I2C_STAT_AD0 (1 << 8) /* Address zero */
88#define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
89#define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */
90#define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */
91#define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */
92#define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */
93
5043e9e7
KJ		 94/* I2C WE wakeup enable register */
95#define OMAP_I2C_WE_XDR_WE (1 << 14) /* TX drain wakup */
96#define OMAP_I2C_WE_RDR_WE (1 << 13) /* RX drain wakeup */
97#define OMAP_I2C_WE_AAS_WE (1 << 9) /* Address as slave wakeup*/
98#define OMAP_I2C_WE_BF_WE (1 << 8) /* Bus free wakeup */
99#define OMAP_I2C_WE_STC_WE (1 << 6) /* Start condition wakeup */
100#define OMAP_I2C_WE_GC_WE (1 << 5) /* General call wakeup */
101#define OMAP_I2C_WE_DRDY_WE (1 << 3) /* TX/RX data ready wakeup */
102#define OMAP_I2C_WE_ARDY_WE (1 << 2) /* Reg access ready wakeup */
103#define OMAP_I2C_WE_NACK_WE (1 << 1) /* No acknowledgment wakeup */
104#define OMAP_I2C_WE_AL_WE (1 << 0) /* Arbitration lost wakeup */
105
106#define OMAP_I2C_WE_ALL (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \
107 OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \
108 OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \
109 OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \
110 OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE)
111
010d442c
KS		 112/* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
113#define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */
b6ee52c3 114#define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */
010d442c 115#define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */
b6ee52c3 116#define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */
010d442c
KS		 117
118/* I2C Configuration Register (OMAP_I2C_CON): */
119#define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */
120#define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */
b6ee52c3 121#define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */
010d442c
KS		 122#define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */
123#define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */
124#define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */
125#define OMAP_I2C_CON_XA (1 << 8) /* Expand address */
126#define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */
127#define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */
128#define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */
129
4574eb68
SMK		 130/* I2C SCL time value when Master */
131#define OMAP_I2C_SCLL_HSSCLL 8
132#define OMAP_I2C_SCLH_HSSCLH 8
133
010d442c
KS		 134/* I2C System Test Register (OMAP_I2C_SYSTEST): */
135#ifdef DEBUG
136#define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
137#define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */
138#define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
139#define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
140#define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */
141#define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */
142#define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */
143#define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */
144#endif
145
fdd07fe6
PW		 146/* OCP_SYSSTATUS bit definitions */
147#define SYSS_RESETDONE_MASK (1 << 0)
148
149/* OCP_SYSCONFIG bit definitions */
150#define SYSC_CLOCKACTIVITY_MASK (0x3 << 8)
151#define SYSC_SIDLEMODE_MASK (0x3 << 3)
152#define SYSC_ENAWAKEUP_MASK (1 << 2)
153#define SYSC_SOFTRESET_MASK (1 << 1)
154#define SYSC_AUTOIDLE_MASK (1 << 0)
155
156#define SYSC_IDLEMODE_SMART 0x2
157#define SYSC_CLOCKACTIVITY_FCLK 0x2
010d442c 158
010d442c 159
010d442c
KS		 160struct omap_i2c_dev {
161 struct device *dev;
162 void __iomem *base; /* virtual */
163 int irq;
164 struct clk *iclk; /* Interface clock */
165 struct clk *fclk; /* Functional clock */
166 struct completion cmd_complete;
167 struct resource *ioarea;
4574eb68 168 u32 speed; /* Speed of bus in Khz */
010d442c
KS		 169 u16 cmd_err;
170 u8 *buf;
171 size_t buf_len;
172 struct i2c_adapter adapter;
b6ee52c3
NM		 173 u8 fifo_size; /* use as flag and value
174 * fifo_size==0 implies no fifo
175 * if set, should be trsh+1
176 */
9c76b878 177 u8 rev;
b6ee52c3 178 unsigned b_hw:1; /* bad h/w fixes */
f08ac4e7
TL		 179 unsigned idle:1;
180 u16 iestate; /* Saved interrupt register */
010d442c
KS		 181};
182
183static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
184 int reg, u16 val)
185{
186 __raw_writew(val, i2c_dev->base + reg);
187}
188
189static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
190{
191 return __raw_readw(i2c_dev->base + reg);
192}
193
510be9c9 194static int __init omap_i2c_get_clocks(struct omap_i2c_dev *dev)
010d442c 195{
5fe23380
RK		 196 int ret;
197
198 dev->iclk = clk_get(dev->dev, "ick");
199 if (IS_ERR(dev->iclk)) {
200 ret = PTR_ERR(dev->iclk);
201 dev->iclk = NULL;
202 return ret;
010d442c
KS		 203 }
204
1d14de08 205 dev->fclk = clk_get(dev->dev, "fck");
010d442c 206 if (IS_ERR(dev->fclk)) {
5fe23380 207 ret = PTR_ERR(dev->fclk);
010d442c
KS		 208 if (dev->iclk != NULL) {
209 clk_put(dev->iclk);
210 dev->iclk = NULL;
211 }
212 dev->fclk = NULL;
5fe23380 213 return ret;
010d442c
KS		 214 }
215
216 return 0;
217}
218
219static void omap_i2c_put_clocks(struct omap_i2c_dev *dev)
220{
221 clk_put(dev->fclk);
222 dev->fclk = NULL;
5fe23380
RK		 223 clk_put(dev->iclk);
224 dev->iclk = NULL;
010d442c
KS		 225}
226
f08ac4e7 227static void omap_i2c_unidle(struct omap_i2c_dev *dev)
010d442c 228{
3831f154
PW		 229 WARN_ON(!dev->idle);
230
5fe23380 231 clk_enable(dev->iclk);
010d442c 232 clk_enable(dev->fclk);
0cbbcffd 233 dev->idle = 0;
f08ac4e7
TL		 234 if (dev->iestate)
235 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
010d442c
KS		 236}
237
f08ac4e7 238static void omap_i2c_idle(struct omap_i2c_dev *dev)
010d442c 239{
f08ac4e7
TL		 240 u16 iv;
241
3831f154
PW		 242 WARN_ON(dev->idle);
243
f08ac4e7
TL		 244 dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
245 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0);
9c76b878 246 if (dev->rev < OMAP_I2C_REV_2) {
c1a473bd 247 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); /* Read clears */
0cbbcffd 248 } else {
f08ac4e7 249 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, dev->iestate);
0cbbcffd
PW		 250
251 /* Flush posted write before the dev->idle store occurs */
252 omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
253 }
254 dev->idle = 1;
f08ac4e7 255 clk_disable(dev->fclk);
5fe23380 256 clk_disable(dev->iclk);
010d442c
KS		 257}
258
259static int omap_i2c_init(struct omap_i2c_dev *dev)
260{
4574eb68
SMK		 261 u16 psc = 0, scll = 0, sclh = 0;
262 u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
010d442c
KS		 263 unsigned long fclk_rate = 12000000;
264 unsigned long timeout;
4574eb68 265 unsigned long internal_clk = 0;
010d442c 266
9c76b878 267 if (dev->rev >= OMAP_I2C_REV_2) {
fdd07fe6 268 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK);
010d442c
KS		 269 /* For some reason we need to set the EN bit before the
270 * reset done bit gets set. */
271 timeout = jiffies + OMAP_I2C_TIMEOUT;
272 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
273 while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
fdd07fe6 274 SYSS_RESETDONE_MASK)) {
010d442c 275 if (time_after(jiffies, timeout)) {
fce3ff03 276 dev_warn(dev->dev, "timeout waiting "
010d442c
KS		 277 "for controller reset\n");
278 return -ETIMEDOUT;
279 }
280 msleep(1);
281 }
fdd07fe6
PW		 282
283 /* SYSC register is cleared by the reset; rewrite it */
284 if (dev->rev == OMAP_I2C_REV_ON_2430) {
285
286 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
287 SYSC_AUTOIDLE_MASK);
288
289 } else if (dev->rev >= OMAP_I2C_REV_ON_3430) {
290 u32 v;
291
292 v = SYSC_AUTOIDLE_MASK;
293 v |= SYSC_ENAWAKEUP_MASK;
294 v |= (SYSC_IDLEMODE_SMART <<
295 __ffs(SYSC_SIDLEMODE_MASK));
296 v |= (SYSC_CLOCKACTIVITY_FCLK <<
297 __ffs(SYSC_CLOCKACTIVITY_MASK));
298
299 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, v);
5043e9e7
KJ		 300 /*
301 * Enabling all wakup sources to stop I2C freezing on
302 * WFI instruction.
303 * REVISIT: Some wkup sources might not be needed.
304 */
305 omap_i2c_write_reg(dev, OMAP_I2C_WE_REG,
306 OMAP_I2C_WE_ALL);
fdd07fe6
PW		 307
308 }
010d442c
KS		 309 }
310 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
311
312 if (cpu_class_is_omap1()) {
0e9ae109
RK		 313 /*
314 * The I2C functional clock is the armxor_ck, so there's
315 * no need to get "armxor_ck" separately. Now, if OMAP2420
316 * always returns 12MHz for the functional clock, we can
317 * do this bit unconditionally.
318 */
319 fclk_rate = clk_get_rate(dev->fclk);
320
010d442c
KS		 321 /* TRM for 5912 says the I2C clock must be prescaled to be
322 * between 7 - 12 MHz. The XOR input clock is typically
323 * 12, 13 or 19.2 MHz. So we should have code that produces:
324 *
325 * XOR MHz Divider Prescaler
326 * 12 1 0
327 * 13 2 1
328 * 19.2 2 1
329 */
d7aef138
JD		 330 if (fclk_rate > 12000000)
331 psc = fclk_rate / 12000000;
010d442c
KS		 332 }
333
3d522fb4 334 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
4574eb68 335
84bf2c86
AK		 336 /*
337 * HSI2C controller internal clk rate should be 19.2 Mhz for
338 * HS and for all modes on 2430. On 34xx we can use lower rate
339 * to get longer filter period for better noise suppression.
340 * The filter is iclk (fclk for HS) period.
341 */
ff0f2426 342 if (dev->speed > 400 || cpu_is_omap2430())
84bf2c86
AK		 343 internal_clk = 19200;
344 else if (dev->speed > 100)
345 internal_clk = 9600;
346 else
347 internal_clk = 4000;
4574eb68
SMK		 348 fclk_rate = clk_get_rate(dev->fclk) / 1000;
349
350 /* Compute prescaler divisor */
351 psc = fclk_rate / internal_clk;
352 psc = psc - 1;
353
354 /* If configured for High Speed */
355 if (dev->speed > 400) {
baf46b4e
AK		 356 unsigned long scl;
357
4574eb68 358 /* For first phase of HS mode */
baf46b4e
AK		 359 scl = internal_clk / 400;
360 fsscll = scl - (scl / 3) - 7;
361 fssclh = (scl / 3) - 5;
4574eb68
SMK		 362
363 /* For second phase of HS mode */
baf46b4e
AK		 364 scl = fclk_rate / dev->speed;
365 hsscll = scl - (scl / 3) - 7;
366 hssclh = (scl / 3) - 5;
367 } else if (dev->speed > 100) {
368 unsigned long scl;
369
370 /* Fast mode */
371 scl = internal_clk / dev->speed;
372 fsscll = scl - (scl / 3) - 7;
373 fssclh = (scl / 3) - 5;
4574eb68 374 } else {
baf46b4e
AK		 375 /* Standard mode */
376 fsscll = internal_clk / (dev->speed * 2) - 7;
377 fssclh = internal_clk / (dev->speed * 2) - 5;
4574eb68
SMK		 378 }
379 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
380 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
381 } else {
382 /* Program desired operating rate */
383 fclk_rate /= (psc + 1) * 1000;
384 if (psc > 2)
385 psc = 2;
386 scll = fclk_rate / (dev->speed * 2) - 7 + psc;
387 sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
388 }
389
010d442c
KS		 390 /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
391 omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);
392
4574eb68
SMK		 393 /* SCL low and high time values */
394 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll);
395 omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh);
010d442c 396
b6ee52c3
NM		 397 if (dev->fifo_size)
398 /* Note: setup required fifo size - 1 */
399 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG,
400 (dev->fifo_size - 1) << 8 | /* RTRSH */
401 OMAP_I2C_BUF_RXFIF_CLR |
402 (dev->fifo_size - 1) | /* XTRSH */
403 OMAP_I2C_BUF_TXFIF_CLR);
404
010d442c
KS		 405 /* Take the I2C module out of reset: */
406 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
407
408 /* Enable interrupts */
409 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG,
c1a473bd
TL		 410 (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
411 OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
412 OMAP_I2C_IE_AL) | ((dev->fifo_size) ?
b6ee52c3 413 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0));
010d442c
KS		 414 return 0;
415}
416
417/*
418 * Waiting on Bus Busy
419 */
420static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
421{
422 unsigned long timeout;
423
424 timeout = jiffies + OMAP_I2C_TIMEOUT;
425 while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
426 if (time_after(jiffies, timeout)) {
427 dev_warn(dev->dev, "timeout waiting for bus ready\n");
428 return -ETIMEDOUT;
429 }
430 msleep(1);
431 }
432
433 return 0;
434}
435
436/*
437 * Low level master read/write transaction.
438 */
439static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
440 struct i2c_msg *msg, int stop)
441{
442 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
443 int r;
444 u16 w;
445
446 dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
447 msg->addr, msg->len, msg->flags, stop);
448
449 if (msg->len == 0)
450 return -EINVAL;
451
452 omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
453
454 /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
455 dev->buf = msg->buf;
456 dev->buf_len = msg->len;
457
458 omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
459
b6ee52c3
NM		 460 /* Clear the FIFO Buffers */
461 w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
462 w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
463 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w);
464
010d442c
KS		 465 init_completion(&dev->cmd_complete);
466 dev->cmd_err = 0;
467
468 w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
4574eb68
SMK		 469
470 /* High speed configuration */
471 if (dev->speed > 400)
b6ee52c3 472 w |= OMAP_I2C_CON_OPMODE_HS;
4574eb68 473
010d442c
KS		 474 if (msg->flags & I2C_M_TEN)
475 w |= OMAP_I2C_CON_XA;
476 if (!(msg->flags & I2C_M_RD))
477 w |= OMAP_I2C_CON_TRX;
c1a473bd 478
b6ee52c3 479 if (!dev->b_hw && stop)
010d442c 480 w |= OMAP_I2C_CON_STP;
c1a473bd 481
010d442c
KS		 482 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
483
b6ee52c3
NM		 484 /*
485 * Don't write stt and stp together on some hardware.
486 */
487 if (dev->b_hw && stop) {
488 unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
489 u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
490 while (con & OMAP_I2C_CON_STT) {
491 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
492
493 /* Let the user know if i2c is in a bad state */
494 if (time_after(jiffies, delay)) {
495 dev_err(dev->dev, "controller timed out "
496 "waiting for start condition to finish\n");
497 return -ETIMEDOUT;
498 }
499 cpu_relax();
500 }
501
502 w |= OMAP_I2C_CON_STP;
503 w &= ~OMAP_I2C_CON_STT;
504 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
505 }
506
b7af349b
JN		 507 /*
508 * REVISIT: We should abort the transfer on signals, but the bus goes
509 * into arbitration and we're currently unable to recover from it.
510 */
511 r = wait_for_completion_timeout(&dev->cmd_complete,
512 OMAP_I2C_TIMEOUT);
010d442c
KS		 513 dev->buf_len = 0;
514 if (r < 0)
515 return r;
516 if (r == 0) {
517 dev_err(dev->dev, "controller timed out\n");
518 omap_i2c_init(dev);
519 return -ETIMEDOUT;
520 }
521
522 if (likely(!dev->cmd_err))
523 return 0;
524
525 /* We have an error */
526 if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
527 OMAP_I2C_STAT_XUDF)) {
528 omap_i2c_init(dev);
529 return -EIO;
530 }
531
532 if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
533 if (msg->flags & I2C_M_IGNORE_NAK)
534 return 0;
535 if (stop) {
536 w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
537 w |= OMAP_I2C_CON_STP;
538 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
539 }
540 return -EREMOTEIO;
541 }
542 return -EIO;
543}
544
545
546/*
547 * Prepare controller for a transaction and call omap_i2c_xfer_msg
548 * to do the work during IRQ processing.
549 */
550static int
551omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
552{
553 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
554 int i;
555 int r;
556
f08ac4e7 557 omap_i2c_unidle(dev);
010d442c 558
c1a473bd
TL		 559 r = omap_i2c_wait_for_bb(dev);
560 if (r < 0)
010d442c
KS		 561 goto out;
562
563 for (i = 0; i < num; i++) {
564 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
565 if (r != 0)
566 break;
567 }
568
569 if (r == 0)
570 r = num;
571out:
f08ac4e7 572 omap_i2c_idle(dev);
010d442c
KS		 573 return r;
574}
575
576static u32
577omap_i2c_func(struct i2c_adapter *adap)
578{
579 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
580}
581
582static inline void
583omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)
584{
585 dev->cmd_err |= err;
586 complete(&dev->cmd_complete);
587}
588
589static inline void
590omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
591{
592 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
593}
594
43469d8e
PW		 595/* rev1 devices are apparently only on some 15xx */
596#ifdef CONFIG_ARCH_OMAP15XX
597
010d442c 598static irqreturn_t
7d12e780 599omap_i2c_rev1_isr(int this_irq, void *dev_id)
010d442c
KS		 600{
601 struct omap_i2c_dev *dev = dev_id;
602 u16 iv, w;
603
f08ac4e7
TL		 604 if (dev->idle)
605 return IRQ_NONE;
606
010d442c
KS		 607 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
608 switch (iv) {
609 case 0x00: /* None */
610 break;
611 case 0x01: /* Arbitration lost */
612 dev_err(dev->dev, "Arbitration lost\n");
613 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
614 break;
615 case 0x02: /* No acknowledgement */
616 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
617 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
618 break;
619 case 0x03: /* Register access ready */
620 omap_i2c_complete_cmd(dev, 0);
621 break;
622 case 0x04: /* Receive data ready */
623 if (dev->buf_len) {
624 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
625 *dev->buf++ = w;
626 dev->buf_len--;
627 if (dev->buf_len) {
628 *dev->buf++ = w >> 8;
629 dev->buf_len--;
630 }
631 } else
632 dev_err(dev->dev, "RRDY IRQ while no data requested\n");
633 break;
634 case 0x05: /* Transmit data ready */
635 if (dev->buf_len) {
636 w = *dev->buf++;
637 dev->buf_len--;
638 if (dev->buf_len) {
639 w |= *dev->buf++ << 8;
640 dev->buf_len--;
641 }
642 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
643 } else
644 dev_err(dev->dev, "XRDY IRQ while no data to send\n");
645 break;
646 default:
647 return IRQ_NONE;
648 }
649
650 return IRQ_HANDLED;
651}
43469d8e 652#else
c1a473bd 653#define omap_i2c_rev1_isr NULL
43469d8e 654#endif
010d442c
KS		 655
656static irqreturn_t
7d12e780 657omap_i2c_isr(int this_irq, void *dev_id)
010d442c
KS		 658{
659 struct omap_i2c_dev *dev = dev_id;
660 u16 bits;
661 u16 stat, w;
b6ee52c3 662 int err, count = 0;
010d442c 663
f08ac4e7
TL		 664 if (dev->idle)
665 return IRQ_NONE;
666
010d442c
KS		 667 bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
668 while ((stat = (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG))) & bits) {
669 dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
670 if (count++ == 100) {
671 dev_warn(dev->dev, "Too much work in one IRQ\n");
672 break;
673 }
674
675 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
676
b6ee52c3
NM		 677 err = 0;
678 if (stat & OMAP_I2C_STAT_NACK) {
679 err |= OMAP_I2C_STAT_NACK;
680 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
681 OMAP_I2C_CON_STP);
010d442c 682 }
b6ee52c3
NM		 683 if (stat & OMAP_I2C_STAT_AL) {
684 dev_err(dev->dev, "Arbitration lost\n");
685 err |= OMAP_I2C_STAT_AL;
686 }
687 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
688 OMAP_I2C_STAT_AL))
689 omap_i2c_complete_cmd(dev, err);
690 if (stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR)) {
691 u8 num_bytes = 1;
692 if (dev->fifo_size) {
693 if (stat & OMAP_I2C_STAT_RRDY)
694 num_bytes = dev->fifo_size;
bfb6b658
SM		 695 else /* read RXSTAT on RDR interrupt */
696 num_bytes = (omap_i2c_read_reg(dev,
697 OMAP_I2C_BUFSTAT_REG)
698 >> 8) & 0x3F;
b6ee52c3
NM		 699 }
700 while (num_bytes) {
701 num_bytes--;
702 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
010d442c 703 if (dev->buf_len) {
b6ee52c3 704 *dev->buf++ = w;
010d442c 705 dev->buf_len--;
b6ee52c3 706 /* Data reg from 2430 is 8 bit wide */
3d522fb4
C		 707 if (!cpu_is_omap2430() &&
708 !cpu_is_omap34xx()) {
b6ee52c3
NM		 709 if (dev->buf_len) {
710 *dev->buf++ = w >> 8;
711 dev->buf_len--;
712 }
713 }
714 } else {
715 if (stat & OMAP_I2C_STAT_RRDY)
716 dev_err(dev->dev,
717 "RRDY IRQ while no data"
718 " requested\n");
719 if (stat & OMAP_I2C_STAT_RDR)
720 dev_err(dev->dev,
721 "RDR IRQ while no data"
722 " requested\n");
723 break;
010d442c 724 }
b6ee52c3
NM		 725 }
726 omap_i2c_ack_stat(dev,
727 stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR));
010d442c
KS		 728 continue;
729 }
b6ee52c3
NM		 730 if (stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)) {
731 u8 num_bytes = 1;
732 if (dev->fifo_size) {
733 if (stat & OMAP_I2C_STAT_XRDY)
734 num_bytes = dev->fifo_size;
bfb6b658 735 else /* read TXSTAT on XDR interrupt */
b6ee52c3 736 num_bytes = omap_i2c_read_reg(dev,
bfb6b658
SM		 737 OMAP_I2C_BUFSTAT_REG)
738 & 0x3F;
b6ee52c3
NM		 739 }
740 while (num_bytes) {
741 num_bytes--;
742 w = 0;
010d442c 743 if (dev->buf_len) {
b6ee52c3 744 w = *dev->buf++;
010d442c 745 dev->buf_len--;
b6ee52c3 746 /* Data reg from 2430 is 8 bit wide */
3d522fb4
C		 747 if (!cpu_is_omap2430() &&
748 !cpu_is_omap34xx()) {
b6ee52c3
NM		 749 if (dev->buf_len) {
750 w |= *dev->buf++ << 8;
751 dev->buf_len--;
752 }
753 }
754 } else {
755 if (stat & OMAP_I2C_STAT_XRDY)
756 dev_err(dev->dev,
757 "XRDY IRQ while no "
758 "data to send\n");
759 if (stat & OMAP_I2C_STAT_XDR)
760 dev_err(dev->dev,
761 "XDR IRQ while no "
762 "data to send\n");
763 break;
010d442c 764 }
b6ee52c3
NM		 765 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
766 }
767 omap_i2c_ack_stat(dev,
768 stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
010d442c
KS		 769 continue;
770 }
771 if (stat & OMAP_I2C_STAT_ROVR) {
772 dev_err(dev->dev, "Receive overrun\n");
773 dev->cmd_err |= OMAP_I2C_STAT_ROVR;
774 }
775 if (stat & OMAP_I2C_STAT_XUDF) {
b6ee52c3 776 dev_err(dev->dev, "Transmit underflow\n");
010d442c
KS		 777 dev->cmd_err |= OMAP_I2C_STAT_XUDF;
778 }
010d442c
KS		 779 }
780
781 return count ? IRQ_HANDLED : IRQ_NONE;
782}
783
8f9082c5 784static const struct i2c_algorithm omap_i2c_algo = {
010d442c
KS		 785 .master_xfer = omap_i2c_xfer,
786 .functionality = omap_i2c_func,
787};
788
510be9c9 789static int __init
010d442c
KS		 790omap_i2c_probe(struct platform_device *pdev)
791{
792 struct omap_i2c_dev *dev;
793 struct i2c_adapter *adap;
794 struct resource *mem, *irq, *ioarea;
e355204e 795 irq_handler_t isr;
010d442c 796 int r;
3d522fb4 797 u32 speed = 0;
010d442c
KS		 798
799 /* NOTE: driver uses the static register mapping */
800 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
801 if (!mem) {
802 dev_err(&pdev->dev, "no mem resource?\n");
803 return -ENODEV;
804 }
805 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
806 if (!irq) {
807 dev_err(&pdev->dev, "no irq resource?\n");
808 return -ENODEV;
809 }
810
59330825 811 ioarea = request_mem_region(mem->start, resource_size(mem),
010d442c
KS		 812 pdev->name);
813 if (!ioarea) {
814 dev_err(&pdev->dev, "I2C region already claimed\n");
815 return -EBUSY;
816 }
817
010d442c
KS		 818 dev = kzalloc(sizeof(struct omap_i2c_dev), GFP_KERNEL);
819 if (!dev) {
820 r = -ENOMEM;
821 goto err_release_region;
822 }
823
4574eb68 824 if (pdev->dev.platform_data != NULL)
3d522fb4 825 speed = *(u32 *)pdev->dev.platform_data;
4574eb68 826 else
3d522fb4 827 speed = 100; /* Defualt speed */
4574eb68 828
3d522fb4 829 dev->speed = speed;
3831f154 830 dev->idle = 1;
010d442c
KS		 831 dev->dev = &pdev->dev;
832 dev->irq = irq->start;
c6ffddea 833 dev->base = ioremap(mem->start, resource_size(mem));
55c381e4
RK		 834 if (!dev->base) {
835 r = -ENOMEM;
836 goto err_free_mem;
837 }
838
010d442c
KS		 839 platform_set_drvdata(pdev, dev);
840
841 if ((r = omap_i2c_get_clocks(dev)) != 0)
55c381e4 842 goto err_iounmap;
010d442c 843
f08ac4e7 844 omap_i2c_unidle(dev);
010d442c 845
9c76b878 846 dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
010d442c 847
3d522fb4 848 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
b6ee52c3
NM		 849 u16 s;
850
851 /* Set up the fifo size - Get total size */
852 s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
853 dev->fifo_size = 0x8 << s;
854
855 /*
856 * Set up notification threshold as half the total available
857 * size. This is to ensure that we can handle the status on int
858 * call back latencies.
859 */
860 dev->fifo_size = (dev->fifo_size / 2);
861 dev->b_hw = 1; /* Enable hardware fixes */
862 }
863
010d442c
KS		 864 /* reset ASAP, clearing any IRQs */
865 omap_i2c_init(dev);
866
9c76b878
PW		 867 isr = (dev->rev < OMAP_I2C_REV_2) ? omap_i2c_rev1_isr : omap_i2c_isr;
868 r = request_irq(dev->irq, isr, 0, pdev->name, dev);
010d442c
KS		 869
870 if (r) {
871 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
872 goto err_unuse_clocks;
873 }
9c76b878 874
010d442c 875 dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n",
9c76b878 876 pdev->id, dev->rev >> 4, dev->rev & 0xf, dev->speed);
010d442c 877
3831f154
PW		 878 omap_i2c_idle(dev);
879
010d442c
KS		 880 adap = &dev->adapter;
881 i2c_set_adapdata(adap, dev);
882 adap->owner = THIS_MODULE;
883 adap->class = I2C_CLASS_HWMON;
783fd6fa 884 strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
010d442c
KS		 885 adap->algo = &omap_i2c_algo;
886 adap->dev.parent = &pdev->dev;
887
888 /* i2c device drivers may be active on return from add_adapter() */
7c175499
DB		 889 adap->nr = pdev->id;
890 r = i2c_add_numbered_adapter(adap);
010d442c
KS		 891 if (r) {
892 dev_err(dev->dev, "failure adding adapter\n");
893 goto err_free_irq;
894 }
895
010d442c
KS		 896 return 0;
897
898err_free_irq:
899 free_irq(dev->irq, dev);
900err_unuse_clocks:
3e39752d 901 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
f08ac4e7 902 omap_i2c_idle(dev);
010d442c 903 omap_i2c_put_clocks(dev);
55c381e4
RK		 904err_iounmap:
905 iounmap(dev->base);
010d442c
KS		 906err_free_mem:
907 platform_set_drvdata(pdev, NULL);
908 kfree(dev);
909err_release_region:
59330825 910 release_mem_region(mem->start, resource_size(mem));
010d442c
KS		 911
912 return r;
913}
914
915static int
916omap_i2c_remove(struct platform_device *pdev)
917{
918 struct omap_i2c_dev *dev = platform_get_drvdata(pdev);
919 struct resource *mem;
920
921 platform_set_drvdata(pdev, NULL);
922
923 free_irq(dev->irq, dev);
924 i2c_del_adapter(&dev->adapter);
925 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
926 omap_i2c_put_clocks(dev);
55c381e4 927 iounmap(dev->base);
010d442c
KS		 928 kfree(dev);
929 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
59330825 930 release_mem_region(mem->start, resource_size(mem));
010d442c
KS		 931 return 0;
932}
933
934static struct platform_driver omap_i2c_driver = {
935 .probe = omap_i2c_probe,
936 .remove = omap_i2c_remove,
937 .driver = {
938 .name = "i2c_omap",
939 .owner = THIS_MODULE,
940 },
941};
942
943/* I2C may be needed to bring up other drivers */
944static int __init
945omap_i2c_init_driver(void)
946{
947 return platform_driver_register(&omap_i2c_driver);
948}
949subsys_initcall(omap_i2c_init_driver);
950
951static void __exit omap_i2c_exit_driver(void)
952{
953 platform_driver_unregister(&omap_i2c_driver);
954}
955module_exit(omap_i2c_exit_driver);
956
957MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
958MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
959MODULE_LICENSE("GPL");
add8eda7 960MODULE_ALIAS("platform:i2c_omap");
Linux 6.x block layer and io_uring tree(s)