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010d442c KS |
1 | /* |
2 | * TI OMAP I2C master mode driver | |
3 | * | |
4 | * Copyright (C) 2003 MontaVista Software, Inc. | |
010d442c | 5 | * Copyright (C) 2005 Nokia Corporation |
c1a473bd | 6 | * Copyright (C) 2004 - 2007 Texas Instruments. |
010d442c | 7 | * |
c1a473bd TL |
8 | * Originally written by MontaVista Software, Inc. |
9 | * Additional contributions by: | |
10 | * Tony Lindgren <tony@atomide.com> | |
11 | * Imre Deak <imre.deak@nokia.com> | |
12 | * Juha Yrjölä <juha.yrjola@solidboot.com> | |
13 | * Syed Khasim <x0khasim@ti.com> | |
14 | * Nishant Menon <nm@ti.com> | |
010d442c KS |
15 | * |
16 | * This program is free software; you can redistribute it and/or modify | |
17 | * it under the terms of the GNU General Public License as published by | |
18 | * the Free Software Foundation; either version 2 of the License, or | |
19 | * (at your option) any later version. | |
20 | * | |
21 | * This program is distributed in the hope that it will be useful, | |
22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
24 | * GNU General Public License for more details. | |
25 | * | |
26 | * You should have received a copy of the GNU General Public License | |
27 | * along with this program; if not, write to the Free Software | |
28 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
29 | */ | |
30 | ||
31 | #include <linux/module.h> | |
32 | #include <linux/delay.h> | |
33 | #include <linux/i2c.h> | |
34 | #include <linux/err.h> | |
35 | #include <linux/interrupt.h> | |
36 | #include <linux/completion.h> | |
37 | #include <linux/platform_device.h> | |
38 | #include <linux/clk.h> | |
c1a473bd | 39 | #include <linux/io.h> |
6145197b BC |
40 | #include <linux/of.h> |
41 | #include <linux/of_i2c.h> | |
42 | #include <linux/of_device.h> | |
5a0e3ad6 | 43 | #include <linux/slab.h> |
20c9d2c4 | 44 | #include <linux/i2c-omap.h> |
27b1fec2 | 45 | #include <linux/pm_runtime.h> |
2d4b4520 | 46 | #include <linux/pinctrl/consumer.h> |
010d442c | 47 | |
9c76b878 | 48 | /* I2C controller revisions */ |
4e80f727 | 49 | #define OMAP_I2C_OMAP1_REV_2 0x20 |
9c76b878 PW |
50 | |
51 | /* I2C controller revisions present on specific hardware */ | |
47dcd016 S |
52 | #define OMAP_I2C_REV_ON_2430 0x00000036 |
53 | #define OMAP_I2C_REV_ON_3430_3530 0x0000003C | |
54 | #define OMAP_I2C_REV_ON_3630 0x00000040 | |
55 | #define OMAP_I2C_REV_ON_4430_PLUS 0x50400002 | |
9c76b878 | 56 | |
010d442c KS |
57 | /* timeout waiting for the controller to respond */ |
58 | #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000)) | |
59 | ||
6d8451d5 FB |
60 | /* timeout for pm runtime autosuspend */ |
61 | #define OMAP_I2C_PM_TIMEOUT 1000 /* ms */ | |
62 | ||
5043e9e7 | 63 | /* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */ |
f38e66e0 SS |
64 | enum { |
65 | OMAP_I2C_REV_REG = 0, | |
66 | OMAP_I2C_IE_REG, | |
67 | OMAP_I2C_STAT_REG, | |
68 | OMAP_I2C_IV_REG, | |
69 | OMAP_I2C_WE_REG, | |
70 | OMAP_I2C_SYSS_REG, | |
71 | OMAP_I2C_BUF_REG, | |
72 | OMAP_I2C_CNT_REG, | |
73 | OMAP_I2C_DATA_REG, | |
74 | OMAP_I2C_SYSC_REG, | |
75 | OMAP_I2C_CON_REG, | |
76 | OMAP_I2C_OA_REG, | |
77 | OMAP_I2C_SA_REG, | |
78 | OMAP_I2C_PSC_REG, | |
79 | OMAP_I2C_SCLL_REG, | |
80 | OMAP_I2C_SCLH_REG, | |
81 | OMAP_I2C_SYSTEST_REG, | |
82 | OMAP_I2C_BUFSTAT_REG, | |
b8853088 AG |
83 | /* only on OMAP4430 */ |
84 | OMAP_I2C_IP_V2_REVNB_LO, | |
85 | OMAP_I2C_IP_V2_REVNB_HI, | |
86 | OMAP_I2C_IP_V2_IRQSTATUS_RAW, | |
87 | OMAP_I2C_IP_V2_IRQENABLE_SET, | |
88 | OMAP_I2C_IP_V2_IRQENABLE_CLR, | |
f38e66e0 | 89 | }; |
010d442c KS |
90 | |
91 | /* I2C Interrupt Enable Register (OMAP_I2C_IE): */ | |
b6ee52c3 NM |
92 | #define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */ |
93 | #define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */ | |
010d442c KS |
94 | #define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */ |
95 | #define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */ | |
96 | #define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */ | |
97 | #define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */ | |
98 | #define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */ | |
99 | ||
100 | /* I2C Status Register (OMAP_I2C_STAT): */ | |
b6ee52c3 NM |
101 | #define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */ |
102 | #define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */ | |
010d442c KS |
103 | #define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */ |
104 | #define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */ | |
105 | #define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ | |
106 | #define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */ | |
107 | #define OMAP_I2C_STAT_AD0 (1 << 8) /* Address zero */ | |
108 | #define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ | |
109 | #define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */ | |
110 | #define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */ | |
111 | #define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */ | |
112 | #define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */ | |
113 | ||
5043e9e7 KJ |
114 | /* I2C WE wakeup enable register */ |
115 | #define OMAP_I2C_WE_XDR_WE (1 << 14) /* TX drain wakup */ | |
116 | #define OMAP_I2C_WE_RDR_WE (1 << 13) /* RX drain wakeup */ | |
117 | #define OMAP_I2C_WE_AAS_WE (1 << 9) /* Address as slave wakeup*/ | |
118 | #define OMAP_I2C_WE_BF_WE (1 << 8) /* Bus free wakeup */ | |
119 | #define OMAP_I2C_WE_STC_WE (1 << 6) /* Start condition wakeup */ | |
120 | #define OMAP_I2C_WE_GC_WE (1 << 5) /* General call wakeup */ | |
121 | #define OMAP_I2C_WE_DRDY_WE (1 << 3) /* TX/RX data ready wakeup */ | |
122 | #define OMAP_I2C_WE_ARDY_WE (1 << 2) /* Reg access ready wakeup */ | |
123 | #define OMAP_I2C_WE_NACK_WE (1 << 1) /* No acknowledgment wakeup */ | |
124 | #define OMAP_I2C_WE_AL_WE (1 << 0) /* Arbitration lost wakeup */ | |
125 | ||
126 | #define OMAP_I2C_WE_ALL (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \ | |
127 | OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \ | |
128 | OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \ | |
129 | OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \ | |
130 | OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE) | |
131 | ||
010d442c KS |
132 | /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */ |
133 | #define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */ | |
b6ee52c3 | 134 | #define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */ |
010d442c | 135 | #define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */ |
b6ee52c3 | 136 | #define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */ |
010d442c KS |
137 | |
138 | /* I2C Configuration Register (OMAP_I2C_CON): */ | |
139 | #define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */ | |
140 | #define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */ | |
b6ee52c3 | 141 | #define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */ |
010d442c KS |
142 | #define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */ |
143 | #define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */ | |
144 | #define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */ | |
145 | #define OMAP_I2C_CON_XA (1 << 8) /* Expand address */ | |
146 | #define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */ | |
147 | #define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */ | |
148 | #define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */ | |
149 | ||
4574eb68 SMK |
150 | /* I2C SCL time value when Master */ |
151 | #define OMAP_I2C_SCLL_HSSCLL 8 | |
152 | #define OMAP_I2C_SCLH_HSSCLH 8 | |
153 | ||
010d442c KS |
154 | /* I2C System Test Register (OMAP_I2C_SYSTEST): */ |
155 | #ifdef DEBUG | |
156 | #define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */ | |
157 | #define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */ | |
158 | #define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */ | |
159 | #define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */ | |
160 | #define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */ | |
161 | #define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */ | |
162 | #define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */ | |
163 | #define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */ | |
164 | #endif | |
165 | ||
fdd07fe6 PW |
166 | /* OCP_SYSSTATUS bit definitions */ |
167 | #define SYSS_RESETDONE_MASK (1 << 0) | |
168 | ||
169 | /* OCP_SYSCONFIG bit definitions */ | |
170 | #define SYSC_CLOCKACTIVITY_MASK (0x3 << 8) | |
171 | #define SYSC_SIDLEMODE_MASK (0x3 << 3) | |
172 | #define SYSC_ENAWAKEUP_MASK (1 << 2) | |
173 | #define SYSC_SOFTRESET_MASK (1 << 1) | |
174 | #define SYSC_AUTOIDLE_MASK (1 << 0) | |
175 | ||
176 | #define SYSC_IDLEMODE_SMART 0x2 | |
177 | #define SYSC_CLOCKACTIVITY_FCLK 0x2 | |
010d442c | 178 | |
f3083d92 | 179 | /* Errata definitions */ |
180 | #define I2C_OMAP_ERRATA_I207 (1 << 0) | |
c8db38f0 | 181 | #define I2C_OMAP_ERRATA_I462 (1 << 1) |
010d442c | 182 | |
010d442c | 183 | struct omap_i2c_dev { |
3b2f8f82 | 184 | spinlock_t lock; /* IRQ synchronization */ |
010d442c KS |
185 | struct device *dev; |
186 | void __iomem *base; /* virtual */ | |
187 | int irq; | |
d84d3ea3 | 188 | int reg_shift; /* bit shift for I2C register addresses */ |
010d442c KS |
189 | struct completion cmd_complete; |
190 | struct resource *ioarea; | |
49839dc9 PW |
191 | u32 latency; /* maximum mpu wkup latency */ |
192 | void (*set_mpu_wkup_lat)(struct device *dev, | |
193 | long latency); | |
6145197b BC |
194 | u32 speed; /* Speed of bus in kHz */ |
195 | u32 dtrev; /* extra revision from DT */ | |
196 | u32 flags; | |
010d442c KS |
197 | u16 cmd_err; |
198 | u8 *buf; | |
f38e66e0 | 199 | u8 *regs; |
010d442c KS |
200 | size_t buf_len; |
201 | struct i2c_adapter adapter; | |
dd74548d | 202 | u8 threshold; |
b6ee52c3 NM |
203 | u8 fifo_size; /* use as flag and value |
204 | * fifo_size==0 implies no fifo | |
205 | * if set, should be trsh+1 | |
206 | */ | |
47dcd016 | 207 | u32 rev; |
b6ee52c3 | 208 | unsigned b_hw:1; /* bad h/w fixes */ |
079d8af2 | 209 | unsigned receiver:1; /* true when we're in receiver mode */ |
f08ac4e7 | 210 | u16 iestate; /* Saved interrupt register */ |
ef871432 RN |
211 | u16 pscstate; |
212 | u16 scllstate; | |
213 | u16 sclhstate; | |
214 | u16 bufstate; | |
215 | u16 syscstate; | |
216 | u16 westate; | |
f3083d92 | 217 | u16 errata; |
2d4b4520 SG |
218 | |
219 | struct pinctrl *pins; | |
010d442c KS |
220 | }; |
221 | ||
a1295577 | 222 | static const u8 reg_map_ip_v1[] = { |
f38e66e0 SS |
223 | [OMAP_I2C_REV_REG] = 0x00, |
224 | [OMAP_I2C_IE_REG] = 0x01, | |
225 | [OMAP_I2C_STAT_REG] = 0x02, | |
226 | [OMAP_I2C_IV_REG] = 0x03, | |
227 | [OMAP_I2C_WE_REG] = 0x03, | |
228 | [OMAP_I2C_SYSS_REG] = 0x04, | |
229 | [OMAP_I2C_BUF_REG] = 0x05, | |
230 | [OMAP_I2C_CNT_REG] = 0x06, | |
231 | [OMAP_I2C_DATA_REG] = 0x07, | |
232 | [OMAP_I2C_SYSC_REG] = 0x08, | |
233 | [OMAP_I2C_CON_REG] = 0x09, | |
234 | [OMAP_I2C_OA_REG] = 0x0a, | |
235 | [OMAP_I2C_SA_REG] = 0x0b, | |
236 | [OMAP_I2C_PSC_REG] = 0x0c, | |
237 | [OMAP_I2C_SCLL_REG] = 0x0d, | |
238 | [OMAP_I2C_SCLH_REG] = 0x0e, | |
239 | [OMAP_I2C_SYSTEST_REG] = 0x0f, | |
240 | [OMAP_I2C_BUFSTAT_REG] = 0x10, | |
241 | }; | |
242 | ||
a1295577 | 243 | static const u8 reg_map_ip_v2[] = { |
f38e66e0 SS |
244 | [OMAP_I2C_REV_REG] = 0x04, |
245 | [OMAP_I2C_IE_REG] = 0x2c, | |
246 | [OMAP_I2C_STAT_REG] = 0x28, | |
247 | [OMAP_I2C_IV_REG] = 0x34, | |
248 | [OMAP_I2C_WE_REG] = 0x34, | |
249 | [OMAP_I2C_SYSS_REG] = 0x90, | |
250 | [OMAP_I2C_BUF_REG] = 0x94, | |
251 | [OMAP_I2C_CNT_REG] = 0x98, | |
252 | [OMAP_I2C_DATA_REG] = 0x9c, | |
2727b175 | 253 | [OMAP_I2C_SYSC_REG] = 0x10, |
f38e66e0 SS |
254 | [OMAP_I2C_CON_REG] = 0xa4, |
255 | [OMAP_I2C_OA_REG] = 0xa8, | |
256 | [OMAP_I2C_SA_REG] = 0xac, | |
257 | [OMAP_I2C_PSC_REG] = 0xb0, | |
258 | [OMAP_I2C_SCLL_REG] = 0xb4, | |
259 | [OMAP_I2C_SCLH_REG] = 0xb8, | |
260 | [OMAP_I2C_SYSTEST_REG] = 0xbC, | |
261 | [OMAP_I2C_BUFSTAT_REG] = 0xc0, | |
b8853088 AG |
262 | [OMAP_I2C_IP_V2_REVNB_LO] = 0x00, |
263 | [OMAP_I2C_IP_V2_REVNB_HI] = 0x04, | |
264 | [OMAP_I2C_IP_V2_IRQSTATUS_RAW] = 0x24, | |
265 | [OMAP_I2C_IP_V2_IRQENABLE_SET] = 0x2c, | |
266 | [OMAP_I2C_IP_V2_IRQENABLE_CLR] = 0x30, | |
f38e66e0 SS |
267 | }; |
268 | ||
010d442c KS |
269 | static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev, |
270 | int reg, u16 val) | |
271 | { | |
f38e66e0 SS |
272 | __raw_writew(val, i2c_dev->base + |
273 | (i2c_dev->regs[reg] << i2c_dev->reg_shift)); | |
010d442c KS |
274 | } |
275 | ||
276 | static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg) | |
277 | { | |
f38e66e0 SS |
278 | return __raw_readw(i2c_dev->base + |
279 | (i2c_dev->regs[reg] << i2c_dev->reg_shift)); | |
010d442c KS |
280 | } |
281 | ||
010d442c KS |
282 | static int omap_i2c_init(struct omap_i2c_dev *dev) |
283 | { | |
ef871432 | 284 | u16 psc = 0, scll = 0, sclh = 0, buf = 0; |
4574eb68 | 285 | u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0; |
010d442c KS |
286 | unsigned long fclk_rate = 12000000; |
287 | unsigned long timeout; | |
4574eb68 | 288 | unsigned long internal_clk = 0; |
27b1fec2 | 289 | struct clk *fclk; |
010d442c | 290 | |
4e80f727 | 291 | if (dev->rev >= OMAP_I2C_OMAP1_REV_2) { |
57eb81b1 MG |
292 | /* Disable I2C controller before soft reset */ |
293 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, | |
294 | omap_i2c_read_reg(dev, OMAP_I2C_CON_REG) & | |
295 | ~(OMAP_I2C_CON_EN)); | |
296 | ||
fdd07fe6 | 297 | omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK); |
010d442c KS |
298 | /* For some reason we need to set the EN bit before the |
299 | * reset done bit gets set. */ | |
300 | timeout = jiffies + OMAP_I2C_TIMEOUT; | |
301 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN); | |
302 | while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) & | |
fdd07fe6 | 303 | SYSS_RESETDONE_MASK)) { |
010d442c | 304 | if (time_after(jiffies, timeout)) { |
fce3ff03 | 305 | dev_warn(dev->dev, "timeout waiting " |
010d442c KS |
306 | "for controller reset\n"); |
307 | return -ETIMEDOUT; | |
308 | } | |
309 | msleep(1); | |
310 | } | |
fdd07fe6 PW |
311 | |
312 | /* SYSC register is cleared by the reset; rewrite it */ | |
313 | if (dev->rev == OMAP_I2C_REV_ON_2430) { | |
314 | ||
315 | omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, | |
316 | SYSC_AUTOIDLE_MASK); | |
317 | ||
f518b482 | 318 | } else if (dev->rev >= OMAP_I2C_REV_ON_3430_3530) { |
ef871432 RN |
319 | dev->syscstate = SYSC_AUTOIDLE_MASK; |
320 | dev->syscstate |= SYSC_ENAWAKEUP_MASK; | |
321 | dev->syscstate |= (SYSC_IDLEMODE_SMART << | |
fdd07fe6 | 322 | __ffs(SYSC_SIDLEMODE_MASK)); |
ef871432 | 323 | dev->syscstate |= (SYSC_CLOCKACTIVITY_FCLK << |
fdd07fe6 PW |
324 | __ffs(SYSC_CLOCKACTIVITY_MASK)); |
325 | ||
ef871432 RN |
326 | omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, |
327 | dev->syscstate); | |
5043e9e7 KJ |
328 | /* |
329 | * Enabling all wakup sources to stop I2C freezing on | |
330 | * WFI instruction. | |
331 | * REVISIT: Some wkup sources might not be needed. | |
332 | */ | |
ef871432 | 333 | dev->westate = OMAP_I2C_WE_ALL; |
cb28e582 S |
334 | omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, |
335 | dev->westate); | |
fdd07fe6 | 336 | } |
010d442c KS |
337 | } |
338 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); | |
339 | ||
6145197b | 340 | if (dev->flags & OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK) { |
0e9ae109 RK |
341 | /* |
342 | * The I2C functional clock is the armxor_ck, so there's | |
343 | * no need to get "armxor_ck" separately. Now, if OMAP2420 | |
344 | * always returns 12MHz for the functional clock, we can | |
345 | * do this bit unconditionally. | |
346 | */ | |
27b1fec2 RN |
347 | fclk = clk_get(dev->dev, "fck"); |
348 | fclk_rate = clk_get_rate(fclk); | |
349 | clk_put(fclk); | |
0e9ae109 | 350 | |
010d442c KS |
351 | /* TRM for 5912 says the I2C clock must be prescaled to be |
352 | * between 7 - 12 MHz. The XOR input clock is typically | |
353 | * 12, 13 or 19.2 MHz. So we should have code that produces: | |
354 | * | |
355 | * XOR MHz Divider Prescaler | |
356 | * 12 1 0 | |
357 | * 13 2 1 | |
358 | * 19.2 2 1 | |
359 | */ | |
d7aef138 JD |
360 | if (fclk_rate > 12000000) |
361 | psc = fclk_rate / 12000000; | |
010d442c KS |
362 | } |
363 | ||
6145197b | 364 | if (!(dev->flags & OMAP_I2C_FLAG_SIMPLE_CLOCK)) { |
4574eb68 | 365 | |
84bf2c86 AK |
366 | /* |
367 | * HSI2C controller internal clk rate should be 19.2 Mhz for | |
368 | * HS and for all modes on 2430. On 34xx we can use lower rate | |
369 | * to get longer filter period for better noise suppression. | |
370 | * The filter is iclk (fclk for HS) period. | |
371 | */ | |
3be0053e | 372 | if (dev->speed > 400 || |
6145197b | 373 | dev->flags & OMAP_I2C_FLAG_FORCE_19200_INT_CLK) |
84bf2c86 AK |
374 | internal_clk = 19200; |
375 | else if (dev->speed > 100) | |
376 | internal_clk = 9600; | |
377 | else | |
378 | internal_clk = 4000; | |
27b1fec2 RN |
379 | fclk = clk_get(dev->dev, "fck"); |
380 | fclk_rate = clk_get_rate(fclk) / 1000; | |
381 | clk_put(fclk); | |
4574eb68 SMK |
382 | |
383 | /* Compute prescaler divisor */ | |
384 | psc = fclk_rate / internal_clk; | |
385 | psc = psc - 1; | |
386 | ||
387 | /* If configured for High Speed */ | |
388 | if (dev->speed > 400) { | |
baf46b4e AK |
389 | unsigned long scl; |
390 | ||
4574eb68 | 391 | /* For first phase of HS mode */ |
baf46b4e AK |
392 | scl = internal_clk / 400; |
393 | fsscll = scl - (scl / 3) - 7; | |
394 | fssclh = (scl / 3) - 5; | |
4574eb68 SMK |
395 | |
396 | /* For second phase of HS mode */ | |
baf46b4e AK |
397 | scl = fclk_rate / dev->speed; |
398 | hsscll = scl - (scl / 3) - 7; | |
399 | hssclh = (scl / 3) - 5; | |
400 | } else if (dev->speed > 100) { | |
401 | unsigned long scl; | |
402 | ||
403 | /* Fast mode */ | |
404 | scl = internal_clk / dev->speed; | |
405 | fsscll = scl - (scl / 3) - 7; | |
406 | fssclh = (scl / 3) - 5; | |
4574eb68 | 407 | } else { |
baf46b4e AK |
408 | /* Standard mode */ |
409 | fsscll = internal_clk / (dev->speed * 2) - 7; | |
410 | fssclh = internal_clk / (dev->speed * 2) - 5; | |
4574eb68 SMK |
411 | } |
412 | scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll; | |
413 | sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh; | |
414 | } else { | |
415 | /* Program desired operating rate */ | |
416 | fclk_rate /= (psc + 1) * 1000; | |
417 | if (psc > 2) | |
418 | psc = 2; | |
419 | scll = fclk_rate / (dev->speed * 2) - 7 + psc; | |
420 | sclh = fclk_rate / (dev->speed * 2) - 7 + psc; | |
421 | } | |
422 | ||
010d442c KS |
423 | /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */ |
424 | omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc); | |
425 | ||
4574eb68 SMK |
426 | /* SCL low and high time values */ |
427 | omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll); | |
428 | omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh); | |
010d442c KS |
429 | |
430 | /* Take the I2C module out of reset: */ | |
431 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN); | |
432 | ||
433 | /* Enable interrupts */ | |
ef871432 | 434 | dev->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY | |
c1a473bd TL |
435 | OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK | |
436 | OMAP_I2C_IE_AL) | ((dev->fifo_size) ? | |
ef871432 RN |
437 | (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0); |
438 | omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate); | |
6145197b | 439 | if (dev->flags & OMAP_I2C_FLAG_RESET_REGS_POSTIDLE) { |
ef871432 RN |
440 | dev->pscstate = psc; |
441 | dev->scllstate = scll; | |
442 | dev->sclhstate = sclh; | |
443 | dev->bufstate = buf; | |
444 | } | |
010d442c KS |
445 | return 0; |
446 | } | |
447 | ||
448 | /* | |
449 | * Waiting on Bus Busy | |
450 | */ | |
451 | static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev) | |
452 | { | |
453 | unsigned long timeout; | |
454 | ||
455 | timeout = jiffies + OMAP_I2C_TIMEOUT; | |
456 | while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) { | |
457 | if (time_after(jiffies, timeout)) { | |
458 | dev_warn(dev->dev, "timeout waiting for bus ready\n"); | |
459 | return -ETIMEDOUT; | |
460 | } | |
461 | msleep(1); | |
462 | } | |
463 | ||
464 | return 0; | |
465 | } | |
466 | ||
dd74548d FB |
467 | static void omap_i2c_resize_fifo(struct omap_i2c_dev *dev, u8 size, bool is_rx) |
468 | { | |
469 | u16 buf; | |
470 | ||
471 | if (dev->flags & OMAP_I2C_FLAG_NO_FIFO) | |
472 | return; | |
473 | ||
474 | /* | |
475 | * Set up notification threshold based on message size. We're doing | |
476 | * this to try and avoid draining feature as much as possible. Whenever | |
477 | * we have big messages to transfer (bigger than our total fifo size) | |
478 | * then we might use draining feature to transfer the remaining bytes. | |
479 | */ | |
480 | ||
481 | dev->threshold = clamp(size, (u8) 1, dev->fifo_size); | |
482 | ||
483 | buf = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG); | |
484 | ||
485 | if (is_rx) { | |
486 | /* Clear RX Threshold */ | |
487 | buf &= ~(0x3f << 8); | |
488 | buf |= ((dev->threshold - 1) << 8) | OMAP_I2C_BUF_RXFIF_CLR; | |
489 | } else { | |
490 | /* Clear TX Threshold */ | |
491 | buf &= ~0x3f; | |
492 | buf |= (dev->threshold - 1) | OMAP_I2C_BUF_TXFIF_CLR; | |
493 | } | |
494 | ||
495 | omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, buf); | |
496 | ||
47dcd016 | 497 | if (dev->rev < OMAP_I2C_REV_ON_3630) |
dd74548d FB |
498 | dev->b_hw = 1; /* Enable hardware fixes */ |
499 | ||
500 | /* calculate wakeup latency constraint for MPU */ | |
49839dc9 PW |
501 | if (dev->set_mpu_wkup_lat != NULL) |
502 | dev->latency = (1000000 * dev->threshold) / | |
503 | (1000 * dev->speed / 8); | |
dd74548d FB |
504 | } |
505 | ||
010d442c KS |
506 | /* |
507 | * Low level master read/write transaction. | |
508 | */ | |
509 | static int omap_i2c_xfer_msg(struct i2c_adapter *adap, | |
510 | struct i2c_msg *msg, int stop) | |
511 | { | |
512 | struct omap_i2c_dev *dev = i2c_get_adapdata(adap); | |
33d54985 | 513 | unsigned long timeout; |
010d442c KS |
514 | u16 w; |
515 | ||
516 | dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n", | |
517 | msg->addr, msg->len, msg->flags, stop); | |
518 | ||
519 | if (msg->len == 0) | |
520 | return -EINVAL; | |
521 | ||
dd74548d FB |
522 | dev->receiver = !!(msg->flags & I2C_M_RD); |
523 | omap_i2c_resize_fifo(dev, msg->len, dev->receiver); | |
524 | ||
010d442c KS |
525 | omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr); |
526 | ||
527 | /* REVISIT: Could the STB bit of I2C_CON be used with probing? */ | |
528 | dev->buf = msg->buf; | |
529 | dev->buf_len = msg->len; | |
530 | ||
d60ece5f FB |
531 | /* make sure writes to dev->buf_len are ordered */ |
532 | barrier(); | |
533 | ||
010d442c KS |
534 | omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len); |
535 | ||
b6ee52c3 NM |
536 | /* Clear the FIFO Buffers */ |
537 | w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG); | |
538 | w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR; | |
539 | omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w); | |
540 | ||
0e33bbb2 | 541 | INIT_COMPLETION(dev->cmd_complete); |
010d442c KS |
542 | dev->cmd_err = 0; |
543 | ||
544 | w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT; | |
4574eb68 SMK |
545 | |
546 | /* High speed configuration */ | |
547 | if (dev->speed > 400) | |
b6ee52c3 | 548 | w |= OMAP_I2C_CON_OPMODE_HS; |
4574eb68 | 549 | |
fb604a3d LP |
550 | if (msg->flags & I2C_M_STOP) |
551 | stop = 1; | |
010d442c KS |
552 | if (msg->flags & I2C_M_TEN) |
553 | w |= OMAP_I2C_CON_XA; | |
554 | if (!(msg->flags & I2C_M_RD)) | |
555 | w |= OMAP_I2C_CON_TRX; | |
c1a473bd | 556 | |
b6ee52c3 | 557 | if (!dev->b_hw && stop) |
010d442c | 558 | w |= OMAP_I2C_CON_STP; |
c1a473bd | 559 | |
010d442c KS |
560 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w); |
561 | ||
b6ee52c3 NM |
562 | /* |
563 | * Don't write stt and stp together on some hardware. | |
564 | */ | |
565 | if (dev->b_hw && stop) { | |
566 | unsigned long delay = jiffies + OMAP_I2C_TIMEOUT; | |
567 | u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG); | |
568 | while (con & OMAP_I2C_CON_STT) { | |
569 | con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG); | |
570 | ||
571 | /* Let the user know if i2c is in a bad state */ | |
572 | if (time_after(jiffies, delay)) { | |
573 | dev_err(dev->dev, "controller timed out " | |
574 | "waiting for start condition to finish\n"); | |
575 | return -ETIMEDOUT; | |
576 | } | |
577 | cpu_relax(); | |
578 | } | |
579 | ||
580 | w |= OMAP_I2C_CON_STP; | |
581 | w &= ~OMAP_I2C_CON_STT; | |
582 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w); | |
583 | } | |
584 | ||
b7af349b JN |
585 | /* |
586 | * REVISIT: We should abort the transfer on signals, but the bus goes | |
587 | * into arbitration and we're currently unable to recover from it. | |
588 | */ | |
33d54985 S |
589 | timeout = wait_for_completion_timeout(&dev->cmd_complete, |
590 | OMAP_I2C_TIMEOUT); | |
33d54985 | 591 | if (timeout == 0) { |
010d442c KS |
592 | dev_err(dev->dev, "controller timed out\n"); |
593 | omap_i2c_init(dev); | |
594 | return -ETIMEDOUT; | |
595 | } | |
596 | ||
597 | if (likely(!dev->cmd_err)) | |
598 | return 0; | |
599 | ||
600 | /* We have an error */ | |
601 | if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR | | |
602 | OMAP_I2C_STAT_XUDF)) { | |
603 | omap_i2c_init(dev); | |
604 | return -EIO; | |
605 | } | |
606 | ||
607 | if (dev->cmd_err & OMAP_I2C_STAT_NACK) { | |
608 | if (msg->flags & I2C_M_IGNORE_NAK) | |
609 | return 0; | |
610 | if (stop) { | |
611 | w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG); | |
612 | w |= OMAP_I2C_CON_STP; | |
613 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w); | |
614 | } | |
615 | return -EREMOTEIO; | |
616 | } | |
617 | return -EIO; | |
618 | } | |
619 | ||
620 | ||
621 | /* | |
622 | * Prepare controller for a transaction and call omap_i2c_xfer_msg | |
623 | * to do the work during IRQ processing. | |
624 | */ | |
625 | static int | |
626 | omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) | |
627 | { | |
628 | struct omap_i2c_dev *dev = i2c_get_adapdata(adap); | |
629 | int i; | |
630 | int r; | |
631 | ||
3b0fb97c S |
632 | r = pm_runtime_get_sync(dev->dev); |
633 | if (IS_ERR_VALUE(r)) | |
33ec5e81 | 634 | goto out; |
010d442c | 635 | |
c1a473bd TL |
636 | r = omap_i2c_wait_for_bb(dev); |
637 | if (r < 0) | |
010d442c KS |
638 | goto out; |
639 | ||
49839dc9 PW |
640 | if (dev->set_mpu_wkup_lat != NULL) |
641 | dev->set_mpu_wkup_lat(dev->dev, dev->latency); | |
6a91b558 | 642 | |
010d442c KS |
643 | for (i = 0; i < num; i++) { |
644 | r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1))); | |
645 | if (r != 0) | |
646 | break; | |
647 | } | |
648 | ||
49839dc9 PW |
649 | if (dev->set_mpu_wkup_lat != NULL) |
650 | dev->set_mpu_wkup_lat(dev->dev, -1); | |
6a91b558 | 651 | |
010d442c KS |
652 | if (r == 0) |
653 | r = num; | |
5c64eb26 MN |
654 | |
655 | omap_i2c_wait_for_bb(dev); | |
010d442c | 656 | out: |
6d8451d5 FB |
657 | pm_runtime_mark_last_busy(dev->dev); |
658 | pm_runtime_put_autosuspend(dev->dev); | |
010d442c KS |
659 | return r; |
660 | } | |
661 | ||
662 | static u32 | |
663 | omap_i2c_func(struct i2c_adapter *adap) | |
664 | { | |
fb604a3d LP |
665 | return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) | |
666 | I2C_FUNC_PROTOCOL_MANGLING; | |
010d442c KS |
667 | } |
668 | ||
669 | static inline void | |
670 | omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err) | |
671 | { | |
672 | dev->cmd_err |= err; | |
673 | complete(&dev->cmd_complete); | |
674 | } | |
675 | ||
676 | static inline void | |
677 | omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat) | |
678 | { | |
679 | omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat); | |
680 | } | |
681 | ||
f3083d92 | 682 | static inline void i2c_omap_errata_i207(struct omap_i2c_dev *dev, u16 stat) |
683 | { | |
684 | /* | |
685 | * I2C Errata(Errata Nos. OMAP2: 1.67, OMAP3: 1.8) | |
686 | * Not applicable for OMAP4. | |
687 | * Under certain rare conditions, RDR could be set again | |
688 | * when the bus is busy, then ignore the interrupt and | |
689 | * clear the interrupt. | |
690 | */ | |
691 | if (stat & OMAP_I2C_STAT_RDR) { | |
692 | /* Step 1: If RDR is set, clear it */ | |
693 | omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR); | |
694 | ||
695 | /* Step 2: */ | |
696 | if (!(omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) | |
697 | & OMAP_I2C_STAT_BB)) { | |
698 | ||
699 | /* Step 3: */ | |
700 | if (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) | |
701 | & OMAP_I2C_STAT_RDR) { | |
702 | omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR); | |
703 | dev_dbg(dev->dev, "RDR when bus is busy.\n"); | |
704 | } | |
705 | ||
706 | } | |
707 | } | |
708 | } | |
709 | ||
43469d8e PW |
710 | /* rev1 devices are apparently only on some 15xx */ |
711 | #ifdef CONFIG_ARCH_OMAP15XX | |
712 | ||
010d442c | 713 | static irqreturn_t |
4e80f727 | 714 | omap_i2c_omap1_isr(int this_irq, void *dev_id) |
010d442c KS |
715 | { |
716 | struct omap_i2c_dev *dev = dev_id; | |
717 | u16 iv, w; | |
718 | ||
fab67afb | 719 | if (pm_runtime_suspended(dev->dev)) |
f08ac4e7 TL |
720 | return IRQ_NONE; |
721 | ||
010d442c KS |
722 | iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); |
723 | switch (iv) { | |
724 | case 0x00: /* None */ | |
725 | break; | |
726 | case 0x01: /* Arbitration lost */ | |
727 | dev_err(dev->dev, "Arbitration lost\n"); | |
728 | omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL); | |
729 | break; | |
730 | case 0x02: /* No acknowledgement */ | |
731 | omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK); | |
732 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP); | |
733 | break; | |
734 | case 0x03: /* Register access ready */ | |
735 | omap_i2c_complete_cmd(dev, 0); | |
736 | break; | |
737 | case 0x04: /* Receive data ready */ | |
738 | if (dev->buf_len) { | |
739 | w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG); | |
740 | *dev->buf++ = w; | |
741 | dev->buf_len--; | |
742 | if (dev->buf_len) { | |
743 | *dev->buf++ = w >> 8; | |
744 | dev->buf_len--; | |
745 | } | |
746 | } else | |
747 | dev_err(dev->dev, "RRDY IRQ while no data requested\n"); | |
748 | break; | |
749 | case 0x05: /* Transmit data ready */ | |
750 | if (dev->buf_len) { | |
751 | w = *dev->buf++; | |
752 | dev->buf_len--; | |
753 | if (dev->buf_len) { | |
754 | w |= *dev->buf++ << 8; | |
755 | dev->buf_len--; | |
756 | } | |
757 | omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w); | |
758 | } else | |
759 | dev_err(dev->dev, "XRDY IRQ while no data to send\n"); | |
760 | break; | |
761 | default: | |
762 | return IRQ_NONE; | |
763 | } | |
764 | ||
765 | return IRQ_HANDLED; | |
766 | } | |
43469d8e | 767 | #else |
4e80f727 | 768 | #define omap_i2c_omap1_isr NULL |
43469d8e | 769 | #endif |
010d442c | 770 | |
2dd151ab | 771 | /* |
c8db38f0 | 772 | * OMAP3430 Errata i462: When an XRDY/XDR is hit, wait for XUDF before writing |
2dd151ab AS |
773 | * data to DATA_REG. Otherwise some data bytes can be lost while transferring |
774 | * them from the memory to the I2C interface. | |
775 | */ | |
4151e741 | 776 | static int errata_omap3_i462(struct omap_i2c_dev *dev) |
2dd151ab | 777 | { |
e9f59b9c | 778 | unsigned long timeout = 10000; |
4151e741 | 779 | u16 stat; |
e9f59b9c | 780 | |
4151e741 FB |
781 | do { |
782 | stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG); | |
783 | if (stat & OMAP_I2C_STAT_XUDF) | |
784 | break; | |
785 | ||
786 | if (stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) { | |
540a4790 | 787 | omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_XRDY | |
2dd151ab | 788 | OMAP_I2C_STAT_XDR)); |
b07be0f3 FB |
789 | if (stat & OMAP_I2C_STAT_NACK) { |
790 | dev->cmd_err |= OMAP_I2C_STAT_NACK; | |
791 | omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK); | |
792 | } | |
793 | ||
794 | if (stat & OMAP_I2C_STAT_AL) { | |
795 | dev_err(dev->dev, "Arbitration lost\n"); | |
796 | dev->cmd_err |= OMAP_I2C_STAT_AL; | |
797 | omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK); | |
798 | } | |
799 | ||
4151e741 | 800 | return -EIO; |
2dd151ab | 801 | } |
e9f59b9c | 802 | |
2dd151ab | 803 | cpu_relax(); |
4151e741 | 804 | } while (--timeout); |
2dd151ab | 805 | |
e9f59b9c AS |
806 | if (!timeout) { |
807 | dev_err(dev->dev, "timeout waiting on XUDF bit\n"); | |
808 | return 0; | |
809 | } | |
810 | ||
2dd151ab AS |
811 | return 0; |
812 | } | |
813 | ||
3312d25e FB |
814 | static void omap_i2c_receive_data(struct omap_i2c_dev *dev, u8 num_bytes, |
815 | bool is_rdr) | |
816 | { | |
817 | u16 w; | |
818 | ||
819 | while (num_bytes--) { | |
3312d25e FB |
820 | w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG); |
821 | *dev->buf++ = w; | |
822 | dev->buf_len--; | |
823 | ||
824 | /* | |
825 | * Data reg in 2430, omap3 and | |
826 | * omap4 is 8 bit wide | |
827 | */ | |
828 | if (dev->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) { | |
dd74548d FB |
829 | *dev->buf++ = w >> 8; |
830 | dev->buf_len--; | |
3312d25e FB |
831 | } |
832 | } | |
833 | } | |
834 | ||
835 | static int omap_i2c_transmit_data(struct omap_i2c_dev *dev, u8 num_bytes, | |
836 | bool is_xdr) | |
837 | { | |
838 | u16 w; | |
839 | ||
840 | while (num_bytes--) { | |
3312d25e FB |
841 | w = *dev->buf++; |
842 | dev->buf_len--; | |
843 | ||
844 | /* | |
845 | * Data reg in 2430, omap3 and | |
846 | * omap4 is 8 bit wide | |
847 | */ | |
848 | if (dev->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) { | |
dd74548d FB |
849 | w |= *dev->buf++ << 8; |
850 | dev->buf_len--; | |
3312d25e FB |
851 | } |
852 | ||
853 | if (dev->errata & I2C_OMAP_ERRATA_I462) { | |
854 | int ret; | |
855 | ||
856 | ret = errata_omap3_i462(dev); | |
857 | if (ret < 0) | |
858 | return ret; | |
859 | } | |
860 | ||
861 | omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w); | |
862 | } | |
863 | ||
864 | return 0; | |
865 | } | |
866 | ||
010d442c | 867 | static irqreturn_t |
3b2f8f82 | 868 | omap_i2c_isr(int irq, void *dev_id) |
010d442c KS |
869 | { |
870 | struct omap_i2c_dev *dev = dev_id; | |
3b2f8f82 FB |
871 | irqreturn_t ret = IRQ_HANDLED; |
872 | u16 mask; | |
873 | u16 stat; | |
874 | ||
875 | spin_lock(&dev->lock); | |
876 | mask = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG); | |
877 | stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG); | |
878 | ||
879 | if (stat & mask) | |
880 | ret = IRQ_WAKE_THREAD; | |
881 | ||
882 | spin_unlock(&dev->lock); | |
883 | ||
884 | return ret; | |
885 | } | |
886 | ||
010d442c | 887 | static irqreturn_t |
3b2f8f82 | 888 | omap_i2c_isr_thread(int this_irq, void *dev_id) |
010d442c KS |
889 | { |
890 | struct omap_i2c_dev *dev = dev_id; | |
3b2f8f82 | 891 | unsigned long flags; |
010d442c | 892 | u16 bits; |
3312d25e | 893 | u16 stat; |
66b92988 | 894 | int err = 0, count = 0; |
010d442c | 895 | |
3b2f8f82 | 896 | spin_lock_irqsave(&dev->lock, flags); |
66b92988 FB |
897 | do { |
898 | bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG); | |
899 | stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG); | |
900 | stat &= bits; | |
901 | ||
079d8af2 FB |
902 | /* If we're in receiver mode, ignore XDR/XRDY */ |
903 | if (dev->receiver) | |
904 | stat &= ~(OMAP_I2C_STAT_XDR | OMAP_I2C_STAT_XRDY); | |
905 | else | |
906 | stat &= ~(OMAP_I2C_STAT_RDR | OMAP_I2C_STAT_RRDY); | |
010d442c | 907 | |
66b92988 FB |
908 | if (!stat) { |
909 | /* my work here is done */ | |
0bdfe0cb | 910 | goto out; |
66b92988 | 911 | } |
f08ac4e7 | 912 | |
010d442c KS |
913 | dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat); |
914 | if (count++ == 100) { | |
915 | dev_warn(dev->dev, "Too much work in one IRQ\n"); | |
916 | break; | |
917 | } | |
918 | ||
1d7afc95 | 919 | if (stat & OMAP_I2C_STAT_NACK) { |
b6ee52c3 | 920 | err |= OMAP_I2C_STAT_NACK; |
1d7afc95 | 921 | omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK); |
0bdfe0cb | 922 | break; |
1d7afc95 | 923 | } |
78e1cf42 | 924 | |
b6ee52c3 NM |
925 | if (stat & OMAP_I2C_STAT_AL) { |
926 | dev_err(dev->dev, "Arbitration lost\n"); | |
927 | err |= OMAP_I2C_STAT_AL; | |
1d7afc95 | 928 | omap_i2c_ack_stat(dev, OMAP_I2C_STAT_AL); |
0bdfe0cb | 929 | break; |
b6ee52c3 | 930 | } |
c55edb99 | 931 | |
a5a595cc | 932 | /* |
cb527ede | 933 | * ProDB0017052: Clear ARDY bit twice |
a5a595cc | 934 | */ |
b6ee52c3 | 935 | if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK | |
04c688dd | 936 | OMAP_I2C_STAT_AL)) { |
540a4790 FB |
937 | omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_RRDY | |
938 | OMAP_I2C_STAT_RDR | | |
939 | OMAP_I2C_STAT_XRDY | | |
940 | OMAP_I2C_STAT_XDR | | |
941 | OMAP_I2C_STAT_ARDY)); | |
0bdfe0cb | 942 | break; |
04c688dd | 943 | } |
c55edb99 | 944 | |
6d9939f6 | 945 | if (stat & OMAP_I2C_STAT_RDR) { |
b6ee52c3 | 946 | u8 num_bytes = 1; |
f3083d92 | 947 | |
6d9939f6 FB |
948 | if (dev->fifo_size) |
949 | num_bytes = dev->buf_len; | |
950 | ||
3312d25e | 951 | omap_i2c_receive_data(dev, num_bytes, true); |
6d9939f6 | 952 | |
f3083d92 | 953 | if (dev->errata & I2C_OMAP_ERRATA_I207) |
954 | i2c_omap_errata_i207(dev, stat); | |
955 | ||
6d9939f6 | 956 | omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR); |
0bdfe0cb | 957 | break; |
6d9939f6 FB |
958 | } |
959 | ||
960 | if (stat & OMAP_I2C_STAT_RRDY) { | |
961 | u8 num_bytes = 1; | |
962 | ||
dd74548d FB |
963 | if (dev->threshold) |
964 | num_bytes = dev->threshold; | |
6d9939f6 | 965 | |
3312d25e | 966 | omap_i2c_receive_data(dev, num_bytes, false); |
6d9939f6 | 967 | omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RRDY); |
010d442c KS |
968 | continue; |
969 | } | |
c55edb99 | 970 | |
6d9939f6 | 971 | if (stat & OMAP_I2C_STAT_XDR) { |
b6ee52c3 | 972 | u8 num_bytes = 1; |
3312d25e | 973 | int ret; |
6d9939f6 FB |
974 | |
975 | if (dev->fifo_size) | |
976 | num_bytes = dev->buf_len; | |
977 | ||
3312d25e | 978 | ret = omap_i2c_transmit_data(dev, num_bytes, true); |
3312d25e | 979 | if (ret < 0) |
0bdfe0cb | 980 | break; |
6d9939f6 FB |
981 | |
982 | omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XDR); | |
0bdfe0cb | 983 | break; |
6d9939f6 FB |
984 | } |
985 | ||
986 | if (stat & OMAP_I2C_STAT_XRDY) { | |
987 | u8 num_bytes = 1; | |
3312d25e | 988 | int ret; |
6d9939f6 | 989 | |
dd74548d FB |
990 | if (dev->threshold) |
991 | num_bytes = dev->threshold; | |
6d9939f6 | 992 | |
3312d25e | 993 | ret = omap_i2c_transmit_data(dev, num_bytes, false); |
3312d25e | 994 | if (ret < 0) |
0bdfe0cb | 995 | break; |
6d9939f6 FB |
996 | |
997 | omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XRDY); | |
010d442c KS |
998 | continue; |
999 | } | |
c55edb99 | 1000 | |
010d442c KS |
1001 | if (stat & OMAP_I2C_STAT_ROVR) { |
1002 | dev_err(dev->dev, "Receive overrun\n"); | |
1d7afc95 FB |
1003 | err |= OMAP_I2C_STAT_ROVR; |
1004 | omap_i2c_ack_stat(dev, OMAP_I2C_STAT_ROVR); | |
0bdfe0cb | 1005 | break; |
010d442c | 1006 | } |
c55edb99 | 1007 | |
010d442c | 1008 | if (stat & OMAP_I2C_STAT_XUDF) { |
b6ee52c3 | 1009 | dev_err(dev->dev, "Transmit underflow\n"); |
1d7afc95 FB |
1010 | err |= OMAP_I2C_STAT_XUDF; |
1011 | omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XUDF); | |
0bdfe0cb | 1012 | break; |
010d442c | 1013 | } |
66b92988 | 1014 | } while (stat); |
010d442c | 1015 | |
4a7ec4ed | 1016 | omap_i2c_complete_cmd(dev, err); |
0bdfe0cb FB |
1017 | |
1018 | out: | |
3b2f8f82 | 1019 | spin_unlock_irqrestore(&dev->lock, flags); |
010d442c | 1020 | |
6a85ced2 | 1021 | return IRQ_HANDLED; |
010d442c KS |
1022 | } |
1023 | ||
8f9082c5 | 1024 | static const struct i2c_algorithm omap_i2c_algo = { |
010d442c KS |
1025 | .master_xfer = omap_i2c_xfer, |
1026 | .functionality = omap_i2c_func, | |
1027 | }; | |
1028 | ||
6145197b BC |
1029 | #ifdef CONFIG_OF |
1030 | static struct omap_i2c_bus_platform_data omap3_pdata = { | |
1031 | .rev = OMAP_I2C_IP_VERSION_1, | |
1032 | .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | | |
1033 | OMAP_I2C_FLAG_RESET_REGS_POSTIDLE | | |
1034 | OMAP_I2C_FLAG_BUS_SHIFT_2, | |
1035 | }; | |
1036 | ||
1037 | static struct omap_i2c_bus_platform_data omap4_pdata = { | |
1038 | .rev = OMAP_I2C_IP_VERSION_2, | |
1039 | }; | |
1040 | ||
1041 | static const struct of_device_id omap_i2c_of_match[] = { | |
1042 | { | |
1043 | .compatible = "ti,omap4-i2c", | |
1044 | .data = &omap4_pdata, | |
1045 | }, | |
1046 | { | |
1047 | .compatible = "ti,omap3-i2c", | |
1048 | .data = &omap3_pdata, | |
1049 | }, | |
1050 | { }, | |
1051 | }; | |
1052 | MODULE_DEVICE_TABLE(of, omap_i2c_of_match); | |
1053 | #endif | |
1054 | ||
47dcd016 S |
1055 | #define OMAP_I2C_SCHEME(rev) ((rev & 0xc000) >> 14) |
1056 | ||
1057 | #define OMAP_I2C_REV_SCHEME_0_MAJOR(rev) (rev >> 4) | |
1058 | #define OMAP_I2C_REV_SCHEME_0_MINOR(rev) (rev & 0xf) | |
1059 | ||
1060 | #define OMAP_I2C_REV_SCHEME_1_MAJOR(rev) ((rev & 0x0700) >> 7) | |
1061 | #define OMAP_I2C_REV_SCHEME_1_MINOR(rev) (rev & 0x1f) | |
1062 | #define OMAP_I2C_SCHEME_0 0 | |
1063 | #define OMAP_I2C_SCHEME_1 1 | |
1064 | ||
1139aea9 | 1065 | static int __devinit |
010d442c KS |
1066 | omap_i2c_probe(struct platform_device *pdev) |
1067 | { | |
1068 | struct omap_i2c_dev *dev; | |
1069 | struct i2c_adapter *adap; | |
ac79e4b2 | 1070 | struct resource *mem; |
c4dba011 UKK |
1071 | const struct omap_i2c_bus_platform_data *pdata = |
1072 | pdev->dev.platform_data; | |
6145197b BC |
1073 | struct device_node *node = pdev->dev.of_node; |
1074 | const struct of_device_id *match; | |
ac79e4b2 | 1075 | int irq; |
010d442c | 1076 | int r; |
47dcd016 S |
1077 | u32 rev; |
1078 | u16 minor, major; | |
010d442c KS |
1079 | |
1080 | /* NOTE: driver uses the static register mapping */ | |
1081 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1082 | if (!mem) { | |
1083 | dev_err(&pdev->dev, "no mem resource?\n"); | |
1084 | return -ENODEV; | |
1085 | } | |
ac79e4b2 FB |
1086 | |
1087 | irq = platform_get_irq(pdev, 0); | |
1088 | if (irq < 0) { | |
010d442c | 1089 | dev_err(&pdev->dev, "no irq resource?\n"); |
ac79e4b2 | 1090 | return irq; |
010d442c KS |
1091 | } |
1092 | ||
d9ebd04d FB |
1093 | dev = devm_kzalloc(&pdev->dev, sizeof(struct omap_i2c_dev), GFP_KERNEL); |
1094 | if (!dev) { | |
1095 | dev_err(&pdev->dev, "Menory allocation failed\n"); | |
1096 | return -ENOMEM; | |
010d442c KS |
1097 | } |
1098 | ||
d9ebd04d FB |
1099 | dev->base = devm_request_and_ioremap(&pdev->dev, mem); |
1100 | if (!dev->base) { | |
1101 | dev_err(&pdev->dev, "I2C region already claimed\n"); | |
1102 | return -ENOMEM; | |
010d442c KS |
1103 | } |
1104 | ||
6c5aa407 | 1105 | match = of_match_device(of_match_ptr(omap_i2c_of_match), &pdev->dev); |
6145197b BC |
1106 | if (match) { |
1107 | u32 freq = 100000; /* default to 100000 Hz */ | |
1108 | ||
1109 | pdata = match->data; | |
1110 | dev->dtrev = pdata->rev; | |
1111 | dev->flags = pdata->flags; | |
1112 | ||
1113 | of_property_read_u32(node, "clock-frequency", &freq); | |
1114 | /* convert DT freq value in Hz into kHz for speed */ | |
1115 | dev->speed = freq / 1000; | |
1116 | } else if (pdata != NULL) { | |
1117 | dev->speed = pdata->clkrate; | |
1118 | dev->flags = pdata->flags; | |
49839dc9 | 1119 | dev->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat; |
6145197b | 1120 | dev->dtrev = pdata->rev; |
20c9d2c4 | 1121 | } |
4574eb68 | 1122 | |
2d4b4520 SG |
1123 | dev->pins = devm_pinctrl_get_select_default(&pdev->dev); |
1124 | if (IS_ERR(dev->pins)) { | |
1125 | if (PTR_ERR(dev->pins) == -EPROBE_DEFER) | |
1126 | return -EPROBE_DEFER; | |
1127 | ||
1128 | dev_warn(&pdev->dev, "did not get pins for i2c error: %li\n", | |
1129 | PTR_ERR(dev->pins)); | |
1130 | dev->pins = NULL; | |
1131 | } | |
1132 | ||
010d442c | 1133 | dev->dev = &pdev->dev; |
ac79e4b2 | 1134 | dev->irq = irq; |
55c381e4 | 1135 | |
3b2f8f82 | 1136 | spin_lock_init(&dev->lock); |
55c381e4 | 1137 | |
010d442c | 1138 | platform_set_drvdata(pdev, dev); |
0e33bbb2 | 1139 | init_completion(&dev->cmd_complete); |
010d442c | 1140 | |
6145197b | 1141 | dev->reg_shift = (dev->flags >> OMAP_I2C_FLAG_BUS_SHIFT__SHIFT) & 3; |
7c6bd201 | 1142 | |
7f4b08ee | 1143 | pm_runtime_enable(dev->dev); |
6d8451d5 FB |
1144 | pm_runtime_set_autosuspend_delay(dev->dev, OMAP_I2C_PM_TIMEOUT); |
1145 | pm_runtime_use_autosuspend(dev->dev); | |
1146 | ||
3b0fb97c S |
1147 | r = pm_runtime_get_sync(dev->dev); |
1148 | if (IS_ERR_VALUE(r)) | |
1149 | goto err_free_mem; | |
010d442c | 1150 | |
47dcd016 S |
1151 | /* |
1152 | * Read the Rev hi bit-[15:14] ie scheme this is 1 indicates ver2. | |
1153 | * On omap1/3/2 Offset 4 is IE Reg the bit [15:14] is 0 at reset. | |
1154 | * Also since the omap_i2c_read_reg uses reg_map_ip_* a | |
1155 | * raw_readw is done. | |
1156 | */ | |
1157 | rev = __raw_readw(dev->base + 0x04); | |
1158 | ||
1159 | switch (OMAP_I2C_SCHEME(rev)) { | |
1160 | case OMAP_I2C_SCHEME_0: | |
1161 | dev->regs = (u8 *)reg_map_ip_v1; | |
1162 | dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG); | |
1163 | minor = OMAP_I2C_REV_SCHEME_0_MAJOR(dev->rev); | |
1164 | major = OMAP_I2C_REV_SCHEME_0_MAJOR(dev->rev); | |
1165 | break; | |
1166 | case OMAP_I2C_SCHEME_1: | |
1167 | /* FALLTHROUGH */ | |
1168 | default: | |
1169 | dev->regs = (u8 *)reg_map_ip_v2; | |
1170 | rev = (rev << 16) | | |
1171 | omap_i2c_read_reg(dev, OMAP_I2C_IP_V2_REVNB_LO); | |
1172 | minor = OMAP_I2C_REV_SCHEME_1_MINOR(rev); | |
1173 | major = OMAP_I2C_REV_SCHEME_1_MAJOR(rev); | |
1174 | dev->rev = rev; | |
1175 | } | |
010d442c | 1176 | |
9aa8ec67 TK |
1177 | dev->errata = 0; |
1178 | ||
a748021c S |
1179 | if (dev->rev >= OMAP_I2C_REV_ON_2430 && |
1180 | dev->rev < OMAP_I2C_REV_ON_4430_PLUS) | |
9aa8ec67 TK |
1181 | dev->errata |= I2C_OMAP_ERRATA_I207; |
1182 | ||
f518b482 | 1183 | if (dev->rev <= OMAP_I2C_REV_ON_3430_3530) |
c8db38f0 | 1184 | dev->errata |= I2C_OMAP_ERRATA_I462; |
8a9d97d3 | 1185 | |
6145197b | 1186 | if (!(dev->flags & OMAP_I2C_FLAG_NO_FIFO)) { |
b6ee52c3 NM |
1187 | u16 s; |
1188 | ||
1189 | /* Set up the fifo size - Get total size */ | |
1190 | s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3; | |
1191 | dev->fifo_size = 0x8 << s; | |
1192 | ||
1193 | /* | |
1194 | * Set up notification threshold as half the total available | |
1195 | * size. This is to ensure that we can handle the status on int | |
1196 | * call back latencies. | |
1197 | */ | |
1d5a34fe S |
1198 | |
1199 | dev->fifo_size = (dev->fifo_size / 2); | |
1200 | ||
47dcd016 | 1201 | if (dev->rev < OMAP_I2C_REV_ON_3630) |
f38e66e0 | 1202 | dev->b_hw = 1; /* Enable hardware fixes */ |
1d5a34fe | 1203 | |
20c9d2c4 | 1204 | /* calculate wakeup latency constraint for MPU */ |
49839dc9 PW |
1205 | if (dev->set_mpu_wkup_lat != NULL) |
1206 | dev->latency = (1000000 * dev->fifo_size) / | |
1207 | (1000 * dev->speed / 8); | |
b6ee52c3 NM |
1208 | } |
1209 | ||
010d442c KS |
1210 | /* reset ASAP, clearing any IRQs */ |
1211 | omap_i2c_init(dev); | |
1212 | ||
3b2f8f82 FB |
1213 | if (dev->rev < OMAP_I2C_OMAP1_REV_2) |
1214 | r = devm_request_irq(&pdev->dev, dev->irq, omap_i2c_omap1_isr, | |
1215 | IRQF_NO_SUSPEND, pdev->name, dev); | |
1216 | else | |
1217 | r = devm_request_threaded_irq(&pdev->dev, dev->irq, | |
1218 | omap_i2c_isr, omap_i2c_isr_thread, | |
1219 | IRQF_NO_SUSPEND | IRQF_ONESHOT, | |
1220 | pdev->name, dev); | |
010d442c KS |
1221 | |
1222 | if (r) { | |
1223 | dev_err(dev->dev, "failure requesting irq %i\n", dev->irq); | |
1224 | goto err_unuse_clocks; | |
1225 | } | |
9c76b878 | 1226 | |
010d442c KS |
1227 | adap = &dev->adapter; |
1228 | i2c_set_adapdata(adap, dev); | |
1229 | adap->owner = THIS_MODULE; | |
1230 | adap->class = I2C_CLASS_HWMON; | |
783fd6fa | 1231 | strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name)); |
010d442c KS |
1232 | adap->algo = &omap_i2c_algo; |
1233 | adap->dev.parent = &pdev->dev; | |
6145197b | 1234 | adap->dev.of_node = pdev->dev.of_node; |
010d442c KS |
1235 | |
1236 | /* i2c device drivers may be active on return from add_adapter() */ | |
7c175499 DB |
1237 | adap->nr = pdev->id; |
1238 | r = i2c_add_numbered_adapter(adap); | |
010d442c KS |
1239 | if (r) { |
1240 | dev_err(dev->dev, "failure adding adapter\n"); | |
d9ebd04d | 1241 | goto err_unuse_clocks; |
010d442c KS |
1242 | } |
1243 | ||
c5d3cd6d | 1244 | dev_info(dev->dev, "bus %d rev%d.%d.%d at %d kHz\n", adap->nr, |
47dcd016 | 1245 | dev->dtrev, major, minor, dev->speed); |
c5d3cd6d | 1246 | |
6145197b BC |
1247 | of_i2c_register_devices(adap); |
1248 | ||
6d8451d5 FB |
1249 | pm_runtime_mark_last_busy(dev->dev); |
1250 | pm_runtime_put_autosuspend(dev->dev); | |
62ff2c2b | 1251 | |
010d442c KS |
1252 | return 0; |
1253 | ||
010d442c | 1254 | err_unuse_clocks: |
3e39752d | 1255 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); |
fab67afb | 1256 | pm_runtime_put(dev->dev); |
24740516 | 1257 | pm_runtime_disable(&pdev->dev); |
010d442c KS |
1258 | err_free_mem: |
1259 | platform_set_drvdata(pdev, NULL); | |
010d442c KS |
1260 | |
1261 | return r; | |
1262 | } | |
1263 | ||
d790aea7 | 1264 | static int __devexit omap_i2c_remove(struct platform_device *pdev) |
010d442c KS |
1265 | { |
1266 | struct omap_i2c_dev *dev = platform_get_drvdata(pdev); | |
3b0fb97c | 1267 | int ret; |
010d442c KS |
1268 | |
1269 | platform_set_drvdata(pdev, NULL); | |
1270 | ||
010d442c | 1271 | i2c_del_adapter(&dev->adapter); |
3b0fb97c S |
1272 | ret = pm_runtime_get_sync(&pdev->dev); |
1273 | if (IS_ERR_VALUE(ret)) | |
1274 | return ret; | |
1275 | ||
010d442c | 1276 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); |
0861f430 | 1277 | pm_runtime_put(&pdev->dev); |
24740516 | 1278 | pm_runtime_disable(&pdev->dev); |
010d442c KS |
1279 | return 0; |
1280 | } | |
1281 | ||
5692d2a2 | 1282 | #ifdef CONFIG_PM |
fab67afb KH |
1283 | #ifdef CONFIG_PM_RUNTIME |
1284 | static int omap_i2c_runtime_suspend(struct device *dev) | |
1285 | { | |
1286 | struct platform_device *pdev = to_platform_device(dev); | |
1287 | struct omap_i2c_dev *_dev = platform_get_drvdata(pdev); | |
3dae3efb S |
1288 | u16 iv; |
1289 | ||
1290 | _dev->iestate = omap_i2c_read_reg(_dev, OMAP_I2C_IE_REG); | |
bd16c82f S |
1291 | |
1292 | omap_i2c_write_reg(_dev, OMAP_I2C_IE_REG, 0); | |
fab67afb | 1293 | |
3dae3efb S |
1294 | if (_dev->rev < OMAP_I2C_OMAP1_REV_2) { |
1295 | iv = omap_i2c_read_reg(_dev, OMAP_I2C_IV_REG); /* Read clears */ | |
1296 | } else { | |
1297 | omap_i2c_write_reg(_dev, OMAP_I2C_STAT_REG, _dev->iestate); | |
fab67afb | 1298 | |
3dae3efb S |
1299 | /* Flush posted write */ |
1300 | omap_i2c_read_reg(_dev, OMAP_I2C_STAT_REG); | |
1301 | } | |
fab67afb KH |
1302 | |
1303 | return 0; | |
1304 | } | |
1305 | ||
1306 | static int omap_i2c_runtime_resume(struct device *dev) | |
1307 | { | |
1308 | struct platform_device *pdev = to_platform_device(dev); | |
1309 | struct omap_i2c_dev *_dev = platform_get_drvdata(pdev); | |
1310 | ||
47dcd016 S |
1311 | if (!_dev->regs) |
1312 | return 0; | |
1313 | ||
3dae3efb S |
1314 | if (_dev->flags & OMAP_I2C_FLAG_RESET_REGS_POSTIDLE) { |
1315 | omap_i2c_write_reg(_dev, OMAP_I2C_CON_REG, 0); | |
1316 | omap_i2c_write_reg(_dev, OMAP_I2C_PSC_REG, _dev->pscstate); | |
1317 | omap_i2c_write_reg(_dev, OMAP_I2C_SCLL_REG, _dev->scllstate); | |
1318 | omap_i2c_write_reg(_dev, OMAP_I2C_SCLH_REG, _dev->sclhstate); | |
1319 | omap_i2c_write_reg(_dev, OMAP_I2C_BUF_REG, _dev->bufstate); | |
1320 | omap_i2c_write_reg(_dev, OMAP_I2C_SYSC_REG, _dev->syscstate); | |
1321 | omap_i2c_write_reg(_dev, OMAP_I2C_WE_REG, _dev->westate); | |
1322 | omap_i2c_write_reg(_dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN); | |
1323 | } | |
1324 | ||
1325 | /* | |
1326 | * Don't write to this register if the IE state is 0 as it can | |
1327 | * cause deadlock. | |
1328 | */ | |
1329 | if (_dev->iestate) | |
1330 | omap_i2c_write_reg(_dev, OMAP_I2C_IE_REG, _dev->iestate); | |
fab67afb KH |
1331 | |
1332 | return 0; | |
1333 | } | |
5692d2a2 | 1334 | #endif /* CONFIG_PM_RUNTIME */ |
fab67afb KH |
1335 | |
1336 | static struct dev_pm_ops omap_i2c_pm_ops = { | |
5692d2a2 S |
1337 | SET_RUNTIME_PM_OPS(omap_i2c_runtime_suspend, |
1338 | omap_i2c_runtime_resume, NULL) | |
fab67afb KH |
1339 | }; |
1340 | #define OMAP_I2C_PM_OPS (&omap_i2c_pm_ops) | |
1341 | #else | |
1342 | #define OMAP_I2C_PM_OPS NULL | |
5692d2a2 | 1343 | #endif /* CONFIG_PM */ |
fab67afb | 1344 | |
010d442c KS |
1345 | static struct platform_driver omap_i2c_driver = { |
1346 | .probe = omap_i2c_probe, | |
d790aea7 | 1347 | .remove = __devexit_p(omap_i2c_remove), |
010d442c | 1348 | .driver = { |
f7bb0d9a | 1349 | .name = "omap_i2c", |
010d442c | 1350 | .owner = THIS_MODULE, |
fab67afb | 1351 | .pm = OMAP_I2C_PM_OPS, |
6145197b | 1352 | .of_match_table = of_match_ptr(omap_i2c_of_match), |
010d442c KS |
1353 | }, |
1354 | }; | |
1355 | ||
1356 | /* I2C may be needed to bring up other drivers */ | |
1357 | static int __init | |
1358 | omap_i2c_init_driver(void) | |
1359 | { | |
1360 | return platform_driver_register(&omap_i2c_driver); | |
1361 | } | |
1362 | subsys_initcall(omap_i2c_init_driver); | |
1363 | ||
1364 | static void __exit omap_i2c_exit_driver(void) | |
1365 | { | |
1366 | platform_driver_unregister(&omap_i2c_driver); | |
1367 | } | |
1368 | module_exit(omap_i2c_exit_driver); | |
1369 | ||
1370 | MODULE_AUTHOR("MontaVista Software, Inc. (and others)"); | |
1371 | MODULE_DESCRIPTION("TI OMAP I2C bus adapter"); | |
1372 | MODULE_LICENSE("GPL"); | |
f7bb0d9a | 1373 | MODULE_ALIAS("platform:omap_i2c"); |