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I2C: OMAP1: set i2c unit feature implementation flags in platform data
[linux-2.6-block.git] / drivers / i2c / busses / i2c-omap.c
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010d442c
KS		 1/*
2 * TI OMAP I2C master mode driver
3 *
4 * Copyright (C) 2003 MontaVista Software, Inc.
010d442c 5 * Copyright (C) 2005 Nokia Corporation
c1a473bd 6 * Copyright (C) 2004 - 2007 Texas Instruments.
010d442c 7 *
c1a473bd
TL		 8 * Originally written by MontaVista Software, Inc.
9 * Additional contributions by:
10 * Tony Lindgren <tony@atomide.com>
11 * Imre Deak <imre.deak@nokia.com>
12 * Juha Yrjölä <juha.yrjola@solidboot.com>
13 * Syed Khasim <x0khasim@ti.com>
14 * Nishant Menon <nm@ti.com>
010d442c
KS		 15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30
31#include <linux/module.h>
32#include <linux/delay.h>
33#include <linux/i2c.h>
34#include <linux/err.h>
35#include <linux/interrupt.h>
36#include <linux/completion.h>
37#include <linux/platform_device.h>
38#include <linux/clk.h>
c1a473bd 39#include <linux/io.h>
5a0e3ad6 40#include <linux/slab.h>
20c9d2c4 41#include <linux/i2c-omap.h>
27b1fec2 42#include <linux/pm_runtime.h>
010d442c 43
9c76b878 44/* I2C controller revisions */
4e80f727 45#define OMAP_I2C_OMAP1_REV_2 0x20
9c76b878
PW		 46
47/* I2C controller revisions present on specific hardware */
48#define OMAP_I2C_REV_ON_2430 0x36
49#define OMAP_I2C_REV_ON_3430 0x3C
4e80f727 50#define OMAP_I2C_REV_ON_3530_4430 0x40
9c76b878 51
010d442c
KS		 52/* timeout waiting for the controller to respond */
53#define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
54
5043e9e7 55/* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
f38e66e0
SS		 56enum {
57 OMAP_I2C_REV_REG = 0,
58 OMAP_I2C_IE_REG,
59 OMAP_I2C_STAT_REG,
60 OMAP_I2C_IV_REG,
61 OMAP_I2C_WE_REG,
62 OMAP_I2C_SYSS_REG,
63 OMAP_I2C_BUF_REG,
64 OMAP_I2C_CNT_REG,
65 OMAP_I2C_DATA_REG,
66 OMAP_I2C_SYSC_REG,
67 OMAP_I2C_CON_REG,
68 OMAP_I2C_OA_REG,
69 OMAP_I2C_SA_REG,
70 OMAP_I2C_PSC_REG,
71 OMAP_I2C_SCLL_REG,
72 OMAP_I2C_SCLH_REG,
73 OMAP_I2C_SYSTEST_REG,
74 OMAP_I2C_BUFSTAT_REG,
b8853088
AG		 75 /* only on OMAP4430 */
76 OMAP_I2C_IP_V2_REVNB_LO,
77 OMAP_I2C_IP_V2_REVNB_HI,
78 OMAP_I2C_IP_V2_IRQSTATUS_RAW,
79 OMAP_I2C_IP_V2_IRQENABLE_SET,
80 OMAP_I2C_IP_V2_IRQENABLE_CLR,
f38e66e0 81};
010d442c
KS		 82
83/* I2C Interrupt Enable Register (OMAP_I2C_IE): */
b6ee52c3
NM		 84#define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */
85#define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */
010d442c
KS		 86#define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */
87#define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */
88#define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */
89#define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */
90#define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */
91
92/* I2C Status Register (OMAP_I2C_STAT): */
b6ee52c3
NM		 93#define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */
94#define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */
010d442c
KS		 95#define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */
96#define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */
97#define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
98#define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */
99#define OMAP_I2C_STAT_AD0 (1 << 8) /* Address zero */
100#define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
101#define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */
102#define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */
103#define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */
104#define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */
105
5043e9e7
KJ		 106/* I2C WE wakeup enable register */
107#define OMAP_I2C_WE_XDR_WE (1 << 14) /* TX drain wakup */
108#define OMAP_I2C_WE_RDR_WE (1 << 13) /* RX drain wakeup */
109#define OMAP_I2C_WE_AAS_WE (1 << 9) /* Address as slave wakeup*/
110#define OMAP_I2C_WE_BF_WE (1 << 8) /* Bus free wakeup */
111#define OMAP_I2C_WE_STC_WE (1 << 6) /* Start condition wakeup */
112#define OMAP_I2C_WE_GC_WE (1 << 5) /* General call wakeup */
113#define OMAP_I2C_WE_DRDY_WE (1 << 3) /* TX/RX data ready wakeup */
114#define OMAP_I2C_WE_ARDY_WE (1 << 2) /* Reg access ready wakeup */
115#define OMAP_I2C_WE_NACK_WE (1 << 1) /* No acknowledgment wakeup */
116#define OMAP_I2C_WE_AL_WE (1 << 0) /* Arbitration lost wakeup */
117
118#define OMAP_I2C_WE_ALL (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \
119 OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \
120 OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \
121 OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \
122 OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE)
123
010d442c
KS		 124/* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
125#define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */
b6ee52c3 126#define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */
010d442c 127#define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */
b6ee52c3 128#define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */
010d442c
KS		 129
130/* I2C Configuration Register (OMAP_I2C_CON): */
131#define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */
132#define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */
b6ee52c3 133#define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */
010d442c
KS		 134#define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */
135#define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */
136#define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */
137#define OMAP_I2C_CON_XA (1 << 8) /* Expand address */
138#define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */
139#define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */
140#define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */
141
4574eb68
SMK		 142/* I2C SCL time value when Master */
143#define OMAP_I2C_SCLL_HSSCLL 8
144#define OMAP_I2C_SCLH_HSSCLH 8
145
010d442c
KS		 146/* I2C System Test Register (OMAP_I2C_SYSTEST): */
147#ifdef DEBUG
148#define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
149#define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */
150#define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
151#define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
152#define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */
153#define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */
154#define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */
155#define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */
156#endif
157
fdd07fe6
PW		 158/* OCP_SYSSTATUS bit definitions */
159#define SYSS_RESETDONE_MASK (1 << 0)
160
161/* OCP_SYSCONFIG bit definitions */
162#define SYSC_CLOCKACTIVITY_MASK (0x3 << 8)
163#define SYSC_SIDLEMODE_MASK (0x3 << 3)
164#define SYSC_ENAWAKEUP_MASK (1 << 2)
165#define SYSC_SOFTRESET_MASK (1 << 1)
166#define SYSC_AUTOIDLE_MASK (1 << 0)
167
168#define SYSC_IDLEMODE_SMART 0x2
169#define SYSC_CLOCKACTIVITY_FCLK 0x2
010d442c 170
f3083d92 171/* Errata definitions */
172#define I2C_OMAP_ERRATA_I207 (1 << 0)
8a9d97d3 173#define I2C_OMAP3_1P153 (1 << 1)
010d442c 174
010d442c
KS		 175struct omap_i2c_dev {
176 struct device *dev;
177 void __iomem *base; /* virtual */
178 int irq;
d84d3ea3 179 int reg_shift; /* bit shift for I2C register addresses */
010d442c
KS		 180 struct completion cmd_complete;
181 struct resource *ioarea;
20c9d2c4
KJ		 182 u32 latency; /* maximum mpu wkup latency */
183 void (*set_mpu_wkup_lat)(struct device *dev,
184 long latency);
4574eb68 185 u32 speed; /* Speed of bus in Khz */
010d442c
KS		 186 u16 cmd_err;
187 u8 *buf;
f38e66e0 188 u8 *regs;
010d442c
KS		 189 size_t buf_len;
190 struct i2c_adapter adapter;
b6ee52c3
NM		 191 u8 fifo_size; /* use as flag and value
192 * fifo_size==0 implies no fifo
193 * if set, should be trsh+1
194 */
9c76b878 195 u8 rev;
b6ee52c3 196 unsigned b_hw:1; /* bad h/w fixes */
f08ac4e7
TL		 197 unsigned idle:1;
198 u16 iestate; /* Saved interrupt register */
ef871432
RN		 199 u16 pscstate;
200 u16 scllstate;
201 u16 sclhstate;
202 u16 bufstate;
203 u16 syscstate;
204 u16 westate;
f3083d92 205 u16 errata;
010d442c
KS		 206};
207
a1295577 208static const u8 reg_map_ip_v1[] = {
f38e66e0
SS		 209 [OMAP_I2C_REV_REG] = 0x00,
210 [OMAP_I2C_IE_REG] = 0x01,
211 [OMAP_I2C_STAT_REG] = 0x02,
212 [OMAP_I2C_IV_REG] = 0x03,
213 [OMAP_I2C_WE_REG] = 0x03,
214 [OMAP_I2C_SYSS_REG] = 0x04,
215 [OMAP_I2C_BUF_REG] = 0x05,
216 [OMAP_I2C_CNT_REG] = 0x06,
217 [OMAP_I2C_DATA_REG] = 0x07,
218 [OMAP_I2C_SYSC_REG] = 0x08,
219 [OMAP_I2C_CON_REG] = 0x09,
220 [OMAP_I2C_OA_REG] = 0x0a,
221 [OMAP_I2C_SA_REG] = 0x0b,
222 [OMAP_I2C_PSC_REG] = 0x0c,
223 [OMAP_I2C_SCLL_REG] = 0x0d,
224 [OMAP_I2C_SCLH_REG] = 0x0e,
225 [OMAP_I2C_SYSTEST_REG] = 0x0f,
226 [OMAP_I2C_BUFSTAT_REG] = 0x10,
227};
228
a1295577 229static const u8 reg_map_ip_v2[] = {
f38e66e0
SS		 230 [OMAP_I2C_REV_REG] = 0x04,
231 [OMAP_I2C_IE_REG] = 0x2c,
232 [OMAP_I2C_STAT_REG] = 0x28,
233 [OMAP_I2C_IV_REG] = 0x34,
234 [OMAP_I2C_WE_REG] = 0x34,
235 [OMAP_I2C_SYSS_REG] = 0x90,
236 [OMAP_I2C_BUF_REG] = 0x94,
237 [OMAP_I2C_CNT_REG] = 0x98,
238 [OMAP_I2C_DATA_REG] = 0x9c,
239 [OMAP_I2C_SYSC_REG] = 0x20,
240 [OMAP_I2C_CON_REG] = 0xa4,
241 [OMAP_I2C_OA_REG] = 0xa8,
242 [OMAP_I2C_SA_REG] = 0xac,
243 [OMAP_I2C_PSC_REG] = 0xb0,
244 [OMAP_I2C_SCLL_REG] = 0xb4,
245 [OMAP_I2C_SCLH_REG] = 0xb8,
246 [OMAP_I2C_SYSTEST_REG] = 0xbC,
247 [OMAP_I2C_BUFSTAT_REG] = 0xc0,
b8853088
AG		 248 [OMAP_I2C_IP_V2_REVNB_LO] = 0x00,
249 [OMAP_I2C_IP_V2_REVNB_HI] = 0x04,
250 [OMAP_I2C_IP_V2_IRQSTATUS_RAW] = 0x24,
251 [OMAP_I2C_IP_V2_IRQENABLE_SET] = 0x2c,
252 [OMAP_I2C_IP_V2_IRQENABLE_CLR] = 0x30,
f38e66e0
SS		 253};
254
010d442c
KS		 255static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
256 int reg, u16 val)
257{
f38e66e0
SS		 258 __raw_writew(val, i2c_dev->base +
259 (i2c_dev->regs[reg] << i2c_dev->reg_shift));
010d442c
KS		 260}
261
262static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
263{
f38e66e0
SS		 264 return __raw_readw(i2c_dev->base +
265 (i2c_dev->regs[reg] << i2c_dev->reg_shift));
010d442c
KS		 266}
267
27b1fec2 268static void omap_i2c_unidle(struct omap_i2c_dev *dev)
010d442c 269{
27b1fec2
RN		 270 struct platform_device *pdev;
271 struct omap_i2c_bus_platform_data *pdata;
5fe23380 272
27b1fec2 273 WARN_ON(!dev->idle);
010d442c 274
27b1fec2
RN		 275 pdev = to_platform_device(dev->dev);
276 pdata = pdev->dev.platform_data;
010d442c 277
27b1fec2 278 pm_runtime_get_sync(&pdev->dev);
010d442c 279
ef871432
RN		 280 if (cpu_is_omap34xx()) {
281 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
282 omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, dev->pscstate);
283 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, dev->scllstate);
284 omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, dev->sclhstate);
285 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, dev->bufstate);
286 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, dev->syscstate);
287 omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate);
288 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
289 }
0cbbcffd 290 dev->idle = 0;
07ac31f6
CM		 291
292 /*
293 * Don't write to this register if the IE state is 0 as it can
294 * cause deadlock.
295 */
296 if (dev->iestate)
297 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
010d442c
KS		 298}
299
f08ac4e7 300static void omap_i2c_idle(struct omap_i2c_dev *dev)
010d442c 301{
27b1fec2
RN		 302 struct platform_device *pdev;
303 struct omap_i2c_bus_platform_data *pdata;
f08ac4e7
TL		 304 u16 iv;
305
3831f154
PW		 306 WARN_ON(dev->idle);
307
27b1fec2
RN		 308 pdev = to_platform_device(dev->dev);
309 pdata = pdev->dev.platform_data;
310
f08ac4e7 311 dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
6314f09e 312 if (pdata->rev == OMAP_I2C_IP_VERSION_2)
b8853088 313 omap_i2c_write_reg(dev, OMAP_I2C_IP_V2_IRQENABLE_CLR, 1);
f38e66e0
SS		 314 else
315 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0);
316
4e80f727 317 if (dev->rev < OMAP_I2C_OMAP1_REV_2) {
c1a473bd 318 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); /* Read clears */
0cbbcffd 319 } else {
f08ac4e7 320 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, dev->iestate);
0cbbcffd
PW		 321
322 /* Flush posted write before the dev->idle store occurs */
323 omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
324 }
325 dev->idle = 1;
27b1fec2
RN		 326
327 pm_runtime_put_sync(&pdev->dev);
010d442c
KS		 328}
329
330static int omap_i2c_init(struct omap_i2c_dev *dev)
331{
ef871432 332 u16 psc = 0, scll = 0, sclh = 0, buf = 0;
4574eb68 333 u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
010d442c
KS		 334 unsigned long fclk_rate = 12000000;
335 unsigned long timeout;
4574eb68 336 unsigned long internal_clk = 0;
27b1fec2 337 struct clk *fclk;
010d442c 338
4e80f727 339 if (dev->rev >= OMAP_I2C_OMAP1_REV_2) {
57eb81b1
MG		 340 /* Disable I2C controller before soft reset */
341 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
342 omap_i2c_read_reg(dev, OMAP_I2C_CON_REG) &
343 ~(OMAP_I2C_CON_EN));
344
fdd07fe6 345 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK);
010d442c
KS		 346 /* For some reason we need to set the EN bit before the
347 * reset done bit gets set. */
348 timeout = jiffies + OMAP_I2C_TIMEOUT;
349 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
350 while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
fdd07fe6 351 SYSS_RESETDONE_MASK)) {
010d442c 352 if (time_after(jiffies, timeout)) {
fce3ff03 353 dev_warn(dev->dev, "timeout waiting "
010d442c
KS		 354 "for controller reset\n");
355 return -ETIMEDOUT;
356 }
357 msleep(1);
358 }
fdd07fe6
PW		 359
360 /* SYSC register is cleared by the reset; rewrite it */
361 if (dev->rev == OMAP_I2C_REV_ON_2430) {
362
363 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
364 SYSC_AUTOIDLE_MASK);
365
366 } else if (dev->rev >= OMAP_I2C_REV_ON_3430) {
ef871432
RN		 367 dev->syscstate = SYSC_AUTOIDLE_MASK;
368 dev->syscstate |= SYSC_ENAWAKEUP_MASK;
369 dev->syscstate |= (SYSC_IDLEMODE_SMART <<
fdd07fe6 370 __ffs(SYSC_SIDLEMODE_MASK));
ef871432 371 dev->syscstate |= (SYSC_CLOCKACTIVITY_FCLK <<
fdd07fe6
PW		 372 __ffs(SYSC_CLOCKACTIVITY_MASK));
373
ef871432
RN		 374 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
375 dev->syscstate);
5043e9e7
KJ		 376 /*
377 * Enabling all wakup sources to stop I2C freezing on
378 * WFI instruction.
379 * REVISIT: Some wkup sources might not be needed.
380 */
ef871432 381 dev->westate = OMAP_I2C_WE_ALL;
4e80f727
AG		 382 if (dev->rev < OMAP_I2C_REV_ON_3530_4430)
383 omap_i2c_write_reg(dev, OMAP_I2C_WE_REG,
384 dev->westate);
fdd07fe6 385 }
010d442c
KS		 386 }
387 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
388
389 if (cpu_class_is_omap1()) {
0e9ae109
RK		 390 /*
391 * The I2C functional clock is the armxor_ck, so there's
392 * no need to get "armxor_ck" separately. Now, if OMAP2420
393 * always returns 12MHz for the functional clock, we can
394 * do this bit unconditionally.
395 */
27b1fec2
RN		 396 fclk = clk_get(dev->dev, "fck");
397 fclk_rate = clk_get_rate(fclk);
398 clk_put(fclk);
0e9ae109 399
010d442c
KS		 400 /* TRM for 5912 says the I2C clock must be prescaled to be
401 * between 7 - 12 MHz. The XOR input clock is typically
402 * 12, 13 or 19.2 MHz. So we should have code that produces:
403 *
404 * XOR MHz Divider Prescaler
405 * 12 1 0
406 * 13 2 1
407 * 19.2 2 1
408 */
d7aef138
JD		 409 if (fclk_rate > 12000000)
410 psc = fclk_rate / 12000000;
010d442c
KS		 411 }
412
f38e66e0 413 if (!(cpu_class_is_omap1() || cpu_is_omap2420())) {
4574eb68 414
84bf2c86
AK		 415 /*
416 * HSI2C controller internal clk rate should be 19.2 Mhz for
417 * HS and for all modes on 2430. On 34xx we can use lower rate
418 * to get longer filter period for better noise suppression.
419 * The filter is iclk (fclk for HS) period.
420 */
ff0f2426 421 if (dev->speed > 400 || cpu_is_omap2430())
84bf2c86
AK		 422 internal_clk = 19200;
423 else if (dev->speed > 100)
424 internal_clk = 9600;
425 else
426 internal_clk = 4000;
27b1fec2
RN		 427 fclk = clk_get(dev->dev, "fck");
428 fclk_rate = clk_get_rate(fclk) / 1000;
429 clk_put(fclk);
4574eb68
SMK		 430
431 /* Compute prescaler divisor */
432 psc = fclk_rate / internal_clk;
433 psc = psc - 1;
434
435 /* If configured for High Speed */
436 if (dev->speed > 400) {
baf46b4e
AK		 437 unsigned long scl;
438
4574eb68 439 /* For first phase of HS mode */
baf46b4e
AK		 440 scl = internal_clk / 400;
441 fsscll = scl - (scl / 3) - 7;
442 fssclh = (scl / 3) - 5;
4574eb68
SMK		 443
444 /* For second phase of HS mode */
baf46b4e
AK		 445 scl = fclk_rate / dev->speed;
446 hsscll = scl - (scl / 3) - 7;
447 hssclh = (scl / 3) - 5;
448 } else if (dev->speed > 100) {
449 unsigned long scl;
450
451 /* Fast mode */
452 scl = internal_clk / dev->speed;
453 fsscll = scl - (scl / 3) - 7;
454 fssclh = (scl / 3) - 5;
4574eb68 455 } else {
baf46b4e
AK		 456 /* Standard mode */
457 fsscll = internal_clk / (dev->speed * 2) - 7;
458 fssclh = internal_clk / (dev->speed * 2) - 5;
4574eb68
SMK		 459 }
460 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
461 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
462 } else {
463 /* Program desired operating rate */
464 fclk_rate /= (psc + 1) * 1000;
465 if (psc > 2)
466 psc = 2;
467 scll = fclk_rate / (dev->speed * 2) - 7 + psc;
468 sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
469 }
470
010d442c
KS		 471 /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
472 omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);
473
4574eb68
SMK		 474 /* SCL low and high time values */
475 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll);
476 omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh);
010d442c 477
ef871432
RN		 478 if (dev->fifo_size) {
479 /* Note: setup required fifo size - 1. RTRSH and XTRSH */
480 buf = (dev->fifo_size - 1) << 8 | OMAP_I2C_BUF_RXFIF_CLR |
481 (dev->fifo_size - 1) | OMAP_I2C_BUF_TXFIF_CLR;
482 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, buf);
483 }
b6ee52c3 484
010d442c
KS		 485 /* Take the I2C module out of reset: */
486 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
487
f3083d92 488 dev->errata = 0;
489
490 if (cpu_is_omap2430() || cpu_is_omap34xx())
491 dev->errata |= I2C_OMAP_ERRATA_I207;
492
010d442c 493 /* Enable interrupts */
ef871432 494 dev->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
c1a473bd
TL		 495 OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
496 OMAP_I2C_IE_AL) | ((dev->fifo_size) ?
ef871432
RN		 497 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0);
498 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
499 if (cpu_is_omap34xx()) {
500 dev->pscstate = psc;
501 dev->scllstate = scll;
502 dev->sclhstate = sclh;
503 dev->bufstate = buf;
504 }
010d442c
KS		 505 return 0;
506}
507
508/*
509 * Waiting on Bus Busy
510 */
511static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
512{
513 unsigned long timeout;
514
515 timeout = jiffies + OMAP_I2C_TIMEOUT;
516 while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
517 if (time_after(jiffies, timeout)) {
518 dev_warn(dev->dev, "timeout waiting for bus ready\n");
519 return -ETIMEDOUT;
520 }
521 msleep(1);
522 }
523
524 return 0;
525}
526
527/*
528 * Low level master read/write transaction.
529 */
530static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
531 struct i2c_msg *msg, int stop)
532{
533 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
534 int r;
535 u16 w;
536
537 dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
538 msg->addr, msg->len, msg->flags, stop);
539
540 if (msg->len == 0)
541 return -EINVAL;
542
543 omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
544
545 /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
546 dev->buf = msg->buf;
547 dev->buf_len = msg->len;
548
549 omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
550
b6ee52c3
NM		 551 /* Clear the FIFO Buffers */
552 w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
553 w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
554 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w);
555
010d442c
KS		 556 init_completion(&dev->cmd_complete);
557 dev->cmd_err = 0;
558
559 w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
4574eb68
SMK		 560
561 /* High speed configuration */
562 if (dev->speed > 400)
b6ee52c3 563 w |= OMAP_I2C_CON_OPMODE_HS;
4574eb68 564
010d442c
KS		 565 if (msg->flags & I2C_M_TEN)
566 w |= OMAP_I2C_CON_XA;
567 if (!(msg->flags & I2C_M_RD))
568 w |= OMAP_I2C_CON_TRX;
c1a473bd 569
b6ee52c3 570 if (!dev->b_hw && stop)
010d442c 571 w |= OMAP_I2C_CON_STP;
c1a473bd 572
010d442c
KS		 573 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
574
b6ee52c3
NM		 575 /*
576 * Don't write stt and stp together on some hardware.
577 */
578 if (dev->b_hw && stop) {
579 unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
580 u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
581 while (con & OMAP_I2C_CON_STT) {
582 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
583
584 /* Let the user know if i2c is in a bad state */
585 if (time_after(jiffies, delay)) {
586 dev_err(dev->dev, "controller timed out "
587 "waiting for start condition to finish\n");
588 return -ETIMEDOUT;
589 }
590 cpu_relax();
591 }
592
593 w |= OMAP_I2C_CON_STP;
594 w &= ~OMAP_I2C_CON_STT;
595 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
596 }
597
b7af349b
JN		 598 /*
599 * REVISIT: We should abort the transfer on signals, but the bus goes
600 * into arbitration and we're currently unable to recover from it.
601 */
602 r = wait_for_completion_timeout(&dev->cmd_complete,
603 OMAP_I2C_TIMEOUT);
010d442c
KS		 604 dev->buf_len = 0;
605 if (r < 0)
606 return r;
607 if (r == 0) {
608 dev_err(dev->dev, "controller timed out\n");
609 omap_i2c_init(dev);
610 return -ETIMEDOUT;
611 }
612
613 if (likely(!dev->cmd_err))
614 return 0;
615
616 /* We have an error */
617 if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
618 OMAP_I2C_STAT_XUDF)) {
619 omap_i2c_init(dev);
620 return -EIO;
621 }
622
623 if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
624 if (msg->flags & I2C_M_IGNORE_NAK)
625 return 0;
626 if (stop) {
627 w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
628 w |= OMAP_I2C_CON_STP;
629 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
630 }
631 return -EREMOTEIO;
632 }
633 return -EIO;
634}
635
636
637/*
638 * Prepare controller for a transaction and call omap_i2c_xfer_msg
639 * to do the work during IRQ processing.
640 */
641static int
642omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
643{
644 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
645 int i;
646 int r;
647
f08ac4e7 648 omap_i2c_unidle(dev);
010d442c 649
c1a473bd
TL		 650 r = omap_i2c_wait_for_bb(dev);
651 if (r < 0)
010d442c
KS		 652 goto out;
653
6a91b558
SO		 654 if (dev->set_mpu_wkup_lat != NULL)
655 dev->set_mpu_wkup_lat(dev->dev, dev->latency);
656
010d442c
KS		 657 for (i = 0; i < num; i++) {
658 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
659 if (r != 0)
660 break;
661 }
662
6a91b558
SO		 663 if (dev->set_mpu_wkup_lat != NULL)
664 dev->set_mpu_wkup_lat(dev->dev, -1);
665
010d442c
KS		 666 if (r == 0)
667 r = num;
5c64eb26
MN		 668
669 omap_i2c_wait_for_bb(dev);
010d442c 670out:
f08ac4e7 671 omap_i2c_idle(dev);
010d442c
KS		 672 return r;
673}
674
675static u32
676omap_i2c_func(struct i2c_adapter *adap)
677{
678 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
679}
680
681static inline void
682omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)
683{
684 dev->cmd_err |= err;
685 complete(&dev->cmd_complete);
686}
687
688static inline void
689omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
690{
691 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
692}
693
f3083d92 694static inline void i2c_omap_errata_i207(struct omap_i2c_dev *dev, u16 stat)
695{
696 /*
697 * I2C Errata(Errata Nos. OMAP2: 1.67, OMAP3: 1.8)
698 * Not applicable for OMAP4.
699 * Under certain rare conditions, RDR could be set again
700 * when the bus is busy, then ignore the interrupt and
701 * clear the interrupt.
702 */
703 if (stat & OMAP_I2C_STAT_RDR) {
704 /* Step 1: If RDR is set, clear it */
705 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
706
707 /* Step 2: */
708 if (!(omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG)
709 & OMAP_I2C_STAT_BB)) {
710
711 /* Step 3: */
712 if (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG)
713 & OMAP_I2C_STAT_RDR) {
714 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
715 dev_dbg(dev->dev, "RDR when bus is busy.\n");
716 }
717
718 }
719 }
720}
721
43469d8e
PW		 722/* rev1 devices are apparently only on some 15xx */
723#ifdef CONFIG_ARCH_OMAP15XX
724
010d442c 725static irqreturn_t
4e80f727 726omap_i2c_omap1_isr(int this_irq, void *dev_id)
010d442c
KS		 727{
728 struct omap_i2c_dev *dev = dev_id;
729 u16 iv, w;
730
f08ac4e7
TL		 731 if (dev->idle)
732 return IRQ_NONE;
733
010d442c
KS		 734 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
735 switch (iv) {
736 case 0x00: /* None */
737 break;
738 case 0x01: /* Arbitration lost */
739 dev_err(dev->dev, "Arbitration lost\n");
740 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
741 break;
742 case 0x02: /* No acknowledgement */
743 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
744 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
745 break;
746 case 0x03: /* Register access ready */
747 omap_i2c_complete_cmd(dev, 0);
748 break;
749 case 0x04: /* Receive data ready */
750 if (dev->buf_len) {
751 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
752 *dev->buf++ = w;
753 dev->buf_len--;
754 if (dev->buf_len) {
755 *dev->buf++ = w >> 8;
756 dev->buf_len--;
757 }
758 } else
759 dev_err(dev->dev, "RRDY IRQ while no data requested\n");
760 break;
761 case 0x05: /* Transmit data ready */
762 if (dev->buf_len) {
763 w = *dev->buf++;
764 dev->buf_len--;
765 if (dev->buf_len) {
766 w |= *dev->buf++ << 8;
767 dev->buf_len--;
768 }
769 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
770 } else
771 dev_err(dev->dev, "XRDY IRQ while no data to send\n");
772 break;
773 default:
774 return IRQ_NONE;
775 }
776
777 return IRQ_HANDLED;
778}
43469d8e 779#else
4e80f727 780#define omap_i2c_omap1_isr NULL
43469d8e 781#endif
010d442c 782
2dd151ab
AS		 783/*
784 * OMAP3430 Errata 1.153: When an XRDY/XDR is hit, wait for XUDF before writing
785 * data to DATA_REG. Otherwise some data bytes can be lost while transferring
786 * them from the memory to the I2C interface.
787 */
788static int errata_omap3_1p153(struct omap_i2c_dev *dev, u16 *stat, int *err)
789{
e9f59b9c
AS		 790 unsigned long timeout = 10000;
791
792 while (--timeout && !(*stat & OMAP_I2C_STAT_XUDF)) {
2dd151ab
AS		 793 if (*stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
794 omap_i2c_ack_stat(dev, *stat & (OMAP_I2C_STAT_XRDY |
795 OMAP_I2C_STAT_XDR));
796 *err |= OMAP_I2C_STAT_XUDF;
797 return -ETIMEDOUT;
798 }
e9f59b9c 799
2dd151ab
AS		 800 cpu_relax();
801 *stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
802 }
803
e9f59b9c
AS		 804 if (!timeout) {
805 dev_err(dev->dev, "timeout waiting on XUDF bit\n");
806 return 0;
807 }
808
2dd151ab
AS		 809 return 0;
810}
811
010d442c 812static irqreturn_t
7d12e780 813omap_i2c_isr(int this_irq, void *dev_id)
010d442c
KS		 814{
815 struct omap_i2c_dev *dev = dev_id;
816 u16 bits;
817 u16 stat, w;
b6ee52c3 818 int err, count = 0;
010d442c 819
f08ac4e7
TL		 820 if (dev->idle)
821 return IRQ_NONE;
822
010d442c
KS		 823 bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
824 while ((stat = (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG))) & bits) {
825 dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
826 if (count++ == 100) {
827 dev_warn(dev->dev, "Too much work in one IRQ\n");
828 break;
829 }
830
cd086d3a
SM		 831 err = 0;
832complete:
dcc4ec26
NM		 833 /*
834 * Ack the stat in one go, but [R/X]DR and [R/X]RDY should be
835 * acked after the data operation is complete.
836 * Ref: TRM SWPU114Q Figure 18-31
837 */
838 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat &
839 ~(OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR |
840 OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
010d442c 841
b6ee52c3
NM		 842 if (stat & OMAP_I2C_STAT_NACK) {
843 err |= OMAP_I2C_STAT_NACK;
844 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
845 OMAP_I2C_CON_STP);
010d442c 846 }
b6ee52c3
NM		 847 if (stat & OMAP_I2C_STAT_AL) {
848 dev_err(dev->dev, "Arbitration lost\n");
849 err |= OMAP_I2C_STAT_AL;
850 }
a5a595cc 851 /*
cb527ede 852 * ProDB0017052: Clear ARDY bit twice
a5a595cc 853 */
b6ee52c3 854 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
04c688dd 855 OMAP_I2C_STAT_AL)) {
dd11976a
MS		 856 omap_i2c_ack_stat(dev, stat &
857 (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR |
cb527ede
R		 858 OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR |
859 OMAP_I2C_STAT_ARDY));
b6ee52c3 860 omap_i2c_complete_cmd(dev, err);
04c688dd
SM		 861 return IRQ_HANDLED;
862 }
b6ee52c3
NM		 863 if (stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR)) {
864 u8 num_bytes = 1;
f3083d92 865
866 if (dev->errata & I2C_OMAP_ERRATA_I207)
867 i2c_omap_errata_i207(dev, stat);
868
b6ee52c3
NM		 869 if (dev->fifo_size) {
870 if (stat & OMAP_I2C_STAT_RRDY)
871 num_bytes = dev->fifo_size;
bfb6b658
SM		 872 else /* read RXSTAT on RDR interrupt */
873 num_bytes = (omap_i2c_read_reg(dev,
874 OMAP_I2C_BUFSTAT_REG)
875 >> 8) & 0x3F;
b6ee52c3
NM		 876 }
877 while (num_bytes) {
878 num_bytes--;
879 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
010d442c 880 if (dev->buf_len) {
b6ee52c3 881 *dev->buf++ = w;
010d442c 882 dev->buf_len--;
f38e66e0
SS		 883 /*
884 * Data reg in 2430, omap3 and
885 * omap4 is 8 bit wide
886 */
887 if (cpu_class_is_omap1() ||
888 cpu_is_omap2420()) {
b6ee52c3
NM		 889 if (dev->buf_len) {
890 *dev->buf++ = w >> 8;
891 dev->buf_len--;
892 }
893 }
894 } else {
895 if (stat & OMAP_I2C_STAT_RRDY)
896 dev_err(dev->dev,
897 "RRDY IRQ while no data"
898 " requested\n");
899 if (stat & OMAP_I2C_STAT_RDR)
900 dev_err(dev->dev,
901 "RDR IRQ while no data"
902 " requested\n");
903 break;
010d442c 904 }
b6ee52c3
NM		 905 }
906 omap_i2c_ack_stat(dev,
907 stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR));
010d442c
KS		 908 continue;
909 }
b6ee52c3
NM		 910 if (stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)) {
911 u8 num_bytes = 1;
912 if (dev->fifo_size) {
913 if (stat & OMAP_I2C_STAT_XRDY)
914 num_bytes = dev->fifo_size;
bfb6b658 915 else /* read TXSTAT on XDR interrupt */
b6ee52c3 916 num_bytes = omap_i2c_read_reg(dev,
bfb6b658
SM		 917 OMAP_I2C_BUFSTAT_REG)
918 & 0x3F;
b6ee52c3
NM		 919 }
920 while (num_bytes) {
921 num_bytes--;
922 w = 0;
010d442c 923 if (dev->buf_len) {
b6ee52c3 924 w = *dev->buf++;
010d442c 925 dev->buf_len--;
f38e66e0
SS		 926 /*
927 * Data reg in 2430, omap3 and
928 * omap4 is 8 bit wide
929 */
930 if (cpu_class_is_omap1() ||
931 cpu_is_omap2420()) {
b6ee52c3
NM		 932 if (dev->buf_len) {
933 w |= *dev->buf++ << 8;
934 dev->buf_len--;
935 }
936 }
937 } else {
938 if (stat & OMAP_I2C_STAT_XRDY)
939 dev_err(dev->dev,
940 "XRDY IRQ while no "
941 "data to send\n");
942 if (stat & OMAP_I2C_STAT_XDR)
943 dev_err(dev->dev,
944 "XDR IRQ while no "
945 "data to send\n");
946 break;
010d442c 947 }
cd086d3a 948
8a9d97d3 949 if ((dev->errata & I2C_OMAP3_1P153) &&
2dd151ab
AS		 950 errata_omap3_1p153(dev, &stat, &err))
951 goto complete;
cd086d3a 952
b6ee52c3
NM		 953 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
954 }
955 omap_i2c_ack_stat(dev,
956 stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
010d442c
KS		 957 continue;
958 }
959 if (stat & OMAP_I2C_STAT_ROVR) {
960 dev_err(dev->dev, "Receive overrun\n");
961 dev->cmd_err |= OMAP_I2C_STAT_ROVR;
962 }
963 if (stat & OMAP_I2C_STAT_XUDF) {
b6ee52c3 964 dev_err(dev->dev, "Transmit underflow\n");
010d442c
KS		 965 dev->cmd_err |= OMAP_I2C_STAT_XUDF;
966 }
010d442c
KS		 967 }
968
969 return count ? IRQ_HANDLED : IRQ_NONE;
970}
971
8f9082c5 972static const struct i2c_algorithm omap_i2c_algo = {
010d442c
KS		 973 .master_xfer = omap_i2c_xfer,
974 .functionality = omap_i2c_func,
975};
976
1139aea9 977static int __devinit
010d442c
KS		 978omap_i2c_probe(struct platform_device *pdev)
979{
980 struct omap_i2c_dev *dev;
981 struct i2c_adapter *adap;
982 struct resource *mem, *irq, *ioarea;
20c9d2c4 983 struct omap_i2c_bus_platform_data *pdata = pdev->dev.platform_data;
e355204e 984 irq_handler_t isr;
010d442c 985 int r;
3d522fb4 986 u32 speed = 0;
010d442c
KS		 987
988 /* NOTE: driver uses the static register mapping */
989 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
990 if (!mem) {
991 dev_err(&pdev->dev, "no mem resource?\n");
992 return -ENODEV;
993 }
994 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
995 if (!irq) {
996 dev_err(&pdev->dev, "no irq resource?\n");
997 return -ENODEV;
998 }
999
59330825 1000 ioarea = request_mem_region(mem->start, resource_size(mem),
010d442c
KS		 1001 pdev->name);
1002 if (!ioarea) {
1003 dev_err(&pdev->dev, "I2C region already claimed\n");
1004 return -EBUSY;
1005 }
1006
010d442c
KS		 1007 dev = kzalloc(sizeof(struct omap_i2c_dev), GFP_KERNEL);
1008 if (!dev) {
1009 r = -ENOMEM;
1010 goto err_release_region;
1011 }
1012
20c9d2c4
KJ		 1013 if (pdata != NULL) {
1014 speed = pdata->clkrate;
1015 dev->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat;
1016 } else {
1017 speed = 100; /* Default speed */
1018 dev->set_mpu_wkup_lat = NULL;
1019 }
4574eb68 1020
3d522fb4 1021 dev->speed = speed;
3831f154 1022 dev->idle = 1;
010d442c
KS		 1023 dev->dev = &pdev->dev;
1024 dev->irq = irq->start;
c6ffddea 1025 dev->base = ioremap(mem->start, resource_size(mem));
55c381e4
RK		 1026 if (!dev->base) {
1027 r = -ENOMEM;
1028 goto err_free_mem;
1029 }
1030
010d442c
KS		 1031 platform_set_drvdata(pdev, dev);
1032
7c6bd201
MW		 1033 if (cpu_is_omap7xx())
1034 dev->reg_shift = 1;
f38e66e0
SS		 1035 else if (cpu_is_omap44xx())
1036 dev->reg_shift = 0;
7c6bd201
MW		 1037 else
1038 dev->reg_shift = 2;
1039
a1295577
AG		 1040 if (pdata->rev == OMAP_I2C_IP_VERSION_2)
1041 dev->regs = (u8 *)reg_map_ip_v2;
f38e66e0 1042 else
a1295577 1043 dev->regs = (u8 *)reg_map_ip_v1;
f38e66e0 1044
27b1fec2 1045 pm_runtime_enable(&pdev->dev);
f08ac4e7 1046 omap_i2c_unidle(dev);
010d442c 1047
9c76b878 1048 dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
010d442c 1049
8a9d97d3 1050 if (dev->rev <= OMAP_I2C_REV_ON_3430)
1051 dev->errata |= I2C_OMAP3_1P153;
1052
f38e66e0 1053 if (!(cpu_class_is_omap1() || cpu_is_omap2420())) {
b6ee52c3
NM		 1054 u16 s;
1055
1056 /* Set up the fifo size - Get total size */
1057 s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
1058 dev->fifo_size = 0x8 << s;
1059
1060 /*
1061 * Set up notification threshold as half the total available
1062 * size. This is to ensure that we can handle the status on int
1063 * call back latencies.
1064 */
4e80f727 1065 if (dev->rev >= OMAP_I2C_REV_ON_3530_4430) {
f38e66e0
SS		 1066 dev->fifo_size = 0;
1067 dev->b_hw = 0; /* Disable hardware fixes */
1068 } else {
1069 dev->fifo_size = (dev->fifo_size / 2);
1070 dev->b_hw = 1; /* Enable hardware fixes */
1071 }
20c9d2c4
KJ		 1072 /* calculate wakeup latency constraint for MPU */
1073 if (dev->set_mpu_wkup_lat != NULL)
1074 dev->latency = (1000000 * dev->fifo_size) /
1075 (1000 * speed / 8);
b6ee52c3
NM		 1076 }
1077
010d442c
KS		 1078 /* reset ASAP, clearing any IRQs */
1079 omap_i2c_init(dev);
1080
4e80f727
AG		 1081 isr = (dev->rev < OMAP_I2C_OMAP1_REV_2) ? omap_i2c_omap1_isr :
1082 omap_i2c_isr;
9c76b878 1083 r = request_irq(dev->irq, isr, 0, pdev->name, dev);
010d442c
KS		 1084
1085 if (r) {
1086 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
1087 goto err_unuse_clocks;
1088 }
9c76b878 1089
010d442c 1090 dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n",
9c76b878 1091 pdev->id, dev->rev >> 4, dev->rev & 0xf, dev->speed);
010d442c 1092
3831f154
PW		 1093 omap_i2c_idle(dev);
1094
010d442c
KS		 1095 adap = &dev->adapter;
1096 i2c_set_adapdata(adap, dev);
1097 adap->owner = THIS_MODULE;
1098 adap->class = I2C_CLASS_HWMON;
783fd6fa 1099 strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
010d442c
KS		 1100 adap->algo = &omap_i2c_algo;
1101 adap->dev.parent = &pdev->dev;
1102
1103 /* i2c device drivers may be active on return from add_adapter() */
7c175499
DB		 1104 adap->nr = pdev->id;
1105 r = i2c_add_numbered_adapter(adap);
010d442c
KS		 1106 if (r) {
1107 dev_err(dev->dev, "failure adding adapter\n");
1108 goto err_free_irq;
1109 }
1110
010d442c
KS		 1111 return 0;
1112
1113err_free_irq:
1114 free_irq(dev->irq, dev);
1115err_unuse_clocks:
3e39752d 1116 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
f08ac4e7 1117 omap_i2c_idle(dev);
55c381e4 1118 iounmap(dev->base);
010d442c
KS		 1119err_free_mem:
1120 platform_set_drvdata(pdev, NULL);
1121 kfree(dev);
1122err_release_region:
59330825 1123 release_mem_region(mem->start, resource_size(mem));
010d442c
KS		 1124
1125 return r;
1126}
1127
1128static int
1129omap_i2c_remove(struct platform_device *pdev)
1130{
1131 struct omap_i2c_dev *dev = platform_get_drvdata(pdev);
1132 struct resource *mem;
1133
1134 platform_set_drvdata(pdev, NULL);
1135
1136 free_irq(dev->irq, dev);
1137 i2c_del_adapter(&dev->adapter);
1138 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
55c381e4 1139 iounmap(dev->base);
010d442c
KS		 1140 kfree(dev);
1141 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
59330825 1142 release_mem_region(mem->start, resource_size(mem));
010d442c
KS		 1143 return 0;
1144}
1145
1146static struct platform_driver omap_i2c_driver = {
1147 .probe = omap_i2c_probe,
1148 .remove = omap_i2c_remove,
1149 .driver = {
f7bb0d9a 1150 .name = "omap_i2c",
010d442c
KS		 1151 .owner = THIS_MODULE,
1152 },
1153};
1154
1155/* I2C may be needed to bring up other drivers */
1156static int __init
1157omap_i2c_init_driver(void)
1158{
1159 return platform_driver_register(&omap_i2c_driver);
1160}
1161subsys_initcall(omap_i2c_init_driver);
1162
1163static void __exit omap_i2c_exit_driver(void)
1164{
1165 platform_driver_unregister(&omap_i2c_driver);
1166}
1167module_exit(omap_i2c_exit_driver);
1168
1169MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
1170MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
1171MODULE_LICENSE("GPL");
f7bb0d9a 1172MODULE_ALIAS("platform:omap_i2c");
Linux 6.x block layer and io_uring tree(s)