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010d442c KS |
1 | /* |
2 | * TI OMAP I2C master mode driver | |
3 | * | |
4 | * Copyright (C) 2003 MontaVista Software, Inc. | |
010d442c | 5 | * Copyright (C) 2005 Nokia Corporation |
c1a473bd | 6 | * Copyright (C) 2004 - 2007 Texas Instruments. |
010d442c | 7 | * |
c1a473bd TL |
8 | * Originally written by MontaVista Software, Inc. |
9 | * Additional contributions by: | |
10 | * Tony Lindgren <tony@atomide.com> | |
11 | * Imre Deak <imre.deak@nokia.com> | |
12 | * Juha Yrjölä <juha.yrjola@solidboot.com> | |
13 | * Syed Khasim <x0khasim@ti.com> | |
14 | * Nishant Menon <nm@ti.com> | |
010d442c KS |
15 | * |
16 | * This program is free software; you can redistribute it and/or modify | |
17 | * it under the terms of the GNU General Public License as published by | |
18 | * the Free Software Foundation; either version 2 of the License, or | |
19 | * (at your option) any later version. | |
20 | * | |
21 | * This program is distributed in the hope that it will be useful, | |
22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
24 | * GNU General Public License for more details. | |
25 | * | |
26 | * You should have received a copy of the GNU General Public License | |
27 | * along with this program; if not, write to the Free Software | |
28 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
29 | */ | |
30 | ||
31 | #include <linux/module.h> | |
32 | #include <linux/delay.h> | |
33 | #include <linux/i2c.h> | |
34 | #include <linux/err.h> | |
35 | #include <linux/interrupt.h> | |
36 | #include <linux/completion.h> | |
37 | #include <linux/platform_device.h> | |
38 | #include <linux/clk.h> | |
c1a473bd | 39 | #include <linux/io.h> |
6145197b BC |
40 | #include <linux/of.h> |
41 | #include <linux/of_i2c.h> | |
42 | #include <linux/of_device.h> | |
5a0e3ad6 | 43 | #include <linux/slab.h> |
20c9d2c4 | 44 | #include <linux/i2c-omap.h> |
27b1fec2 | 45 | #include <linux/pm_runtime.h> |
010d442c | 46 | |
9c76b878 | 47 | /* I2C controller revisions */ |
4e80f727 | 48 | #define OMAP_I2C_OMAP1_REV_2 0x20 |
9c76b878 PW |
49 | |
50 | /* I2C controller revisions present on specific hardware */ | |
51 | #define OMAP_I2C_REV_ON_2430 0x36 | |
f518b482 JH |
52 | #define OMAP_I2C_REV_ON_3430_3530 0x3C |
53 | #define OMAP_I2C_REV_ON_3630_4430 0x40 | |
9c76b878 | 54 | |
010d442c KS |
55 | /* timeout waiting for the controller to respond */ |
56 | #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000)) | |
57 | ||
6d8451d5 FB |
58 | /* timeout for pm runtime autosuspend */ |
59 | #define OMAP_I2C_PM_TIMEOUT 1000 /* ms */ | |
60 | ||
5043e9e7 | 61 | /* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */ |
f38e66e0 SS |
62 | enum { |
63 | OMAP_I2C_REV_REG = 0, | |
64 | OMAP_I2C_IE_REG, | |
65 | OMAP_I2C_STAT_REG, | |
66 | OMAP_I2C_IV_REG, | |
67 | OMAP_I2C_WE_REG, | |
68 | OMAP_I2C_SYSS_REG, | |
69 | OMAP_I2C_BUF_REG, | |
70 | OMAP_I2C_CNT_REG, | |
71 | OMAP_I2C_DATA_REG, | |
72 | OMAP_I2C_SYSC_REG, | |
73 | OMAP_I2C_CON_REG, | |
74 | OMAP_I2C_OA_REG, | |
75 | OMAP_I2C_SA_REG, | |
76 | OMAP_I2C_PSC_REG, | |
77 | OMAP_I2C_SCLL_REG, | |
78 | OMAP_I2C_SCLH_REG, | |
79 | OMAP_I2C_SYSTEST_REG, | |
80 | OMAP_I2C_BUFSTAT_REG, | |
b8853088 AG |
81 | /* only on OMAP4430 */ |
82 | OMAP_I2C_IP_V2_REVNB_LO, | |
83 | OMAP_I2C_IP_V2_REVNB_HI, | |
84 | OMAP_I2C_IP_V2_IRQSTATUS_RAW, | |
85 | OMAP_I2C_IP_V2_IRQENABLE_SET, | |
86 | OMAP_I2C_IP_V2_IRQENABLE_CLR, | |
f38e66e0 | 87 | }; |
010d442c KS |
88 | |
89 | /* I2C Interrupt Enable Register (OMAP_I2C_IE): */ | |
b6ee52c3 NM |
90 | #define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */ |
91 | #define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */ | |
010d442c KS |
92 | #define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */ |
93 | #define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */ | |
94 | #define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */ | |
95 | #define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */ | |
96 | #define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */ | |
97 | ||
98 | /* I2C Status Register (OMAP_I2C_STAT): */ | |
b6ee52c3 NM |
99 | #define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */ |
100 | #define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */ | |
010d442c KS |
101 | #define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */ |
102 | #define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */ | |
103 | #define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ | |
104 | #define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */ | |
105 | #define OMAP_I2C_STAT_AD0 (1 << 8) /* Address zero */ | |
106 | #define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ | |
107 | #define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */ | |
108 | #define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */ | |
109 | #define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */ | |
110 | #define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */ | |
111 | ||
5043e9e7 KJ |
112 | /* I2C WE wakeup enable register */ |
113 | #define OMAP_I2C_WE_XDR_WE (1 << 14) /* TX drain wakup */ | |
114 | #define OMAP_I2C_WE_RDR_WE (1 << 13) /* RX drain wakeup */ | |
115 | #define OMAP_I2C_WE_AAS_WE (1 << 9) /* Address as slave wakeup*/ | |
116 | #define OMAP_I2C_WE_BF_WE (1 << 8) /* Bus free wakeup */ | |
117 | #define OMAP_I2C_WE_STC_WE (1 << 6) /* Start condition wakeup */ | |
118 | #define OMAP_I2C_WE_GC_WE (1 << 5) /* General call wakeup */ | |
119 | #define OMAP_I2C_WE_DRDY_WE (1 << 3) /* TX/RX data ready wakeup */ | |
120 | #define OMAP_I2C_WE_ARDY_WE (1 << 2) /* Reg access ready wakeup */ | |
121 | #define OMAP_I2C_WE_NACK_WE (1 << 1) /* No acknowledgment wakeup */ | |
122 | #define OMAP_I2C_WE_AL_WE (1 << 0) /* Arbitration lost wakeup */ | |
123 | ||
124 | #define OMAP_I2C_WE_ALL (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \ | |
125 | OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \ | |
126 | OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \ | |
127 | OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \ | |
128 | OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE) | |
129 | ||
010d442c KS |
130 | /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */ |
131 | #define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */ | |
b6ee52c3 | 132 | #define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */ |
010d442c | 133 | #define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */ |
b6ee52c3 | 134 | #define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */ |
010d442c KS |
135 | |
136 | /* I2C Configuration Register (OMAP_I2C_CON): */ | |
137 | #define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */ | |
138 | #define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */ | |
b6ee52c3 | 139 | #define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */ |
010d442c KS |
140 | #define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */ |
141 | #define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */ | |
142 | #define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */ | |
143 | #define OMAP_I2C_CON_XA (1 << 8) /* Expand address */ | |
144 | #define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */ | |
145 | #define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */ | |
146 | #define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */ | |
147 | ||
4574eb68 SMK |
148 | /* I2C SCL time value when Master */ |
149 | #define OMAP_I2C_SCLL_HSSCLL 8 | |
150 | #define OMAP_I2C_SCLH_HSSCLH 8 | |
151 | ||
010d442c KS |
152 | /* I2C System Test Register (OMAP_I2C_SYSTEST): */ |
153 | #ifdef DEBUG | |
154 | #define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */ | |
155 | #define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */ | |
156 | #define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */ | |
157 | #define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */ | |
158 | #define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */ | |
159 | #define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */ | |
160 | #define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */ | |
161 | #define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */ | |
162 | #endif | |
163 | ||
fdd07fe6 PW |
164 | /* OCP_SYSSTATUS bit definitions */ |
165 | #define SYSS_RESETDONE_MASK (1 << 0) | |
166 | ||
167 | /* OCP_SYSCONFIG bit definitions */ | |
168 | #define SYSC_CLOCKACTIVITY_MASK (0x3 << 8) | |
169 | #define SYSC_SIDLEMODE_MASK (0x3 << 3) | |
170 | #define SYSC_ENAWAKEUP_MASK (1 << 2) | |
171 | #define SYSC_SOFTRESET_MASK (1 << 1) | |
172 | #define SYSC_AUTOIDLE_MASK (1 << 0) | |
173 | ||
174 | #define SYSC_IDLEMODE_SMART 0x2 | |
175 | #define SYSC_CLOCKACTIVITY_FCLK 0x2 | |
010d442c | 176 | |
f3083d92 | 177 | /* Errata definitions */ |
178 | #define I2C_OMAP_ERRATA_I207 (1 << 0) | |
c8db38f0 | 179 | #define I2C_OMAP_ERRATA_I462 (1 << 1) |
010d442c | 180 | |
010d442c | 181 | struct omap_i2c_dev { |
3b2f8f82 | 182 | spinlock_t lock; /* IRQ synchronization */ |
010d442c KS |
183 | struct device *dev; |
184 | void __iomem *base; /* virtual */ | |
185 | int irq; | |
d84d3ea3 | 186 | int reg_shift; /* bit shift for I2C register addresses */ |
010d442c KS |
187 | struct completion cmd_complete; |
188 | struct resource *ioarea; | |
49839dc9 PW |
189 | u32 latency; /* maximum mpu wkup latency */ |
190 | void (*set_mpu_wkup_lat)(struct device *dev, | |
191 | long latency); | |
6145197b BC |
192 | u32 speed; /* Speed of bus in kHz */ |
193 | u32 dtrev; /* extra revision from DT */ | |
194 | u32 flags; | |
010d442c KS |
195 | u16 cmd_err; |
196 | u8 *buf; | |
f38e66e0 | 197 | u8 *regs; |
010d442c KS |
198 | size_t buf_len; |
199 | struct i2c_adapter adapter; | |
dd74548d | 200 | u8 threshold; |
b6ee52c3 NM |
201 | u8 fifo_size; /* use as flag and value |
202 | * fifo_size==0 implies no fifo | |
203 | * if set, should be trsh+1 | |
204 | */ | |
9c76b878 | 205 | u8 rev; |
b6ee52c3 | 206 | unsigned b_hw:1; /* bad h/w fixes */ |
079d8af2 | 207 | unsigned receiver:1; /* true when we're in receiver mode */ |
f08ac4e7 | 208 | u16 iestate; /* Saved interrupt register */ |
ef871432 RN |
209 | u16 pscstate; |
210 | u16 scllstate; | |
211 | u16 sclhstate; | |
212 | u16 bufstate; | |
213 | u16 syscstate; | |
214 | u16 westate; | |
f3083d92 | 215 | u16 errata; |
010d442c KS |
216 | }; |
217 | ||
a1295577 | 218 | static const u8 reg_map_ip_v1[] = { |
f38e66e0 SS |
219 | [OMAP_I2C_REV_REG] = 0x00, |
220 | [OMAP_I2C_IE_REG] = 0x01, | |
221 | [OMAP_I2C_STAT_REG] = 0x02, | |
222 | [OMAP_I2C_IV_REG] = 0x03, | |
223 | [OMAP_I2C_WE_REG] = 0x03, | |
224 | [OMAP_I2C_SYSS_REG] = 0x04, | |
225 | [OMAP_I2C_BUF_REG] = 0x05, | |
226 | [OMAP_I2C_CNT_REG] = 0x06, | |
227 | [OMAP_I2C_DATA_REG] = 0x07, | |
228 | [OMAP_I2C_SYSC_REG] = 0x08, | |
229 | [OMAP_I2C_CON_REG] = 0x09, | |
230 | [OMAP_I2C_OA_REG] = 0x0a, | |
231 | [OMAP_I2C_SA_REG] = 0x0b, | |
232 | [OMAP_I2C_PSC_REG] = 0x0c, | |
233 | [OMAP_I2C_SCLL_REG] = 0x0d, | |
234 | [OMAP_I2C_SCLH_REG] = 0x0e, | |
235 | [OMAP_I2C_SYSTEST_REG] = 0x0f, | |
236 | [OMAP_I2C_BUFSTAT_REG] = 0x10, | |
237 | }; | |
238 | ||
a1295577 | 239 | static const u8 reg_map_ip_v2[] = { |
f38e66e0 SS |
240 | [OMAP_I2C_REV_REG] = 0x04, |
241 | [OMAP_I2C_IE_REG] = 0x2c, | |
242 | [OMAP_I2C_STAT_REG] = 0x28, | |
243 | [OMAP_I2C_IV_REG] = 0x34, | |
244 | [OMAP_I2C_WE_REG] = 0x34, | |
245 | [OMAP_I2C_SYSS_REG] = 0x90, | |
246 | [OMAP_I2C_BUF_REG] = 0x94, | |
247 | [OMAP_I2C_CNT_REG] = 0x98, | |
248 | [OMAP_I2C_DATA_REG] = 0x9c, | |
2727b175 | 249 | [OMAP_I2C_SYSC_REG] = 0x10, |
f38e66e0 SS |
250 | [OMAP_I2C_CON_REG] = 0xa4, |
251 | [OMAP_I2C_OA_REG] = 0xa8, | |
252 | [OMAP_I2C_SA_REG] = 0xac, | |
253 | [OMAP_I2C_PSC_REG] = 0xb0, | |
254 | [OMAP_I2C_SCLL_REG] = 0xb4, | |
255 | [OMAP_I2C_SCLH_REG] = 0xb8, | |
256 | [OMAP_I2C_SYSTEST_REG] = 0xbC, | |
257 | [OMAP_I2C_BUFSTAT_REG] = 0xc0, | |
b8853088 AG |
258 | [OMAP_I2C_IP_V2_REVNB_LO] = 0x00, |
259 | [OMAP_I2C_IP_V2_REVNB_HI] = 0x04, | |
260 | [OMAP_I2C_IP_V2_IRQSTATUS_RAW] = 0x24, | |
261 | [OMAP_I2C_IP_V2_IRQENABLE_SET] = 0x2c, | |
262 | [OMAP_I2C_IP_V2_IRQENABLE_CLR] = 0x30, | |
f38e66e0 SS |
263 | }; |
264 | ||
010d442c KS |
265 | static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev, |
266 | int reg, u16 val) | |
267 | { | |
f38e66e0 SS |
268 | __raw_writew(val, i2c_dev->base + |
269 | (i2c_dev->regs[reg] << i2c_dev->reg_shift)); | |
010d442c KS |
270 | } |
271 | ||
272 | static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg) | |
273 | { | |
f38e66e0 SS |
274 | return __raw_readw(i2c_dev->base + |
275 | (i2c_dev->regs[reg] << i2c_dev->reg_shift)); | |
010d442c KS |
276 | } |
277 | ||
010d442c KS |
278 | static int omap_i2c_init(struct omap_i2c_dev *dev) |
279 | { | |
ef871432 | 280 | u16 psc = 0, scll = 0, sclh = 0, buf = 0; |
4574eb68 | 281 | u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0; |
010d442c KS |
282 | unsigned long fclk_rate = 12000000; |
283 | unsigned long timeout; | |
4574eb68 | 284 | unsigned long internal_clk = 0; |
27b1fec2 | 285 | struct clk *fclk; |
010d442c | 286 | |
4e80f727 | 287 | if (dev->rev >= OMAP_I2C_OMAP1_REV_2) { |
57eb81b1 MG |
288 | /* Disable I2C controller before soft reset */ |
289 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, | |
290 | omap_i2c_read_reg(dev, OMAP_I2C_CON_REG) & | |
291 | ~(OMAP_I2C_CON_EN)); | |
292 | ||
fdd07fe6 | 293 | omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK); |
010d442c KS |
294 | /* For some reason we need to set the EN bit before the |
295 | * reset done bit gets set. */ | |
296 | timeout = jiffies + OMAP_I2C_TIMEOUT; | |
297 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN); | |
298 | while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) & | |
fdd07fe6 | 299 | SYSS_RESETDONE_MASK)) { |
010d442c | 300 | if (time_after(jiffies, timeout)) { |
fce3ff03 | 301 | dev_warn(dev->dev, "timeout waiting " |
010d442c KS |
302 | "for controller reset\n"); |
303 | return -ETIMEDOUT; | |
304 | } | |
305 | msleep(1); | |
306 | } | |
fdd07fe6 PW |
307 | |
308 | /* SYSC register is cleared by the reset; rewrite it */ | |
309 | if (dev->rev == OMAP_I2C_REV_ON_2430) { | |
310 | ||
311 | omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, | |
312 | SYSC_AUTOIDLE_MASK); | |
313 | ||
f518b482 | 314 | } else if (dev->rev >= OMAP_I2C_REV_ON_3430_3530) { |
ef871432 RN |
315 | dev->syscstate = SYSC_AUTOIDLE_MASK; |
316 | dev->syscstate |= SYSC_ENAWAKEUP_MASK; | |
317 | dev->syscstate |= (SYSC_IDLEMODE_SMART << | |
fdd07fe6 | 318 | __ffs(SYSC_SIDLEMODE_MASK)); |
ef871432 | 319 | dev->syscstate |= (SYSC_CLOCKACTIVITY_FCLK << |
fdd07fe6 PW |
320 | __ffs(SYSC_CLOCKACTIVITY_MASK)); |
321 | ||
ef871432 RN |
322 | omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, |
323 | dev->syscstate); | |
5043e9e7 KJ |
324 | /* |
325 | * Enabling all wakup sources to stop I2C freezing on | |
326 | * WFI instruction. | |
327 | * REVISIT: Some wkup sources might not be needed. | |
328 | */ | |
ef871432 | 329 | dev->westate = OMAP_I2C_WE_ALL; |
cb28e582 S |
330 | omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, |
331 | dev->westate); | |
fdd07fe6 | 332 | } |
010d442c KS |
333 | } |
334 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); | |
335 | ||
6145197b | 336 | if (dev->flags & OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK) { |
0e9ae109 RK |
337 | /* |
338 | * The I2C functional clock is the armxor_ck, so there's | |
339 | * no need to get "armxor_ck" separately. Now, if OMAP2420 | |
340 | * always returns 12MHz for the functional clock, we can | |
341 | * do this bit unconditionally. | |
342 | */ | |
27b1fec2 RN |
343 | fclk = clk_get(dev->dev, "fck"); |
344 | fclk_rate = clk_get_rate(fclk); | |
345 | clk_put(fclk); | |
0e9ae109 | 346 | |
010d442c KS |
347 | /* TRM for 5912 says the I2C clock must be prescaled to be |
348 | * between 7 - 12 MHz. The XOR input clock is typically | |
349 | * 12, 13 or 19.2 MHz. So we should have code that produces: | |
350 | * | |
351 | * XOR MHz Divider Prescaler | |
352 | * 12 1 0 | |
353 | * 13 2 1 | |
354 | * 19.2 2 1 | |
355 | */ | |
d7aef138 JD |
356 | if (fclk_rate > 12000000) |
357 | psc = fclk_rate / 12000000; | |
010d442c KS |
358 | } |
359 | ||
6145197b | 360 | if (!(dev->flags & OMAP_I2C_FLAG_SIMPLE_CLOCK)) { |
4574eb68 | 361 | |
84bf2c86 AK |
362 | /* |
363 | * HSI2C controller internal clk rate should be 19.2 Mhz for | |
364 | * HS and for all modes on 2430. On 34xx we can use lower rate | |
365 | * to get longer filter period for better noise suppression. | |
366 | * The filter is iclk (fclk for HS) period. | |
367 | */ | |
3be0053e | 368 | if (dev->speed > 400 || |
6145197b | 369 | dev->flags & OMAP_I2C_FLAG_FORCE_19200_INT_CLK) |
84bf2c86 AK |
370 | internal_clk = 19200; |
371 | else if (dev->speed > 100) | |
372 | internal_clk = 9600; | |
373 | else | |
374 | internal_clk = 4000; | |
27b1fec2 RN |
375 | fclk = clk_get(dev->dev, "fck"); |
376 | fclk_rate = clk_get_rate(fclk) / 1000; | |
377 | clk_put(fclk); | |
4574eb68 SMK |
378 | |
379 | /* Compute prescaler divisor */ | |
380 | psc = fclk_rate / internal_clk; | |
381 | psc = psc - 1; | |
382 | ||
383 | /* If configured for High Speed */ | |
384 | if (dev->speed > 400) { | |
baf46b4e AK |
385 | unsigned long scl; |
386 | ||
4574eb68 | 387 | /* For first phase of HS mode */ |
baf46b4e AK |
388 | scl = internal_clk / 400; |
389 | fsscll = scl - (scl / 3) - 7; | |
390 | fssclh = (scl / 3) - 5; | |
4574eb68 SMK |
391 | |
392 | /* For second phase of HS mode */ | |
baf46b4e AK |
393 | scl = fclk_rate / dev->speed; |
394 | hsscll = scl - (scl / 3) - 7; | |
395 | hssclh = (scl / 3) - 5; | |
396 | } else if (dev->speed > 100) { | |
397 | unsigned long scl; | |
398 | ||
399 | /* Fast mode */ | |
400 | scl = internal_clk / dev->speed; | |
401 | fsscll = scl - (scl / 3) - 7; | |
402 | fssclh = (scl / 3) - 5; | |
4574eb68 | 403 | } else { |
baf46b4e AK |
404 | /* Standard mode */ |
405 | fsscll = internal_clk / (dev->speed * 2) - 7; | |
406 | fssclh = internal_clk / (dev->speed * 2) - 5; | |
4574eb68 SMK |
407 | } |
408 | scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll; | |
409 | sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh; | |
410 | } else { | |
411 | /* Program desired operating rate */ | |
412 | fclk_rate /= (psc + 1) * 1000; | |
413 | if (psc > 2) | |
414 | psc = 2; | |
415 | scll = fclk_rate / (dev->speed * 2) - 7 + psc; | |
416 | sclh = fclk_rate / (dev->speed * 2) - 7 + psc; | |
417 | } | |
418 | ||
010d442c KS |
419 | /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */ |
420 | omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc); | |
421 | ||
4574eb68 SMK |
422 | /* SCL low and high time values */ |
423 | omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll); | |
424 | omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh); | |
010d442c KS |
425 | |
426 | /* Take the I2C module out of reset: */ | |
427 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN); | |
428 | ||
429 | /* Enable interrupts */ | |
ef871432 | 430 | dev->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY | |
c1a473bd TL |
431 | OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK | |
432 | OMAP_I2C_IE_AL) | ((dev->fifo_size) ? | |
ef871432 RN |
433 | (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0); |
434 | omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate); | |
6145197b | 435 | if (dev->flags & OMAP_I2C_FLAG_RESET_REGS_POSTIDLE) { |
ef871432 RN |
436 | dev->pscstate = psc; |
437 | dev->scllstate = scll; | |
438 | dev->sclhstate = sclh; | |
439 | dev->bufstate = buf; | |
440 | } | |
010d442c KS |
441 | return 0; |
442 | } | |
443 | ||
444 | /* | |
445 | * Waiting on Bus Busy | |
446 | */ | |
447 | static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev) | |
448 | { | |
449 | unsigned long timeout; | |
450 | ||
451 | timeout = jiffies + OMAP_I2C_TIMEOUT; | |
452 | while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) { | |
453 | if (time_after(jiffies, timeout)) { | |
454 | dev_warn(dev->dev, "timeout waiting for bus ready\n"); | |
455 | return -ETIMEDOUT; | |
456 | } | |
457 | msleep(1); | |
458 | } | |
459 | ||
460 | return 0; | |
461 | } | |
462 | ||
dd74548d FB |
463 | static void omap_i2c_resize_fifo(struct omap_i2c_dev *dev, u8 size, bool is_rx) |
464 | { | |
465 | u16 buf; | |
466 | ||
467 | if (dev->flags & OMAP_I2C_FLAG_NO_FIFO) | |
468 | return; | |
469 | ||
470 | /* | |
471 | * Set up notification threshold based on message size. We're doing | |
472 | * this to try and avoid draining feature as much as possible. Whenever | |
473 | * we have big messages to transfer (bigger than our total fifo size) | |
474 | * then we might use draining feature to transfer the remaining bytes. | |
475 | */ | |
476 | ||
477 | dev->threshold = clamp(size, (u8) 1, dev->fifo_size); | |
478 | ||
479 | buf = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG); | |
480 | ||
481 | if (is_rx) { | |
482 | /* Clear RX Threshold */ | |
483 | buf &= ~(0x3f << 8); | |
484 | buf |= ((dev->threshold - 1) << 8) | OMAP_I2C_BUF_RXFIF_CLR; | |
485 | } else { | |
486 | /* Clear TX Threshold */ | |
487 | buf &= ~0x3f; | |
488 | buf |= (dev->threshold - 1) | OMAP_I2C_BUF_TXFIF_CLR; | |
489 | } | |
490 | ||
491 | omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, buf); | |
492 | ||
493 | if (dev->rev < OMAP_I2C_REV_ON_3630_4430) | |
494 | dev->b_hw = 1; /* Enable hardware fixes */ | |
495 | ||
496 | /* calculate wakeup latency constraint for MPU */ | |
49839dc9 PW |
497 | if (dev->set_mpu_wkup_lat != NULL) |
498 | dev->latency = (1000000 * dev->threshold) / | |
499 | (1000 * dev->speed / 8); | |
dd74548d FB |
500 | } |
501 | ||
010d442c KS |
502 | /* |
503 | * Low level master read/write transaction. | |
504 | */ | |
505 | static int omap_i2c_xfer_msg(struct i2c_adapter *adap, | |
506 | struct i2c_msg *msg, int stop) | |
507 | { | |
508 | struct omap_i2c_dev *dev = i2c_get_adapdata(adap); | |
33d54985 | 509 | unsigned long timeout; |
010d442c KS |
510 | u16 w; |
511 | ||
512 | dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n", | |
513 | msg->addr, msg->len, msg->flags, stop); | |
514 | ||
515 | if (msg->len == 0) | |
516 | return -EINVAL; | |
517 | ||
dd74548d FB |
518 | dev->receiver = !!(msg->flags & I2C_M_RD); |
519 | omap_i2c_resize_fifo(dev, msg->len, dev->receiver); | |
520 | ||
010d442c KS |
521 | omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr); |
522 | ||
523 | /* REVISIT: Could the STB bit of I2C_CON be used with probing? */ | |
524 | dev->buf = msg->buf; | |
525 | dev->buf_len = msg->len; | |
526 | ||
527 | omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len); | |
528 | ||
b6ee52c3 NM |
529 | /* Clear the FIFO Buffers */ |
530 | w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG); | |
531 | w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR; | |
532 | omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w); | |
533 | ||
0e33bbb2 | 534 | INIT_COMPLETION(dev->cmd_complete); |
010d442c KS |
535 | dev->cmd_err = 0; |
536 | ||
537 | w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT; | |
4574eb68 SMK |
538 | |
539 | /* High speed configuration */ | |
540 | if (dev->speed > 400) | |
b6ee52c3 | 541 | w |= OMAP_I2C_CON_OPMODE_HS; |
4574eb68 | 542 | |
fb604a3d LP |
543 | if (msg->flags & I2C_M_STOP) |
544 | stop = 1; | |
010d442c KS |
545 | if (msg->flags & I2C_M_TEN) |
546 | w |= OMAP_I2C_CON_XA; | |
547 | if (!(msg->flags & I2C_M_RD)) | |
548 | w |= OMAP_I2C_CON_TRX; | |
c1a473bd | 549 | |
b6ee52c3 | 550 | if (!dev->b_hw && stop) |
010d442c | 551 | w |= OMAP_I2C_CON_STP; |
c1a473bd | 552 | |
010d442c KS |
553 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w); |
554 | ||
b6ee52c3 NM |
555 | /* |
556 | * Don't write stt and stp together on some hardware. | |
557 | */ | |
558 | if (dev->b_hw && stop) { | |
559 | unsigned long delay = jiffies + OMAP_I2C_TIMEOUT; | |
560 | u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG); | |
561 | while (con & OMAP_I2C_CON_STT) { | |
562 | con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG); | |
563 | ||
564 | /* Let the user know if i2c is in a bad state */ | |
565 | if (time_after(jiffies, delay)) { | |
566 | dev_err(dev->dev, "controller timed out " | |
567 | "waiting for start condition to finish\n"); | |
568 | return -ETIMEDOUT; | |
569 | } | |
570 | cpu_relax(); | |
571 | } | |
572 | ||
573 | w |= OMAP_I2C_CON_STP; | |
574 | w &= ~OMAP_I2C_CON_STT; | |
575 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w); | |
576 | } | |
577 | ||
b7af349b JN |
578 | /* |
579 | * REVISIT: We should abort the transfer on signals, but the bus goes | |
580 | * into arbitration and we're currently unable to recover from it. | |
581 | */ | |
33d54985 S |
582 | timeout = wait_for_completion_timeout(&dev->cmd_complete, |
583 | OMAP_I2C_TIMEOUT); | |
010d442c | 584 | dev->buf_len = 0; |
33d54985 | 585 | if (timeout == 0) { |
010d442c KS |
586 | dev_err(dev->dev, "controller timed out\n"); |
587 | omap_i2c_init(dev); | |
588 | return -ETIMEDOUT; | |
589 | } | |
590 | ||
591 | if (likely(!dev->cmd_err)) | |
592 | return 0; | |
593 | ||
594 | /* We have an error */ | |
595 | if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR | | |
596 | OMAP_I2C_STAT_XUDF)) { | |
597 | omap_i2c_init(dev); | |
598 | return -EIO; | |
599 | } | |
600 | ||
601 | if (dev->cmd_err & OMAP_I2C_STAT_NACK) { | |
602 | if (msg->flags & I2C_M_IGNORE_NAK) | |
603 | return 0; | |
604 | if (stop) { | |
605 | w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG); | |
606 | w |= OMAP_I2C_CON_STP; | |
607 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w); | |
608 | } | |
609 | return -EREMOTEIO; | |
610 | } | |
611 | return -EIO; | |
612 | } | |
613 | ||
614 | ||
615 | /* | |
616 | * Prepare controller for a transaction and call omap_i2c_xfer_msg | |
617 | * to do the work during IRQ processing. | |
618 | */ | |
619 | static int | |
620 | omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) | |
621 | { | |
622 | struct omap_i2c_dev *dev = i2c_get_adapdata(adap); | |
623 | int i; | |
624 | int r; | |
625 | ||
3b0fb97c S |
626 | r = pm_runtime_get_sync(dev->dev); |
627 | if (IS_ERR_VALUE(r)) | |
33ec5e81 | 628 | goto out; |
010d442c | 629 | |
c1a473bd TL |
630 | r = omap_i2c_wait_for_bb(dev); |
631 | if (r < 0) | |
010d442c KS |
632 | goto out; |
633 | ||
49839dc9 PW |
634 | if (dev->set_mpu_wkup_lat != NULL) |
635 | dev->set_mpu_wkup_lat(dev->dev, dev->latency); | |
6a91b558 | 636 | |
010d442c KS |
637 | for (i = 0; i < num; i++) { |
638 | r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1))); | |
639 | if (r != 0) | |
640 | break; | |
641 | } | |
642 | ||
49839dc9 PW |
643 | if (dev->set_mpu_wkup_lat != NULL) |
644 | dev->set_mpu_wkup_lat(dev->dev, -1); | |
6a91b558 | 645 | |
010d442c KS |
646 | if (r == 0) |
647 | r = num; | |
5c64eb26 MN |
648 | |
649 | omap_i2c_wait_for_bb(dev); | |
010d442c | 650 | out: |
6d8451d5 FB |
651 | pm_runtime_mark_last_busy(dev->dev); |
652 | pm_runtime_put_autosuspend(dev->dev); | |
010d442c KS |
653 | return r; |
654 | } | |
655 | ||
656 | static u32 | |
657 | omap_i2c_func(struct i2c_adapter *adap) | |
658 | { | |
fb604a3d LP |
659 | return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) | |
660 | I2C_FUNC_PROTOCOL_MANGLING; | |
010d442c KS |
661 | } |
662 | ||
663 | static inline void | |
664 | omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err) | |
665 | { | |
666 | dev->cmd_err |= err; | |
667 | complete(&dev->cmd_complete); | |
668 | } | |
669 | ||
670 | static inline void | |
671 | omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat) | |
672 | { | |
673 | omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat); | |
674 | } | |
675 | ||
f3083d92 | 676 | static inline void i2c_omap_errata_i207(struct omap_i2c_dev *dev, u16 stat) |
677 | { | |
678 | /* | |
679 | * I2C Errata(Errata Nos. OMAP2: 1.67, OMAP3: 1.8) | |
680 | * Not applicable for OMAP4. | |
681 | * Under certain rare conditions, RDR could be set again | |
682 | * when the bus is busy, then ignore the interrupt and | |
683 | * clear the interrupt. | |
684 | */ | |
685 | if (stat & OMAP_I2C_STAT_RDR) { | |
686 | /* Step 1: If RDR is set, clear it */ | |
687 | omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR); | |
688 | ||
689 | /* Step 2: */ | |
690 | if (!(omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) | |
691 | & OMAP_I2C_STAT_BB)) { | |
692 | ||
693 | /* Step 3: */ | |
694 | if (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) | |
695 | & OMAP_I2C_STAT_RDR) { | |
696 | omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR); | |
697 | dev_dbg(dev->dev, "RDR when bus is busy.\n"); | |
698 | } | |
699 | ||
700 | } | |
701 | } | |
702 | } | |
703 | ||
43469d8e PW |
704 | /* rev1 devices are apparently only on some 15xx */ |
705 | #ifdef CONFIG_ARCH_OMAP15XX | |
706 | ||
010d442c | 707 | static irqreturn_t |
4e80f727 | 708 | omap_i2c_omap1_isr(int this_irq, void *dev_id) |
010d442c KS |
709 | { |
710 | struct omap_i2c_dev *dev = dev_id; | |
711 | u16 iv, w; | |
712 | ||
fab67afb | 713 | if (pm_runtime_suspended(dev->dev)) |
f08ac4e7 TL |
714 | return IRQ_NONE; |
715 | ||
010d442c KS |
716 | iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); |
717 | switch (iv) { | |
718 | case 0x00: /* None */ | |
719 | break; | |
720 | case 0x01: /* Arbitration lost */ | |
721 | dev_err(dev->dev, "Arbitration lost\n"); | |
722 | omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL); | |
723 | break; | |
724 | case 0x02: /* No acknowledgement */ | |
725 | omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK); | |
726 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP); | |
727 | break; | |
728 | case 0x03: /* Register access ready */ | |
729 | omap_i2c_complete_cmd(dev, 0); | |
730 | break; | |
731 | case 0x04: /* Receive data ready */ | |
732 | if (dev->buf_len) { | |
733 | w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG); | |
734 | *dev->buf++ = w; | |
735 | dev->buf_len--; | |
736 | if (dev->buf_len) { | |
737 | *dev->buf++ = w >> 8; | |
738 | dev->buf_len--; | |
739 | } | |
740 | } else | |
741 | dev_err(dev->dev, "RRDY IRQ while no data requested\n"); | |
742 | break; | |
743 | case 0x05: /* Transmit data ready */ | |
744 | if (dev->buf_len) { | |
745 | w = *dev->buf++; | |
746 | dev->buf_len--; | |
747 | if (dev->buf_len) { | |
748 | w |= *dev->buf++ << 8; | |
749 | dev->buf_len--; | |
750 | } | |
751 | omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w); | |
752 | } else | |
753 | dev_err(dev->dev, "XRDY IRQ while no data to send\n"); | |
754 | break; | |
755 | default: | |
756 | return IRQ_NONE; | |
757 | } | |
758 | ||
759 | return IRQ_HANDLED; | |
760 | } | |
43469d8e | 761 | #else |
4e80f727 | 762 | #define omap_i2c_omap1_isr NULL |
43469d8e | 763 | #endif |
010d442c | 764 | |
2dd151ab | 765 | /* |
c8db38f0 | 766 | * OMAP3430 Errata i462: When an XRDY/XDR is hit, wait for XUDF before writing |
2dd151ab AS |
767 | * data to DATA_REG. Otherwise some data bytes can be lost while transferring |
768 | * them from the memory to the I2C interface. | |
769 | */ | |
4151e741 | 770 | static int errata_omap3_i462(struct omap_i2c_dev *dev) |
2dd151ab | 771 | { |
e9f59b9c | 772 | unsigned long timeout = 10000; |
4151e741 | 773 | u16 stat; |
e9f59b9c | 774 | |
4151e741 FB |
775 | do { |
776 | stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG); | |
777 | if (stat & OMAP_I2C_STAT_XUDF) | |
778 | break; | |
779 | ||
780 | if (stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) { | |
540a4790 | 781 | omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_XRDY | |
2dd151ab | 782 | OMAP_I2C_STAT_XDR)); |
b07be0f3 FB |
783 | if (stat & OMAP_I2C_STAT_NACK) { |
784 | dev->cmd_err |= OMAP_I2C_STAT_NACK; | |
785 | omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK); | |
786 | } | |
787 | ||
788 | if (stat & OMAP_I2C_STAT_AL) { | |
789 | dev_err(dev->dev, "Arbitration lost\n"); | |
790 | dev->cmd_err |= OMAP_I2C_STAT_AL; | |
791 | omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK); | |
792 | } | |
793 | ||
4151e741 | 794 | return -EIO; |
2dd151ab | 795 | } |
e9f59b9c | 796 | |
2dd151ab | 797 | cpu_relax(); |
4151e741 | 798 | } while (--timeout); |
2dd151ab | 799 | |
e9f59b9c AS |
800 | if (!timeout) { |
801 | dev_err(dev->dev, "timeout waiting on XUDF bit\n"); | |
802 | return 0; | |
803 | } | |
804 | ||
2dd151ab AS |
805 | return 0; |
806 | } | |
807 | ||
3312d25e FB |
808 | static void omap_i2c_receive_data(struct omap_i2c_dev *dev, u8 num_bytes, |
809 | bool is_rdr) | |
810 | { | |
811 | u16 w; | |
812 | ||
813 | while (num_bytes--) { | |
3312d25e FB |
814 | w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG); |
815 | *dev->buf++ = w; | |
816 | dev->buf_len--; | |
817 | ||
818 | /* | |
819 | * Data reg in 2430, omap3 and | |
820 | * omap4 is 8 bit wide | |
821 | */ | |
822 | if (dev->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) { | |
dd74548d FB |
823 | *dev->buf++ = w >> 8; |
824 | dev->buf_len--; | |
3312d25e FB |
825 | } |
826 | } | |
827 | } | |
828 | ||
829 | static int omap_i2c_transmit_data(struct omap_i2c_dev *dev, u8 num_bytes, | |
830 | bool is_xdr) | |
831 | { | |
832 | u16 w; | |
833 | ||
834 | while (num_bytes--) { | |
3312d25e FB |
835 | w = *dev->buf++; |
836 | dev->buf_len--; | |
837 | ||
838 | /* | |
839 | * Data reg in 2430, omap3 and | |
840 | * omap4 is 8 bit wide | |
841 | */ | |
842 | if (dev->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) { | |
dd74548d FB |
843 | w |= *dev->buf++ << 8; |
844 | dev->buf_len--; | |
3312d25e FB |
845 | } |
846 | ||
847 | if (dev->errata & I2C_OMAP_ERRATA_I462) { | |
848 | int ret; | |
849 | ||
850 | ret = errata_omap3_i462(dev); | |
851 | if (ret < 0) | |
852 | return ret; | |
853 | } | |
854 | ||
855 | omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w); | |
856 | } | |
857 | ||
858 | return 0; | |
859 | } | |
860 | ||
010d442c | 861 | static irqreturn_t |
3b2f8f82 | 862 | omap_i2c_isr(int irq, void *dev_id) |
010d442c KS |
863 | { |
864 | struct omap_i2c_dev *dev = dev_id; | |
3b2f8f82 FB |
865 | irqreturn_t ret = IRQ_HANDLED; |
866 | u16 mask; | |
867 | u16 stat; | |
868 | ||
869 | spin_lock(&dev->lock); | |
870 | mask = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG); | |
871 | stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG); | |
872 | ||
873 | if (stat & mask) | |
874 | ret = IRQ_WAKE_THREAD; | |
875 | ||
876 | spin_unlock(&dev->lock); | |
877 | ||
878 | return ret; | |
879 | } | |
880 | ||
010d442c | 881 | static irqreturn_t |
3b2f8f82 | 882 | omap_i2c_isr_thread(int this_irq, void *dev_id) |
010d442c KS |
883 | { |
884 | struct omap_i2c_dev *dev = dev_id; | |
3b2f8f82 | 885 | unsigned long flags; |
010d442c | 886 | u16 bits; |
3312d25e | 887 | u16 stat; |
66b92988 | 888 | int err = 0, count = 0; |
010d442c | 889 | |
3b2f8f82 | 890 | spin_lock_irqsave(&dev->lock, flags); |
66b92988 FB |
891 | do { |
892 | bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG); | |
893 | stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG); | |
894 | stat &= bits; | |
895 | ||
079d8af2 FB |
896 | /* If we're in receiver mode, ignore XDR/XRDY */ |
897 | if (dev->receiver) | |
898 | stat &= ~(OMAP_I2C_STAT_XDR | OMAP_I2C_STAT_XRDY); | |
899 | else | |
900 | stat &= ~(OMAP_I2C_STAT_RDR | OMAP_I2C_STAT_RRDY); | |
010d442c | 901 | |
66b92988 FB |
902 | if (!stat) { |
903 | /* my work here is done */ | |
0bdfe0cb | 904 | goto out; |
66b92988 | 905 | } |
f08ac4e7 | 906 | |
010d442c KS |
907 | dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat); |
908 | if (count++ == 100) { | |
909 | dev_warn(dev->dev, "Too much work in one IRQ\n"); | |
910 | break; | |
911 | } | |
912 | ||
1d7afc95 | 913 | if (stat & OMAP_I2C_STAT_NACK) { |
b6ee52c3 | 914 | err |= OMAP_I2C_STAT_NACK; |
1d7afc95 | 915 | omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK); |
0bdfe0cb | 916 | break; |
1d7afc95 | 917 | } |
78e1cf42 | 918 | |
b6ee52c3 NM |
919 | if (stat & OMAP_I2C_STAT_AL) { |
920 | dev_err(dev->dev, "Arbitration lost\n"); | |
921 | err |= OMAP_I2C_STAT_AL; | |
1d7afc95 | 922 | omap_i2c_ack_stat(dev, OMAP_I2C_STAT_AL); |
0bdfe0cb | 923 | break; |
b6ee52c3 | 924 | } |
c55edb99 | 925 | |
a5a595cc | 926 | /* |
cb527ede | 927 | * ProDB0017052: Clear ARDY bit twice |
a5a595cc | 928 | */ |
b6ee52c3 | 929 | if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK | |
04c688dd | 930 | OMAP_I2C_STAT_AL)) { |
540a4790 FB |
931 | omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_RRDY | |
932 | OMAP_I2C_STAT_RDR | | |
933 | OMAP_I2C_STAT_XRDY | | |
934 | OMAP_I2C_STAT_XDR | | |
935 | OMAP_I2C_STAT_ARDY)); | |
0bdfe0cb | 936 | break; |
04c688dd | 937 | } |
c55edb99 | 938 | |
6d9939f6 | 939 | if (stat & OMAP_I2C_STAT_RDR) { |
b6ee52c3 | 940 | u8 num_bytes = 1; |
f3083d92 | 941 | |
6d9939f6 FB |
942 | if (dev->fifo_size) |
943 | num_bytes = dev->buf_len; | |
944 | ||
3312d25e | 945 | omap_i2c_receive_data(dev, num_bytes, true); |
6d9939f6 | 946 | |
f3083d92 | 947 | if (dev->errata & I2C_OMAP_ERRATA_I207) |
948 | i2c_omap_errata_i207(dev, stat); | |
949 | ||
6d9939f6 | 950 | omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR); |
0bdfe0cb | 951 | break; |
6d9939f6 FB |
952 | } |
953 | ||
954 | if (stat & OMAP_I2C_STAT_RRDY) { | |
955 | u8 num_bytes = 1; | |
956 | ||
dd74548d FB |
957 | if (dev->threshold) |
958 | num_bytes = dev->threshold; | |
6d9939f6 | 959 | |
3312d25e | 960 | omap_i2c_receive_data(dev, num_bytes, false); |
6d9939f6 | 961 | omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RRDY); |
010d442c KS |
962 | continue; |
963 | } | |
c55edb99 | 964 | |
6d9939f6 | 965 | if (stat & OMAP_I2C_STAT_XDR) { |
b6ee52c3 | 966 | u8 num_bytes = 1; |
3312d25e | 967 | int ret; |
6d9939f6 FB |
968 | |
969 | if (dev->fifo_size) | |
970 | num_bytes = dev->buf_len; | |
971 | ||
3312d25e | 972 | ret = omap_i2c_transmit_data(dev, num_bytes, true); |
3312d25e | 973 | if (ret < 0) |
0bdfe0cb | 974 | break; |
6d9939f6 FB |
975 | |
976 | omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XDR); | |
0bdfe0cb | 977 | break; |
6d9939f6 FB |
978 | } |
979 | ||
980 | if (stat & OMAP_I2C_STAT_XRDY) { | |
981 | u8 num_bytes = 1; | |
3312d25e | 982 | int ret; |
6d9939f6 | 983 | |
dd74548d FB |
984 | if (dev->threshold) |
985 | num_bytes = dev->threshold; | |
6d9939f6 | 986 | |
3312d25e | 987 | ret = omap_i2c_transmit_data(dev, num_bytes, false); |
3312d25e | 988 | if (ret < 0) |
0bdfe0cb | 989 | break; |
6d9939f6 FB |
990 | |
991 | omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XRDY); | |
010d442c KS |
992 | continue; |
993 | } | |
c55edb99 | 994 | |
010d442c KS |
995 | if (stat & OMAP_I2C_STAT_ROVR) { |
996 | dev_err(dev->dev, "Receive overrun\n"); | |
1d7afc95 FB |
997 | err |= OMAP_I2C_STAT_ROVR; |
998 | omap_i2c_ack_stat(dev, OMAP_I2C_STAT_ROVR); | |
0bdfe0cb | 999 | break; |
010d442c | 1000 | } |
c55edb99 | 1001 | |
010d442c | 1002 | if (stat & OMAP_I2C_STAT_XUDF) { |
b6ee52c3 | 1003 | dev_err(dev->dev, "Transmit underflow\n"); |
1d7afc95 FB |
1004 | err |= OMAP_I2C_STAT_XUDF; |
1005 | omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XUDF); | |
0bdfe0cb | 1006 | break; |
010d442c | 1007 | } |
66b92988 | 1008 | } while (stat); |
010d442c | 1009 | |
4a7ec4ed | 1010 | omap_i2c_complete_cmd(dev, err); |
0bdfe0cb FB |
1011 | |
1012 | out: | |
3b2f8f82 | 1013 | spin_unlock_irqrestore(&dev->lock, flags); |
010d442c | 1014 | |
6a85ced2 | 1015 | return IRQ_HANDLED; |
010d442c KS |
1016 | } |
1017 | ||
8f9082c5 | 1018 | static const struct i2c_algorithm omap_i2c_algo = { |
010d442c KS |
1019 | .master_xfer = omap_i2c_xfer, |
1020 | .functionality = omap_i2c_func, | |
1021 | }; | |
1022 | ||
6145197b BC |
1023 | #ifdef CONFIG_OF |
1024 | static struct omap_i2c_bus_platform_data omap3_pdata = { | |
1025 | .rev = OMAP_I2C_IP_VERSION_1, | |
1026 | .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | | |
1027 | OMAP_I2C_FLAG_RESET_REGS_POSTIDLE | | |
1028 | OMAP_I2C_FLAG_BUS_SHIFT_2, | |
1029 | }; | |
1030 | ||
1031 | static struct omap_i2c_bus_platform_data omap4_pdata = { | |
1032 | .rev = OMAP_I2C_IP_VERSION_2, | |
1033 | }; | |
1034 | ||
1035 | static const struct of_device_id omap_i2c_of_match[] = { | |
1036 | { | |
1037 | .compatible = "ti,omap4-i2c", | |
1038 | .data = &omap4_pdata, | |
1039 | }, | |
1040 | { | |
1041 | .compatible = "ti,omap3-i2c", | |
1042 | .data = &omap3_pdata, | |
1043 | }, | |
1044 | { }, | |
1045 | }; | |
1046 | MODULE_DEVICE_TABLE(of, omap_i2c_of_match); | |
1047 | #endif | |
1048 | ||
1139aea9 | 1049 | static int __devinit |
010d442c KS |
1050 | omap_i2c_probe(struct platform_device *pdev) |
1051 | { | |
1052 | struct omap_i2c_dev *dev; | |
1053 | struct i2c_adapter *adap; | |
ac79e4b2 | 1054 | struct resource *mem; |
c4dba011 UKK |
1055 | const struct omap_i2c_bus_platform_data *pdata = |
1056 | pdev->dev.platform_data; | |
6145197b BC |
1057 | struct device_node *node = pdev->dev.of_node; |
1058 | const struct of_device_id *match; | |
ac79e4b2 | 1059 | int irq; |
010d442c KS |
1060 | int r; |
1061 | ||
1062 | /* NOTE: driver uses the static register mapping */ | |
1063 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1064 | if (!mem) { | |
1065 | dev_err(&pdev->dev, "no mem resource?\n"); | |
1066 | return -ENODEV; | |
1067 | } | |
ac79e4b2 FB |
1068 | |
1069 | irq = platform_get_irq(pdev, 0); | |
1070 | if (irq < 0) { | |
010d442c | 1071 | dev_err(&pdev->dev, "no irq resource?\n"); |
ac79e4b2 | 1072 | return irq; |
010d442c KS |
1073 | } |
1074 | ||
d9ebd04d FB |
1075 | dev = devm_kzalloc(&pdev->dev, sizeof(struct omap_i2c_dev), GFP_KERNEL); |
1076 | if (!dev) { | |
1077 | dev_err(&pdev->dev, "Menory allocation failed\n"); | |
1078 | return -ENOMEM; | |
010d442c KS |
1079 | } |
1080 | ||
d9ebd04d FB |
1081 | dev->base = devm_request_and_ioremap(&pdev->dev, mem); |
1082 | if (!dev->base) { | |
1083 | dev_err(&pdev->dev, "I2C region already claimed\n"); | |
1084 | return -ENOMEM; | |
010d442c KS |
1085 | } |
1086 | ||
6c5aa407 | 1087 | match = of_match_device(of_match_ptr(omap_i2c_of_match), &pdev->dev); |
6145197b BC |
1088 | if (match) { |
1089 | u32 freq = 100000; /* default to 100000 Hz */ | |
1090 | ||
1091 | pdata = match->data; | |
1092 | dev->dtrev = pdata->rev; | |
1093 | dev->flags = pdata->flags; | |
1094 | ||
1095 | of_property_read_u32(node, "clock-frequency", &freq); | |
1096 | /* convert DT freq value in Hz into kHz for speed */ | |
1097 | dev->speed = freq / 1000; | |
1098 | } else if (pdata != NULL) { | |
1099 | dev->speed = pdata->clkrate; | |
1100 | dev->flags = pdata->flags; | |
49839dc9 | 1101 | dev->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat; |
6145197b | 1102 | dev->dtrev = pdata->rev; |
20c9d2c4 | 1103 | } |
4574eb68 | 1104 | |
010d442c | 1105 | dev->dev = &pdev->dev; |
ac79e4b2 | 1106 | dev->irq = irq; |
55c381e4 | 1107 | |
3b2f8f82 | 1108 | spin_lock_init(&dev->lock); |
55c381e4 | 1109 | |
010d442c | 1110 | platform_set_drvdata(pdev, dev); |
0e33bbb2 | 1111 | init_completion(&dev->cmd_complete); |
010d442c | 1112 | |
6145197b | 1113 | dev->reg_shift = (dev->flags >> OMAP_I2C_FLAG_BUS_SHIFT__SHIFT) & 3; |
7c6bd201 | 1114 | |
6145197b | 1115 | if (dev->dtrev == OMAP_I2C_IP_VERSION_2) |
a1295577 | 1116 | dev->regs = (u8 *)reg_map_ip_v2; |
f38e66e0 | 1117 | else |
a1295577 | 1118 | dev->regs = (u8 *)reg_map_ip_v1; |
f38e66e0 | 1119 | |
7f4b08ee | 1120 | pm_runtime_enable(dev->dev); |
6d8451d5 FB |
1121 | pm_runtime_set_autosuspend_delay(dev->dev, OMAP_I2C_PM_TIMEOUT); |
1122 | pm_runtime_use_autosuspend(dev->dev); | |
1123 | ||
3b0fb97c S |
1124 | r = pm_runtime_get_sync(dev->dev); |
1125 | if (IS_ERR_VALUE(r)) | |
1126 | goto err_free_mem; | |
010d442c | 1127 | |
9c76b878 | 1128 | dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff; |
010d442c | 1129 | |
9aa8ec67 TK |
1130 | dev->errata = 0; |
1131 | ||
1132 | if (dev->flags & OMAP_I2C_FLAG_APPLY_ERRATA_I207) | |
1133 | dev->errata |= I2C_OMAP_ERRATA_I207; | |
1134 | ||
f518b482 | 1135 | if (dev->rev <= OMAP_I2C_REV_ON_3430_3530) |
c8db38f0 | 1136 | dev->errata |= I2C_OMAP_ERRATA_I462; |
8a9d97d3 | 1137 | |
6145197b | 1138 | if (!(dev->flags & OMAP_I2C_FLAG_NO_FIFO)) { |
b6ee52c3 NM |
1139 | u16 s; |
1140 | ||
1141 | /* Set up the fifo size - Get total size */ | |
1142 | s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3; | |
1143 | dev->fifo_size = 0x8 << s; | |
1144 | ||
1145 | /* | |
1146 | * Set up notification threshold as half the total available | |
1147 | * size. This is to ensure that we can handle the status on int | |
1148 | * call back latencies. | |
1149 | */ | |
1d5a34fe S |
1150 | |
1151 | dev->fifo_size = (dev->fifo_size / 2); | |
1152 | ||
3ff4443f | 1153 | if (dev->rev < OMAP_I2C_REV_ON_3630_4430) |
f38e66e0 | 1154 | dev->b_hw = 1; /* Enable hardware fixes */ |
1d5a34fe | 1155 | |
20c9d2c4 | 1156 | /* calculate wakeup latency constraint for MPU */ |
49839dc9 PW |
1157 | if (dev->set_mpu_wkup_lat != NULL) |
1158 | dev->latency = (1000000 * dev->fifo_size) / | |
1159 | (1000 * dev->speed / 8); | |
b6ee52c3 NM |
1160 | } |
1161 | ||
010d442c KS |
1162 | /* reset ASAP, clearing any IRQs */ |
1163 | omap_i2c_init(dev); | |
1164 | ||
3b2f8f82 FB |
1165 | if (dev->rev < OMAP_I2C_OMAP1_REV_2) |
1166 | r = devm_request_irq(&pdev->dev, dev->irq, omap_i2c_omap1_isr, | |
1167 | IRQF_NO_SUSPEND, pdev->name, dev); | |
1168 | else | |
1169 | r = devm_request_threaded_irq(&pdev->dev, dev->irq, | |
1170 | omap_i2c_isr, omap_i2c_isr_thread, | |
1171 | IRQF_NO_SUSPEND | IRQF_ONESHOT, | |
1172 | pdev->name, dev); | |
010d442c KS |
1173 | |
1174 | if (r) { | |
1175 | dev_err(dev->dev, "failure requesting irq %i\n", dev->irq); | |
1176 | goto err_unuse_clocks; | |
1177 | } | |
9c76b878 | 1178 | |
010d442c KS |
1179 | adap = &dev->adapter; |
1180 | i2c_set_adapdata(adap, dev); | |
1181 | adap->owner = THIS_MODULE; | |
1182 | adap->class = I2C_CLASS_HWMON; | |
783fd6fa | 1183 | strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name)); |
010d442c KS |
1184 | adap->algo = &omap_i2c_algo; |
1185 | adap->dev.parent = &pdev->dev; | |
6145197b | 1186 | adap->dev.of_node = pdev->dev.of_node; |
010d442c KS |
1187 | |
1188 | /* i2c device drivers may be active on return from add_adapter() */ | |
7c175499 DB |
1189 | adap->nr = pdev->id; |
1190 | r = i2c_add_numbered_adapter(adap); | |
010d442c KS |
1191 | if (r) { |
1192 | dev_err(dev->dev, "failure adding adapter\n"); | |
d9ebd04d | 1193 | goto err_unuse_clocks; |
010d442c KS |
1194 | } |
1195 | ||
c5d3cd6d FV |
1196 | dev_info(dev->dev, "bus %d rev%d.%d.%d at %d kHz\n", adap->nr, |
1197 | dev->dtrev, dev->rev >> 4, dev->rev & 0xf, dev->speed); | |
1198 | ||
6145197b BC |
1199 | of_i2c_register_devices(adap); |
1200 | ||
6d8451d5 FB |
1201 | pm_runtime_mark_last_busy(dev->dev); |
1202 | pm_runtime_put_autosuspend(dev->dev); | |
62ff2c2b | 1203 | |
010d442c KS |
1204 | return 0; |
1205 | ||
010d442c | 1206 | err_unuse_clocks: |
3e39752d | 1207 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); |
fab67afb | 1208 | pm_runtime_put(dev->dev); |
24740516 | 1209 | pm_runtime_disable(&pdev->dev); |
010d442c KS |
1210 | err_free_mem: |
1211 | platform_set_drvdata(pdev, NULL); | |
010d442c KS |
1212 | |
1213 | return r; | |
1214 | } | |
1215 | ||
d790aea7 | 1216 | static int __devexit omap_i2c_remove(struct platform_device *pdev) |
010d442c KS |
1217 | { |
1218 | struct omap_i2c_dev *dev = platform_get_drvdata(pdev); | |
3b0fb97c | 1219 | int ret; |
010d442c KS |
1220 | |
1221 | platform_set_drvdata(pdev, NULL); | |
1222 | ||
010d442c | 1223 | i2c_del_adapter(&dev->adapter); |
3b0fb97c S |
1224 | ret = pm_runtime_get_sync(&pdev->dev); |
1225 | if (IS_ERR_VALUE(ret)) | |
1226 | return ret; | |
1227 | ||
010d442c | 1228 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); |
0861f430 | 1229 | pm_runtime_put(&pdev->dev); |
24740516 | 1230 | pm_runtime_disable(&pdev->dev); |
010d442c KS |
1231 | return 0; |
1232 | } | |
1233 | ||
5692d2a2 | 1234 | #ifdef CONFIG_PM |
fab67afb KH |
1235 | #ifdef CONFIG_PM_RUNTIME |
1236 | static int omap_i2c_runtime_suspend(struct device *dev) | |
1237 | { | |
1238 | struct platform_device *pdev = to_platform_device(dev); | |
1239 | struct omap_i2c_dev *_dev = platform_get_drvdata(pdev); | |
3dae3efb S |
1240 | u16 iv; |
1241 | ||
1242 | _dev->iestate = omap_i2c_read_reg(_dev, OMAP_I2C_IE_REG); | |
bd16c82f S |
1243 | |
1244 | omap_i2c_write_reg(_dev, OMAP_I2C_IE_REG, 0); | |
fab67afb | 1245 | |
3dae3efb S |
1246 | if (_dev->rev < OMAP_I2C_OMAP1_REV_2) { |
1247 | iv = omap_i2c_read_reg(_dev, OMAP_I2C_IV_REG); /* Read clears */ | |
1248 | } else { | |
1249 | omap_i2c_write_reg(_dev, OMAP_I2C_STAT_REG, _dev->iestate); | |
fab67afb | 1250 | |
3dae3efb S |
1251 | /* Flush posted write */ |
1252 | omap_i2c_read_reg(_dev, OMAP_I2C_STAT_REG); | |
1253 | } | |
fab67afb KH |
1254 | |
1255 | return 0; | |
1256 | } | |
1257 | ||
1258 | static int omap_i2c_runtime_resume(struct device *dev) | |
1259 | { | |
1260 | struct platform_device *pdev = to_platform_device(dev); | |
1261 | struct omap_i2c_dev *_dev = platform_get_drvdata(pdev); | |
1262 | ||
3dae3efb S |
1263 | if (_dev->flags & OMAP_I2C_FLAG_RESET_REGS_POSTIDLE) { |
1264 | omap_i2c_write_reg(_dev, OMAP_I2C_CON_REG, 0); | |
1265 | omap_i2c_write_reg(_dev, OMAP_I2C_PSC_REG, _dev->pscstate); | |
1266 | omap_i2c_write_reg(_dev, OMAP_I2C_SCLL_REG, _dev->scllstate); | |
1267 | omap_i2c_write_reg(_dev, OMAP_I2C_SCLH_REG, _dev->sclhstate); | |
1268 | omap_i2c_write_reg(_dev, OMAP_I2C_BUF_REG, _dev->bufstate); | |
1269 | omap_i2c_write_reg(_dev, OMAP_I2C_SYSC_REG, _dev->syscstate); | |
1270 | omap_i2c_write_reg(_dev, OMAP_I2C_WE_REG, _dev->westate); | |
1271 | omap_i2c_write_reg(_dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN); | |
1272 | } | |
1273 | ||
1274 | /* | |
1275 | * Don't write to this register if the IE state is 0 as it can | |
1276 | * cause deadlock. | |
1277 | */ | |
1278 | if (_dev->iestate) | |
1279 | omap_i2c_write_reg(_dev, OMAP_I2C_IE_REG, _dev->iestate); | |
fab67afb KH |
1280 | |
1281 | return 0; | |
1282 | } | |
5692d2a2 | 1283 | #endif /* CONFIG_PM_RUNTIME */ |
fab67afb KH |
1284 | |
1285 | static struct dev_pm_ops omap_i2c_pm_ops = { | |
5692d2a2 S |
1286 | SET_RUNTIME_PM_OPS(omap_i2c_runtime_suspend, |
1287 | omap_i2c_runtime_resume, NULL) | |
fab67afb KH |
1288 | }; |
1289 | #define OMAP_I2C_PM_OPS (&omap_i2c_pm_ops) | |
1290 | #else | |
1291 | #define OMAP_I2C_PM_OPS NULL | |
5692d2a2 | 1292 | #endif /* CONFIG_PM */ |
fab67afb | 1293 | |
010d442c KS |
1294 | static struct platform_driver omap_i2c_driver = { |
1295 | .probe = omap_i2c_probe, | |
d790aea7 | 1296 | .remove = __devexit_p(omap_i2c_remove), |
010d442c | 1297 | .driver = { |
f7bb0d9a | 1298 | .name = "omap_i2c", |
010d442c | 1299 | .owner = THIS_MODULE, |
fab67afb | 1300 | .pm = OMAP_I2C_PM_OPS, |
6145197b | 1301 | .of_match_table = of_match_ptr(omap_i2c_of_match), |
010d442c KS |
1302 | }, |
1303 | }; | |
1304 | ||
1305 | /* I2C may be needed to bring up other drivers */ | |
1306 | static int __init | |
1307 | omap_i2c_init_driver(void) | |
1308 | { | |
1309 | return platform_driver_register(&omap_i2c_driver); | |
1310 | } | |
1311 | subsys_initcall(omap_i2c_init_driver); | |
1312 | ||
1313 | static void __exit omap_i2c_exit_driver(void) | |
1314 | { | |
1315 | platform_driver_unregister(&omap_i2c_driver); | |
1316 | } | |
1317 | module_exit(omap_i2c_exit_driver); | |
1318 | ||
1319 | MODULE_AUTHOR("MontaVista Software, Inc. (and others)"); | |
1320 | MODULE_DESCRIPTION("TI OMAP I2C bus adapter"); | |
1321 | MODULE_LICENSE("GPL"); | |
f7bb0d9a | 1322 | MODULE_ALIAS("platform:omap_i2c"); |