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i2c: omap: simplify errata check
[linux-2.6-block.git] / drivers / i2c / busses / i2c-omap.c
CommitLineData
010d442c
KS		 1/*
2 * TI OMAP I2C master mode driver
3 *
4 * Copyright (C) 2003 MontaVista Software, Inc.
010d442c 5 * Copyright (C) 2005 Nokia Corporation
c1a473bd 6 * Copyright (C) 2004 - 2007 Texas Instruments.
010d442c 7 *
c1a473bd
TL		 8 * Originally written by MontaVista Software, Inc.
9 * Additional contributions by:
10 * Tony Lindgren <tony@atomide.com>
11 * Imre Deak <imre.deak@nokia.com>
12 * Juha Yrjölä <juha.yrjola@solidboot.com>
13 * Syed Khasim <x0khasim@ti.com>
14 * Nishant Menon <nm@ti.com>
010d442c
KS		 15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30
31#include <linux/module.h>
32#include <linux/delay.h>
33#include <linux/i2c.h>
34#include <linux/err.h>
35#include <linux/interrupt.h>
36#include <linux/completion.h>
37#include <linux/platform_device.h>
38#include <linux/clk.h>
c1a473bd 39#include <linux/io.h>
6145197b
BC		 40#include <linux/of.h>
41#include <linux/of_i2c.h>
42#include <linux/of_device.h>
5a0e3ad6 43#include <linux/slab.h>
20c9d2c4 44#include <linux/i2c-omap.h>
27b1fec2 45#include <linux/pm_runtime.h>
010d442c 46
9c76b878 47/* I2C controller revisions */
4e80f727 48#define OMAP_I2C_OMAP1_REV_2 0x20
9c76b878
PW		 49
50/* I2C controller revisions present on specific hardware */
51#define OMAP_I2C_REV_ON_2430 0x36
f518b482
JH		 52#define OMAP_I2C_REV_ON_3430_3530 0x3C
53#define OMAP_I2C_REV_ON_3630_4430 0x40
9c76b878 54
010d442c
KS		 55/* timeout waiting for the controller to respond */
56#define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
57
5043e9e7 58/* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
f38e66e0
SS		 59enum {
60 OMAP_I2C_REV_REG = 0,
61 OMAP_I2C_IE_REG,
62 OMAP_I2C_STAT_REG,
63 OMAP_I2C_IV_REG,
64 OMAP_I2C_WE_REG,
65 OMAP_I2C_SYSS_REG,
66 OMAP_I2C_BUF_REG,
67 OMAP_I2C_CNT_REG,
68 OMAP_I2C_DATA_REG,
69 OMAP_I2C_SYSC_REG,
70 OMAP_I2C_CON_REG,
71 OMAP_I2C_OA_REG,
72 OMAP_I2C_SA_REG,
73 OMAP_I2C_PSC_REG,
74 OMAP_I2C_SCLL_REG,
75 OMAP_I2C_SCLH_REG,
76 OMAP_I2C_SYSTEST_REG,
77 OMAP_I2C_BUFSTAT_REG,
b8853088
AG		 78 /* only on OMAP4430 */
79 OMAP_I2C_IP_V2_REVNB_LO,
80 OMAP_I2C_IP_V2_REVNB_HI,
81 OMAP_I2C_IP_V2_IRQSTATUS_RAW,
82 OMAP_I2C_IP_V2_IRQENABLE_SET,
83 OMAP_I2C_IP_V2_IRQENABLE_CLR,
f38e66e0 84};
010d442c
KS		 85
86/* I2C Interrupt Enable Register (OMAP_I2C_IE): */
b6ee52c3
NM		 87#define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */
88#define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */
010d442c
KS		 89#define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */
90#define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */
91#define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */
92#define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */
93#define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */
94
95/* I2C Status Register (OMAP_I2C_STAT): */
b6ee52c3
NM		 96#define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */
97#define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */
010d442c
KS		 98#define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */
99#define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */
100#define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
101#define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */
102#define OMAP_I2C_STAT_AD0 (1 << 8) /* Address zero */
103#define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
104#define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */
105#define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */
106#define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */
107#define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */
108
5043e9e7
KJ		 109/* I2C WE wakeup enable register */
110#define OMAP_I2C_WE_XDR_WE (1 << 14) /* TX drain wakup */
111#define OMAP_I2C_WE_RDR_WE (1 << 13) /* RX drain wakeup */
112#define OMAP_I2C_WE_AAS_WE (1 << 9) /* Address as slave wakeup*/
113#define OMAP_I2C_WE_BF_WE (1 << 8) /* Bus free wakeup */
114#define OMAP_I2C_WE_STC_WE (1 << 6) /* Start condition wakeup */
115#define OMAP_I2C_WE_GC_WE (1 << 5) /* General call wakeup */
116#define OMAP_I2C_WE_DRDY_WE (1 << 3) /* TX/RX data ready wakeup */
117#define OMAP_I2C_WE_ARDY_WE (1 << 2) /* Reg access ready wakeup */
118#define OMAP_I2C_WE_NACK_WE (1 << 1) /* No acknowledgment wakeup */
119#define OMAP_I2C_WE_AL_WE (1 << 0) /* Arbitration lost wakeup */
120
121#define OMAP_I2C_WE_ALL (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \
122 OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \
123 OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \
124 OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \
125 OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE)
126
010d442c
KS		 127/* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
128#define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */
b6ee52c3 129#define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */
010d442c 130#define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */
b6ee52c3 131#define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */
010d442c
KS		 132
133/* I2C Configuration Register (OMAP_I2C_CON): */
134#define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */
135#define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */
b6ee52c3 136#define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */
010d442c
KS		 137#define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */
138#define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */
139#define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */
140#define OMAP_I2C_CON_XA (1 << 8) /* Expand address */
141#define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */
142#define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */
143#define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */
144
4574eb68
SMK		 145/* I2C SCL time value when Master */
146#define OMAP_I2C_SCLL_HSSCLL 8
147#define OMAP_I2C_SCLH_HSSCLH 8
148
010d442c
KS		 149/* I2C System Test Register (OMAP_I2C_SYSTEST): */
150#ifdef DEBUG
151#define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
152#define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */
153#define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
154#define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
155#define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */
156#define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */
157#define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */
158#define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */
159#endif
160
fdd07fe6
PW		 161/* OCP_SYSSTATUS bit definitions */
162#define SYSS_RESETDONE_MASK (1 << 0)
163
164/* OCP_SYSCONFIG bit definitions */
165#define SYSC_CLOCKACTIVITY_MASK (0x3 << 8)
166#define SYSC_SIDLEMODE_MASK (0x3 << 3)
167#define SYSC_ENAWAKEUP_MASK (1 << 2)
168#define SYSC_SOFTRESET_MASK (1 << 1)
169#define SYSC_AUTOIDLE_MASK (1 << 0)
170
171#define SYSC_IDLEMODE_SMART 0x2
172#define SYSC_CLOCKACTIVITY_FCLK 0x2
010d442c 173
f3083d92 174/* Errata definitions */
175#define I2C_OMAP_ERRATA_I207 (1 << 0)
c8db38f0 176#define I2C_OMAP_ERRATA_I462 (1 << 1)
010d442c 177
010d442c
KS		 178struct omap_i2c_dev {
179 struct device *dev;
180 void __iomem *base; /* virtual */
181 int irq;
d84d3ea3 182 int reg_shift; /* bit shift for I2C register addresses */
010d442c
KS		 183 struct completion cmd_complete;
184 struct resource *ioarea;
20c9d2c4
KJ		 185 u32 latency; /* maximum mpu wkup latency */
186 void (*set_mpu_wkup_lat)(struct device *dev,
187 long latency);
6145197b
BC		 188 u32 speed; /* Speed of bus in kHz */
189 u32 dtrev; /* extra revision from DT */
190 u32 flags;
010d442c
KS		 191 u16 cmd_err;
192 u8 *buf;
f38e66e0 193 u8 *regs;
010d442c
KS		 194 size_t buf_len;
195 struct i2c_adapter adapter;
b6ee52c3
NM		 196 u8 fifo_size; /* use as flag and value
197 * fifo_size==0 implies no fifo
198 * if set, should be trsh+1
199 */
9c76b878 200 u8 rev;
b6ee52c3 201 unsigned b_hw:1; /* bad h/w fixes */
079d8af2 202 unsigned receiver:1; /* true when we're in receiver mode */
f08ac4e7 203 u16 iestate; /* Saved interrupt register */
ef871432
RN		 204 u16 pscstate;
205 u16 scllstate;
206 u16 sclhstate;
207 u16 bufstate;
208 u16 syscstate;
209 u16 westate;
f3083d92 210 u16 errata;
010d442c
KS		 211};
212
a1295577 213static const u8 reg_map_ip_v1[] = {
f38e66e0
SS		 214 [OMAP_I2C_REV_REG] = 0x00,
215 [OMAP_I2C_IE_REG] = 0x01,
216 [OMAP_I2C_STAT_REG] = 0x02,
217 [OMAP_I2C_IV_REG] = 0x03,
218 [OMAP_I2C_WE_REG] = 0x03,
219 [OMAP_I2C_SYSS_REG] = 0x04,
220 [OMAP_I2C_BUF_REG] = 0x05,
221 [OMAP_I2C_CNT_REG] = 0x06,
222 [OMAP_I2C_DATA_REG] = 0x07,
223 [OMAP_I2C_SYSC_REG] = 0x08,
224 [OMAP_I2C_CON_REG] = 0x09,
225 [OMAP_I2C_OA_REG] = 0x0a,
226 [OMAP_I2C_SA_REG] = 0x0b,
227 [OMAP_I2C_PSC_REG] = 0x0c,
228 [OMAP_I2C_SCLL_REG] = 0x0d,
229 [OMAP_I2C_SCLH_REG] = 0x0e,
230 [OMAP_I2C_SYSTEST_REG] = 0x0f,
231 [OMAP_I2C_BUFSTAT_REG] = 0x10,
232};
233
a1295577 234static const u8 reg_map_ip_v2[] = {
f38e66e0
SS		 235 [OMAP_I2C_REV_REG] = 0x04,
236 [OMAP_I2C_IE_REG] = 0x2c,
237 [OMAP_I2C_STAT_REG] = 0x28,
238 [OMAP_I2C_IV_REG] = 0x34,
239 [OMAP_I2C_WE_REG] = 0x34,
240 [OMAP_I2C_SYSS_REG] = 0x90,
241 [OMAP_I2C_BUF_REG] = 0x94,
242 [OMAP_I2C_CNT_REG] = 0x98,
243 [OMAP_I2C_DATA_REG] = 0x9c,
2727b175 244 [OMAP_I2C_SYSC_REG] = 0x10,
f38e66e0
SS		 245 [OMAP_I2C_CON_REG] = 0xa4,
246 [OMAP_I2C_OA_REG] = 0xa8,
247 [OMAP_I2C_SA_REG] = 0xac,
248 [OMAP_I2C_PSC_REG] = 0xb0,
249 [OMAP_I2C_SCLL_REG] = 0xb4,
250 [OMAP_I2C_SCLH_REG] = 0xb8,
251 [OMAP_I2C_SYSTEST_REG] = 0xbC,
252 [OMAP_I2C_BUFSTAT_REG] = 0xc0,
b8853088
AG		 253 [OMAP_I2C_IP_V2_REVNB_LO] = 0x00,
254 [OMAP_I2C_IP_V2_REVNB_HI] = 0x04,
255 [OMAP_I2C_IP_V2_IRQSTATUS_RAW] = 0x24,
256 [OMAP_I2C_IP_V2_IRQENABLE_SET] = 0x2c,
257 [OMAP_I2C_IP_V2_IRQENABLE_CLR] = 0x30,
f38e66e0
SS		 258};
259
010d442c
KS		 260static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
261 int reg, u16 val)
262{
f38e66e0
SS		 263 __raw_writew(val, i2c_dev->base +
264 (i2c_dev->regs[reg] << i2c_dev->reg_shift));
010d442c
KS		 265}
266
267static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
268{
f38e66e0
SS		 269 return __raw_readw(i2c_dev->base +
270 (i2c_dev->regs[reg] << i2c_dev->reg_shift));
010d442c
KS		 271}
272
010d442c
KS		 273static int omap_i2c_init(struct omap_i2c_dev *dev)
274{
ef871432 275 u16 psc = 0, scll = 0, sclh = 0, buf = 0;
4574eb68 276 u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
010d442c
KS		 277 unsigned long fclk_rate = 12000000;
278 unsigned long timeout;
4574eb68 279 unsigned long internal_clk = 0;
27b1fec2 280 struct clk *fclk;
010d442c 281
4e80f727 282 if (dev->rev >= OMAP_I2C_OMAP1_REV_2) {
57eb81b1
MG		 283 /* Disable I2C controller before soft reset */
284 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
285 omap_i2c_read_reg(dev, OMAP_I2C_CON_REG) &
286 ~(OMAP_I2C_CON_EN));
287
fdd07fe6 288 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK);
010d442c
KS		 289 /* For some reason we need to set the EN bit before the
290 * reset done bit gets set. */
291 timeout = jiffies + OMAP_I2C_TIMEOUT;
292 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
293 while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
fdd07fe6 294 SYSS_RESETDONE_MASK)) {
010d442c 295 if (time_after(jiffies, timeout)) {
fce3ff03 296 dev_warn(dev->dev, "timeout waiting "
010d442c
KS		 297 "for controller reset\n");
298 return -ETIMEDOUT;
299 }
300 msleep(1);
301 }
fdd07fe6
PW		 302
303 /* SYSC register is cleared by the reset; rewrite it */
304 if (dev->rev == OMAP_I2C_REV_ON_2430) {
305
306 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
307 SYSC_AUTOIDLE_MASK);
308
f518b482 309 } else if (dev->rev >= OMAP_I2C_REV_ON_3430_3530) {
ef871432
RN		 310 dev->syscstate = SYSC_AUTOIDLE_MASK;
311 dev->syscstate |= SYSC_ENAWAKEUP_MASK;
312 dev->syscstate |= (SYSC_IDLEMODE_SMART <<
fdd07fe6 313 __ffs(SYSC_SIDLEMODE_MASK));
ef871432 314 dev->syscstate |= (SYSC_CLOCKACTIVITY_FCLK <<
fdd07fe6
PW		 315 __ffs(SYSC_CLOCKACTIVITY_MASK));
316
ef871432
RN		 317 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
318 dev->syscstate);
5043e9e7
KJ		 319 /*
320 * Enabling all wakup sources to stop I2C freezing on
321 * WFI instruction.
322 * REVISIT: Some wkup sources might not be needed.
323 */
ef871432 324 dev->westate = OMAP_I2C_WE_ALL;
cb28e582
S		 325 omap_i2c_write_reg(dev, OMAP_I2C_WE_REG,
326 dev->westate);
fdd07fe6 327 }
010d442c
KS		 328 }
329 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
330
6145197b 331 if (dev->flags & OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK) {
0e9ae109
RK		 332 /*
333 * The I2C functional clock is the armxor_ck, so there's
334 * no need to get "armxor_ck" separately. Now, if OMAP2420
335 * always returns 12MHz for the functional clock, we can
336 * do this bit unconditionally.
337 */
27b1fec2
RN		 338 fclk = clk_get(dev->dev, "fck");
339 fclk_rate = clk_get_rate(fclk);
340 clk_put(fclk);
0e9ae109 341
010d442c
KS		 342 /* TRM for 5912 says the I2C clock must be prescaled to be
343 * between 7 - 12 MHz. The XOR input clock is typically
344 * 12, 13 or 19.2 MHz. So we should have code that produces:
345 *
346 * XOR MHz Divider Prescaler
347 * 12 1 0
348 * 13 2 1
349 * 19.2 2 1
350 */
d7aef138
JD		 351 if (fclk_rate > 12000000)
352 psc = fclk_rate / 12000000;
010d442c
KS		 353 }
354
6145197b 355 if (!(dev->flags & OMAP_I2C_FLAG_SIMPLE_CLOCK)) {
4574eb68 356
84bf2c86
AK		 357 /*
358 * HSI2C controller internal clk rate should be 19.2 Mhz for
359 * HS and for all modes on 2430. On 34xx we can use lower rate
360 * to get longer filter period for better noise suppression.
361 * The filter is iclk (fclk for HS) period.
362 */
3be0053e 363 if (dev->speed > 400 ||
6145197b 364 dev->flags & OMAP_I2C_FLAG_FORCE_19200_INT_CLK)
84bf2c86
AK		 365 internal_clk = 19200;
366 else if (dev->speed > 100)
367 internal_clk = 9600;
368 else
369 internal_clk = 4000;
27b1fec2
RN		 370 fclk = clk_get(dev->dev, "fck");
371 fclk_rate = clk_get_rate(fclk) / 1000;
372 clk_put(fclk);
4574eb68
SMK		 373
374 /* Compute prescaler divisor */
375 psc = fclk_rate / internal_clk;
376 psc = psc - 1;
377
378 /* If configured for High Speed */
379 if (dev->speed > 400) {
baf46b4e
AK		 380 unsigned long scl;
381
4574eb68 382 /* For first phase of HS mode */
baf46b4e
AK		 383 scl = internal_clk / 400;
384 fsscll = scl - (scl / 3) - 7;
385 fssclh = (scl / 3) - 5;
4574eb68
SMK		 386
387 /* For second phase of HS mode */
baf46b4e
AK		 388 scl = fclk_rate / dev->speed;
389 hsscll = scl - (scl / 3) - 7;
390 hssclh = (scl / 3) - 5;
391 } else if (dev->speed > 100) {
392 unsigned long scl;
393
394 /* Fast mode */
395 scl = internal_clk / dev->speed;
396 fsscll = scl - (scl / 3) - 7;
397 fssclh = (scl / 3) - 5;
4574eb68 398 } else {
baf46b4e
AK		 399 /* Standard mode */
400 fsscll = internal_clk / (dev->speed * 2) - 7;
401 fssclh = internal_clk / (dev->speed * 2) - 5;
4574eb68
SMK		 402 }
403 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
404 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
405 } else {
406 /* Program desired operating rate */
407 fclk_rate /= (psc + 1) * 1000;
408 if (psc > 2)
409 psc = 2;
410 scll = fclk_rate / (dev->speed * 2) - 7 + psc;
411 sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
412 }
413
010d442c
KS		 414 /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
415 omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);
416
4574eb68
SMK		 417 /* SCL low and high time values */
418 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll);
419 omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh);
010d442c 420
ef871432
RN		 421 if (dev->fifo_size) {
422 /* Note: setup required fifo size - 1. RTRSH and XTRSH */
423 buf = (dev->fifo_size - 1) << 8 | OMAP_I2C_BUF_RXFIF_CLR |
424 (dev->fifo_size - 1) | OMAP_I2C_BUF_TXFIF_CLR;
425 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, buf);
426 }
b6ee52c3 427
010d442c
KS		 428 /* Take the I2C module out of reset: */
429 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
430
431 /* Enable interrupts */
ef871432 432 dev->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
c1a473bd
TL		 433 OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
434 OMAP_I2C_IE_AL) | ((dev->fifo_size) ?
ef871432
RN		 435 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0);
436 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
6145197b 437 if (dev->flags & OMAP_I2C_FLAG_RESET_REGS_POSTIDLE) {
ef871432
RN		 438 dev->pscstate = psc;
439 dev->scllstate = scll;
440 dev->sclhstate = sclh;
441 dev->bufstate = buf;
442 }
010d442c
KS		 443 return 0;
444}
445
446/*
447 * Waiting on Bus Busy
448 */
449static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
450{
451 unsigned long timeout;
452
453 timeout = jiffies + OMAP_I2C_TIMEOUT;
454 while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
455 if (time_after(jiffies, timeout)) {
456 dev_warn(dev->dev, "timeout waiting for bus ready\n");
457 return -ETIMEDOUT;
458 }
459 msleep(1);
460 }
461
462 return 0;
463}
464
465/*
466 * Low level master read/write transaction.
467 */
468static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
469 struct i2c_msg *msg, int stop)
470{
471 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
33d54985 472 unsigned long timeout;
010d442c
KS		 473 u16 w;
474
475 dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
476 msg->addr, msg->len, msg->flags, stop);
477
478 if (msg->len == 0)
479 return -EINVAL;
480
481 omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
482
483 /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
484 dev->buf = msg->buf;
485 dev->buf_len = msg->len;
486
487 omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
488
b6ee52c3
NM		 489 /* Clear the FIFO Buffers */
490 w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
491 w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
492 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w);
493
0e33bbb2 494 INIT_COMPLETION(dev->cmd_complete);
010d442c 495 dev->cmd_err = 0;
079d8af2 496 dev->receiver = !!(msg->flags & I2C_M_RD);
010d442c
KS		 497
498 w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
4574eb68
SMK		 499
500 /* High speed configuration */
501 if (dev->speed > 400)
b6ee52c3 502 w |= OMAP_I2C_CON_OPMODE_HS;
4574eb68 503
fb604a3d
LP		 504 if (msg->flags & I2C_M_STOP)
505 stop = 1;
010d442c
KS		 506 if (msg->flags & I2C_M_TEN)
507 w |= OMAP_I2C_CON_XA;
508 if (!(msg->flags & I2C_M_RD))
509 w |= OMAP_I2C_CON_TRX;
c1a473bd 510
b6ee52c3 511 if (!dev->b_hw && stop)
010d442c 512 w |= OMAP_I2C_CON_STP;
c1a473bd 513
010d442c
KS		 514 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
515
b6ee52c3
NM		 516 /*
517 * Don't write stt and stp together on some hardware.
518 */
519 if (dev->b_hw && stop) {
520 unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
521 u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
522 while (con & OMAP_I2C_CON_STT) {
523 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
524
525 /* Let the user know if i2c is in a bad state */
526 if (time_after(jiffies, delay)) {
527 dev_err(dev->dev, "controller timed out "
528 "waiting for start condition to finish\n");
529 return -ETIMEDOUT;
530 }
531 cpu_relax();
532 }
533
534 w |= OMAP_I2C_CON_STP;
535 w &= ~OMAP_I2C_CON_STT;
536 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
537 }
538
b7af349b
JN		 539 /*
540 * REVISIT: We should abort the transfer on signals, but the bus goes
541 * into arbitration and we're currently unable to recover from it.
542 */
33d54985
S		 543 timeout = wait_for_completion_timeout(&dev->cmd_complete,
544 OMAP_I2C_TIMEOUT);
010d442c 545 dev->buf_len = 0;
33d54985 546 if (timeout == 0) {
010d442c
KS		 547 dev_err(dev->dev, "controller timed out\n");
548 omap_i2c_init(dev);
549 return -ETIMEDOUT;
550 }
551
552 if (likely(!dev->cmd_err))
553 return 0;
554
555 /* We have an error */
556 if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
557 OMAP_I2C_STAT_XUDF)) {
558 omap_i2c_init(dev);
559 return -EIO;
560 }
561
562 if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
563 if (msg->flags & I2C_M_IGNORE_NAK)
564 return 0;
565 if (stop) {
566 w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
567 w |= OMAP_I2C_CON_STP;
568 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
569 }
570 return -EREMOTEIO;
571 }
572 return -EIO;
573}
574
575
576/*
577 * Prepare controller for a transaction and call omap_i2c_xfer_msg
578 * to do the work during IRQ processing.
579 */
580static int
581omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
582{
583 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
584 int i;
585 int r;
586
3b0fb97c
S		 587 r = pm_runtime_get_sync(dev->dev);
588 if (IS_ERR_VALUE(r))
33ec5e81 589 goto out;
010d442c 590
c1a473bd
TL		 591 r = omap_i2c_wait_for_bb(dev);
592 if (r < 0)
010d442c
KS		 593 goto out;
594
6a91b558
SO		 595 if (dev->set_mpu_wkup_lat != NULL)
596 dev->set_mpu_wkup_lat(dev->dev, dev->latency);
597
010d442c
KS		 598 for (i = 0; i < num; i++) {
599 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
600 if (r != 0)
601 break;
602 }
603
6a91b558
SO		 604 if (dev->set_mpu_wkup_lat != NULL)
605 dev->set_mpu_wkup_lat(dev->dev, -1);
606
010d442c
KS		 607 if (r == 0)
608 r = num;
5c64eb26
MN		 609
610 omap_i2c_wait_for_bb(dev);
010d442c 611out:
fab67afb 612 pm_runtime_put(dev->dev);
010d442c
KS		 613 return r;
614}
615
616static u32
617omap_i2c_func(struct i2c_adapter *adap)
618{
fb604a3d
LP		 619 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
620 I2C_FUNC_PROTOCOL_MANGLING;
010d442c
KS		 621}
622
623static inline void
624omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)
625{
626 dev->cmd_err |= err;
627 complete(&dev->cmd_complete);
628}
629
630static inline void
631omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
632{
633 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
634}
635
f3083d92 636static inline void i2c_omap_errata_i207(struct omap_i2c_dev *dev, u16 stat)
637{
638 /*
639 * I2C Errata(Errata Nos. OMAP2: 1.67, OMAP3: 1.8)
640 * Not applicable for OMAP4.
641 * Under certain rare conditions, RDR could be set again
642 * when the bus is busy, then ignore the interrupt and
643 * clear the interrupt.
644 */
645 if (stat & OMAP_I2C_STAT_RDR) {
646 /* Step 1: If RDR is set, clear it */
647 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
648
649 /* Step 2: */
650 if (!(omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG)
651 & OMAP_I2C_STAT_BB)) {
652
653 /* Step 3: */
654 if (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG)
655 & OMAP_I2C_STAT_RDR) {
656 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
657 dev_dbg(dev->dev, "RDR when bus is busy.\n");
658 }
659
660 }
661 }
662}
663
43469d8e
PW		 664/* rev1 devices are apparently only on some 15xx */
665#ifdef CONFIG_ARCH_OMAP15XX
666
010d442c 667static irqreturn_t
4e80f727 668omap_i2c_omap1_isr(int this_irq, void *dev_id)
010d442c
KS		 669{
670 struct omap_i2c_dev *dev = dev_id;
671 u16 iv, w;
672
fab67afb 673 if (pm_runtime_suspended(dev->dev))
f08ac4e7
TL		 674 return IRQ_NONE;
675
010d442c
KS		 676 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
677 switch (iv) {
678 case 0x00: /* None */
679 break;
680 case 0x01: /* Arbitration lost */
681 dev_err(dev->dev, "Arbitration lost\n");
682 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
683 break;
684 case 0x02: /* No acknowledgement */
685 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
686 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
687 break;
688 case 0x03: /* Register access ready */
689 omap_i2c_complete_cmd(dev, 0);
690 break;
691 case 0x04: /* Receive data ready */
692 if (dev->buf_len) {
693 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
694 *dev->buf++ = w;
695 dev->buf_len--;
696 if (dev->buf_len) {
697 *dev->buf++ = w >> 8;
698 dev->buf_len--;
699 }
700 } else
701 dev_err(dev->dev, "RRDY IRQ while no data requested\n");
702 break;
703 case 0x05: /* Transmit data ready */
704 if (dev->buf_len) {
705 w = *dev->buf++;
706 dev->buf_len--;
707 if (dev->buf_len) {
708 w |= *dev->buf++ << 8;
709 dev->buf_len--;
710 }
711 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
712 } else
713 dev_err(dev->dev, "XRDY IRQ while no data to send\n");
714 break;
715 default:
716 return IRQ_NONE;
717 }
718
719 return IRQ_HANDLED;
720}
43469d8e 721#else
4e80f727 722#define omap_i2c_omap1_isr NULL
43469d8e 723#endif
010d442c 724
2dd151ab 725/*
c8db38f0 726 * OMAP3430 Errata i462: When an XRDY/XDR is hit, wait for XUDF before writing
2dd151ab
AS		 727 * data to DATA_REG. Otherwise some data bytes can be lost while transferring
728 * them from the memory to the I2C interface.
729 */
4151e741 730static int errata_omap3_i462(struct omap_i2c_dev *dev)
2dd151ab 731{
e9f59b9c 732 unsigned long timeout = 10000;
4151e741 733 u16 stat;
e9f59b9c 734
4151e741
FB		 735 do {
736 stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
737 if (stat & OMAP_I2C_STAT_XUDF)
738 break;
739
740 if (stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
540a4790 741 omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_XRDY |
2dd151ab 742 OMAP_I2C_STAT_XDR));
4151e741 743 return -EIO;
2dd151ab 744 }
e9f59b9c 745
2dd151ab 746 cpu_relax();
4151e741 747 } while (--timeout);
2dd151ab 748
e9f59b9c
AS		 749 if (!timeout) {
750 dev_err(dev->dev, "timeout waiting on XUDF bit\n");
751 return 0;
752 }
753
2dd151ab
AS		 754 return 0;
755}
756
3312d25e
FB		 757static void omap_i2c_receive_data(struct omap_i2c_dev *dev, u8 num_bytes,
758 bool is_rdr)
759{
760 u16 w;
761
762 while (num_bytes--) {
763 if (!dev->buf_len) {
764 dev_err(dev->dev, "%s without data",
765 is_rdr ? "RDR" : "RRDY");
766 break;
767 }
768
769 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
770 *dev->buf++ = w;
771 dev->buf_len--;
772
773 /*
774 * Data reg in 2430, omap3 and
775 * omap4 is 8 bit wide
776 */
777 if (dev->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
778 if (dev->buf_len) {
779 *dev->buf++ = w >> 8;
780 dev->buf_len--;
781 }
782 }
783 }
784}
785
786static int omap_i2c_transmit_data(struct omap_i2c_dev *dev, u8 num_bytes,
787 bool is_xdr)
788{
789 u16 w;
790
791 while (num_bytes--) {
792 if (!dev->buf_len) {
793 dev_err(dev->dev, "%s without data",
794 is_xdr ? "XDR" : "XRDY");
795 break;
796 }
797
798 w = *dev->buf++;
799 dev->buf_len--;
800
801 /*
802 * Data reg in 2430, omap3 and
803 * omap4 is 8 bit wide
804 */
805 if (dev->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
806 if (dev->buf_len) {
807 w |= *dev->buf++ << 8;
808 dev->buf_len--;
809 }
810 }
811
812 if (dev->errata & I2C_OMAP_ERRATA_I462) {
813 int ret;
814
815 ret = errata_omap3_i462(dev);
816 if (ret < 0)
817 return ret;
818 }
819
820 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
821 }
822
823 return 0;
824}
825
010d442c 826static irqreturn_t
7d12e780 827omap_i2c_isr(int this_irq, void *dev_id)
010d442c
KS		 828{
829 struct omap_i2c_dev *dev = dev_id;
830 u16 bits;
3312d25e 831 u16 stat;
66b92988 832 int err = 0, count = 0;
010d442c 833
fab67afb 834 if (pm_runtime_suspended(dev->dev))
f08ac4e7
TL		 835 return IRQ_NONE;
836
66b92988
FB		 837 do {
838 bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
839 stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
840 stat &= bits;
841
079d8af2
FB		 842 /* If we're in receiver mode, ignore XDR/XRDY */
843 if (dev->receiver)
844 stat &= ~(OMAP_I2C_STAT_XDR | OMAP_I2C_STAT_XRDY);
845 else
846 stat &= ~(OMAP_I2C_STAT_RDR | OMAP_I2C_STAT_RRDY);
847
66b92988
FB		 848 if (!stat) {
849 /* my work here is done */
850 return IRQ_HANDLED;
851 }
852
010d442c
KS		 853 dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
854 if (count++ == 100) {
855 dev_warn(dev->dev, "Too much work in one IRQ\n");
66b92988
FB		 856 omap_i2c_complete_cmd(dev, err);
857 return IRQ_HANDLED;
010d442c
KS		 858 }
859
cd086d3a 860complete:
1d7afc95 861 if (stat & OMAP_I2C_STAT_NACK) {
b6ee52c3 862 err |= OMAP_I2C_STAT_NACK;
1d7afc95
FB		 863 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK);
864 omap_i2c_complete_cmd(dev, err);
865 return IRQ_HANDLED;
866 }
78e1cf42 867
b6ee52c3
NM		 868 if (stat & OMAP_I2C_STAT_AL) {
869 dev_err(dev->dev, "Arbitration lost\n");
870 err |= OMAP_I2C_STAT_AL;
1d7afc95
FB		 871 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_AL);
872 omap_i2c_complete_cmd(dev, err);
873 return IRQ_HANDLED;
b6ee52c3 874 }
c55edb99 875
a5a595cc 876 /*
cb527ede 877 * ProDB0017052: Clear ARDY bit twice
a5a595cc 878 */
b6ee52c3 879 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
04c688dd 880 OMAP_I2C_STAT_AL)) {
540a4790
FB		 881 omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_RRDY |
882 OMAP_I2C_STAT_RDR |
883 OMAP_I2C_STAT_XRDY |
884 OMAP_I2C_STAT_XDR |
885 OMAP_I2C_STAT_ARDY));
b6ee52c3 886 omap_i2c_complete_cmd(dev, err);
04c688dd
SM		 887 return IRQ_HANDLED;
888 }
c55edb99 889
6d9939f6 890 if (stat & OMAP_I2C_STAT_RDR) {
b6ee52c3 891 u8 num_bytes = 1;
f3083d92 892
6d9939f6
FB		 893 if (dev->fifo_size)
894 num_bytes = dev->buf_len;
895
3312d25e 896 omap_i2c_receive_data(dev, num_bytes, true);
6d9939f6 897
f3083d92 898 if (dev->errata & I2C_OMAP_ERRATA_I207)
899 i2c_omap_errata_i207(dev, stat);
900
6d9939f6
FB		 901 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
902 continue;
903 }
904
905 if (stat & OMAP_I2C_STAT_RRDY) {
906 u8 num_bytes = 1;
907
908 if (dev->fifo_size)
909 num_bytes = dev->fifo_size;
910
3312d25e 911 omap_i2c_receive_data(dev, num_bytes, false);
6d9939f6 912 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RRDY);
010d442c
KS		 913 continue;
914 }
c55edb99 915
6d9939f6 916 if (stat & OMAP_I2C_STAT_XDR) {
b6ee52c3 917 u8 num_bytes = 1;
3312d25e 918 int ret;
6d9939f6
FB		 919
920 if (dev->fifo_size)
921 num_bytes = dev->buf_len;
922
3312d25e
FB		 923 ret = omap_i2c_transmit_data(dev, num_bytes, true);
924 stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
925 if (ret < 0)
926 goto complete;
6d9939f6
FB		 927
928 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XDR);
929 continue;
930 }
931
932 if (stat & OMAP_I2C_STAT_XRDY) {
933 u8 num_bytes = 1;
3312d25e 934 int ret;
6d9939f6
FB		 935
936 if (dev->fifo_size)
937 num_bytes = dev->fifo_size;
938
3312d25e
FB		 939 ret = omap_i2c_transmit_data(dev, num_bytes, false);
940 stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
941 if (ret < 0)
942 goto complete;
6d9939f6
FB		 943
944 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XRDY);
010d442c
KS		 945 continue;
946 }
c55edb99 947
010d442c
KS		 948 if (stat & OMAP_I2C_STAT_ROVR) {
949 dev_err(dev->dev, "Receive overrun\n");
1d7afc95
FB		 950 err |= OMAP_I2C_STAT_ROVR;
951 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_ROVR);
952 omap_i2c_complete_cmd(dev, err);
953 return IRQ_HANDLED;
010d442c 954 }
c55edb99 955
010d442c 956 if (stat & OMAP_I2C_STAT_XUDF) {
b6ee52c3 957 dev_err(dev->dev, "Transmit underflow\n");
1d7afc95
FB		 958 err |= OMAP_I2C_STAT_XUDF;
959 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XUDF);
960 omap_i2c_complete_cmd(dev, err);
961 return IRQ_HANDLED;
010d442c 962 }
66b92988 963 } while (stat);
010d442c
KS		 964
965 return count ? IRQ_HANDLED : IRQ_NONE;
966}
967
8f9082c5 968static const struct i2c_algorithm omap_i2c_algo = {
010d442c
KS		 969 .master_xfer = omap_i2c_xfer,
970 .functionality = omap_i2c_func,
971};
972
6145197b
BC		 973#ifdef CONFIG_OF
974static struct omap_i2c_bus_platform_data omap3_pdata = {
975 .rev = OMAP_I2C_IP_VERSION_1,
976 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
977 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
978 OMAP_I2C_FLAG_BUS_SHIFT_2,
979};
980
981static struct omap_i2c_bus_platform_data omap4_pdata = {
982 .rev = OMAP_I2C_IP_VERSION_2,
983};
984
985static const struct of_device_id omap_i2c_of_match[] = {
986 {
987 .compatible = "ti,omap4-i2c",
988 .data = &omap4_pdata,
989 },
990 {
991 .compatible = "ti,omap3-i2c",
992 .data = &omap3_pdata,
993 },
994 { },
995};
996MODULE_DEVICE_TABLE(of, omap_i2c_of_match);
997#endif
998
1139aea9 999static int __devinit
010d442c
KS		 1000omap_i2c_probe(struct platform_device *pdev)
1001{
1002 struct omap_i2c_dev *dev;
1003 struct i2c_adapter *adap;
ac79e4b2 1004 struct resource *mem;
20c9d2c4 1005 struct omap_i2c_bus_platform_data *pdata = pdev->dev.platform_data;
6145197b
BC		 1006 struct device_node *node = pdev->dev.of_node;
1007 const struct of_device_id *match;
e355204e 1008 irq_handler_t isr;
ac79e4b2 1009 int irq;
010d442c
KS		 1010 int r;
1011
1012 /* NOTE: driver uses the static register mapping */
1013 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1014 if (!mem) {
1015 dev_err(&pdev->dev, "no mem resource?\n");
1016 return -ENODEV;
1017 }
ac79e4b2
FB		 1018
1019 irq = platform_get_irq(pdev, 0);
1020 if (irq < 0) {
010d442c 1021 dev_err(&pdev->dev, "no irq resource?\n");
ac79e4b2 1022 return irq;
010d442c
KS		 1023 }
1024
d9ebd04d
FB		 1025 dev = devm_kzalloc(&pdev->dev, sizeof(struct omap_i2c_dev), GFP_KERNEL);
1026 if (!dev) {
1027 dev_err(&pdev->dev, "Menory allocation failed\n");
1028 return -ENOMEM;
010d442c
KS		 1029 }
1030
d9ebd04d
FB		 1031 dev->base = devm_request_and_ioremap(&pdev->dev, mem);
1032 if (!dev->base) {
1033 dev_err(&pdev->dev, "I2C region already claimed\n");
1034 return -ENOMEM;
010d442c
KS		 1035 }
1036
6c5aa407 1037 match = of_match_device(of_match_ptr(omap_i2c_of_match), &pdev->dev);
6145197b
BC		 1038 if (match) {
1039 u32 freq = 100000; /* default to 100000 Hz */
1040
1041 pdata = match->data;
1042 dev->dtrev = pdata->rev;
1043 dev->flags = pdata->flags;
1044
1045 of_property_read_u32(node, "clock-frequency", &freq);
1046 /* convert DT freq value in Hz into kHz for speed */
1047 dev->speed = freq / 1000;
1048 } else if (pdata != NULL) {
1049 dev->speed = pdata->clkrate;
1050 dev->flags = pdata->flags;
20c9d2c4 1051 dev->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat;
6145197b 1052 dev->dtrev = pdata->rev;
20c9d2c4 1053 }
4574eb68 1054
010d442c 1055 dev->dev = &pdev->dev;
ac79e4b2 1056 dev->irq = irq;
55c381e4 1057
010d442c 1058 platform_set_drvdata(pdev, dev);
0e33bbb2 1059 init_completion(&dev->cmd_complete);
010d442c 1060
6145197b 1061 dev->reg_shift = (dev->flags >> OMAP_I2C_FLAG_BUS_SHIFT__SHIFT) & 3;
7c6bd201 1062
6145197b 1063 if (dev->dtrev == OMAP_I2C_IP_VERSION_2)
a1295577 1064 dev->regs = (u8 *)reg_map_ip_v2;
f38e66e0 1065 else
a1295577 1066 dev->regs = (u8 *)reg_map_ip_v1;
f38e66e0 1067
7f4b08ee 1068 pm_runtime_enable(dev->dev);
3b0fb97c
S		 1069 r = pm_runtime_get_sync(dev->dev);
1070 if (IS_ERR_VALUE(r))
1071 goto err_free_mem;
010d442c 1072
9c76b878 1073 dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
010d442c 1074
9aa8ec67
TK		 1075 dev->errata = 0;
1076
1077 if (dev->flags & OMAP_I2C_FLAG_APPLY_ERRATA_I207)
1078 dev->errata |= I2C_OMAP_ERRATA_I207;
1079
f518b482 1080 if (dev->rev <= OMAP_I2C_REV_ON_3430_3530)
c8db38f0 1081 dev->errata |= I2C_OMAP_ERRATA_I462;
8a9d97d3 1082
6145197b 1083 if (!(dev->flags & OMAP_I2C_FLAG_NO_FIFO)) {
b6ee52c3
NM		 1084 u16 s;
1085
1086 /* Set up the fifo size - Get total size */
1087 s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
1088 dev->fifo_size = 0x8 << s;
1089
1090 /*
1091 * Set up notification threshold as half the total available
1092 * size. This is to ensure that we can handle the status on int
1093 * call back latencies.
1094 */
1d5a34fe
S		 1095
1096 dev->fifo_size = (dev->fifo_size / 2);
1097
3ff4443f 1098 if (dev->rev < OMAP_I2C_REV_ON_3630_4430)
f38e66e0 1099 dev->b_hw = 1; /* Enable hardware fixes */
1d5a34fe 1100
20c9d2c4
KJ		 1101 /* calculate wakeup latency constraint for MPU */
1102 if (dev->set_mpu_wkup_lat != NULL)
1103 dev->latency = (1000000 * dev->fifo_size) /
6145197b 1104 (1000 * dev->speed / 8);
b6ee52c3
NM		 1105 }
1106
010d442c
KS		 1107 /* reset ASAP, clearing any IRQs */
1108 omap_i2c_init(dev);
1109
4e80f727
AG		 1110 isr = (dev->rev < OMAP_I2C_OMAP1_REV_2) ? omap_i2c_omap1_isr :
1111 omap_i2c_isr;
d9ebd04d
FB		 1112 r = devm_request_irq(&pdev->dev, dev->irq, isr, IRQF_NO_SUSPEND,
1113 pdev->name, dev);
010d442c
KS		 1114
1115 if (r) {
1116 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
1117 goto err_unuse_clocks;
1118 }
9c76b878 1119
9550d4d7 1120 dev_info(dev->dev, "bus %d rev%d.%d.%d at %d kHz\n", pdev->id,
6145197b 1121 dev->dtrev, dev->rev >> 4, dev->rev & 0xf, dev->speed);
010d442c
KS		 1122
1123 adap = &dev->adapter;
1124 i2c_set_adapdata(adap, dev);
1125 adap->owner = THIS_MODULE;
1126 adap->class = I2C_CLASS_HWMON;
783fd6fa 1127 strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
010d442c
KS		 1128 adap->algo = &omap_i2c_algo;
1129 adap->dev.parent = &pdev->dev;
6145197b 1130 adap->dev.of_node = pdev->dev.of_node;
010d442c
KS		 1131
1132 /* i2c device drivers may be active on return from add_adapter() */
7c175499
DB		 1133 adap->nr = pdev->id;
1134 r = i2c_add_numbered_adapter(adap);
010d442c
KS		 1135 if (r) {
1136 dev_err(dev->dev, "failure adding adapter\n");
d9ebd04d 1137 goto err_unuse_clocks;
010d442c
KS		 1138 }
1139
6145197b
BC		 1140 of_i2c_register_devices(adap);
1141
62ff2c2b
S		 1142 pm_runtime_put(dev->dev);
1143
010d442c
KS		 1144 return 0;
1145
010d442c 1146err_unuse_clocks:
3e39752d 1147 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
fab67afb 1148 pm_runtime_put(dev->dev);
24740516 1149 pm_runtime_disable(&pdev->dev);
010d442c
KS		 1150err_free_mem:
1151 platform_set_drvdata(pdev, NULL);
010d442c
KS		 1152
1153 return r;
1154}
1155
d790aea7 1156static int __devexit omap_i2c_remove(struct platform_device *pdev)
010d442c
KS		 1157{
1158 struct omap_i2c_dev *dev = platform_get_drvdata(pdev);
3b0fb97c 1159 int ret;
010d442c
KS		 1160
1161 platform_set_drvdata(pdev, NULL);
1162
010d442c 1163 i2c_del_adapter(&dev->adapter);
3b0fb97c
S		 1164 ret = pm_runtime_get_sync(&pdev->dev);
1165 if (IS_ERR_VALUE(ret))
1166 return ret;
1167
010d442c 1168 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
0861f430 1169 pm_runtime_put(&pdev->dev);
24740516 1170 pm_runtime_disable(&pdev->dev);
010d442c
KS		 1171 return 0;
1172}
1173
5692d2a2 1174#ifdef CONFIG_PM
fab67afb
KH		 1175#ifdef CONFIG_PM_RUNTIME
1176static int omap_i2c_runtime_suspend(struct device *dev)
1177{
1178 struct platform_device *pdev = to_platform_device(dev);
1179 struct omap_i2c_dev *_dev = platform_get_drvdata(pdev);
3dae3efb
S		 1180 u16 iv;
1181
1182 _dev->iestate = omap_i2c_read_reg(_dev, OMAP_I2C_IE_REG);
bd16c82f
S		 1183
1184 omap_i2c_write_reg(_dev, OMAP_I2C_IE_REG, 0);
fab67afb 1185
3dae3efb
S		 1186 if (_dev->rev < OMAP_I2C_OMAP1_REV_2) {
1187 iv = omap_i2c_read_reg(_dev, OMAP_I2C_IV_REG); /* Read clears */
1188 } else {
1189 omap_i2c_write_reg(_dev, OMAP_I2C_STAT_REG, _dev->iestate);
fab67afb 1190
3dae3efb
S		 1191 /* Flush posted write */
1192 omap_i2c_read_reg(_dev, OMAP_I2C_STAT_REG);
1193 }
fab67afb
KH		 1194
1195 return 0;
1196}
1197
1198static int omap_i2c_runtime_resume(struct device *dev)
1199{
1200 struct platform_device *pdev = to_platform_device(dev);
1201 struct omap_i2c_dev *_dev = platform_get_drvdata(pdev);
1202
3dae3efb
S		 1203 if (_dev->flags & OMAP_I2C_FLAG_RESET_REGS_POSTIDLE) {
1204 omap_i2c_write_reg(_dev, OMAP_I2C_CON_REG, 0);
1205 omap_i2c_write_reg(_dev, OMAP_I2C_PSC_REG, _dev->pscstate);
1206 omap_i2c_write_reg(_dev, OMAP_I2C_SCLL_REG, _dev->scllstate);
1207 omap_i2c_write_reg(_dev, OMAP_I2C_SCLH_REG, _dev->sclhstate);
1208 omap_i2c_write_reg(_dev, OMAP_I2C_BUF_REG, _dev->bufstate);
1209 omap_i2c_write_reg(_dev, OMAP_I2C_SYSC_REG, _dev->syscstate);
1210 omap_i2c_write_reg(_dev, OMAP_I2C_WE_REG, _dev->westate);
1211 omap_i2c_write_reg(_dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
1212 }
1213
1214 /*
1215 * Don't write to this register if the IE state is 0 as it can
1216 * cause deadlock.
1217 */
1218 if (_dev->iestate)
1219 omap_i2c_write_reg(_dev, OMAP_I2C_IE_REG, _dev->iestate);
fab67afb
KH		 1220
1221 return 0;
1222}
5692d2a2 1223#endif /* CONFIG_PM_RUNTIME */
fab67afb
KH		 1224
1225static struct dev_pm_ops omap_i2c_pm_ops = {
5692d2a2
S		 1226 SET_RUNTIME_PM_OPS(omap_i2c_runtime_suspend,
1227 omap_i2c_runtime_resume, NULL)
fab67afb
KH		 1228};
1229#define OMAP_I2C_PM_OPS (&omap_i2c_pm_ops)
1230#else
1231#define OMAP_I2C_PM_OPS NULL
5692d2a2 1232#endif /* CONFIG_PM */
fab67afb 1233
010d442c
KS		 1234static struct platform_driver omap_i2c_driver = {
1235 .probe = omap_i2c_probe,
d790aea7 1236 .remove = __devexit_p(omap_i2c_remove),
010d442c 1237 .driver = {
f7bb0d9a 1238 .name = "omap_i2c",
010d442c 1239 .owner = THIS_MODULE,
fab67afb 1240 .pm = OMAP_I2C_PM_OPS,
6145197b 1241 .of_match_table = of_match_ptr(omap_i2c_of_match),
010d442c
KS		 1242 },
1243};
1244
1245/* I2C may be needed to bring up other drivers */
1246static int __init
1247omap_i2c_init_driver(void)
1248{
1249 return platform_driver_register(&omap_i2c_driver);
1250}
1251subsys_initcall(omap_i2c_init_driver);
1252
1253static void __exit omap_i2c_exit_driver(void)
1254{
1255 platform_driver_unregister(&omap_i2c_driver);
1256}
1257module_exit(omap_i2c_exit_driver);
1258
1259MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
1260MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
1261MODULE_LICENSE("GPL");
f7bb0d9a 1262MODULE_ALIAS("platform:omap_i2c");
Linux 6.x block layer and io_uring tree(s)