Commit | Line | Data |
---|---|---|
010d442c KS |
1 | /* |
2 | * TI OMAP I2C master mode driver | |
3 | * | |
4 | * Copyright (C) 2003 MontaVista Software, Inc. | |
010d442c | 5 | * Copyright (C) 2005 Nokia Corporation |
c1a473bd | 6 | * Copyright (C) 2004 - 2007 Texas Instruments. |
010d442c | 7 | * |
c1a473bd TL |
8 | * Originally written by MontaVista Software, Inc. |
9 | * Additional contributions by: | |
10 | * Tony Lindgren <tony@atomide.com> | |
11 | * Imre Deak <imre.deak@nokia.com> | |
12 | * Juha Yrjölä <juha.yrjola@solidboot.com> | |
13 | * Syed Khasim <x0khasim@ti.com> | |
14 | * Nishant Menon <nm@ti.com> | |
010d442c KS |
15 | * |
16 | * This program is free software; you can redistribute it and/or modify | |
17 | * it under the terms of the GNU General Public License as published by | |
18 | * the Free Software Foundation; either version 2 of the License, or | |
19 | * (at your option) any later version. | |
20 | * | |
21 | * This program is distributed in the hope that it will be useful, | |
22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
24 | * GNU General Public License for more details. | |
25 | * | |
26 | * You should have received a copy of the GNU General Public License | |
27 | * along with this program; if not, write to the Free Software | |
28 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
29 | */ | |
30 | ||
31 | #include <linux/module.h> | |
32 | #include <linux/delay.h> | |
33 | #include <linux/i2c.h> | |
34 | #include <linux/err.h> | |
35 | #include <linux/interrupt.h> | |
36 | #include <linux/completion.h> | |
37 | #include <linux/platform_device.h> | |
38 | #include <linux/clk.h> | |
c1a473bd | 39 | #include <linux/io.h> |
5a0e3ad6 | 40 | #include <linux/slab.h> |
20c9d2c4 | 41 | #include <linux/i2c-omap.h> |
27b1fec2 | 42 | #include <linux/pm_runtime.h> |
010d442c | 43 | |
9c76b878 PW |
44 | /* I2C controller revisions */ |
45 | #define OMAP_I2C_REV_2 0x20 | |
46 | ||
47 | /* I2C controller revisions present on specific hardware */ | |
48 | #define OMAP_I2C_REV_ON_2430 0x36 | |
49 | #define OMAP_I2C_REV_ON_3430 0x3C | |
f38e66e0 | 50 | #define OMAP_I2C_REV_ON_4430 0x40 |
9c76b878 | 51 | |
010d442c KS |
52 | /* timeout waiting for the controller to respond */ |
53 | #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000)) | |
54 | ||
5043e9e7 | 55 | /* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */ |
f38e66e0 SS |
56 | enum { |
57 | OMAP_I2C_REV_REG = 0, | |
58 | OMAP_I2C_IE_REG, | |
59 | OMAP_I2C_STAT_REG, | |
60 | OMAP_I2C_IV_REG, | |
61 | OMAP_I2C_WE_REG, | |
62 | OMAP_I2C_SYSS_REG, | |
63 | OMAP_I2C_BUF_REG, | |
64 | OMAP_I2C_CNT_REG, | |
65 | OMAP_I2C_DATA_REG, | |
66 | OMAP_I2C_SYSC_REG, | |
67 | OMAP_I2C_CON_REG, | |
68 | OMAP_I2C_OA_REG, | |
69 | OMAP_I2C_SA_REG, | |
70 | OMAP_I2C_PSC_REG, | |
71 | OMAP_I2C_SCLL_REG, | |
72 | OMAP_I2C_SCLH_REG, | |
73 | OMAP_I2C_SYSTEST_REG, | |
74 | OMAP_I2C_BUFSTAT_REG, | |
75 | OMAP_I2C_REVNB_LO, | |
76 | OMAP_I2C_REVNB_HI, | |
77 | OMAP_I2C_IRQSTATUS_RAW, | |
78 | OMAP_I2C_IRQENABLE_SET, | |
79 | OMAP_I2C_IRQENABLE_CLR, | |
80 | }; | |
010d442c KS |
81 | |
82 | /* I2C Interrupt Enable Register (OMAP_I2C_IE): */ | |
b6ee52c3 NM |
83 | #define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */ |
84 | #define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */ | |
010d442c KS |
85 | #define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */ |
86 | #define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */ | |
87 | #define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */ | |
88 | #define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */ | |
89 | #define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */ | |
90 | ||
91 | /* I2C Status Register (OMAP_I2C_STAT): */ | |
b6ee52c3 NM |
92 | #define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */ |
93 | #define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */ | |
010d442c KS |
94 | #define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */ |
95 | #define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */ | |
96 | #define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ | |
97 | #define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */ | |
98 | #define OMAP_I2C_STAT_AD0 (1 << 8) /* Address zero */ | |
99 | #define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ | |
100 | #define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */ | |
101 | #define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */ | |
102 | #define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */ | |
103 | #define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */ | |
104 | ||
5043e9e7 KJ |
105 | /* I2C WE wakeup enable register */ |
106 | #define OMAP_I2C_WE_XDR_WE (1 << 14) /* TX drain wakup */ | |
107 | #define OMAP_I2C_WE_RDR_WE (1 << 13) /* RX drain wakeup */ | |
108 | #define OMAP_I2C_WE_AAS_WE (1 << 9) /* Address as slave wakeup*/ | |
109 | #define OMAP_I2C_WE_BF_WE (1 << 8) /* Bus free wakeup */ | |
110 | #define OMAP_I2C_WE_STC_WE (1 << 6) /* Start condition wakeup */ | |
111 | #define OMAP_I2C_WE_GC_WE (1 << 5) /* General call wakeup */ | |
112 | #define OMAP_I2C_WE_DRDY_WE (1 << 3) /* TX/RX data ready wakeup */ | |
113 | #define OMAP_I2C_WE_ARDY_WE (1 << 2) /* Reg access ready wakeup */ | |
114 | #define OMAP_I2C_WE_NACK_WE (1 << 1) /* No acknowledgment wakeup */ | |
115 | #define OMAP_I2C_WE_AL_WE (1 << 0) /* Arbitration lost wakeup */ | |
116 | ||
117 | #define OMAP_I2C_WE_ALL (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \ | |
118 | OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \ | |
119 | OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \ | |
120 | OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \ | |
121 | OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE) | |
122 | ||
010d442c KS |
123 | /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */ |
124 | #define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */ | |
b6ee52c3 | 125 | #define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */ |
010d442c | 126 | #define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */ |
b6ee52c3 | 127 | #define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */ |
010d442c KS |
128 | |
129 | /* I2C Configuration Register (OMAP_I2C_CON): */ | |
130 | #define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */ | |
131 | #define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */ | |
b6ee52c3 | 132 | #define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */ |
010d442c KS |
133 | #define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */ |
134 | #define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */ | |
135 | #define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */ | |
136 | #define OMAP_I2C_CON_XA (1 << 8) /* Expand address */ | |
137 | #define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */ | |
138 | #define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */ | |
139 | #define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */ | |
140 | ||
4574eb68 SMK |
141 | /* I2C SCL time value when Master */ |
142 | #define OMAP_I2C_SCLL_HSSCLL 8 | |
143 | #define OMAP_I2C_SCLH_HSSCLH 8 | |
144 | ||
010d442c KS |
145 | /* I2C System Test Register (OMAP_I2C_SYSTEST): */ |
146 | #ifdef DEBUG | |
147 | #define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */ | |
148 | #define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */ | |
149 | #define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */ | |
150 | #define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */ | |
151 | #define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */ | |
152 | #define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */ | |
153 | #define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */ | |
154 | #define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */ | |
155 | #endif | |
156 | ||
fdd07fe6 PW |
157 | /* OCP_SYSSTATUS bit definitions */ |
158 | #define SYSS_RESETDONE_MASK (1 << 0) | |
159 | ||
160 | /* OCP_SYSCONFIG bit definitions */ | |
161 | #define SYSC_CLOCKACTIVITY_MASK (0x3 << 8) | |
162 | #define SYSC_SIDLEMODE_MASK (0x3 << 3) | |
163 | #define SYSC_ENAWAKEUP_MASK (1 << 2) | |
164 | #define SYSC_SOFTRESET_MASK (1 << 1) | |
165 | #define SYSC_AUTOIDLE_MASK (1 << 0) | |
166 | ||
167 | #define SYSC_IDLEMODE_SMART 0x2 | |
168 | #define SYSC_CLOCKACTIVITY_FCLK 0x2 | |
010d442c | 169 | |
f3083d92 | 170 | /* Errata definitions */ |
171 | #define I2C_OMAP_ERRATA_I207 (1 << 0) | |
8a9d97d3 | 172 | #define I2C_OMAP3_1P153 (1 << 1) |
010d442c | 173 | |
010d442c KS |
174 | struct omap_i2c_dev { |
175 | struct device *dev; | |
176 | void __iomem *base; /* virtual */ | |
177 | int irq; | |
d84d3ea3 | 178 | int reg_shift; /* bit shift for I2C register addresses */ |
010d442c KS |
179 | struct completion cmd_complete; |
180 | struct resource *ioarea; | |
20c9d2c4 KJ |
181 | u32 latency; /* maximum mpu wkup latency */ |
182 | void (*set_mpu_wkup_lat)(struct device *dev, | |
183 | long latency); | |
4574eb68 | 184 | u32 speed; /* Speed of bus in Khz */ |
010d442c KS |
185 | u16 cmd_err; |
186 | u8 *buf; | |
f38e66e0 | 187 | u8 *regs; |
010d442c KS |
188 | size_t buf_len; |
189 | struct i2c_adapter adapter; | |
b6ee52c3 NM |
190 | u8 fifo_size; /* use as flag and value |
191 | * fifo_size==0 implies no fifo | |
192 | * if set, should be trsh+1 | |
193 | */ | |
9c76b878 | 194 | u8 rev; |
b6ee52c3 | 195 | unsigned b_hw:1; /* bad h/w fixes */ |
f08ac4e7 TL |
196 | unsigned idle:1; |
197 | u16 iestate; /* Saved interrupt register */ | |
ef871432 RN |
198 | u16 pscstate; |
199 | u16 scllstate; | |
200 | u16 sclhstate; | |
201 | u16 bufstate; | |
202 | u16 syscstate; | |
203 | u16 westate; | |
f3083d92 | 204 | u16 errata; |
010d442c KS |
205 | }; |
206 | ||
f38e66e0 SS |
207 | const static u8 reg_map[] = { |
208 | [OMAP_I2C_REV_REG] = 0x00, | |
209 | [OMAP_I2C_IE_REG] = 0x01, | |
210 | [OMAP_I2C_STAT_REG] = 0x02, | |
211 | [OMAP_I2C_IV_REG] = 0x03, | |
212 | [OMAP_I2C_WE_REG] = 0x03, | |
213 | [OMAP_I2C_SYSS_REG] = 0x04, | |
214 | [OMAP_I2C_BUF_REG] = 0x05, | |
215 | [OMAP_I2C_CNT_REG] = 0x06, | |
216 | [OMAP_I2C_DATA_REG] = 0x07, | |
217 | [OMAP_I2C_SYSC_REG] = 0x08, | |
218 | [OMAP_I2C_CON_REG] = 0x09, | |
219 | [OMAP_I2C_OA_REG] = 0x0a, | |
220 | [OMAP_I2C_SA_REG] = 0x0b, | |
221 | [OMAP_I2C_PSC_REG] = 0x0c, | |
222 | [OMAP_I2C_SCLL_REG] = 0x0d, | |
223 | [OMAP_I2C_SCLH_REG] = 0x0e, | |
224 | [OMAP_I2C_SYSTEST_REG] = 0x0f, | |
225 | [OMAP_I2C_BUFSTAT_REG] = 0x10, | |
226 | }; | |
227 | ||
228 | const static u8 omap4_reg_map[] = { | |
229 | [OMAP_I2C_REV_REG] = 0x04, | |
230 | [OMAP_I2C_IE_REG] = 0x2c, | |
231 | [OMAP_I2C_STAT_REG] = 0x28, | |
232 | [OMAP_I2C_IV_REG] = 0x34, | |
233 | [OMAP_I2C_WE_REG] = 0x34, | |
234 | [OMAP_I2C_SYSS_REG] = 0x90, | |
235 | [OMAP_I2C_BUF_REG] = 0x94, | |
236 | [OMAP_I2C_CNT_REG] = 0x98, | |
237 | [OMAP_I2C_DATA_REG] = 0x9c, | |
238 | [OMAP_I2C_SYSC_REG] = 0x20, | |
239 | [OMAP_I2C_CON_REG] = 0xa4, | |
240 | [OMAP_I2C_OA_REG] = 0xa8, | |
241 | [OMAP_I2C_SA_REG] = 0xac, | |
242 | [OMAP_I2C_PSC_REG] = 0xb0, | |
243 | [OMAP_I2C_SCLL_REG] = 0xb4, | |
244 | [OMAP_I2C_SCLH_REG] = 0xb8, | |
245 | [OMAP_I2C_SYSTEST_REG] = 0xbC, | |
246 | [OMAP_I2C_BUFSTAT_REG] = 0xc0, | |
247 | [OMAP_I2C_REVNB_LO] = 0x00, | |
248 | [OMAP_I2C_REVNB_HI] = 0x04, | |
249 | [OMAP_I2C_IRQSTATUS_RAW] = 0x24, | |
250 | [OMAP_I2C_IRQENABLE_SET] = 0x2c, | |
251 | [OMAP_I2C_IRQENABLE_CLR] = 0x30, | |
252 | }; | |
253 | ||
010d442c KS |
254 | static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev, |
255 | int reg, u16 val) | |
256 | { | |
f38e66e0 SS |
257 | __raw_writew(val, i2c_dev->base + |
258 | (i2c_dev->regs[reg] << i2c_dev->reg_shift)); | |
010d442c KS |
259 | } |
260 | ||
261 | static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg) | |
262 | { | |
f38e66e0 SS |
263 | return __raw_readw(i2c_dev->base + |
264 | (i2c_dev->regs[reg] << i2c_dev->reg_shift)); | |
010d442c KS |
265 | } |
266 | ||
27b1fec2 | 267 | static void omap_i2c_unidle(struct omap_i2c_dev *dev) |
010d442c | 268 | { |
27b1fec2 RN |
269 | struct platform_device *pdev; |
270 | struct omap_i2c_bus_platform_data *pdata; | |
5fe23380 | 271 | |
27b1fec2 | 272 | WARN_ON(!dev->idle); |
010d442c | 273 | |
27b1fec2 RN |
274 | pdev = to_platform_device(dev->dev); |
275 | pdata = pdev->dev.platform_data; | |
010d442c | 276 | |
27b1fec2 | 277 | pm_runtime_get_sync(&pdev->dev); |
010d442c | 278 | |
ef871432 RN |
279 | if (cpu_is_omap34xx()) { |
280 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); | |
281 | omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, dev->pscstate); | |
282 | omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, dev->scllstate); | |
283 | omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, dev->sclhstate); | |
284 | omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, dev->bufstate); | |
285 | omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, dev->syscstate); | |
286 | omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate); | |
287 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN); | |
288 | } | |
0cbbcffd | 289 | dev->idle = 0; |
07ac31f6 CM |
290 | |
291 | /* | |
292 | * Don't write to this register if the IE state is 0 as it can | |
293 | * cause deadlock. | |
294 | */ | |
295 | if (dev->iestate) | |
296 | omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate); | |
010d442c KS |
297 | } |
298 | ||
f08ac4e7 | 299 | static void omap_i2c_idle(struct omap_i2c_dev *dev) |
010d442c | 300 | { |
27b1fec2 RN |
301 | struct platform_device *pdev; |
302 | struct omap_i2c_bus_platform_data *pdata; | |
f08ac4e7 TL |
303 | u16 iv; |
304 | ||
3831f154 PW |
305 | WARN_ON(dev->idle); |
306 | ||
27b1fec2 RN |
307 | pdev = to_platform_device(dev->dev); |
308 | pdata = pdev->dev.platform_data; | |
309 | ||
f08ac4e7 | 310 | dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG); |
f38e66e0 SS |
311 | if (dev->rev >= OMAP_I2C_REV_ON_4430) |
312 | omap_i2c_write_reg(dev, OMAP_I2C_IRQENABLE_CLR, 1); | |
313 | else | |
314 | omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0); | |
315 | ||
9c76b878 | 316 | if (dev->rev < OMAP_I2C_REV_2) { |
c1a473bd | 317 | iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); /* Read clears */ |
0cbbcffd | 318 | } else { |
f08ac4e7 | 319 | omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, dev->iestate); |
0cbbcffd PW |
320 | |
321 | /* Flush posted write before the dev->idle store occurs */ | |
322 | omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG); | |
323 | } | |
324 | dev->idle = 1; | |
27b1fec2 RN |
325 | |
326 | pm_runtime_put_sync(&pdev->dev); | |
010d442c KS |
327 | } |
328 | ||
329 | static int omap_i2c_init(struct omap_i2c_dev *dev) | |
330 | { | |
ef871432 | 331 | u16 psc = 0, scll = 0, sclh = 0, buf = 0; |
4574eb68 | 332 | u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0; |
010d442c KS |
333 | unsigned long fclk_rate = 12000000; |
334 | unsigned long timeout; | |
4574eb68 | 335 | unsigned long internal_clk = 0; |
27b1fec2 | 336 | struct clk *fclk; |
010d442c | 337 | |
9c76b878 | 338 | if (dev->rev >= OMAP_I2C_REV_2) { |
57eb81b1 MG |
339 | /* Disable I2C controller before soft reset */ |
340 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, | |
341 | omap_i2c_read_reg(dev, OMAP_I2C_CON_REG) & | |
342 | ~(OMAP_I2C_CON_EN)); | |
343 | ||
fdd07fe6 | 344 | omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK); |
010d442c KS |
345 | /* For some reason we need to set the EN bit before the |
346 | * reset done bit gets set. */ | |
347 | timeout = jiffies + OMAP_I2C_TIMEOUT; | |
348 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN); | |
349 | while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) & | |
fdd07fe6 | 350 | SYSS_RESETDONE_MASK)) { |
010d442c | 351 | if (time_after(jiffies, timeout)) { |
fce3ff03 | 352 | dev_warn(dev->dev, "timeout waiting " |
010d442c KS |
353 | "for controller reset\n"); |
354 | return -ETIMEDOUT; | |
355 | } | |
356 | msleep(1); | |
357 | } | |
fdd07fe6 PW |
358 | |
359 | /* SYSC register is cleared by the reset; rewrite it */ | |
360 | if (dev->rev == OMAP_I2C_REV_ON_2430) { | |
361 | ||
362 | omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, | |
363 | SYSC_AUTOIDLE_MASK); | |
364 | ||
365 | } else if (dev->rev >= OMAP_I2C_REV_ON_3430) { | |
ef871432 RN |
366 | dev->syscstate = SYSC_AUTOIDLE_MASK; |
367 | dev->syscstate |= SYSC_ENAWAKEUP_MASK; | |
368 | dev->syscstate |= (SYSC_IDLEMODE_SMART << | |
fdd07fe6 | 369 | __ffs(SYSC_SIDLEMODE_MASK)); |
ef871432 | 370 | dev->syscstate |= (SYSC_CLOCKACTIVITY_FCLK << |
fdd07fe6 PW |
371 | __ffs(SYSC_CLOCKACTIVITY_MASK)); |
372 | ||
ef871432 RN |
373 | omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, |
374 | dev->syscstate); | |
5043e9e7 KJ |
375 | /* |
376 | * Enabling all wakup sources to stop I2C freezing on | |
377 | * WFI instruction. | |
378 | * REVISIT: Some wkup sources might not be needed. | |
379 | */ | |
ef871432 | 380 | dev->westate = OMAP_I2C_WE_ALL; |
f38e66e0 SS |
381 | if (dev->rev < OMAP_I2C_REV_ON_4430) |
382 | omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, | |
383 | dev->westate); | |
fdd07fe6 | 384 | } |
010d442c KS |
385 | } |
386 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); | |
387 | ||
388 | if (cpu_class_is_omap1()) { | |
0e9ae109 RK |
389 | /* |
390 | * The I2C functional clock is the armxor_ck, so there's | |
391 | * no need to get "armxor_ck" separately. Now, if OMAP2420 | |
392 | * always returns 12MHz for the functional clock, we can | |
393 | * do this bit unconditionally. | |
394 | */ | |
27b1fec2 RN |
395 | fclk = clk_get(dev->dev, "fck"); |
396 | fclk_rate = clk_get_rate(fclk); | |
397 | clk_put(fclk); | |
0e9ae109 | 398 | |
010d442c KS |
399 | /* TRM for 5912 says the I2C clock must be prescaled to be |
400 | * between 7 - 12 MHz. The XOR input clock is typically | |
401 | * 12, 13 or 19.2 MHz. So we should have code that produces: | |
402 | * | |
403 | * XOR MHz Divider Prescaler | |
404 | * 12 1 0 | |
405 | * 13 2 1 | |
406 | * 19.2 2 1 | |
407 | */ | |
d7aef138 JD |
408 | if (fclk_rate > 12000000) |
409 | psc = fclk_rate / 12000000; | |
010d442c KS |
410 | } |
411 | ||
f38e66e0 | 412 | if (!(cpu_class_is_omap1() || cpu_is_omap2420())) { |
4574eb68 | 413 | |
84bf2c86 AK |
414 | /* |
415 | * HSI2C controller internal clk rate should be 19.2 Mhz for | |
416 | * HS and for all modes on 2430. On 34xx we can use lower rate | |
417 | * to get longer filter period for better noise suppression. | |
418 | * The filter is iclk (fclk for HS) period. | |
419 | */ | |
ff0f2426 | 420 | if (dev->speed > 400 || cpu_is_omap2430()) |
84bf2c86 AK |
421 | internal_clk = 19200; |
422 | else if (dev->speed > 100) | |
423 | internal_clk = 9600; | |
424 | else | |
425 | internal_clk = 4000; | |
27b1fec2 RN |
426 | fclk = clk_get(dev->dev, "fck"); |
427 | fclk_rate = clk_get_rate(fclk) / 1000; | |
428 | clk_put(fclk); | |
4574eb68 SMK |
429 | |
430 | /* Compute prescaler divisor */ | |
431 | psc = fclk_rate / internal_clk; | |
432 | psc = psc - 1; | |
433 | ||
434 | /* If configured for High Speed */ | |
435 | if (dev->speed > 400) { | |
baf46b4e AK |
436 | unsigned long scl; |
437 | ||
4574eb68 | 438 | /* For first phase of HS mode */ |
baf46b4e AK |
439 | scl = internal_clk / 400; |
440 | fsscll = scl - (scl / 3) - 7; | |
441 | fssclh = (scl / 3) - 5; | |
4574eb68 SMK |
442 | |
443 | /* For second phase of HS mode */ | |
baf46b4e AK |
444 | scl = fclk_rate / dev->speed; |
445 | hsscll = scl - (scl / 3) - 7; | |
446 | hssclh = (scl / 3) - 5; | |
447 | } else if (dev->speed > 100) { | |
448 | unsigned long scl; | |
449 | ||
450 | /* Fast mode */ | |
451 | scl = internal_clk / dev->speed; | |
452 | fsscll = scl - (scl / 3) - 7; | |
453 | fssclh = (scl / 3) - 5; | |
4574eb68 | 454 | } else { |
baf46b4e AK |
455 | /* Standard mode */ |
456 | fsscll = internal_clk / (dev->speed * 2) - 7; | |
457 | fssclh = internal_clk / (dev->speed * 2) - 5; | |
4574eb68 SMK |
458 | } |
459 | scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll; | |
460 | sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh; | |
461 | } else { | |
462 | /* Program desired operating rate */ | |
463 | fclk_rate /= (psc + 1) * 1000; | |
464 | if (psc > 2) | |
465 | psc = 2; | |
466 | scll = fclk_rate / (dev->speed * 2) - 7 + psc; | |
467 | sclh = fclk_rate / (dev->speed * 2) - 7 + psc; | |
468 | } | |
469 | ||
010d442c KS |
470 | /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */ |
471 | omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc); | |
472 | ||
4574eb68 SMK |
473 | /* SCL low and high time values */ |
474 | omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll); | |
475 | omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh); | |
010d442c | 476 | |
ef871432 RN |
477 | if (dev->fifo_size) { |
478 | /* Note: setup required fifo size - 1. RTRSH and XTRSH */ | |
479 | buf = (dev->fifo_size - 1) << 8 | OMAP_I2C_BUF_RXFIF_CLR | | |
480 | (dev->fifo_size - 1) | OMAP_I2C_BUF_TXFIF_CLR; | |
481 | omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, buf); | |
482 | } | |
b6ee52c3 | 483 | |
010d442c KS |
484 | /* Take the I2C module out of reset: */ |
485 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN); | |
486 | ||
f3083d92 | 487 | dev->errata = 0; |
488 | ||
489 | if (cpu_is_omap2430() || cpu_is_omap34xx()) | |
490 | dev->errata |= I2C_OMAP_ERRATA_I207; | |
491 | ||
010d442c | 492 | /* Enable interrupts */ |
ef871432 | 493 | dev->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY | |
c1a473bd TL |
494 | OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK | |
495 | OMAP_I2C_IE_AL) | ((dev->fifo_size) ? | |
ef871432 RN |
496 | (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0); |
497 | omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate); | |
498 | if (cpu_is_omap34xx()) { | |
499 | dev->pscstate = psc; | |
500 | dev->scllstate = scll; | |
501 | dev->sclhstate = sclh; | |
502 | dev->bufstate = buf; | |
503 | } | |
010d442c KS |
504 | return 0; |
505 | } | |
506 | ||
507 | /* | |
508 | * Waiting on Bus Busy | |
509 | */ | |
510 | static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev) | |
511 | { | |
512 | unsigned long timeout; | |
513 | ||
514 | timeout = jiffies + OMAP_I2C_TIMEOUT; | |
515 | while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) { | |
516 | if (time_after(jiffies, timeout)) { | |
517 | dev_warn(dev->dev, "timeout waiting for bus ready\n"); | |
518 | return -ETIMEDOUT; | |
519 | } | |
520 | msleep(1); | |
521 | } | |
522 | ||
523 | return 0; | |
524 | } | |
525 | ||
526 | /* | |
527 | * Low level master read/write transaction. | |
528 | */ | |
529 | static int omap_i2c_xfer_msg(struct i2c_adapter *adap, | |
530 | struct i2c_msg *msg, int stop) | |
531 | { | |
532 | struct omap_i2c_dev *dev = i2c_get_adapdata(adap); | |
533 | int r; | |
534 | u16 w; | |
535 | ||
536 | dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n", | |
537 | msg->addr, msg->len, msg->flags, stop); | |
538 | ||
539 | if (msg->len == 0) | |
540 | return -EINVAL; | |
541 | ||
542 | omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr); | |
543 | ||
544 | /* REVISIT: Could the STB bit of I2C_CON be used with probing? */ | |
545 | dev->buf = msg->buf; | |
546 | dev->buf_len = msg->len; | |
547 | ||
548 | omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len); | |
549 | ||
b6ee52c3 NM |
550 | /* Clear the FIFO Buffers */ |
551 | w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG); | |
552 | w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR; | |
553 | omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w); | |
554 | ||
010d442c KS |
555 | init_completion(&dev->cmd_complete); |
556 | dev->cmd_err = 0; | |
557 | ||
558 | w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT; | |
4574eb68 SMK |
559 | |
560 | /* High speed configuration */ | |
561 | if (dev->speed > 400) | |
b6ee52c3 | 562 | w |= OMAP_I2C_CON_OPMODE_HS; |
4574eb68 | 563 | |
010d442c KS |
564 | if (msg->flags & I2C_M_TEN) |
565 | w |= OMAP_I2C_CON_XA; | |
566 | if (!(msg->flags & I2C_M_RD)) | |
567 | w |= OMAP_I2C_CON_TRX; | |
c1a473bd | 568 | |
b6ee52c3 | 569 | if (!dev->b_hw && stop) |
010d442c | 570 | w |= OMAP_I2C_CON_STP; |
c1a473bd | 571 | |
010d442c KS |
572 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w); |
573 | ||
b6ee52c3 NM |
574 | /* |
575 | * Don't write stt and stp together on some hardware. | |
576 | */ | |
577 | if (dev->b_hw && stop) { | |
578 | unsigned long delay = jiffies + OMAP_I2C_TIMEOUT; | |
579 | u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG); | |
580 | while (con & OMAP_I2C_CON_STT) { | |
581 | con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG); | |
582 | ||
583 | /* Let the user know if i2c is in a bad state */ | |
584 | if (time_after(jiffies, delay)) { | |
585 | dev_err(dev->dev, "controller timed out " | |
586 | "waiting for start condition to finish\n"); | |
587 | return -ETIMEDOUT; | |
588 | } | |
589 | cpu_relax(); | |
590 | } | |
591 | ||
592 | w |= OMAP_I2C_CON_STP; | |
593 | w &= ~OMAP_I2C_CON_STT; | |
594 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w); | |
595 | } | |
596 | ||
b7af349b JN |
597 | /* |
598 | * REVISIT: We should abort the transfer on signals, but the bus goes | |
599 | * into arbitration and we're currently unable to recover from it. | |
600 | */ | |
601 | r = wait_for_completion_timeout(&dev->cmd_complete, | |
602 | OMAP_I2C_TIMEOUT); | |
010d442c KS |
603 | dev->buf_len = 0; |
604 | if (r < 0) | |
605 | return r; | |
606 | if (r == 0) { | |
607 | dev_err(dev->dev, "controller timed out\n"); | |
608 | omap_i2c_init(dev); | |
609 | return -ETIMEDOUT; | |
610 | } | |
611 | ||
612 | if (likely(!dev->cmd_err)) | |
613 | return 0; | |
614 | ||
615 | /* We have an error */ | |
616 | if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR | | |
617 | OMAP_I2C_STAT_XUDF)) { | |
618 | omap_i2c_init(dev); | |
619 | return -EIO; | |
620 | } | |
621 | ||
622 | if (dev->cmd_err & OMAP_I2C_STAT_NACK) { | |
623 | if (msg->flags & I2C_M_IGNORE_NAK) | |
624 | return 0; | |
625 | if (stop) { | |
626 | w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG); | |
627 | w |= OMAP_I2C_CON_STP; | |
628 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w); | |
629 | } | |
630 | return -EREMOTEIO; | |
631 | } | |
632 | return -EIO; | |
633 | } | |
634 | ||
635 | ||
636 | /* | |
637 | * Prepare controller for a transaction and call omap_i2c_xfer_msg | |
638 | * to do the work during IRQ processing. | |
639 | */ | |
640 | static int | |
641 | omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) | |
642 | { | |
643 | struct omap_i2c_dev *dev = i2c_get_adapdata(adap); | |
644 | int i; | |
645 | int r; | |
646 | ||
f08ac4e7 | 647 | omap_i2c_unidle(dev); |
010d442c | 648 | |
c1a473bd TL |
649 | r = omap_i2c_wait_for_bb(dev); |
650 | if (r < 0) | |
010d442c KS |
651 | goto out; |
652 | ||
6a91b558 SO |
653 | if (dev->set_mpu_wkup_lat != NULL) |
654 | dev->set_mpu_wkup_lat(dev->dev, dev->latency); | |
655 | ||
010d442c KS |
656 | for (i = 0; i < num; i++) { |
657 | r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1))); | |
658 | if (r != 0) | |
659 | break; | |
660 | } | |
661 | ||
6a91b558 SO |
662 | if (dev->set_mpu_wkup_lat != NULL) |
663 | dev->set_mpu_wkup_lat(dev->dev, -1); | |
664 | ||
010d442c KS |
665 | if (r == 0) |
666 | r = num; | |
5c64eb26 MN |
667 | |
668 | omap_i2c_wait_for_bb(dev); | |
010d442c | 669 | out: |
f08ac4e7 | 670 | omap_i2c_idle(dev); |
010d442c KS |
671 | return r; |
672 | } | |
673 | ||
674 | static u32 | |
675 | omap_i2c_func(struct i2c_adapter *adap) | |
676 | { | |
677 | return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); | |
678 | } | |
679 | ||
680 | static inline void | |
681 | omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err) | |
682 | { | |
683 | dev->cmd_err |= err; | |
684 | complete(&dev->cmd_complete); | |
685 | } | |
686 | ||
687 | static inline void | |
688 | omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat) | |
689 | { | |
690 | omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat); | |
691 | } | |
692 | ||
f3083d92 | 693 | static inline void i2c_omap_errata_i207(struct omap_i2c_dev *dev, u16 stat) |
694 | { | |
695 | /* | |
696 | * I2C Errata(Errata Nos. OMAP2: 1.67, OMAP3: 1.8) | |
697 | * Not applicable for OMAP4. | |
698 | * Under certain rare conditions, RDR could be set again | |
699 | * when the bus is busy, then ignore the interrupt and | |
700 | * clear the interrupt. | |
701 | */ | |
702 | if (stat & OMAP_I2C_STAT_RDR) { | |
703 | /* Step 1: If RDR is set, clear it */ | |
704 | omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR); | |
705 | ||
706 | /* Step 2: */ | |
707 | if (!(omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) | |
708 | & OMAP_I2C_STAT_BB)) { | |
709 | ||
710 | /* Step 3: */ | |
711 | if (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) | |
712 | & OMAP_I2C_STAT_RDR) { | |
713 | omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR); | |
714 | dev_dbg(dev->dev, "RDR when bus is busy.\n"); | |
715 | } | |
716 | ||
717 | } | |
718 | } | |
719 | } | |
720 | ||
43469d8e PW |
721 | /* rev1 devices are apparently only on some 15xx */ |
722 | #ifdef CONFIG_ARCH_OMAP15XX | |
723 | ||
010d442c | 724 | static irqreturn_t |
7d12e780 | 725 | omap_i2c_rev1_isr(int this_irq, void *dev_id) |
010d442c KS |
726 | { |
727 | struct omap_i2c_dev *dev = dev_id; | |
728 | u16 iv, w; | |
729 | ||
f08ac4e7 TL |
730 | if (dev->idle) |
731 | return IRQ_NONE; | |
732 | ||
010d442c KS |
733 | iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); |
734 | switch (iv) { | |
735 | case 0x00: /* None */ | |
736 | break; | |
737 | case 0x01: /* Arbitration lost */ | |
738 | dev_err(dev->dev, "Arbitration lost\n"); | |
739 | omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL); | |
740 | break; | |
741 | case 0x02: /* No acknowledgement */ | |
742 | omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK); | |
743 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP); | |
744 | break; | |
745 | case 0x03: /* Register access ready */ | |
746 | omap_i2c_complete_cmd(dev, 0); | |
747 | break; | |
748 | case 0x04: /* Receive data ready */ | |
749 | if (dev->buf_len) { | |
750 | w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG); | |
751 | *dev->buf++ = w; | |
752 | dev->buf_len--; | |
753 | if (dev->buf_len) { | |
754 | *dev->buf++ = w >> 8; | |
755 | dev->buf_len--; | |
756 | } | |
757 | } else | |
758 | dev_err(dev->dev, "RRDY IRQ while no data requested\n"); | |
759 | break; | |
760 | case 0x05: /* Transmit data ready */ | |
761 | if (dev->buf_len) { | |
762 | w = *dev->buf++; | |
763 | dev->buf_len--; | |
764 | if (dev->buf_len) { | |
765 | w |= *dev->buf++ << 8; | |
766 | dev->buf_len--; | |
767 | } | |
768 | omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w); | |
769 | } else | |
770 | dev_err(dev->dev, "XRDY IRQ while no data to send\n"); | |
771 | break; | |
772 | default: | |
773 | return IRQ_NONE; | |
774 | } | |
775 | ||
776 | return IRQ_HANDLED; | |
777 | } | |
43469d8e | 778 | #else |
c1a473bd | 779 | #define omap_i2c_rev1_isr NULL |
43469d8e | 780 | #endif |
010d442c | 781 | |
2dd151ab AS |
782 | /* |
783 | * OMAP3430 Errata 1.153: When an XRDY/XDR is hit, wait for XUDF before writing | |
784 | * data to DATA_REG. Otherwise some data bytes can be lost while transferring | |
785 | * them from the memory to the I2C interface. | |
786 | */ | |
787 | static int errata_omap3_1p153(struct omap_i2c_dev *dev, u16 *stat, int *err) | |
788 | { | |
e9f59b9c AS |
789 | unsigned long timeout = 10000; |
790 | ||
791 | while (--timeout && !(*stat & OMAP_I2C_STAT_XUDF)) { | |
2dd151ab AS |
792 | if (*stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) { |
793 | omap_i2c_ack_stat(dev, *stat & (OMAP_I2C_STAT_XRDY | | |
794 | OMAP_I2C_STAT_XDR)); | |
795 | *err |= OMAP_I2C_STAT_XUDF; | |
796 | return -ETIMEDOUT; | |
797 | } | |
e9f59b9c | 798 | |
2dd151ab AS |
799 | cpu_relax(); |
800 | *stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG); | |
801 | } | |
802 | ||
e9f59b9c AS |
803 | if (!timeout) { |
804 | dev_err(dev->dev, "timeout waiting on XUDF bit\n"); | |
805 | return 0; | |
806 | } | |
807 | ||
2dd151ab AS |
808 | return 0; |
809 | } | |
810 | ||
010d442c | 811 | static irqreturn_t |
7d12e780 | 812 | omap_i2c_isr(int this_irq, void *dev_id) |
010d442c KS |
813 | { |
814 | struct omap_i2c_dev *dev = dev_id; | |
815 | u16 bits; | |
816 | u16 stat, w; | |
b6ee52c3 | 817 | int err, count = 0; |
010d442c | 818 | |
f08ac4e7 TL |
819 | if (dev->idle) |
820 | return IRQ_NONE; | |
821 | ||
010d442c KS |
822 | bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG); |
823 | while ((stat = (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG))) & bits) { | |
824 | dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat); | |
825 | if (count++ == 100) { | |
826 | dev_warn(dev->dev, "Too much work in one IRQ\n"); | |
827 | break; | |
828 | } | |
829 | ||
cd086d3a SM |
830 | err = 0; |
831 | complete: | |
dcc4ec26 NM |
832 | /* |
833 | * Ack the stat in one go, but [R/X]DR and [R/X]RDY should be | |
834 | * acked after the data operation is complete. | |
835 | * Ref: TRM SWPU114Q Figure 18-31 | |
836 | */ | |
837 | omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat & | |
838 | ~(OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR | | |
839 | OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)); | |
010d442c | 840 | |
b6ee52c3 NM |
841 | if (stat & OMAP_I2C_STAT_NACK) { |
842 | err |= OMAP_I2C_STAT_NACK; | |
843 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, | |
844 | OMAP_I2C_CON_STP); | |
010d442c | 845 | } |
b6ee52c3 NM |
846 | if (stat & OMAP_I2C_STAT_AL) { |
847 | dev_err(dev->dev, "Arbitration lost\n"); | |
848 | err |= OMAP_I2C_STAT_AL; | |
849 | } | |
a5a595cc | 850 | /* |
cb527ede | 851 | * ProDB0017052: Clear ARDY bit twice |
a5a595cc | 852 | */ |
b6ee52c3 | 853 | if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK | |
04c688dd | 854 | OMAP_I2C_STAT_AL)) { |
dd11976a MS |
855 | omap_i2c_ack_stat(dev, stat & |
856 | (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR | | |
cb527ede R |
857 | OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR | |
858 | OMAP_I2C_STAT_ARDY)); | |
b6ee52c3 | 859 | omap_i2c_complete_cmd(dev, err); |
04c688dd SM |
860 | return IRQ_HANDLED; |
861 | } | |
b6ee52c3 NM |
862 | if (stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR)) { |
863 | u8 num_bytes = 1; | |
f3083d92 | 864 | |
865 | if (dev->errata & I2C_OMAP_ERRATA_I207) | |
866 | i2c_omap_errata_i207(dev, stat); | |
867 | ||
b6ee52c3 NM |
868 | if (dev->fifo_size) { |
869 | if (stat & OMAP_I2C_STAT_RRDY) | |
870 | num_bytes = dev->fifo_size; | |
bfb6b658 SM |
871 | else /* read RXSTAT on RDR interrupt */ |
872 | num_bytes = (omap_i2c_read_reg(dev, | |
873 | OMAP_I2C_BUFSTAT_REG) | |
874 | >> 8) & 0x3F; | |
b6ee52c3 NM |
875 | } |
876 | while (num_bytes) { | |
877 | num_bytes--; | |
878 | w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG); | |
010d442c | 879 | if (dev->buf_len) { |
b6ee52c3 | 880 | *dev->buf++ = w; |
010d442c | 881 | dev->buf_len--; |
f38e66e0 SS |
882 | /* |
883 | * Data reg in 2430, omap3 and | |
884 | * omap4 is 8 bit wide | |
885 | */ | |
886 | if (cpu_class_is_omap1() || | |
887 | cpu_is_omap2420()) { | |
b6ee52c3 NM |
888 | if (dev->buf_len) { |
889 | *dev->buf++ = w >> 8; | |
890 | dev->buf_len--; | |
891 | } | |
892 | } | |
893 | } else { | |
894 | if (stat & OMAP_I2C_STAT_RRDY) | |
895 | dev_err(dev->dev, | |
896 | "RRDY IRQ while no data" | |
897 | " requested\n"); | |
898 | if (stat & OMAP_I2C_STAT_RDR) | |
899 | dev_err(dev->dev, | |
900 | "RDR IRQ while no data" | |
901 | " requested\n"); | |
902 | break; | |
010d442c | 903 | } |
b6ee52c3 NM |
904 | } |
905 | omap_i2c_ack_stat(dev, | |
906 | stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR)); | |
010d442c KS |
907 | continue; |
908 | } | |
b6ee52c3 NM |
909 | if (stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)) { |
910 | u8 num_bytes = 1; | |
911 | if (dev->fifo_size) { | |
912 | if (stat & OMAP_I2C_STAT_XRDY) | |
913 | num_bytes = dev->fifo_size; | |
bfb6b658 | 914 | else /* read TXSTAT on XDR interrupt */ |
b6ee52c3 | 915 | num_bytes = omap_i2c_read_reg(dev, |
bfb6b658 SM |
916 | OMAP_I2C_BUFSTAT_REG) |
917 | & 0x3F; | |
b6ee52c3 NM |
918 | } |
919 | while (num_bytes) { | |
920 | num_bytes--; | |
921 | w = 0; | |
010d442c | 922 | if (dev->buf_len) { |
b6ee52c3 | 923 | w = *dev->buf++; |
010d442c | 924 | dev->buf_len--; |
f38e66e0 SS |
925 | /* |
926 | * Data reg in 2430, omap3 and | |
927 | * omap4 is 8 bit wide | |
928 | */ | |
929 | if (cpu_class_is_omap1() || | |
930 | cpu_is_omap2420()) { | |
b6ee52c3 NM |
931 | if (dev->buf_len) { |
932 | w |= *dev->buf++ << 8; | |
933 | dev->buf_len--; | |
934 | } | |
935 | } | |
936 | } else { | |
937 | if (stat & OMAP_I2C_STAT_XRDY) | |
938 | dev_err(dev->dev, | |
939 | "XRDY IRQ while no " | |
940 | "data to send\n"); | |
941 | if (stat & OMAP_I2C_STAT_XDR) | |
942 | dev_err(dev->dev, | |
943 | "XDR IRQ while no " | |
944 | "data to send\n"); | |
945 | break; | |
010d442c | 946 | } |
cd086d3a | 947 | |
8a9d97d3 | 948 | if ((dev->errata & I2C_OMAP3_1P153) && |
2dd151ab AS |
949 | errata_omap3_1p153(dev, &stat, &err)) |
950 | goto complete; | |
cd086d3a | 951 | |
b6ee52c3 NM |
952 | omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w); |
953 | } | |
954 | omap_i2c_ack_stat(dev, | |
955 | stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)); | |
010d442c KS |
956 | continue; |
957 | } | |
958 | if (stat & OMAP_I2C_STAT_ROVR) { | |
959 | dev_err(dev->dev, "Receive overrun\n"); | |
960 | dev->cmd_err |= OMAP_I2C_STAT_ROVR; | |
961 | } | |
962 | if (stat & OMAP_I2C_STAT_XUDF) { | |
b6ee52c3 | 963 | dev_err(dev->dev, "Transmit underflow\n"); |
010d442c KS |
964 | dev->cmd_err |= OMAP_I2C_STAT_XUDF; |
965 | } | |
010d442c KS |
966 | } |
967 | ||
968 | return count ? IRQ_HANDLED : IRQ_NONE; | |
969 | } | |
970 | ||
8f9082c5 | 971 | static const struct i2c_algorithm omap_i2c_algo = { |
010d442c KS |
972 | .master_xfer = omap_i2c_xfer, |
973 | .functionality = omap_i2c_func, | |
974 | }; | |
975 | ||
1139aea9 | 976 | static int __devinit |
010d442c KS |
977 | omap_i2c_probe(struct platform_device *pdev) |
978 | { | |
979 | struct omap_i2c_dev *dev; | |
980 | struct i2c_adapter *adap; | |
981 | struct resource *mem, *irq, *ioarea; | |
20c9d2c4 | 982 | struct omap_i2c_bus_platform_data *pdata = pdev->dev.platform_data; |
e355204e | 983 | irq_handler_t isr; |
010d442c | 984 | int r; |
3d522fb4 | 985 | u32 speed = 0; |
010d442c KS |
986 | |
987 | /* NOTE: driver uses the static register mapping */ | |
988 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
989 | if (!mem) { | |
990 | dev_err(&pdev->dev, "no mem resource?\n"); | |
991 | return -ENODEV; | |
992 | } | |
993 | irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
994 | if (!irq) { | |
995 | dev_err(&pdev->dev, "no irq resource?\n"); | |
996 | return -ENODEV; | |
997 | } | |
998 | ||
59330825 | 999 | ioarea = request_mem_region(mem->start, resource_size(mem), |
010d442c KS |
1000 | pdev->name); |
1001 | if (!ioarea) { | |
1002 | dev_err(&pdev->dev, "I2C region already claimed\n"); | |
1003 | return -EBUSY; | |
1004 | } | |
1005 | ||
010d442c KS |
1006 | dev = kzalloc(sizeof(struct omap_i2c_dev), GFP_KERNEL); |
1007 | if (!dev) { | |
1008 | r = -ENOMEM; | |
1009 | goto err_release_region; | |
1010 | } | |
1011 | ||
20c9d2c4 KJ |
1012 | if (pdata != NULL) { |
1013 | speed = pdata->clkrate; | |
1014 | dev->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat; | |
1015 | } else { | |
1016 | speed = 100; /* Default speed */ | |
1017 | dev->set_mpu_wkup_lat = NULL; | |
1018 | } | |
4574eb68 | 1019 | |
3d522fb4 | 1020 | dev->speed = speed; |
3831f154 | 1021 | dev->idle = 1; |
010d442c KS |
1022 | dev->dev = &pdev->dev; |
1023 | dev->irq = irq->start; | |
c6ffddea | 1024 | dev->base = ioremap(mem->start, resource_size(mem)); |
55c381e4 RK |
1025 | if (!dev->base) { |
1026 | r = -ENOMEM; | |
1027 | goto err_free_mem; | |
1028 | } | |
1029 | ||
010d442c KS |
1030 | platform_set_drvdata(pdev, dev); |
1031 | ||
7c6bd201 MW |
1032 | if (cpu_is_omap7xx()) |
1033 | dev->reg_shift = 1; | |
f38e66e0 SS |
1034 | else if (cpu_is_omap44xx()) |
1035 | dev->reg_shift = 0; | |
7c6bd201 MW |
1036 | else |
1037 | dev->reg_shift = 2; | |
1038 | ||
f38e66e0 SS |
1039 | if (cpu_is_omap44xx()) |
1040 | dev->regs = (u8 *) omap4_reg_map; | |
1041 | else | |
1042 | dev->regs = (u8 *) reg_map; | |
1043 | ||
27b1fec2 | 1044 | pm_runtime_enable(&pdev->dev); |
f08ac4e7 | 1045 | omap_i2c_unidle(dev); |
010d442c | 1046 | |
9c76b878 | 1047 | dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff; |
010d442c | 1048 | |
8a9d97d3 | 1049 | if (dev->rev <= OMAP_I2C_REV_ON_3430) |
1050 | dev->errata |= I2C_OMAP3_1P153; | |
1051 | ||
f38e66e0 | 1052 | if (!(cpu_class_is_omap1() || cpu_is_omap2420())) { |
b6ee52c3 NM |
1053 | u16 s; |
1054 | ||
1055 | /* Set up the fifo size - Get total size */ | |
1056 | s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3; | |
1057 | dev->fifo_size = 0x8 << s; | |
1058 | ||
1059 | /* | |
1060 | * Set up notification threshold as half the total available | |
1061 | * size. This is to ensure that we can handle the status on int | |
1062 | * call back latencies. | |
1063 | */ | |
f38e66e0 SS |
1064 | if (dev->rev >= OMAP_I2C_REV_ON_4430) { |
1065 | dev->fifo_size = 0; | |
1066 | dev->b_hw = 0; /* Disable hardware fixes */ | |
1067 | } else { | |
1068 | dev->fifo_size = (dev->fifo_size / 2); | |
1069 | dev->b_hw = 1; /* Enable hardware fixes */ | |
1070 | } | |
20c9d2c4 KJ |
1071 | /* calculate wakeup latency constraint for MPU */ |
1072 | if (dev->set_mpu_wkup_lat != NULL) | |
1073 | dev->latency = (1000000 * dev->fifo_size) / | |
1074 | (1000 * speed / 8); | |
b6ee52c3 NM |
1075 | } |
1076 | ||
010d442c KS |
1077 | /* reset ASAP, clearing any IRQs */ |
1078 | omap_i2c_init(dev); | |
1079 | ||
9c76b878 PW |
1080 | isr = (dev->rev < OMAP_I2C_REV_2) ? omap_i2c_rev1_isr : omap_i2c_isr; |
1081 | r = request_irq(dev->irq, isr, 0, pdev->name, dev); | |
010d442c KS |
1082 | |
1083 | if (r) { | |
1084 | dev_err(dev->dev, "failure requesting irq %i\n", dev->irq); | |
1085 | goto err_unuse_clocks; | |
1086 | } | |
9c76b878 | 1087 | |
010d442c | 1088 | dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n", |
9c76b878 | 1089 | pdev->id, dev->rev >> 4, dev->rev & 0xf, dev->speed); |
010d442c | 1090 | |
3831f154 PW |
1091 | omap_i2c_idle(dev); |
1092 | ||
010d442c KS |
1093 | adap = &dev->adapter; |
1094 | i2c_set_adapdata(adap, dev); | |
1095 | adap->owner = THIS_MODULE; | |
1096 | adap->class = I2C_CLASS_HWMON; | |
783fd6fa | 1097 | strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name)); |
010d442c KS |
1098 | adap->algo = &omap_i2c_algo; |
1099 | adap->dev.parent = &pdev->dev; | |
1100 | ||
1101 | /* i2c device drivers may be active on return from add_adapter() */ | |
7c175499 DB |
1102 | adap->nr = pdev->id; |
1103 | r = i2c_add_numbered_adapter(adap); | |
010d442c KS |
1104 | if (r) { |
1105 | dev_err(dev->dev, "failure adding adapter\n"); | |
1106 | goto err_free_irq; | |
1107 | } | |
1108 | ||
010d442c KS |
1109 | return 0; |
1110 | ||
1111 | err_free_irq: | |
1112 | free_irq(dev->irq, dev); | |
1113 | err_unuse_clocks: | |
3e39752d | 1114 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); |
f08ac4e7 | 1115 | omap_i2c_idle(dev); |
55c381e4 | 1116 | iounmap(dev->base); |
010d442c KS |
1117 | err_free_mem: |
1118 | platform_set_drvdata(pdev, NULL); | |
1119 | kfree(dev); | |
1120 | err_release_region: | |
59330825 | 1121 | release_mem_region(mem->start, resource_size(mem)); |
010d442c KS |
1122 | |
1123 | return r; | |
1124 | } | |
1125 | ||
1126 | static int | |
1127 | omap_i2c_remove(struct platform_device *pdev) | |
1128 | { | |
1129 | struct omap_i2c_dev *dev = platform_get_drvdata(pdev); | |
1130 | struct resource *mem; | |
1131 | ||
1132 | platform_set_drvdata(pdev, NULL); | |
1133 | ||
1134 | free_irq(dev->irq, dev); | |
1135 | i2c_del_adapter(&dev->adapter); | |
1136 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); | |
55c381e4 | 1137 | iounmap(dev->base); |
010d442c KS |
1138 | kfree(dev); |
1139 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
59330825 | 1140 | release_mem_region(mem->start, resource_size(mem)); |
010d442c KS |
1141 | return 0; |
1142 | } | |
1143 | ||
adf6e079 KH |
1144 | #ifdef CONFIG_SUSPEND |
1145 | static int omap_i2c_suspend(struct device *dev) | |
1146 | { | |
1147 | if (!pm_runtime_suspended(dev)) | |
1148 | if (dev->bus && dev->bus->pm && dev->bus->pm->runtime_suspend) | |
1149 | dev->bus->pm->runtime_suspend(dev); | |
1150 | ||
1151 | return 0; | |
1152 | } | |
1153 | ||
1154 | static int omap_i2c_resume(struct device *dev) | |
1155 | { | |
1156 | if (!pm_runtime_suspended(dev)) | |
1157 | if (dev->bus && dev->bus->pm && dev->bus->pm->runtime_resume) | |
1158 | dev->bus->pm->runtime_resume(dev); | |
1159 | ||
1160 | return 0; | |
1161 | } | |
1162 | ||
1163 | static struct dev_pm_ops omap_i2c_pm_ops = { | |
1164 | .suspend = omap_i2c_suspend, | |
1165 | .resume = omap_i2c_resume, | |
1166 | }; | |
f72487e7 | 1167 | #define OMAP_I2C_PM_OPS (&omap_i2c_pm_ops) |
adf6e079 | 1168 | #else |
f72487e7 | 1169 | #define OMAP_I2C_PM_OPS NULL |
adf6e079 KH |
1170 | #endif |
1171 | ||
010d442c KS |
1172 | static struct platform_driver omap_i2c_driver = { |
1173 | .probe = omap_i2c_probe, | |
1174 | .remove = omap_i2c_remove, | |
1175 | .driver = { | |
f7bb0d9a | 1176 | .name = "omap_i2c", |
010d442c | 1177 | .owner = THIS_MODULE, |
f72487e7 | 1178 | .pm = OMAP_I2C_PM_OPS, |
010d442c KS |
1179 | }, |
1180 | }; | |
1181 | ||
1182 | /* I2C may be needed to bring up other drivers */ | |
1183 | static int __init | |
1184 | omap_i2c_init_driver(void) | |
1185 | { | |
1186 | return platform_driver_register(&omap_i2c_driver); | |
1187 | } | |
1188 | subsys_initcall(omap_i2c_init_driver); | |
1189 | ||
1190 | static void __exit omap_i2c_exit_driver(void) | |
1191 | { | |
1192 | platform_driver_unregister(&omap_i2c_driver); | |
1193 | } | |
1194 | module_exit(omap_i2c_exit_driver); | |
1195 | ||
1196 | MODULE_AUTHOR("MontaVista Software, Inc. (and others)"); | |
1197 | MODULE_DESCRIPTION("TI OMAP I2C bus adapter"); | |
1198 | MODULE_LICENSE("GPL"); | |
f7bb0d9a | 1199 | MODULE_ALIAS("platform:omap_i2c"); |