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c942fddf | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
010d442c KS |
2 | /* |
3 | * TI OMAP I2C master mode driver | |
4 | * | |
5 | * Copyright (C) 2003 MontaVista Software, Inc. | |
010d442c | 6 | * Copyright (C) 2005 Nokia Corporation |
c1a473bd | 7 | * Copyright (C) 2004 - 2007 Texas Instruments. |
010d442c | 8 | * |
c1a473bd TL |
9 | * Originally written by MontaVista Software, Inc. |
10 | * Additional contributions by: | |
11 | * Tony Lindgren <tony@atomide.com> | |
12 | * Imre Deak <imre.deak@nokia.com> | |
13 | * Juha Yrjölä <juha.yrjola@solidboot.com> | |
14 | * Syed Khasim <x0khasim@ti.com> | |
15 | * Nishant Menon <nm@ti.com> | |
010d442c KS |
16 | */ |
17 | ||
18 | #include <linux/module.h> | |
19 | #include <linux/delay.h> | |
20 | #include <linux/i2c.h> | |
21 | #include <linux/err.h> | |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/completion.h> | |
24 | #include <linux/platform_device.h> | |
25 | #include <linux/clk.h> | |
c1a473bd | 26 | #include <linux/io.h> |
6145197b | 27 | #include <linux/of.h> |
5a0e3ad6 | 28 | #include <linux/slab.h> |
79fc540f | 29 | #include <linux/platform_data/i2c-omap.h> |
27b1fec2 | 30 | #include <linux/pm_runtime.h> |
096ea30c | 31 | #include <linux/pinctrl/consumer.h> |
8cafbf26 | 32 | #include <linux/property.h> |
010d442c | 33 | |
9c76b878 | 34 | /* I2C controller revisions */ |
4e80f727 | 35 | #define OMAP_I2C_OMAP1_REV_2 0x20 |
9c76b878 PW |
36 | |
37 | /* I2C controller revisions present on specific hardware */ | |
47dcd016 S |
38 | #define OMAP_I2C_REV_ON_2430 0x00000036 |
39 | #define OMAP_I2C_REV_ON_3430_3530 0x0000003C | |
40 | #define OMAP_I2C_REV_ON_3630 0x00000040 | |
41 | #define OMAP_I2C_REV_ON_4430_PLUS 0x50400002 | |
9c76b878 | 42 | |
010d442c KS |
43 | /* timeout waiting for the controller to respond */ |
44 | #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000)) | |
45 | ||
6d8451d5 FB |
46 | /* timeout for pm runtime autosuspend */ |
47 | #define OMAP_I2C_PM_TIMEOUT 1000 /* ms */ | |
48 | ||
0f5768bf AK |
49 | /* timeout for making decision on bus free status */ |
50 | #define OMAP_I2C_BUS_FREE_TIMEOUT (msecs_to_jiffies(10)) | |
51 | ||
5043e9e7 | 52 | /* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */ |
f38e66e0 SS |
53 | enum { |
54 | OMAP_I2C_REV_REG = 0, | |
55 | OMAP_I2C_IE_REG, | |
56 | OMAP_I2C_STAT_REG, | |
57 | OMAP_I2C_IV_REG, | |
58 | OMAP_I2C_WE_REG, | |
59 | OMAP_I2C_SYSS_REG, | |
60 | OMAP_I2C_BUF_REG, | |
61 | OMAP_I2C_CNT_REG, | |
62 | OMAP_I2C_DATA_REG, | |
63 | OMAP_I2C_SYSC_REG, | |
64 | OMAP_I2C_CON_REG, | |
65 | OMAP_I2C_OA_REG, | |
66 | OMAP_I2C_SA_REG, | |
67 | OMAP_I2C_PSC_REG, | |
68 | OMAP_I2C_SCLL_REG, | |
69 | OMAP_I2C_SCLH_REG, | |
70 | OMAP_I2C_SYSTEST_REG, | |
71 | OMAP_I2C_BUFSTAT_REG, | |
b8853088 AG |
72 | /* only on OMAP4430 */ |
73 | OMAP_I2C_IP_V2_REVNB_LO, | |
74 | OMAP_I2C_IP_V2_REVNB_HI, | |
75 | OMAP_I2C_IP_V2_IRQSTATUS_RAW, | |
76 | OMAP_I2C_IP_V2_IRQENABLE_SET, | |
77 | OMAP_I2C_IP_V2_IRQENABLE_CLR, | |
f38e66e0 | 78 | }; |
010d442c KS |
79 | |
80 | /* I2C Interrupt Enable Register (OMAP_I2C_IE): */ | |
b6ee52c3 NM |
81 | #define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */ |
82 | #define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */ | |
010d442c KS |
83 | #define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */ |
84 | #define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */ | |
85 | #define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */ | |
86 | #define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */ | |
87 | #define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */ | |
88 | ||
89 | /* I2C Status Register (OMAP_I2C_STAT): */ | |
b6ee52c3 NM |
90 | #define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */ |
91 | #define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */ | |
010d442c KS |
92 | #define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */ |
93 | #define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */ | |
94 | #define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ | |
95 | #define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */ | |
9fd6ada8 | 96 | #define OMAP_I2C_STAT_BF (1 << 8) /* Bus Free */ |
010d442c KS |
97 | #define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ |
98 | #define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */ | |
99 | #define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */ | |
100 | #define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */ | |
101 | #define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */ | |
102 | ||
5043e9e7 KJ |
103 | /* I2C WE wakeup enable register */ |
104 | #define OMAP_I2C_WE_XDR_WE (1 << 14) /* TX drain wakup */ | |
105 | #define OMAP_I2C_WE_RDR_WE (1 << 13) /* RX drain wakeup */ | |
106 | #define OMAP_I2C_WE_AAS_WE (1 << 9) /* Address as slave wakeup*/ | |
107 | #define OMAP_I2C_WE_BF_WE (1 << 8) /* Bus free wakeup */ | |
108 | #define OMAP_I2C_WE_STC_WE (1 << 6) /* Start condition wakeup */ | |
109 | #define OMAP_I2C_WE_GC_WE (1 << 5) /* General call wakeup */ | |
110 | #define OMAP_I2C_WE_DRDY_WE (1 << 3) /* TX/RX data ready wakeup */ | |
111 | #define OMAP_I2C_WE_ARDY_WE (1 << 2) /* Reg access ready wakeup */ | |
112 | #define OMAP_I2C_WE_NACK_WE (1 << 1) /* No acknowledgment wakeup */ | |
113 | #define OMAP_I2C_WE_AL_WE (1 << 0) /* Arbitration lost wakeup */ | |
114 | ||
115 | #define OMAP_I2C_WE_ALL (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \ | |
116 | OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \ | |
117 | OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \ | |
118 | OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \ | |
119 | OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE) | |
120 | ||
010d442c KS |
121 | /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */ |
122 | #define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */ | |
b6ee52c3 | 123 | #define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */ |
010d442c | 124 | #define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */ |
b6ee52c3 | 125 | #define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */ |
010d442c KS |
126 | |
127 | /* I2C Configuration Register (OMAP_I2C_CON): */ | |
128 | #define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */ | |
129 | #define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */ | |
b6ee52c3 | 130 | #define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */ |
010d442c KS |
131 | #define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */ |
132 | #define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */ | |
133 | #define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */ | |
134 | #define OMAP_I2C_CON_XA (1 << 8) /* Expand address */ | |
135 | #define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */ | |
136 | #define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */ | |
137 | #define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */ | |
138 | ||
4574eb68 SMK |
139 | /* I2C SCL time value when Master */ |
140 | #define OMAP_I2C_SCLL_HSSCLL 8 | |
141 | #define OMAP_I2C_SCLH_HSSCLH 8 | |
142 | ||
010d442c | 143 | /* I2C System Test Register (OMAP_I2C_SYSTEST): */ |
010d442c KS |
144 | #define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */ |
145 | #define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */ | |
146 | #define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */ | |
147 | #define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */ | |
9fd6ada8 AK |
148 | /* Functional mode */ |
149 | #define OMAP_I2C_SYSTEST_SCL_I_FUNC (1 << 8) /* SCL line input value */ | |
150 | #define OMAP_I2C_SYSTEST_SCL_O_FUNC (1 << 7) /* SCL line output value */ | |
151 | #define OMAP_I2C_SYSTEST_SDA_I_FUNC (1 << 6) /* SDA line input value */ | |
152 | #define OMAP_I2C_SYSTEST_SDA_O_FUNC (1 << 5) /* SDA line output value */ | |
153 | /* SDA/SCL IO mode */ | |
010d442c KS |
154 | #define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */ |
155 | #define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */ | |
156 | #define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */ | |
157 | #define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */ | |
010d442c | 158 | |
fdd07fe6 PW |
159 | /* OCP_SYSSTATUS bit definitions */ |
160 | #define SYSS_RESETDONE_MASK (1 << 0) | |
161 | ||
162 | /* OCP_SYSCONFIG bit definitions */ | |
163 | #define SYSC_CLOCKACTIVITY_MASK (0x3 << 8) | |
164 | #define SYSC_SIDLEMODE_MASK (0x3 << 3) | |
165 | #define SYSC_ENAWAKEUP_MASK (1 << 2) | |
166 | #define SYSC_SOFTRESET_MASK (1 << 1) | |
167 | #define SYSC_AUTOIDLE_MASK (1 << 0) | |
168 | ||
169 | #define SYSC_IDLEMODE_SMART 0x2 | |
170 | #define SYSC_CLOCKACTIVITY_FCLK 0x2 | |
010d442c | 171 | |
f3083d92 | 172 | /* Errata definitions */ |
173 | #define I2C_OMAP_ERRATA_I207 (1 << 0) | |
c8db38f0 | 174 | #define I2C_OMAP_ERRATA_I462 (1 << 1) |
010d442c | 175 | |
4368de19 OD |
176 | #define OMAP_I2C_IP_V2_INTERRUPTS_MASK 0x6FFF |
177 | ||
010d442c KS |
178 | struct omap_i2c_dev { |
179 | struct device *dev; | |
180 | void __iomem *base; /* virtual */ | |
181 | int irq; | |
d84d3ea3 | 182 | int reg_shift; /* bit shift for I2C register addresses */ |
010d442c KS |
183 | struct completion cmd_complete; |
184 | struct resource *ioarea; | |
49839dc9 PW |
185 | u32 latency; /* maximum mpu wkup latency */ |
186 | void (*set_mpu_wkup_lat)(struct device *dev, | |
187 | long latency); | |
6145197b | 188 | u32 speed; /* Speed of bus in kHz */ |
6145197b | 189 | u32 flags; |
4368de19 | 190 | u16 scheme; |
010d442c KS |
191 | u16 cmd_err; |
192 | u8 *buf; | |
f38e66e0 | 193 | u8 *regs; |
010d442c KS |
194 | size_t buf_len; |
195 | struct i2c_adapter adapter; | |
dd74548d | 196 | u8 threshold; |
b6ee52c3 NM |
197 | u8 fifo_size; /* use as flag and value |
198 | * fifo_size==0 implies no fifo | |
199 | * if set, should be trsh+1 | |
200 | */ | |
47dcd016 | 201 | u32 rev; |
b6ee52c3 | 202 | unsigned b_hw:1; /* bad h/w fixes */ |
0f5768bf AK |
203 | unsigned bb_valid:1; /* true when BB-bit reflects |
204 | * the I2C bus state | |
205 | */ | |
079d8af2 | 206 | unsigned receiver:1; /* true when we're in receiver mode */ |
f08ac4e7 | 207 | u16 iestate; /* Saved interrupt register */ |
ef871432 RN |
208 | u16 pscstate; |
209 | u16 scllstate; | |
210 | u16 sclhstate; | |
ef871432 RN |
211 | u16 syscstate; |
212 | u16 westate; | |
f3083d92 | 213 | u16 errata; |
010d442c KS |
214 | }; |
215 | ||
a1295577 | 216 | static const u8 reg_map_ip_v1[] = { |
f38e66e0 SS |
217 | [OMAP_I2C_REV_REG] = 0x00, |
218 | [OMAP_I2C_IE_REG] = 0x01, | |
219 | [OMAP_I2C_STAT_REG] = 0x02, | |
220 | [OMAP_I2C_IV_REG] = 0x03, | |
221 | [OMAP_I2C_WE_REG] = 0x03, | |
222 | [OMAP_I2C_SYSS_REG] = 0x04, | |
223 | [OMAP_I2C_BUF_REG] = 0x05, | |
224 | [OMAP_I2C_CNT_REG] = 0x06, | |
225 | [OMAP_I2C_DATA_REG] = 0x07, | |
226 | [OMAP_I2C_SYSC_REG] = 0x08, | |
227 | [OMAP_I2C_CON_REG] = 0x09, | |
228 | [OMAP_I2C_OA_REG] = 0x0a, | |
229 | [OMAP_I2C_SA_REG] = 0x0b, | |
230 | [OMAP_I2C_PSC_REG] = 0x0c, | |
231 | [OMAP_I2C_SCLL_REG] = 0x0d, | |
232 | [OMAP_I2C_SCLH_REG] = 0x0e, | |
233 | [OMAP_I2C_SYSTEST_REG] = 0x0f, | |
234 | [OMAP_I2C_BUFSTAT_REG] = 0x10, | |
235 | }; | |
236 | ||
a1295577 | 237 | static const u8 reg_map_ip_v2[] = { |
f38e66e0 SS |
238 | [OMAP_I2C_REV_REG] = 0x04, |
239 | [OMAP_I2C_IE_REG] = 0x2c, | |
240 | [OMAP_I2C_STAT_REG] = 0x28, | |
241 | [OMAP_I2C_IV_REG] = 0x34, | |
242 | [OMAP_I2C_WE_REG] = 0x34, | |
243 | [OMAP_I2C_SYSS_REG] = 0x90, | |
244 | [OMAP_I2C_BUF_REG] = 0x94, | |
245 | [OMAP_I2C_CNT_REG] = 0x98, | |
246 | [OMAP_I2C_DATA_REG] = 0x9c, | |
2727b175 | 247 | [OMAP_I2C_SYSC_REG] = 0x10, |
f38e66e0 SS |
248 | [OMAP_I2C_CON_REG] = 0xa4, |
249 | [OMAP_I2C_OA_REG] = 0xa8, | |
250 | [OMAP_I2C_SA_REG] = 0xac, | |
251 | [OMAP_I2C_PSC_REG] = 0xb0, | |
252 | [OMAP_I2C_SCLL_REG] = 0xb4, | |
253 | [OMAP_I2C_SCLH_REG] = 0xb8, | |
254 | [OMAP_I2C_SYSTEST_REG] = 0xbC, | |
255 | [OMAP_I2C_BUFSTAT_REG] = 0xc0, | |
b8853088 AG |
256 | [OMAP_I2C_IP_V2_REVNB_LO] = 0x00, |
257 | [OMAP_I2C_IP_V2_REVNB_HI] = 0x04, | |
258 | [OMAP_I2C_IP_V2_IRQSTATUS_RAW] = 0x24, | |
259 | [OMAP_I2C_IP_V2_IRQENABLE_SET] = 0x2c, | |
260 | [OMAP_I2C_IP_V2_IRQENABLE_CLR] = 0x30, | |
f38e66e0 SS |
261 | }; |
262 | ||
89f845a6 WS |
263 | static int omap_i2c_xfer_data(struct omap_i2c_dev *omap); |
264 | ||
63f8f856 | 265 | static inline void omap_i2c_write_reg(struct omap_i2c_dev *omap, |
010d442c KS |
266 | int reg, u16 val) |
267 | { | |
63f8f856 FB |
268 | writew_relaxed(val, omap->base + |
269 | (omap->regs[reg] << omap->reg_shift)); | |
010d442c KS |
270 | } |
271 | ||
63f8f856 | 272 | static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *omap, int reg) |
010d442c | 273 | { |
63f8f856 FB |
274 | return readw_relaxed(omap->base + |
275 | (omap->regs[reg] << omap->reg_shift)); | |
010d442c KS |
276 | } |
277 | ||
63f8f856 | 278 | static void __omap_i2c_init(struct omap_i2c_dev *omap) |
95dd3032 S |
279 | { |
280 | ||
63f8f856 | 281 | omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, 0); |
95dd3032 S |
282 | |
283 | /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */ | |
63f8f856 | 284 | omap_i2c_write_reg(omap, OMAP_I2C_PSC_REG, omap->pscstate); |
95dd3032 S |
285 | |
286 | /* SCL low and high time values */ | |
63f8f856 FB |
287 | omap_i2c_write_reg(omap, OMAP_I2C_SCLL_REG, omap->scllstate); |
288 | omap_i2c_write_reg(omap, OMAP_I2C_SCLH_REG, omap->sclhstate); | |
289 | if (omap->rev >= OMAP_I2C_REV_ON_3430_3530) | |
290 | omap_i2c_write_reg(omap, OMAP_I2C_WE_REG, omap->westate); | |
95dd3032 S |
291 | |
292 | /* Take the I2C module out of reset: */ | |
63f8f856 | 293 | omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN); |
95dd3032 | 294 | |
4f734a3a AK |
295 | /* |
296 | * NOTE: right after setting CON_EN, STAT_BB could be 0 while the | |
297 | * bus is busy. It will be changed to 1 on the next IP FCLK clock. | |
298 | * udelay(1) will be enough to fix that. | |
299 | */ | |
300 | ||
95dd3032 S |
301 | /* |
302 | * Don't write to this register if the IE state is 0 as it can | |
303 | * cause deadlock. | |
304 | */ | |
63f8f856 FB |
305 | if (omap->iestate) |
306 | omap_i2c_write_reg(omap, OMAP_I2C_IE_REG, omap->iestate); | |
95dd3032 S |
307 | } |
308 | ||
63f8f856 | 309 | static int omap_i2c_reset(struct omap_i2c_dev *omap) |
010d442c | 310 | { |
010d442c | 311 | unsigned long timeout; |
ca85e248 S |
312 | u16 sysc; |
313 | ||
63f8f856 FB |
314 | if (omap->rev >= OMAP_I2C_OMAP1_REV_2) { |
315 | sysc = omap_i2c_read_reg(omap, OMAP_I2C_SYSC_REG); | |
ca85e248 | 316 | |
57eb81b1 | 317 | /* Disable I2C controller before soft reset */ |
63f8f856 FB |
318 | omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, |
319 | omap_i2c_read_reg(omap, OMAP_I2C_CON_REG) & | |
57eb81b1 MG |
320 | ~(OMAP_I2C_CON_EN)); |
321 | ||
63f8f856 | 322 | omap_i2c_write_reg(omap, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK); |
010d442c KS |
323 | /* For some reason we need to set the EN bit before the |
324 | * reset done bit gets set. */ | |
325 | timeout = jiffies + OMAP_I2C_TIMEOUT; | |
63f8f856 FB |
326 | omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN); |
327 | while (!(omap_i2c_read_reg(omap, OMAP_I2C_SYSS_REG) & | |
fdd07fe6 | 328 | SYSS_RESETDONE_MASK)) { |
010d442c | 329 | if (time_after(jiffies, timeout)) { |
63f8f856 | 330 | dev_warn(omap->dev, "timeout waiting " |
010d442c KS |
331 | "for controller reset\n"); |
332 | return -ETIMEDOUT; | |
333 | } | |
334 | msleep(1); | |
335 | } | |
fdd07fe6 PW |
336 | |
337 | /* SYSC register is cleared by the reset; rewrite it */ | |
63f8f856 | 338 | omap_i2c_write_reg(omap, OMAP_I2C_SYSC_REG, sysc); |
fdd07fe6 | 339 | |
63f8f856 | 340 | if (omap->rev > OMAP_I2C_REV_ON_3430_3530) { |
23173eae | 341 | /* Schedule I2C-bus monitoring on the next transfer */ |
63f8f856 | 342 | omap->bb_valid = 0; |
23173eae | 343 | } |
010d442c | 344 | } |
0f5768bf | 345 | |
d6c842ad S |
346 | return 0; |
347 | } | |
348 | ||
63f8f856 | 349 | static int omap_i2c_init(struct omap_i2c_dev *omap) |
d6c842ad S |
350 | { |
351 | u16 psc = 0, scll = 0, sclh = 0; | |
352 | u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0; | |
353 | unsigned long fclk_rate = 12000000; | |
354 | unsigned long internal_clk = 0; | |
355 | struct clk *fclk; | |
883b3b65 | 356 | int error; |
d6c842ad | 357 | |
63f8f856 | 358 | if (omap->rev >= OMAP_I2C_REV_ON_3430_3530) { |
d6c842ad S |
359 | /* |
360 | * Enabling all wakup sources to stop I2C freezing on | |
361 | * WFI instruction. | |
362 | * REVISIT: Some wkup sources might not be needed. | |
363 | */ | |
63f8f856 | 364 | omap->westate = OMAP_I2C_WE_ALL; |
d6c842ad | 365 | } |
010d442c | 366 | |
63f8f856 | 367 | if (omap->flags & OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK) { |
0e9ae109 RK |
368 | /* |
369 | * The I2C functional clock is the armxor_ck, so there's | |
370 | * no need to get "armxor_ck" separately. Now, if OMAP2420 | |
371 | * always returns 12MHz for the functional clock, we can | |
372 | * do this bit unconditionally. | |
373 | */ | |
63f8f856 | 374 | fclk = clk_get(omap->dev, "fck"); |
883b3b65 TL |
375 | if (IS_ERR(fclk)) { |
376 | error = PTR_ERR(fclk); | |
377 | dev_err(omap->dev, "could not get fck: %i\n", error); | |
378 | ||
379 | return error; | |
380 | } | |
381 | ||
27b1fec2 RN |
382 | fclk_rate = clk_get_rate(fclk); |
383 | clk_put(fclk); | |
0e9ae109 | 384 | |
010d442c KS |
385 | /* TRM for 5912 says the I2C clock must be prescaled to be |
386 | * between 7 - 12 MHz. The XOR input clock is typically | |
387 | * 12, 13 or 19.2 MHz. So we should have code that produces: | |
388 | * | |
389 | * XOR MHz Divider Prescaler | |
390 | * 12 1 0 | |
391 | * 13 2 1 | |
392 | * 19.2 2 1 | |
393 | */ | |
d7aef138 JD |
394 | if (fclk_rate > 12000000) |
395 | psc = fclk_rate / 12000000; | |
010d442c KS |
396 | } |
397 | ||
63f8f856 | 398 | if (!(omap->flags & OMAP_I2C_FLAG_SIMPLE_CLOCK)) { |
4574eb68 | 399 | |
84bf2c86 AK |
400 | /* |
401 | * HSI2C controller internal clk rate should be 19.2 Mhz for | |
402 | * HS and for all modes on 2430. On 34xx we can use lower rate | |
403 | * to get longer filter period for better noise suppression. | |
404 | * The filter is iclk (fclk for HS) period. | |
405 | */ | |
63f8f856 FB |
406 | if (omap->speed > 400 || |
407 | omap->flags & OMAP_I2C_FLAG_FORCE_19200_INT_CLK) | |
84bf2c86 | 408 | internal_clk = 19200; |
63f8f856 | 409 | else if (omap->speed > 100) |
84bf2c86 AK |
410 | internal_clk = 9600; |
411 | else | |
412 | internal_clk = 4000; | |
63f8f856 | 413 | fclk = clk_get(omap->dev, "fck"); |
883b3b65 TL |
414 | if (IS_ERR(fclk)) { |
415 | error = PTR_ERR(fclk); | |
416 | dev_err(omap->dev, "could not get fck: %i\n", error); | |
417 | ||
418 | return error; | |
419 | } | |
27b1fec2 RN |
420 | fclk_rate = clk_get_rate(fclk) / 1000; |
421 | clk_put(fclk); | |
4574eb68 SMK |
422 | |
423 | /* Compute prescaler divisor */ | |
424 | psc = fclk_rate / internal_clk; | |
425 | psc = psc - 1; | |
426 | ||
427 | /* If configured for High Speed */ | |
63f8f856 | 428 | if (omap->speed > 400) { |
baf46b4e AK |
429 | unsigned long scl; |
430 | ||
4574eb68 | 431 | /* For first phase of HS mode */ |
baf46b4e AK |
432 | scl = internal_clk / 400; |
433 | fsscll = scl - (scl / 3) - 7; | |
434 | fssclh = (scl / 3) - 5; | |
4574eb68 SMK |
435 | |
436 | /* For second phase of HS mode */ | |
63f8f856 | 437 | scl = fclk_rate / omap->speed; |
baf46b4e AK |
438 | hsscll = scl - (scl / 3) - 7; |
439 | hssclh = (scl / 3) - 5; | |
63f8f856 | 440 | } else if (omap->speed > 100) { |
baf46b4e AK |
441 | unsigned long scl; |
442 | ||
443 | /* Fast mode */ | |
63f8f856 | 444 | scl = internal_clk / omap->speed; |
baf46b4e AK |
445 | fsscll = scl - (scl / 3) - 7; |
446 | fssclh = (scl / 3) - 5; | |
4574eb68 | 447 | } else { |
baf46b4e | 448 | /* Standard mode */ |
63f8f856 FB |
449 | fsscll = internal_clk / (omap->speed * 2) - 7; |
450 | fssclh = internal_clk / (omap->speed * 2) - 5; | |
4574eb68 SMK |
451 | } |
452 | scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll; | |
453 | sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh; | |
454 | } else { | |
455 | /* Program desired operating rate */ | |
456 | fclk_rate /= (psc + 1) * 1000; | |
457 | if (psc > 2) | |
458 | psc = 2; | |
63f8f856 FB |
459 | scll = fclk_rate / (omap->speed * 2) - 7 + psc; |
460 | sclh = fclk_rate / (omap->speed * 2) - 7 + psc; | |
4574eb68 SMK |
461 | } |
462 | ||
63f8f856 | 463 | omap->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY | |
c1a473bd | 464 | OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK | |
63f8f856 | 465 | OMAP_I2C_IE_AL) | ((omap->fifo_size) ? |
ef871432 | 466 | (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0); |
95dd3032 | 467 | |
63f8f856 FB |
468 | omap->pscstate = psc; |
469 | omap->scllstate = scll; | |
470 | omap->sclhstate = sclh; | |
95dd3032 | 471 | |
63f8f856 | 472 | if (omap->rev <= OMAP_I2C_REV_ON_3430_3530) { |
0f5768bf | 473 | /* Not implemented */ |
63f8f856 | 474 | omap->bb_valid = 1; |
0f5768bf AK |
475 | } |
476 | ||
63f8f856 | 477 | __omap_i2c_init(omap); |
95dd3032 | 478 | |
010d442c KS |
479 | return 0; |
480 | } | |
481 | ||
93367bfc CF |
482 | /* |
483 | * Try bus recovery, but only if SDA is actually low. | |
484 | */ | |
485 | static int omap_i2c_recover_bus(struct omap_i2c_dev *omap) | |
486 | { | |
487 | u16 systest; | |
488 | ||
489 | systest = omap_i2c_read_reg(omap, OMAP_I2C_SYSTEST_REG); | |
490 | if ((systest & OMAP_I2C_SYSTEST_SCL_I_FUNC) && | |
491 | (systest & OMAP_I2C_SYSTEST_SDA_I_FUNC)) | |
492 | return 0; /* bus seems to already be fine */ | |
493 | if (!(systest & OMAP_I2C_SYSTEST_SCL_I_FUNC)) | |
494 | return -EBUSY; /* recovery would not fix SCL */ | |
495 | return i2c_recover_bus(&omap->adapter); | |
496 | } | |
497 | ||
010d442c KS |
498 | /* |
499 | * Waiting on Bus Busy | |
500 | */ | |
63f8f856 | 501 | static int omap_i2c_wait_for_bb(struct omap_i2c_dev *omap) |
010d442c KS |
502 | { |
503 | unsigned long timeout; | |
504 | ||
505 | timeout = jiffies + OMAP_I2C_TIMEOUT; | |
63f8f856 | 506 | while (omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) { |
9dcb0e7b | 507 | if (time_after(jiffies, timeout)) |
93367bfc | 508 | return omap_i2c_recover_bus(omap); |
010d442c KS |
509 | msleep(1); |
510 | } | |
511 | ||
512 | return 0; | |
513 | } | |
514 | ||
0f5768bf AK |
515 | /* |
516 | * Wait while BB-bit doesn't reflect the I2C bus state | |
517 | * | |
518 | * In a multimaster environment, after IP software reset, BB-bit value doesn't | |
519 | * correspond to the current bus state. It may happen what BB-bit will be 0, | |
520 | * while the bus is busy due to another I2C master activity. | |
521 | * Here are BB-bit values after reset: | |
522 | * SDA SCL BB NOTES | |
523 | * 0 0 0 1, 2 | |
524 | * 1 0 0 1, 2 | |
525 | * 0 1 1 | |
526 | * 1 1 0 3 | |
527 | * Later, if IP detect SDA=0 and SCL=1 (ACK) or SDA 1->0 while SCL=1 (START) | |
528 | * combinations on the bus, it set BB-bit to 1. | |
529 | * If IP detect SDA 0->1 while SCL=1 (STOP) combination on the bus, | |
530 | * it set BB-bit to 0 and BF to 1. | |
531 | * BB and BF bits correctly tracks the bus state while IP is suspended | |
532 | * BB bit became valid on the next FCLK clock after CON_EN bit set | |
533 | * | |
534 | * NOTES: | |
535 | * 1. Any transfer started when BB=0 and bus is busy wouldn't be | |
536 | * completed by IP and results in controller timeout. | |
537 | * 2. Any transfer started when BB=0 and SCL=0 results in IP | |
538 | * starting to drive SDA low. In that case IP corrupt data | |
539 | * on the bus. | |
540 | * 3. Any transfer started in the middle of another master's transfer | |
541 | * results in unpredictable results and data corruption | |
542 | */ | |
63f8f856 | 543 | static int omap_i2c_wait_for_bb_valid(struct omap_i2c_dev *omap) |
0f5768bf AK |
544 | { |
545 | unsigned long bus_free_timeout = 0; | |
546 | unsigned long timeout; | |
547 | int bus_free = 0; | |
548 | u16 stat, systest; | |
549 | ||
63f8f856 | 550 | if (omap->bb_valid) |
0f5768bf AK |
551 | return 0; |
552 | ||
553 | timeout = jiffies + OMAP_I2C_TIMEOUT; | |
554 | while (1) { | |
63f8f856 | 555 | stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG); |
0f5768bf AK |
556 | /* |
557 | * We will see BB or BF event in a case IP had detected any | |
558 | * activity on the I2C bus. Now IP correctly tracks the bus | |
559 | * state. BB-bit value is valid. | |
560 | */ | |
561 | if (stat & (OMAP_I2C_STAT_BB | OMAP_I2C_STAT_BF)) | |
562 | break; | |
563 | ||
564 | /* | |
565 | * Otherwise, we must look signals on the bus to make | |
566 | * the right decision. | |
567 | */ | |
63f8f856 | 568 | systest = omap_i2c_read_reg(omap, OMAP_I2C_SYSTEST_REG); |
0f5768bf AK |
569 | if ((systest & OMAP_I2C_SYSTEST_SCL_I_FUNC) && |
570 | (systest & OMAP_I2C_SYSTEST_SDA_I_FUNC)) { | |
571 | if (!bus_free) { | |
572 | bus_free_timeout = jiffies + | |
573 | OMAP_I2C_BUS_FREE_TIMEOUT; | |
574 | bus_free = 1; | |
575 | } | |
576 | ||
577 | /* | |
578 | * SDA and SCL lines was high for 10 ms without bus | |
579 | * activity detected. The bus is free. Consider | |
580 | * BB-bit value is valid. | |
581 | */ | |
582 | if (time_after(jiffies, bus_free_timeout)) | |
583 | break; | |
584 | } else { | |
585 | bus_free = 0; | |
586 | } | |
587 | ||
588 | if (time_after(jiffies, timeout)) { | |
93367bfc CF |
589 | /* |
590 | * SDA or SCL were low for the entire timeout without | |
591 | * any activity detected. Most likely, a slave is | |
592 | * locking up the bus with no master driving the clock. | |
593 | */ | |
63f8f856 | 594 | dev_warn(omap->dev, "timeout waiting for bus ready\n"); |
93367bfc | 595 | return omap_i2c_recover_bus(omap); |
0f5768bf AK |
596 | } |
597 | ||
598 | msleep(1); | |
599 | } | |
600 | ||
63f8f856 | 601 | omap->bb_valid = 1; |
0f5768bf AK |
602 | return 0; |
603 | } | |
604 | ||
63f8f856 | 605 | static void omap_i2c_resize_fifo(struct omap_i2c_dev *omap, u8 size, bool is_rx) |
dd74548d FB |
606 | { |
607 | u16 buf; | |
608 | ||
63f8f856 | 609 | if (omap->flags & OMAP_I2C_FLAG_NO_FIFO) |
dd74548d FB |
610 | return; |
611 | ||
612 | /* | |
613 | * Set up notification threshold based on message size. We're doing | |
614 | * this to try and avoid draining feature as much as possible. Whenever | |
615 | * we have big messages to transfer (bigger than our total fifo size) | |
616 | * then we might use draining feature to transfer the remaining bytes. | |
617 | */ | |
618 | ||
63f8f856 | 619 | omap->threshold = clamp(size, (u8) 1, omap->fifo_size); |
dd74548d | 620 | |
63f8f856 | 621 | buf = omap_i2c_read_reg(omap, OMAP_I2C_BUF_REG); |
dd74548d FB |
622 | |
623 | if (is_rx) { | |
624 | /* Clear RX Threshold */ | |
625 | buf &= ~(0x3f << 8); | |
63f8f856 | 626 | buf |= ((omap->threshold - 1) << 8) | OMAP_I2C_BUF_RXFIF_CLR; |
dd74548d FB |
627 | } else { |
628 | /* Clear TX Threshold */ | |
629 | buf &= ~0x3f; | |
63f8f856 | 630 | buf |= (omap->threshold - 1) | OMAP_I2C_BUF_TXFIF_CLR; |
dd74548d FB |
631 | } |
632 | ||
63f8f856 | 633 | omap_i2c_write_reg(omap, OMAP_I2C_BUF_REG, buf); |
dd74548d | 634 | |
63f8f856 FB |
635 | if (omap->rev < OMAP_I2C_REV_ON_3630) |
636 | omap->b_hw = 1; /* Enable hardware fixes */ | |
dd74548d FB |
637 | |
638 | /* calculate wakeup latency constraint for MPU */ | |
63f8f856 FB |
639 | if (omap->set_mpu_wkup_lat != NULL) |
640 | omap->latency = (1000000 * omap->threshold) / | |
641 | (1000 * omap->speed / 8); | |
dd74548d FB |
642 | } |
643 | ||
89f845a6 WS |
644 | static void omap_i2c_wait(struct omap_i2c_dev *omap) |
645 | { | |
646 | u16 stat; | |
647 | u16 mask = omap_i2c_read_reg(omap, OMAP_I2C_IE_REG); | |
648 | int count = 0; | |
649 | ||
650 | do { | |
651 | stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG); | |
652 | count++; | |
653 | } while (!(stat & mask) && count < 5); | |
654 | } | |
655 | ||
010d442c KS |
656 | /* |
657 | * Low level master read/write transaction. | |
658 | */ | |
659 | static int omap_i2c_xfer_msg(struct i2c_adapter *adap, | |
89f845a6 | 660 | struct i2c_msg *msg, int stop, bool polling) |
010d442c | 661 | { |
63f8f856 | 662 | struct omap_i2c_dev *omap = i2c_get_adapdata(adap); |
33d54985 | 663 | unsigned long timeout; |
010d442c | 664 | u16 w; |
89f845a6 | 665 | int ret; |
010d442c | 666 | |
63f8f856 | 667 | dev_dbg(omap->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n", |
010d442c KS |
668 | msg->addr, msg->len, msg->flags, stop); |
669 | ||
63f8f856 FB |
670 | omap->receiver = !!(msg->flags & I2C_M_RD); |
671 | omap_i2c_resize_fifo(omap, msg->len, omap->receiver); | |
dd74548d | 672 | |
63f8f856 | 673 | omap_i2c_write_reg(omap, OMAP_I2C_SA_REG, msg->addr); |
010d442c KS |
674 | |
675 | /* REVISIT: Could the STB bit of I2C_CON be used with probing? */ | |
63f8f856 FB |
676 | omap->buf = msg->buf; |
677 | omap->buf_len = msg->len; | |
010d442c | 678 | |
63f8f856 | 679 | /* make sure writes to omap->buf_len are ordered */ |
d60ece5f FB |
680 | barrier(); |
681 | ||
63f8f856 | 682 | omap_i2c_write_reg(omap, OMAP_I2C_CNT_REG, omap->buf_len); |
010d442c | 683 | |
b6ee52c3 | 684 | /* Clear the FIFO Buffers */ |
63f8f856 | 685 | w = omap_i2c_read_reg(omap, OMAP_I2C_BUF_REG); |
b6ee52c3 | 686 | w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR; |
63f8f856 | 687 | omap_i2c_write_reg(omap, OMAP_I2C_BUF_REG, w); |
b6ee52c3 | 688 | |
89f845a6 WS |
689 | if (!polling) |
690 | reinit_completion(&omap->cmd_complete); | |
63f8f856 | 691 | omap->cmd_err = 0; |
010d442c KS |
692 | |
693 | w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT; | |
4574eb68 SMK |
694 | |
695 | /* High speed configuration */ | |
63f8f856 | 696 | if (omap->speed > 400) |
b6ee52c3 | 697 | w |= OMAP_I2C_CON_OPMODE_HS; |
4574eb68 | 698 | |
fb604a3d LP |
699 | if (msg->flags & I2C_M_STOP) |
700 | stop = 1; | |
010d442c KS |
701 | if (msg->flags & I2C_M_TEN) |
702 | w |= OMAP_I2C_CON_XA; | |
703 | if (!(msg->flags & I2C_M_RD)) | |
704 | w |= OMAP_I2C_CON_TRX; | |
c1a473bd | 705 | |
63f8f856 | 706 | if (!omap->b_hw && stop) |
010d442c | 707 | w |= OMAP_I2C_CON_STP; |
4f734a3a AK |
708 | /* |
709 | * NOTE: STAT_BB bit could became 1 here if another master occupy | |
710 | * the bus. IP successfully complete transfer when the bus will be | |
711 | * free again (BB reset to 0). | |
712 | */ | |
63f8f856 | 713 | omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, w); |
010d442c | 714 | |
b6ee52c3 NM |
715 | /* |
716 | * Don't write stt and stp together on some hardware. | |
717 | */ | |
63f8f856 | 718 | if (omap->b_hw && stop) { |
b6ee52c3 | 719 | unsigned long delay = jiffies + OMAP_I2C_TIMEOUT; |
63f8f856 | 720 | u16 con = omap_i2c_read_reg(omap, OMAP_I2C_CON_REG); |
b6ee52c3 | 721 | while (con & OMAP_I2C_CON_STT) { |
63f8f856 | 722 | con = omap_i2c_read_reg(omap, OMAP_I2C_CON_REG); |
b6ee52c3 NM |
723 | |
724 | /* Let the user know if i2c is in a bad state */ | |
725 | if (time_after(jiffies, delay)) { | |
63f8f856 | 726 | dev_err(omap->dev, "controller timed out " |
b6ee52c3 NM |
727 | "waiting for start condition to finish\n"); |
728 | return -ETIMEDOUT; | |
729 | } | |
730 | cpu_relax(); | |
731 | } | |
732 | ||
733 | w |= OMAP_I2C_CON_STP; | |
734 | w &= ~OMAP_I2C_CON_STT; | |
63f8f856 | 735 | omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, w); |
b6ee52c3 NM |
736 | } |
737 | ||
b7af349b JN |
738 | /* |
739 | * REVISIT: We should abort the transfer on signals, but the bus goes | |
740 | * into arbitration and we're currently unable to recover from it. | |
741 | */ | |
89f845a6 WS |
742 | if (!polling) { |
743 | timeout = wait_for_completion_timeout(&omap->cmd_complete, | |
744 | OMAP_I2C_TIMEOUT); | |
745 | } else { | |
746 | do { | |
747 | omap_i2c_wait(omap); | |
748 | ret = omap_i2c_xfer_data(omap); | |
749 | } while (ret == -EAGAIN); | |
750 | ||
751 | timeout = !ret; | |
752 | } | |
753 | ||
33d54985 | 754 | if (timeout == 0) { |
63f8f856 FB |
755 | dev_err(omap->dev, "controller timed out\n"); |
756 | omap_i2c_reset(omap); | |
757 | __omap_i2c_init(omap); | |
010d442c KS |
758 | return -ETIMEDOUT; |
759 | } | |
760 | ||
63f8f856 | 761 | if (likely(!omap->cmd_err)) |
010d442c KS |
762 | return 0; |
763 | ||
764 | /* We have an error */ | |
63f8f856 FB |
765 | if (omap->cmd_err & (OMAP_I2C_STAT_ROVR | OMAP_I2C_STAT_XUDF)) { |
766 | omap_i2c_reset(omap); | |
767 | __omap_i2c_init(omap); | |
010d442c KS |
768 | return -EIO; |
769 | } | |
770 | ||
63f8f856 | 771 | if (omap->cmd_err & OMAP_I2C_STAT_AL) |
b76911d2 AK |
772 | return -EAGAIN; |
773 | ||
63f8f856 | 774 | if (omap->cmd_err & OMAP_I2C_STAT_NACK) { |
010d442c KS |
775 | if (msg->flags & I2C_M_IGNORE_NAK) |
776 | return 0; | |
cda2109a | 777 | |
63f8f856 | 778 | w = omap_i2c_read_reg(omap, OMAP_I2C_CON_REG); |
cda2109a | 779 | w |= OMAP_I2C_CON_STP; |
63f8f856 | 780 | omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, w); |
010d442c KS |
781 | return -EREMOTEIO; |
782 | } | |
783 | return -EIO; | |
784 | } | |
785 | ||
786 | ||
787 | /* | |
788 | * Prepare controller for a transaction and call omap_i2c_xfer_msg | |
789 | * to do the work during IRQ processing. | |
790 | */ | |
791 | static int | |
89f845a6 WS |
792 | omap_i2c_xfer_common(struct i2c_adapter *adap, struct i2c_msg msgs[], int num, |
793 | bool polling) | |
010d442c | 794 | { |
63f8f856 | 795 | struct omap_i2c_dev *omap = i2c_get_adapdata(adap); |
010d442c KS |
796 | int i; |
797 | int r; | |
798 | ||
63f8f856 | 799 | r = pm_runtime_get_sync(omap->dev); |
ff370257 | 800 | if (r < 0) |
33ec5e81 | 801 | goto out; |
010d442c | 802 | |
63f8f856 | 803 | r = omap_i2c_wait_for_bb_valid(omap); |
0f5768bf AK |
804 | if (r < 0) |
805 | goto out; | |
806 | ||
63f8f856 | 807 | r = omap_i2c_wait_for_bb(omap); |
c1a473bd | 808 | if (r < 0) |
010d442c KS |
809 | goto out; |
810 | ||
63f8f856 FB |
811 | if (omap->set_mpu_wkup_lat != NULL) |
812 | omap->set_mpu_wkup_lat(omap->dev, omap->latency); | |
6a91b558 | 813 | |
010d442c | 814 | for (i = 0; i < num; i++) { |
89f845a6 WS |
815 | r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)), |
816 | polling); | |
010d442c KS |
817 | if (r != 0) |
818 | break; | |
819 | } | |
820 | ||
821 | if (r == 0) | |
822 | r = num; | |
5c64eb26 | 823 | |
63f8f856 | 824 | omap_i2c_wait_for_bb(omap); |
1ab36045 | 825 | |
63f8f856 FB |
826 | if (omap->set_mpu_wkup_lat != NULL) |
827 | omap->set_mpu_wkup_lat(omap->dev, -1); | |
1ab36045 | 828 | |
010d442c | 829 | out: |
63f8f856 FB |
830 | pm_runtime_mark_last_busy(omap->dev); |
831 | pm_runtime_put_autosuspend(omap->dev); | |
010d442c KS |
832 | return r; |
833 | } | |
834 | ||
89f845a6 WS |
835 | static int |
836 | omap_i2c_xfer_irq(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) | |
837 | { | |
838 | return omap_i2c_xfer_common(adap, msgs, num, false); | |
839 | } | |
840 | ||
841 | static int | |
842 | omap_i2c_xfer_polling(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) | |
843 | { | |
844 | return omap_i2c_xfer_common(adap, msgs, num, true); | |
845 | } | |
846 | ||
010d442c KS |
847 | static u32 |
848 | omap_i2c_func(struct i2c_adapter *adap) | |
849 | { | |
fb604a3d LP |
850 | return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) | |
851 | I2C_FUNC_PROTOCOL_MANGLING; | |
010d442c KS |
852 | } |
853 | ||
854 | static inline void | |
63f8f856 | 855 | omap_i2c_complete_cmd(struct omap_i2c_dev *omap, u16 err) |
010d442c | 856 | { |
63f8f856 FB |
857 | omap->cmd_err |= err; |
858 | complete(&omap->cmd_complete); | |
010d442c KS |
859 | } |
860 | ||
861 | static inline void | |
63f8f856 | 862 | omap_i2c_ack_stat(struct omap_i2c_dev *omap, u16 stat) |
010d442c | 863 | { |
63f8f856 | 864 | omap_i2c_write_reg(omap, OMAP_I2C_STAT_REG, stat); |
010d442c KS |
865 | } |
866 | ||
63f8f856 | 867 | static inline void i2c_omap_errata_i207(struct omap_i2c_dev *omap, u16 stat) |
f3083d92 | 868 | { |
869 | /* | |
870 | * I2C Errata(Errata Nos. OMAP2: 1.67, OMAP3: 1.8) | |
871 | * Not applicable for OMAP4. | |
872 | * Under certain rare conditions, RDR could be set again | |
873 | * when the bus is busy, then ignore the interrupt and | |
874 | * clear the interrupt. | |
875 | */ | |
876 | if (stat & OMAP_I2C_STAT_RDR) { | |
877 | /* Step 1: If RDR is set, clear it */ | |
63f8f856 | 878 | omap_i2c_ack_stat(omap, OMAP_I2C_STAT_RDR); |
f3083d92 | 879 | |
880 | /* Step 2: */ | |
63f8f856 | 881 | if (!(omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG) |
f3083d92 | 882 | & OMAP_I2C_STAT_BB)) { |
883 | ||
884 | /* Step 3: */ | |
63f8f856 | 885 | if (omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG) |
f3083d92 | 886 | & OMAP_I2C_STAT_RDR) { |
63f8f856 FB |
887 | omap_i2c_ack_stat(omap, OMAP_I2C_STAT_RDR); |
888 | dev_dbg(omap->dev, "RDR when bus is busy.\n"); | |
f3083d92 | 889 | } |
890 | ||
891 | } | |
892 | } | |
893 | } | |
894 | ||
43469d8e PW |
895 | /* rev1 devices are apparently only on some 15xx */ |
896 | #ifdef CONFIG_ARCH_OMAP15XX | |
897 | ||
010d442c | 898 | static irqreturn_t |
4e80f727 | 899 | omap_i2c_omap1_isr(int this_irq, void *dev_id) |
010d442c | 900 | { |
63f8f856 | 901 | struct omap_i2c_dev *omap = dev_id; |
010d442c KS |
902 | u16 iv, w; |
903 | ||
63f8f856 | 904 | if (pm_runtime_suspended(omap->dev)) |
f08ac4e7 TL |
905 | return IRQ_NONE; |
906 | ||
63f8f856 | 907 | iv = omap_i2c_read_reg(omap, OMAP_I2C_IV_REG); |
010d442c KS |
908 | switch (iv) { |
909 | case 0x00: /* None */ | |
910 | break; | |
911 | case 0x01: /* Arbitration lost */ | |
63f8f856 FB |
912 | dev_err(omap->dev, "Arbitration lost\n"); |
913 | omap_i2c_complete_cmd(omap, OMAP_I2C_STAT_AL); | |
010d442c KS |
914 | break; |
915 | case 0x02: /* No acknowledgement */ | |
63f8f856 FB |
916 | omap_i2c_complete_cmd(omap, OMAP_I2C_STAT_NACK); |
917 | omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP); | |
010d442c KS |
918 | break; |
919 | case 0x03: /* Register access ready */ | |
63f8f856 | 920 | omap_i2c_complete_cmd(omap, 0); |
010d442c KS |
921 | break; |
922 | case 0x04: /* Receive data ready */ | |
63f8f856 FB |
923 | if (omap->buf_len) { |
924 | w = omap_i2c_read_reg(omap, OMAP_I2C_DATA_REG); | |
925 | *omap->buf++ = w; | |
926 | omap->buf_len--; | |
927 | if (omap->buf_len) { | |
928 | *omap->buf++ = w >> 8; | |
929 | omap->buf_len--; | |
010d442c KS |
930 | } |
931 | } else | |
63f8f856 | 932 | dev_err(omap->dev, "RRDY IRQ while no data requested\n"); |
010d442c KS |
933 | break; |
934 | case 0x05: /* Transmit data ready */ | |
63f8f856 FB |
935 | if (omap->buf_len) { |
936 | w = *omap->buf++; | |
937 | omap->buf_len--; | |
938 | if (omap->buf_len) { | |
939 | w |= *omap->buf++ << 8; | |
940 | omap->buf_len--; | |
010d442c | 941 | } |
63f8f856 | 942 | omap_i2c_write_reg(omap, OMAP_I2C_DATA_REG, w); |
010d442c | 943 | } else |
63f8f856 | 944 | dev_err(omap->dev, "XRDY IRQ while no data to send\n"); |
010d442c KS |
945 | break; |
946 | default: | |
947 | return IRQ_NONE; | |
948 | } | |
949 | ||
950 | return IRQ_HANDLED; | |
951 | } | |
43469d8e | 952 | #else |
4e80f727 | 953 | #define omap_i2c_omap1_isr NULL |
43469d8e | 954 | #endif |
010d442c | 955 | |
2dd151ab | 956 | /* |
c8db38f0 | 957 | * OMAP3430 Errata i462: When an XRDY/XDR is hit, wait for XUDF before writing |
2dd151ab AS |
958 | * data to DATA_REG. Otherwise some data bytes can be lost while transferring |
959 | * them from the memory to the I2C interface. | |
960 | */ | |
63f8f856 | 961 | static int errata_omap3_i462(struct omap_i2c_dev *omap) |
2dd151ab | 962 | { |
e9f59b9c | 963 | unsigned long timeout = 10000; |
4151e741 | 964 | u16 stat; |
e9f59b9c | 965 | |
4151e741 | 966 | do { |
63f8f856 | 967 | stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG); |
4151e741 FB |
968 | if (stat & OMAP_I2C_STAT_XUDF) |
969 | break; | |
970 | ||
971 | if (stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) { | |
63f8f856 | 972 | omap_i2c_ack_stat(omap, (OMAP_I2C_STAT_XRDY | |
2dd151ab | 973 | OMAP_I2C_STAT_XDR)); |
b07be0f3 | 974 | if (stat & OMAP_I2C_STAT_NACK) { |
63f8f856 FB |
975 | omap->cmd_err |= OMAP_I2C_STAT_NACK; |
976 | omap_i2c_ack_stat(omap, OMAP_I2C_STAT_NACK); | |
b07be0f3 FB |
977 | } |
978 | ||
979 | if (stat & OMAP_I2C_STAT_AL) { | |
63f8f856 FB |
980 | dev_err(omap->dev, "Arbitration lost\n"); |
981 | omap->cmd_err |= OMAP_I2C_STAT_AL; | |
982 | omap_i2c_ack_stat(omap, OMAP_I2C_STAT_AL); | |
b07be0f3 FB |
983 | } |
984 | ||
4151e741 | 985 | return -EIO; |
2dd151ab | 986 | } |
e9f59b9c | 987 | |
2dd151ab | 988 | cpu_relax(); |
4151e741 | 989 | } while (--timeout); |
2dd151ab | 990 | |
e9f59b9c | 991 | if (!timeout) { |
63f8f856 | 992 | dev_err(omap->dev, "timeout waiting on XUDF bit\n"); |
e9f59b9c AS |
993 | return 0; |
994 | } | |
995 | ||
2dd151ab AS |
996 | return 0; |
997 | } | |
998 | ||
63f8f856 | 999 | static void omap_i2c_receive_data(struct omap_i2c_dev *omap, u8 num_bytes, |
3312d25e FB |
1000 | bool is_rdr) |
1001 | { | |
1002 | u16 w; | |
1003 | ||
1004 | while (num_bytes--) { | |
63f8f856 FB |
1005 | w = omap_i2c_read_reg(omap, OMAP_I2C_DATA_REG); |
1006 | *omap->buf++ = w; | |
1007 | omap->buf_len--; | |
3312d25e FB |
1008 | |
1009 | /* | |
1010 | * Data reg in 2430, omap3 and | |
1011 | * omap4 is 8 bit wide | |
1012 | */ | |
63f8f856 FB |
1013 | if (omap->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) { |
1014 | *omap->buf++ = w >> 8; | |
1015 | omap->buf_len--; | |
3312d25e FB |
1016 | } |
1017 | } | |
1018 | } | |
1019 | ||
63f8f856 | 1020 | static int omap_i2c_transmit_data(struct omap_i2c_dev *omap, u8 num_bytes, |
3312d25e FB |
1021 | bool is_xdr) |
1022 | { | |
1023 | u16 w; | |
1024 | ||
1025 | while (num_bytes--) { | |
63f8f856 FB |
1026 | w = *omap->buf++; |
1027 | omap->buf_len--; | |
3312d25e FB |
1028 | |
1029 | /* | |
1030 | * Data reg in 2430, omap3 and | |
1031 | * omap4 is 8 bit wide | |
1032 | */ | |
63f8f856 FB |
1033 | if (omap->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) { |
1034 | w |= *omap->buf++ << 8; | |
1035 | omap->buf_len--; | |
3312d25e FB |
1036 | } |
1037 | ||
63f8f856 | 1038 | if (omap->errata & I2C_OMAP_ERRATA_I462) { |
3312d25e FB |
1039 | int ret; |
1040 | ||
63f8f856 | 1041 | ret = errata_omap3_i462(omap); |
3312d25e FB |
1042 | if (ret < 0) |
1043 | return ret; | |
1044 | } | |
1045 | ||
63f8f856 | 1046 | omap_i2c_write_reg(omap, OMAP_I2C_DATA_REG, w); |
3312d25e FB |
1047 | } |
1048 | ||
1049 | return 0; | |
1050 | } | |
1051 | ||
010d442c | 1052 | static irqreturn_t |
3b2f8f82 | 1053 | omap_i2c_isr(int irq, void *dev_id) |
010d442c | 1054 | { |
63f8f856 | 1055 | struct omap_i2c_dev *omap = dev_id; |
3b2f8f82 FB |
1056 | irqreturn_t ret = IRQ_HANDLED; |
1057 | u16 mask; | |
1058 | u16 stat; | |
1059 | ||
63f8f856 | 1060 | stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG); |
c770657b | 1061 | mask = omap_i2c_read_reg(omap, OMAP_I2C_IE_REG) & ~OMAP_I2C_STAT_NACK; |
3b2f8f82 FB |
1062 | |
1063 | if (stat & mask) | |
1064 | ret = IRQ_WAKE_THREAD; | |
1065 | ||
3b2f8f82 FB |
1066 | return ret; |
1067 | } | |
1068 | ||
89f845a6 | 1069 | static int omap_i2c_xfer_data(struct omap_i2c_dev *omap) |
010d442c | 1070 | { |
010d442c | 1071 | u16 bits; |
3312d25e | 1072 | u16 stat; |
66b92988 | 1073 | int err = 0, count = 0; |
010d442c | 1074 | |
66b92988 | 1075 | do { |
63f8f856 FB |
1076 | bits = omap_i2c_read_reg(omap, OMAP_I2C_IE_REG); |
1077 | stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG); | |
66b92988 FB |
1078 | stat &= bits; |
1079 | ||
079d8af2 | 1080 | /* If we're in receiver mode, ignore XDR/XRDY */ |
63f8f856 | 1081 | if (omap->receiver) |
079d8af2 FB |
1082 | stat &= ~(OMAP_I2C_STAT_XDR | OMAP_I2C_STAT_XRDY); |
1083 | else | |
1084 | stat &= ~(OMAP_I2C_STAT_RDR | OMAP_I2C_STAT_RRDY); | |
010d442c | 1085 | |
66b92988 FB |
1086 | if (!stat) { |
1087 | /* my work here is done */ | |
89f845a6 WS |
1088 | err = -EAGAIN; |
1089 | break; | |
66b92988 | 1090 | } |
f08ac4e7 | 1091 | |
63f8f856 | 1092 | dev_dbg(omap->dev, "IRQ (ISR = 0x%04x)\n", stat); |
010d442c | 1093 | if (count++ == 100) { |
63f8f856 | 1094 | dev_warn(omap->dev, "Too much work in one IRQ\n"); |
010d442c KS |
1095 | break; |
1096 | } | |
1097 | ||
1d7afc95 | 1098 | if (stat & OMAP_I2C_STAT_NACK) { |
b6ee52c3 | 1099 | err |= OMAP_I2C_STAT_NACK; |
63f8f856 | 1100 | omap_i2c_ack_stat(omap, OMAP_I2C_STAT_NACK); |
1d7afc95 | 1101 | } |
78e1cf42 | 1102 | |
b6ee52c3 | 1103 | if (stat & OMAP_I2C_STAT_AL) { |
63f8f856 | 1104 | dev_err(omap->dev, "Arbitration lost\n"); |
b6ee52c3 | 1105 | err |= OMAP_I2C_STAT_AL; |
63f8f856 | 1106 | omap_i2c_ack_stat(omap, OMAP_I2C_STAT_AL); |
b6ee52c3 | 1107 | } |
c55edb99 | 1108 | |
a5a595cc | 1109 | /* |
cb527ede | 1110 | * ProDB0017052: Clear ARDY bit twice |
a5a595cc | 1111 | */ |
4cdbf7d3 | 1112 | if (stat & OMAP_I2C_STAT_ARDY) |
63f8f856 | 1113 | omap_i2c_ack_stat(omap, OMAP_I2C_STAT_ARDY); |
4cdbf7d3 | 1114 | |
b6ee52c3 | 1115 | if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK | |
04c688dd | 1116 | OMAP_I2C_STAT_AL)) { |
63f8f856 | 1117 | omap_i2c_ack_stat(omap, (OMAP_I2C_STAT_RRDY | |
540a4790 FB |
1118 | OMAP_I2C_STAT_RDR | |
1119 | OMAP_I2C_STAT_XRDY | | |
1120 | OMAP_I2C_STAT_XDR | | |
1121 | OMAP_I2C_STAT_ARDY)); | |
0bdfe0cb | 1122 | break; |
04c688dd | 1123 | } |
c55edb99 | 1124 | |
6d9939f6 | 1125 | if (stat & OMAP_I2C_STAT_RDR) { |
b6ee52c3 | 1126 | u8 num_bytes = 1; |
f3083d92 | 1127 | |
63f8f856 FB |
1128 | if (omap->fifo_size) |
1129 | num_bytes = omap->buf_len; | |
6d9939f6 | 1130 | |
63f8f856 FB |
1131 | if (omap->errata & I2C_OMAP_ERRATA_I207) { |
1132 | i2c_omap_errata_i207(omap, stat); | |
1133 | num_bytes = (omap_i2c_read_reg(omap, | |
ccfc8663 AK |
1134 | OMAP_I2C_BUFSTAT_REG) >> 8) & 0x3F; |
1135 | } | |
f3083d92 | 1136 | |
63f8f856 FB |
1137 | omap_i2c_receive_data(omap, num_bytes, true); |
1138 | omap_i2c_ack_stat(omap, OMAP_I2C_STAT_RDR); | |
9eb13cf3 | 1139 | continue; |
6d9939f6 FB |
1140 | } |
1141 | ||
1142 | if (stat & OMAP_I2C_STAT_RRDY) { | |
1143 | u8 num_bytes = 1; | |
1144 | ||
63f8f856 FB |
1145 | if (omap->threshold) |
1146 | num_bytes = omap->threshold; | |
6d9939f6 | 1147 | |
63f8f856 FB |
1148 | omap_i2c_receive_data(omap, num_bytes, false); |
1149 | omap_i2c_ack_stat(omap, OMAP_I2C_STAT_RRDY); | |
010d442c KS |
1150 | continue; |
1151 | } | |
c55edb99 | 1152 | |
6d9939f6 | 1153 | if (stat & OMAP_I2C_STAT_XDR) { |
b6ee52c3 | 1154 | u8 num_bytes = 1; |
3312d25e | 1155 | int ret; |
6d9939f6 | 1156 | |
63f8f856 FB |
1157 | if (omap->fifo_size) |
1158 | num_bytes = omap->buf_len; | |
6d9939f6 | 1159 | |
63f8f856 | 1160 | ret = omap_i2c_transmit_data(omap, num_bytes, true); |
3312d25e | 1161 | if (ret < 0) |
0bdfe0cb | 1162 | break; |
6d9939f6 | 1163 | |
63f8f856 | 1164 | omap_i2c_ack_stat(omap, OMAP_I2C_STAT_XDR); |
9eb13cf3 | 1165 | continue; |
6d9939f6 FB |
1166 | } |
1167 | ||
1168 | if (stat & OMAP_I2C_STAT_XRDY) { | |
1169 | u8 num_bytes = 1; | |
3312d25e | 1170 | int ret; |
6d9939f6 | 1171 | |
63f8f856 FB |
1172 | if (omap->threshold) |
1173 | num_bytes = omap->threshold; | |
6d9939f6 | 1174 | |
63f8f856 | 1175 | ret = omap_i2c_transmit_data(omap, num_bytes, false); |
3312d25e | 1176 | if (ret < 0) |
0bdfe0cb | 1177 | break; |
6d9939f6 | 1178 | |
63f8f856 | 1179 | omap_i2c_ack_stat(omap, OMAP_I2C_STAT_XRDY); |
010d442c KS |
1180 | continue; |
1181 | } | |
c55edb99 | 1182 | |
010d442c | 1183 | if (stat & OMAP_I2C_STAT_ROVR) { |
63f8f856 | 1184 | dev_err(omap->dev, "Receive overrun\n"); |
1d7afc95 | 1185 | err |= OMAP_I2C_STAT_ROVR; |
63f8f856 | 1186 | omap_i2c_ack_stat(omap, OMAP_I2C_STAT_ROVR); |
0bdfe0cb | 1187 | break; |
010d442c | 1188 | } |
c55edb99 | 1189 | |
010d442c | 1190 | if (stat & OMAP_I2C_STAT_XUDF) { |
63f8f856 | 1191 | dev_err(omap->dev, "Transmit underflow\n"); |
1d7afc95 | 1192 | err |= OMAP_I2C_STAT_XUDF; |
63f8f856 | 1193 | omap_i2c_ack_stat(omap, OMAP_I2C_STAT_XUDF); |
0bdfe0cb | 1194 | break; |
010d442c | 1195 | } |
66b92988 | 1196 | } while (stat); |
010d442c | 1197 | |
89f845a6 WS |
1198 | return err; |
1199 | } | |
1200 | ||
1201 | static irqreturn_t | |
1202 | omap_i2c_isr_thread(int this_irq, void *dev_id) | |
1203 | { | |
1204 | int ret; | |
1205 | struct omap_i2c_dev *omap = dev_id; | |
1206 | ||
1207 | ret = omap_i2c_xfer_data(omap); | |
1208 | if (ret != -EAGAIN) | |
1209 | omap_i2c_complete_cmd(omap, ret); | |
0bdfe0cb | 1210 | |
6a85ced2 | 1211 | return IRQ_HANDLED; |
010d442c KS |
1212 | } |
1213 | ||
8f9082c5 | 1214 | static const struct i2c_algorithm omap_i2c_algo = { |
89f845a6 WS |
1215 | .master_xfer = omap_i2c_xfer_irq, |
1216 | .master_xfer_atomic = omap_i2c_xfer_polling, | |
010d442c KS |
1217 | .functionality = omap_i2c_func, |
1218 | }; | |
1219 | ||
f37b2bb6 WS |
1220 | static const struct i2c_adapter_quirks omap_i2c_quirks = { |
1221 | .flags = I2C_AQ_NO_ZERO_LEN, | |
1222 | }; | |
1223 | ||
6145197b | 1224 | #ifdef CONFIG_OF |
4c624840 TL |
1225 | static struct omap_i2c_bus_platform_data omap2420_pdata = { |
1226 | .rev = OMAP_I2C_IP_VERSION_1, | |
1227 | .flags = OMAP_I2C_FLAG_NO_FIFO | | |
1228 | OMAP_I2C_FLAG_SIMPLE_CLOCK | | |
1229 | OMAP_I2C_FLAG_16BIT_DATA_REG | | |
1230 | OMAP_I2C_FLAG_BUS_SHIFT_2, | |
1231 | }; | |
1232 | ||
1233 | static struct omap_i2c_bus_platform_data omap2430_pdata = { | |
1234 | .rev = OMAP_I2C_IP_VERSION_1, | |
1235 | .flags = OMAP_I2C_FLAG_BUS_SHIFT_2 | | |
1236 | OMAP_I2C_FLAG_FORCE_19200_INT_CLK, | |
1237 | }; | |
1238 | ||
6145197b BC |
1239 | static struct omap_i2c_bus_platform_data omap3_pdata = { |
1240 | .rev = OMAP_I2C_IP_VERSION_1, | |
972deb4f | 1241 | .flags = OMAP_I2C_FLAG_BUS_SHIFT_2, |
6145197b BC |
1242 | }; |
1243 | ||
1244 | static struct omap_i2c_bus_platform_data omap4_pdata = { | |
1245 | .rev = OMAP_I2C_IP_VERSION_2, | |
1246 | }; | |
1247 | ||
1248 | static const struct of_device_id omap_i2c_of_match[] = { | |
1249 | { | |
1250 | .compatible = "ti,omap4-i2c", | |
1251 | .data = &omap4_pdata, | |
1252 | }, | |
1253 | { | |
1254 | .compatible = "ti,omap3-i2c", | |
1255 | .data = &omap3_pdata, | |
1256 | }, | |
4c624840 TL |
1257 | { |
1258 | .compatible = "ti,omap2430-i2c", | |
1259 | .data = &omap2430_pdata, | |
1260 | }, | |
1261 | { | |
1262 | .compatible = "ti,omap2420-i2c", | |
1263 | .data = &omap2420_pdata, | |
1264 | }, | |
6145197b BC |
1265 | { }, |
1266 | }; | |
1267 | MODULE_DEVICE_TABLE(of, omap_i2c_of_match); | |
1268 | #endif | |
1269 | ||
47dcd016 S |
1270 | #define OMAP_I2C_SCHEME(rev) ((rev & 0xc000) >> 14) |
1271 | ||
1272 | #define OMAP_I2C_REV_SCHEME_0_MAJOR(rev) (rev >> 4) | |
1273 | #define OMAP_I2C_REV_SCHEME_0_MINOR(rev) (rev & 0xf) | |
1274 | ||
1275 | #define OMAP_I2C_REV_SCHEME_1_MAJOR(rev) ((rev & 0x0700) >> 7) | |
1276 | #define OMAP_I2C_REV_SCHEME_1_MINOR(rev) (rev & 0x1f) | |
1277 | #define OMAP_I2C_SCHEME_0 0 | |
1278 | #define OMAP_I2C_SCHEME_1 1 | |
1279 | ||
9dcb0e7b FB |
1280 | static int omap_i2c_get_scl(struct i2c_adapter *adap) |
1281 | { | |
1282 | struct omap_i2c_dev *dev = i2c_get_adapdata(adap); | |
1283 | u32 reg; | |
1284 | ||
1285 | reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG); | |
1286 | ||
1287 | return reg & OMAP_I2C_SYSTEST_SCL_I_FUNC; | |
1288 | } | |
1289 | ||
1290 | static int omap_i2c_get_sda(struct i2c_adapter *adap) | |
1291 | { | |
1292 | struct omap_i2c_dev *dev = i2c_get_adapdata(adap); | |
1293 | u32 reg; | |
1294 | ||
1295 | reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG); | |
1296 | ||
1297 | return reg & OMAP_I2C_SYSTEST_SDA_I_FUNC; | |
1298 | } | |
1299 | ||
1300 | static void omap_i2c_set_scl(struct i2c_adapter *adap, int val) | |
1301 | { | |
1302 | struct omap_i2c_dev *dev = i2c_get_adapdata(adap); | |
1303 | u32 reg; | |
1304 | ||
1305 | reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG); | |
1306 | if (val) | |
1307 | reg |= OMAP_I2C_SYSTEST_SCL_O; | |
1308 | else | |
1309 | reg &= ~OMAP_I2C_SYSTEST_SCL_O; | |
1310 | omap_i2c_write_reg(dev, OMAP_I2C_SYSTEST_REG, reg); | |
1311 | } | |
1312 | ||
1313 | static void omap_i2c_prepare_recovery(struct i2c_adapter *adap) | |
1314 | { | |
1315 | struct omap_i2c_dev *dev = i2c_get_adapdata(adap); | |
1316 | u32 reg; | |
1317 | ||
1318 | reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG); | |
828e66c0 | 1319 | /* enable test mode */ |
9dcb0e7b | 1320 | reg |= OMAP_I2C_SYSTEST_ST_EN; |
828e66c0 JL |
1321 | /* select SDA/SCL IO mode */ |
1322 | reg |= 3 << OMAP_I2C_SYSTEST_TMODE_SHIFT; | |
1323 | /* set SCL to high-impedance state (reset value is 0) */ | |
1324 | reg |= OMAP_I2C_SYSTEST_SCL_O; | |
1325 | /* set SDA to high-impedance state (reset value is 0) */ | |
1326 | reg |= OMAP_I2C_SYSTEST_SDA_O; | |
9dcb0e7b FB |
1327 | omap_i2c_write_reg(dev, OMAP_I2C_SYSTEST_REG, reg); |
1328 | } | |
1329 | ||
1330 | static void omap_i2c_unprepare_recovery(struct i2c_adapter *adap) | |
1331 | { | |
1332 | struct omap_i2c_dev *dev = i2c_get_adapdata(adap); | |
1333 | u32 reg; | |
1334 | ||
1335 | reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG); | |
828e66c0 | 1336 | /* restore reset values */ |
9dcb0e7b | 1337 | reg &= ~OMAP_I2C_SYSTEST_ST_EN; |
828e66c0 JL |
1338 | reg &= ~OMAP_I2C_SYSTEST_TMODE_MASK; |
1339 | reg &= ~OMAP_I2C_SYSTEST_SCL_O; | |
1340 | reg &= ~OMAP_I2C_SYSTEST_SDA_O; | |
9dcb0e7b FB |
1341 | omap_i2c_write_reg(dev, OMAP_I2C_SYSTEST_REG, reg); |
1342 | } | |
1343 | ||
1344 | static struct i2c_bus_recovery_info omap_i2c_bus_recovery_info = { | |
1345 | .get_scl = omap_i2c_get_scl, | |
1346 | .get_sda = omap_i2c_get_sda, | |
1347 | .set_scl = omap_i2c_set_scl, | |
1348 | .prepare_recovery = omap_i2c_prepare_recovery, | |
1349 | .unprepare_recovery = omap_i2c_unprepare_recovery, | |
1350 | .recover_bus = i2c_generic_scl_recovery, | |
1351 | }; | |
1352 | ||
0b255e92 | 1353 | static int |
010d442c KS |
1354 | omap_i2c_probe(struct platform_device *pdev) |
1355 | { | |
63f8f856 | 1356 | struct omap_i2c_dev *omap; |
010d442c | 1357 | struct i2c_adapter *adap; |
c4dba011 | 1358 | const struct omap_i2c_bus_platform_data *pdata = |
6d4028c6 | 1359 | dev_get_platdata(&pdev->dev); |
6145197b | 1360 | struct device_node *node = pdev->dev.of_node; |
ac79e4b2 | 1361 | int irq; |
010d442c | 1362 | int r; |
47dcd016 | 1363 | u32 rev; |
4368de19 | 1364 | u16 minor, major; |
010d442c | 1365 | |
ac79e4b2 | 1366 | irq = platform_get_irq(pdev, 0); |
e42688ed | 1367 | if (irq < 0) |
ac79e4b2 | 1368 | return irq; |
010d442c | 1369 | |
63f8f856 FB |
1370 | omap = devm_kzalloc(&pdev->dev, sizeof(struct omap_i2c_dev), GFP_KERNEL); |
1371 | if (!omap) | |
d9ebd04d | 1372 | return -ENOMEM; |
010d442c | 1373 | |
f16c1408 | 1374 | omap->base = devm_platform_ioremap_resource(pdev, 0); |
63f8f856 FB |
1375 | if (IS_ERR(omap->base)) |
1376 | return PTR_ERR(omap->base); | |
010d442c | 1377 | |
8cafbf26 | 1378 | if (pdev->dev.of_node) { |
90224e64 | 1379 | u32 freq = I2C_MAX_STANDARD_MODE_FREQ; |
6145197b | 1380 | |
8cafbf26 | 1381 | pdata = device_get_match_data(&pdev->dev); |
63f8f856 | 1382 | omap->flags = pdata->flags; |
6145197b BC |
1383 | |
1384 | of_property_read_u32(node, "clock-frequency", &freq); | |
1385 | /* convert DT freq value in Hz into kHz for speed */ | |
63f8f856 | 1386 | omap->speed = freq / 1000; |
6145197b | 1387 | } else if (pdata != NULL) { |
63f8f856 FB |
1388 | omap->speed = pdata->clkrate; |
1389 | omap->flags = pdata->flags; | |
1390 | omap->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat; | |
20c9d2c4 | 1391 | } |
4574eb68 | 1392 | |
63f8f856 FB |
1393 | omap->dev = &pdev->dev; |
1394 | omap->irq = irq; | |
55c381e4 | 1395 | |
63f8f856 FB |
1396 | platform_set_drvdata(pdev, omap); |
1397 | init_completion(&omap->cmd_complete); | |
010d442c | 1398 | |
63f8f856 | 1399 | omap->reg_shift = (omap->flags >> OMAP_I2C_FLAG_BUS_SHIFT__SHIFT) & 3; |
7c6bd201 | 1400 | |
63f8f856 FB |
1401 | pm_runtime_enable(omap->dev); |
1402 | pm_runtime_set_autosuspend_delay(omap->dev, OMAP_I2C_PM_TIMEOUT); | |
1403 | pm_runtime_use_autosuspend(omap->dev); | |
6d8451d5 | 1404 | |
780f6297 | 1405 | r = pm_runtime_resume_and_get(omap->dev); |
77441ac0 | 1406 | if (r < 0) |
780f6297 | 1407 | goto err_disable_pm; |
010d442c | 1408 | |
47dcd016 S |
1409 | /* |
1410 | * Read the Rev hi bit-[15:14] ie scheme this is 1 indicates ver2. | |
1411 | * On omap1/3/2 Offset 4 is IE Reg the bit [15:14] is 0 at reset. | |
1412 | * Also since the omap_i2c_read_reg uses reg_map_ip_* a | |
40b13ca8 | 1413 | * readw_relaxed is done. |
47dcd016 | 1414 | */ |
63f8f856 | 1415 | rev = readw_relaxed(omap->base + 0x04); |
47dcd016 | 1416 | |
63f8f856 FB |
1417 | omap->scheme = OMAP_I2C_SCHEME(rev); |
1418 | switch (omap->scheme) { | |
47dcd016 | 1419 | case OMAP_I2C_SCHEME_0: |
63f8f856 FB |
1420 | omap->regs = (u8 *)reg_map_ip_v1; |
1421 | omap->rev = omap_i2c_read_reg(omap, OMAP_I2C_REV_REG); | |
1422 | minor = OMAP_I2C_REV_SCHEME_0_MAJOR(omap->rev); | |
1423 | major = OMAP_I2C_REV_SCHEME_0_MAJOR(omap->rev); | |
47dcd016 S |
1424 | break; |
1425 | case OMAP_I2C_SCHEME_1: | |
47dcd016 | 1426 | default: |
63f8f856 | 1427 | omap->regs = (u8 *)reg_map_ip_v2; |
47dcd016 | 1428 | rev = (rev << 16) | |
63f8f856 | 1429 | omap_i2c_read_reg(omap, OMAP_I2C_IP_V2_REVNB_LO); |
47dcd016 S |
1430 | minor = OMAP_I2C_REV_SCHEME_1_MINOR(rev); |
1431 | major = OMAP_I2C_REV_SCHEME_1_MAJOR(rev); | |
63f8f856 | 1432 | omap->rev = rev; |
47dcd016 | 1433 | } |
010d442c | 1434 | |
63f8f856 | 1435 | omap->errata = 0; |
9aa8ec67 | 1436 | |
63f8f856 FB |
1437 | if (omap->rev >= OMAP_I2C_REV_ON_2430 && |
1438 | omap->rev < OMAP_I2C_REV_ON_4430_PLUS) | |
1439 | omap->errata |= I2C_OMAP_ERRATA_I207; | |
9aa8ec67 | 1440 | |
63f8f856 FB |
1441 | if (omap->rev <= OMAP_I2C_REV_ON_3430_3530) |
1442 | omap->errata |= I2C_OMAP_ERRATA_I462; | |
8a9d97d3 | 1443 | |
63f8f856 | 1444 | if (!(omap->flags & OMAP_I2C_FLAG_NO_FIFO)) { |
b6ee52c3 NM |
1445 | u16 s; |
1446 | ||
1447 | /* Set up the fifo size - Get total size */ | |
63f8f856 FB |
1448 | s = (omap_i2c_read_reg(omap, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3; |
1449 | omap->fifo_size = 0x8 << s; | |
b6ee52c3 NM |
1450 | |
1451 | /* | |
1452 | * Set up notification threshold as half the total available | |
1453 | * size. This is to ensure that we can handle the status on int | |
1454 | * call back latencies. | |
1455 | */ | |
1d5a34fe | 1456 | |
63f8f856 | 1457 | omap->fifo_size = (omap->fifo_size / 2); |
1d5a34fe | 1458 | |
63f8f856 FB |
1459 | if (omap->rev < OMAP_I2C_REV_ON_3630) |
1460 | omap->b_hw = 1; /* Enable hardware fixes */ | |
1d5a34fe | 1461 | |
20c9d2c4 | 1462 | /* calculate wakeup latency constraint for MPU */ |
63f8f856 FB |
1463 | if (omap->set_mpu_wkup_lat != NULL) |
1464 | omap->latency = (1000000 * omap->fifo_size) / | |
1465 | (1000 * omap->speed / 8); | |
b6ee52c3 NM |
1466 | } |
1467 | ||
010d442c | 1468 | /* reset ASAP, clearing any IRQs */ |
63f8f856 | 1469 | omap_i2c_init(omap); |
010d442c | 1470 | |
63f8f856 FB |
1471 | if (omap->rev < OMAP_I2C_OMAP1_REV_2) |
1472 | r = devm_request_irq(&pdev->dev, omap->irq, omap_i2c_omap1_isr, | |
1473 | IRQF_NO_SUSPEND, pdev->name, omap); | |
3b2f8f82 | 1474 | else |
63f8f856 | 1475 | r = devm_request_threaded_irq(&pdev->dev, omap->irq, |
3b2f8f82 FB |
1476 | omap_i2c_isr, omap_i2c_isr_thread, |
1477 | IRQF_NO_SUSPEND | IRQF_ONESHOT, | |
63f8f856 | 1478 | pdev->name, omap); |
010d442c KS |
1479 | |
1480 | if (r) { | |
63f8f856 | 1481 | dev_err(omap->dev, "failure requesting irq %i\n", omap->irq); |
010d442c KS |
1482 | goto err_unuse_clocks; |
1483 | } | |
9c76b878 | 1484 | |
63f8f856 FB |
1485 | adap = &omap->adapter; |
1486 | i2c_set_adapdata(adap, omap); | |
010d442c | 1487 | adap->owner = THIS_MODULE; |
cfac71d9 | 1488 | adap->class = I2C_CLASS_DEPRECATED; |
ea1558ce | 1489 | strscpy(adap->name, "OMAP I2C adapter", sizeof(adap->name)); |
010d442c | 1490 | adap->algo = &omap_i2c_algo; |
f37b2bb6 | 1491 | adap->quirks = &omap_i2c_quirks; |
010d442c | 1492 | adap->dev.parent = &pdev->dev; |
6145197b | 1493 | adap->dev.of_node = pdev->dev.of_node; |
9dcb0e7b | 1494 | adap->bus_recovery_info = &omap_i2c_bus_recovery_info; |
010d442c KS |
1495 | |
1496 | /* i2c device drivers may be active on return from add_adapter() */ | |
7c175499 DB |
1497 | adap->nr = pdev->id; |
1498 | r = i2c_add_numbered_adapter(adap); | |
ea734404 | 1499 | if (r) |
d9ebd04d | 1500 | goto err_unuse_clocks; |
010d442c | 1501 | |
63f8f856 FB |
1502 | dev_info(omap->dev, "bus %d rev%d.%d at %d kHz\n", adap->nr, |
1503 | major, minor, omap->speed); | |
c5d3cd6d | 1504 | |
63f8f856 FB |
1505 | pm_runtime_mark_last_busy(omap->dev); |
1506 | pm_runtime_put_autosuspend(omap->dev); | |
62ff2c2b | 1507 | |
010d442c KS |
1508 | return 0; |
1509 | ||
010d442c | 1510 | err_unuse_clocks: |
63f8f856 | 1511 | omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, 0); |
e6244dee TL |
1512 | pm_runtime_dont_use_autosuspend(omap->dev); |
1513 | pm_runtime_put_sync(omap->dev); | |
780f6297 | 1514 | err_disable_pm: |
24740516 | 1515 | pm_runtime_disable(&pdev->dev); |
010d442c KS |
1516 | |
1517 | return r; | |
1518 | } | |
1519 | ||
e190a0c3 | 1520 | static void omap_i2c_remove(struct platform_device *pdev) |
010d442c | 1521 | { |
63f8f856 | 1522 | struct omap_i2c_dev *omap = platform_get_drvdata(pdev); |
3b0fb97c | 1523 | int ret; |
010d442c | 1524 | |
63f8f856 | 1525 | i2c_del_adapter(&omap->adapter); |
9496fffc UKK |
1526 | |
1527 | ret = pm_runtime_get_sync(&pdev->dev); | |
ff370257 | 1528 | if (ret < 0) |
9496fffc UKK |
1529 | dev_err(omap->dev, "Failed to resume hardware, skip disable\n"); |
1530 | else | |
1531 | omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, 0); | |
3b0fb97c | 1532 | |
e6244dee | 1533 | pm_runtime_dont_use_autosuspend(&pdev->dev); |
1c4828f9 | 1534 | pm_runtime_put_sync(&pdev->dev); |
24740516 | 1535 | pm_runtime_disable(&pdev->dev); |
010d442c KS |
1536 | } |
1537 | ||
c6e2bd95 | 1538 | static int __maybe_unused omap_i2c_runtime_suspend(struct device *dev) |
fab67afb | 1539 | { |
63f8f856 | 1540 | struct omap_i2c_dev *omap = dev_get_drvdata(dev); |
3dae3efb | 1541 | |
63f8f856 | 1542 | omap->iestate = omap_i2c_read_reg(omap, OMAP_I2C_IE_REG); |
bd16c82f | 1543 | |
63f8f856 FB |
1544 | if (omap->scheme == OMAP_I2C_SCHEME_0) |
1545 | omap_i2c_write_reg(omap, OMAP_I2C_IE_REG, 0); | |
4368de19 | 1546 | else |
63f8f856 | 1547 | omap_i2c_write_reg(omap, OMAP_I2C_IP_V2_IRQENABLE_CLR, |
4368de19 | 1548 | OMAP_I2C_IP_V2_INTERRUPTS_MASK); |
fab67afb | 1549 | |
63f8f856 FB |
1550 | if (omap->rev < OMAP_I2C_OMAP1_REV_2) { |
1551 | omap_i2c_read_reg(omap, OMAP_I2C_IV_REG); /* Read clears */ | |
3dae3efb | 1552 | } else { |
63f8f856 | 1553 | omap_i2c_write_reg(omap, OMAP_I2C_STAT_REG, omap->iestate); |
fab67afb | 1554 | |
3dae3efb | 1555 | /* Flush posted write */ |
63f8f856 | 1556 | omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG); |
3dae3efb | 1557 | } |
fab67afb | 1558 | |
096ea30c PH |
1559 | pinctrl_pm_select_sleep_state(dev); |
1560 | ||
fab67afb KH |
1561 | return 0; |
1562 | } | |
1563 | ||
c6e2bd95 | 1564 | static int __maybe_unused omap_i2c_runtime_resume(struct device *dev) |
fab67afb | 1565 | { |
63f8f856 | 1566 | struct omap_i2c_dev *omap = dev_get_drvdata(dev); |
096ea30c PH |
1567 | |
1568 | pinctrl_pm_select_default_state(dev); | |
fab67afb | 1569 | |
63f8f856 | 1570 | if (!omap->regs) |
47dcd016 S |
1571 | return 0; |
1572 | ||
63f8f856 | 1573 | __omap_i2c_init(omap); |
fab67afb KH |
1574 | |
1575 | return 0; | |
1576 | } | |
1577 | ||
50b918c5 | 1578 | static const struct dev_pm_ops omap_i2c_pm_ops = { |
c6e2bd95 TL |
1579 | SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, |
1580 | pm_runtime_force_resume) | |
5692d2a2 S |
1581 | SET_RUNTIME_PM_OPS(omap_i2c_runtime_suspend, |
1582 | omap_i2c_runtime_resume, NULL) | |
fab67afb | 1583 | }; |
fab67afb | 1584 | |
010d442c KS |
1585 | static struct platform_driver omap_i2c_driver = { |
1586 | .probe = omap_i2c_probe, | |
e190a0c3 | 1587 | .remove_new = omap_i2c_remove, |
010d442c | 1588 | .driver = { |
f7bb0d9a | 1589 | .name = "omap_i2c", |
c6e2bd95 | 1590 | .pm = &omap_i2c_pm_ops, |
6145197b | 1591 | .of_match_table = of_match_ptr(omap_i2c_of_match), |
010d442c KS |
1592 | }, |
1593 | }; | |
1594 | ||
1595 | /* I2C may be needed to bring up other drivers */ | |
1596 | static int __init | |
1597 | omap_i2c_init_driver(void) | |
1598 | { | |
1599 | return platform_driver_register(&omap_i2c_driver); | |
1600 | } | |
1601 | subsys_initcall(omap_i2c_init_driver); | |
1602 | ||
1603 | static void __exit omap_i2c_exit_driver(void) | |
1604 | { | |
1605 | platform_driver_unregister(&omap_i2c_driver); | |
1606 | } | |
1607 | module_exit(omap_i2c_exit_driver); | |
1608 | ||
1609 | MODULE_AUTHOR("MontaVista Software, Inc. (and others)"); | |
1610 | MODULE_DESCRIPTION("TI OMAP I2C bus adapter"); | |
1611 | MODULE_LICENSE("GPL"); | |
f7bb0d9a | 1612 | MODULE_ALIAS("platform:omap_i2c"); |