[linux-block.git] / drivers / i2c / busses / i2c-octeon-core.h

/* SPDX-License-Identifier: GPL-2.0 */
#include <linux/atomic.h>
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/i2c.h>
#include <linux/i2c-smbus.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/pci.h>

/* Controller command patterns */
#define SW_TWSI_V		BIT_ULL(63)	/* Valid bit */
#define SW_TWSI_EIA		BIT_ULL(61)	/* Extended internal address */
#define SW_TWSI_R		BIT_ULL(56)	/* Result or read bit */
#define SW_TWSI_SOVR		BIT_ULL(55)	/* Size override */
#define SW_TWSI_SIZE_SHIFT	52
#define SW_TWSI_ADDR_SHIFT	40
#define SW_TWSI_IA_SHIFT	32		/* Internal address */

/* Controller opcode word (bits 60:57) */
#define SW_TWSI_OP_SHIFT	57
#define SW_TWSI_OP_7		(0ULL << SW_TWSI_OP_SHIFT)
#define SW_TWSI_OP_7_IA		(1ULL << SW_TWSI_OP_SHIFT)
#define SW_TWSI_OP_10		(2ULL << SW_TWSI_OP_SHIFT)
#define SW_TWSI_OP_10_IA	(3ULL << SW_TWSI_OP_SHIFT)
#define SW_TWSI_OP_TWSI_CLK	(4ULL << SW_TWSI_OP_SHIFT)
#define SW_TWSI_OP_EOP		(6ULL << SW_TWSI_OP_SHIFT) /* Extended opcode */

/* Controller extended opcode word (bits 34:32) */
#define SW_TWSI_EOP_SHIFT	32
#define SW_TWSI_EOP_TWSI_DATA	(SW_TWSI_OP_EOP | 1ULL << SW_TWSI_EOP_SHIFT)
#define SW_TWSI_EOP_TWSI_CTL	(SW_TWSI_OP_EOP | 2ULL << SW_TWSI_EOP_SHIFT)
#define SW_TWSI_EOP_TWSI_CLKCTL	(SW_TWSI_OP_EOP | 3ULL << SW_TWSI_EOP_SHIFT)
#define SW_TWSI_EOP_TWSI_STAT	(SW_TWSI_OP_EOP | 3ULL << SW_TWSI_EOP_SHIFT)
#define SW_TWSI_EOP_TWSI_RST	(SW_TWSI_OP_EOP | 7ULL << SW_TWSI_EOP_SHIFT)

/* Controller command and status bits */
#define TWSI_CTL_CE		0x80	/* High level controller enable */
#define TWSI_CTL_ENAB		0x40	/* Bus enable */
#define TWSI_CTL_STA		0x20	/* Master-mode start, HW clears when done */
#define TWSI_CTL_STP		0x10	/* Master-mode stop, HW clears when done */
#define TWSI_CTL_IFLG		0x08	/* HW event, SW writes 0 to ACK */
#define TWSI_CTL_AAK		0x04	/* Assert ACK */

/* Status values */
#define STAT_BUS_ERROR		0x00
#define STAT_START		0x08
#define STAT_REP_START		0x10
#define STAT_TXADDR_ACK		0x18
#define STAT_TXADDR_NAK		0x20
#define STAT_TXDATA_ACK		0x28
#define STAT_TXDATA_NAK		0x30
#define STAT_LOST_ARB_38	0x38
#define STAT_RXADDR_ACK		0x40
#define STAT_RXADDR_NAK		0x48
#define STAT_RXDATA_ACK		0x50
#define STAT_RXDATA_NAK		0x58
#define STAT_SLAVE_60		0x60
#define STAT_LOST_ARB_68	0x68
#define STAT_SLAVE_70		0x70
#define STAT_LOST_ARB_78	0x78
#define STAT_SLAVE_80		0x80
#define STAT_SLAVE_88		0x88
#define STAT_GENDATA_ACK	0x90
#define STAT_GENDATA_NAK	0x98
#define STAT_SLAVE_A0		0xA0
#define STAT_SLAVE_A8		0xA8
#define STAT_LOST_ARB_B0	0xB0
#define STAT_SLAVE_LOST		0xB8
#define STAT_SLAVE_NAK		0xC0
#define STAT_SLAVE_ACK		0xC8
#define STAT_AD2W_ACK		0xD0
#define STAT_AD2W_NAK		0xD8
#define STAT_WDOG_TOUT		0xF0
#define STAT_IDLE		0xF8

/* TWSI_INT values */
#define TWSI_INT_ST_INT		BIT_ULL(0)
#define TWSI_INT_TS_INT		BIT_ULL(1)
#define TWSI_INT_CORE_INT	BIT_ULL(2)
#define TWSI_INT_ST_EN		BIT_ULL(4)
#define TWSI_INT_TS_EN		BIT_ULL(5)
#define TWSI_INT_CORE_EN	BIT_ULL(6)
#define TWSI_INT_SDA_OVR	BIT_ULL(8)
#define TWSI_INT_SCL_OVR	BIT_ULL(9)
#define TWSI_INT_SDA		BIT_ULL(10)
#define TWSI_INT_SCL		BIT_ULL(11)

#define I2C_OCTEON_EVENT_WAIT 80 /* microseconds */

/* Register offsets */
struct octeon_i2c_reg_offset {
	unsigned int sw_twsi;
	unsigned int twsi_int;
	unsigned int sw_twsi_ext;
	unsigned int mode;
};

#define OCTEON_REG_SW_TWSI(x)		((x)->roff.sw_twsi)
#define OCTEON_REG_TWSI_INT(x)		((x)->roff.twsi_int)
#define OCTEON_REG_SW_TWSI_EXT(x)	((x)->roff.sw_twsi_ext)
#define OCTEON_REG_MODE(x)		((x)->roff.mode)

/* Set REFCLK_SRC and HS_MODE in TWSX_MODE register */
#define TWSX_MODE_REFCLK_SRC	BIT(4)
#define TWSX_MODE_HS_MODE	BIT(0)
#define TWSX_MODE_HS_MASK	(TWSX_MODE_REFCLK_SRC | TWSX_MODE_HS_MODE)

/* Set BUS_MON_RST to reset bus monitor */
#define BUS_MON_RST_MASK	BIT(3)

struct octeon_i2c {
	wait_queue_head_t queue;
	struct i2c_adapter adap;
	struct octeon_i2c_reg_offset roff;
	struct clk *clk;
	int irq;
	int hlc_irq;		/* For cn7890 only */
	u32 twsi_freq;
	int sys_freq;
	void __iomem *twsi_base;
	struct device *dev;
	bool hlc_enabled;
	bool broken_irq_mode;
	bool broken_irq_check;
	void (*int_enable)(struct octeon_i2c *);
	void (*int_disable)(struct octeon_i2c *);
	void (*hlc_int_enable)(struct octeon_i2c *);
	void (*hlc_int_disable)(struct octeon_i2c *);
	atomic_t int_enable_cnt;
	atomic_t hlc_int_enable_cnt;
	struct i2c_smbus_alert_setup alert_data;
	struct i2c_client *ara;
};

static inline void octeon_i2c_writeq_flush(u64 val, void __iomem *addr)
{
	__raw_writeq(val, addr);
	__raw_readq(addr);	/* wait for write to land */
}

/**
 * octeon_i2c_reg_write - write an I2C core register
 * @i2c: The struct octeon_i2c
 * @eop_reg: Register selector
 * @data: Value to be written
 *
 * The I2C core registers are accessed indirectly via the OCTEON_REG_SW_TWSI CSR.
 */
static inline void octeon_i2c_reg_write(struct octeon_i2c *i2c, u64 eop_reg, u8 data)
{
	int tries = 1000;
	u64 tmp;

	__raw_writeq(SW_TWSI_V | eop_reg | data, i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));
	do {
		tmp = __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));
		if (--tries < 0)
			return;
	} while ((tmp & SW_TWSI_V) != 0);
}

#define octeon_i2c_ctl_write(i2c, val)					\
	octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CTL, val)
#define octeon_i2c_data_write(i2c, val)					\
	octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_DATA, val)

/**
 * octeon_i2c_reg_read - read lower bits of an I2C core register
 * @i2c: The struct octeon_i2c
 * @eop_reg: Register selector
 *
 * Returns the data.
 *
 * The I2C core registers are accessed indirectly via the SW_TWSI CSR.
 */
static inline int octeon_i2c_reg_read(struct octeon_i2c *i2c, u64 eop_reg,
				      int *error)
{
	int tries = 1000;
	u64 tmp;

	__raw_writeq(SW_TWSI_V | eop_reg | SW_TWSI_R, i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));
	do {
		tmp = __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));
		if (--tries < 0) {
			/* signal that the returned data is invalid */
			if (error)
				*error = -EIO;
			return 0;
		}
	} while ((tmp & SW_TWSI_V) != 0);

	return tmp & 0xFF;
}

#define octeon_i2c_ctl_read(i2c)					\
	octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_CTL, NULL)
#define octeon_i2c_data_read(i2c, error)				\
	octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_DATA, error)
#define octeon_i2c_stat_read(i2c)					\
	octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_STAT, NULL)

/**
 * octeon_i2c_read_int - read the OCTEON_REG_TWSI_INT register
 * @i2c: The struct octeon_i2c
 *
 * Returns the value of the register.
 */
static inline u64 octeon_i2c_read_int(struct octeon_i2c *i2c)
{
	return __raw_readq(i2c->twsi_base + OCTEON_REG_TWSI_INT(i2c));
}

/**
 * octeon_i2c_write_int - write the OCTEON_REG_TWSI_INT register
 * @i2c: The struct octeon_i2c
 * @data: Value to be written
 */
static inline void octeon_i2c_write_int(struct octeon_i2c *i2c, u64 data)
{
	octeon_i2c_writeq_flush(data, i2c->twsi_base + OCTEON_REG_TWSI_INT(i2c));
}

#define IS_LS_FREQ(twsi_freq)	((twsi_freq) <= 400000)
#define PCI_SUBSYS_DEVID_9XXX	0xB
#define PCI_SUBSYS_MASK		GENMASK(15, 12)
/**
 * octeon_i2c_is_otx2 - check for chip ID
 * @pdev: PCI dev structure
 *
 * Returns true if the device is an OcteonTX2, false otherwise.
 */
static inline bool octeon_i2c_is_otx2(struct pci_dev *pdev)
{
	u32 chip_id = FIELD_GET(PCI_SUBSYS_MASK, pdev->subsystem_device);

	return (chip_id == PCI_SUBSYS_DEVID_9XXX);
}

/* Prototypes */
irqreturn_t octeon_i2c_isr(int irq, void *dev_id);
int octeon_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num);
int octeon_i2c_init_lowlevel(struct octeon_i2c *i2c);
void octeon_i2c_set_clock(struct octeon_i2c *i2c);
extern struct i2c_bus_recovery_info octeon_i2c_recovery_info;
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
ad83665b	2	#include <linux/atomic.h>
114c69f4	3	#include <linux/bitfield.h>
ad83665b JG	4	#include <linux/clk.h>
	5	#include <linux/delay.h>
	6	#include <linux/device.h>
	7	#include <linux/i2c.h>
1e586671	8	#include <linux/i2c-smbus.h>
ad83665b JG	9	#include <linux/io.h>
ad83665b JG	10	#include <linux/kernel.h>
114c69f4	11	#include <linux/pci.h>
ad83665b	12
ad83665b JG	13	/* Controller command patterns */
	14	#define SW_TWSI_V BIT_ULL(63) /* Valid bit */
	15	#define SW_TWSI_EIA BIT_ULL(61) /* Extended internal address */
	16	#define SW_TWSI_R BIT_ULL(56) /* Result or read bit */
	17	#define SW_TWSI_SOVR BIT_ULL(55) /* Size override */
	18	#define SW_TWSI_SIZE_SHIFT 52
	19	#define SW_TWSI_ADDR_SHIFT 40
	20	#define SW_TWSI_IA_SHIFT 32 /* Internal address */
	21
	22	/* Controller opcode word (bits 60:57) */
	23	#define SW_TWSI_OP_SHIFT 57
	24	#define SW_TWSI_OP_7 (0ULL << SW_TWSI_OP_SHIFT)
	25	#define SW_TWSI_OP_7_IA (1ULL << SW_TWSI_OP_SHIFT)
	26	#define SW_TWSI_OP_10 (2ULL << SW_TWSI_OP_SHIFT)
	27	#define SW_TWSI_OP_10_IA (3ULL << SW_TWSI_OP_SHIFT)
	28	#define SW_TWSI_OP_TWSI_CLK (4ULL << SW_TWSI_OP_SHIFT)
	29	#define SW_TWSI_OP_EOP (6ULL << SW_TWSI_OP_SHIFT) /* Extended opcode */
	30
	31	/* Controller extended opcode word (bits 34:32) */
	32	#define SW_TWSI_EOP_SHIFT 32
	33	#define SW_TWSI_EOP_TWSI_DATA (SW_TWSI_OP_EOP \| 1ULL << SW_TWSI_EOP_SHIFT)
	34	#define SW_TWSI_EOP_TWSI_CTL (SW_TWSI_OP_EOP \| 2ULL << SW_TWSI_EOP_SHIFT)
	35	#define SW_TWSI_EOP_TWSI_CLKCTL (SW_TWSI_OP_EOP \| 3ULL << SW_TWSI_EOP_SHIFT)
	36	#define SW_TWSI_EOP_TWSI_STAT (SW_TWSI_OP_EOP \| 3ULL << SW_TWSI_EOP_SHIFT)
	37	#define SW_TWSI_EOP_TWSI_RST (SW_TWSI_OP_EOP \| 7ULL << SW_TWSI_EOP_SHIFT)
	38
	39	/* Controller command and status bits */
	40	#define TWSI_CTL_CE 0x80 /* High level controller enable */
	41	#define TWSI_CTL_ENAB 0x40 /* Bus enable */
	42	#define TWSI_CTL_STA 0x20 /* Master-mode start, HW clears when done */
	43	#define TWSI_CTL_STP 0x10 /* Master-mode stop, HW clears when done */
	44	#define TWSI_CTL_IFLG 0x08 /* HW event, SW writes 0 to ACK */
	45	#define TWSI_CTL_AAK 0x04 /* Assert ACK */
	46
	47	/* Status values */
7c424679	48	#define STAT_BUS_ERROR 0x00
ad83665b JG	49	#define STAT_START 0x08
	50	#define STAT_REP_START 0x10
	51	#define STAT_TXADDR_ACK 0x18
	52	#define STAT_TXADDR_NAK 0x20
	53	#define STAT_TXDATA_ACK 0x28
	54	#define STAT_TXDATA_NAK 0x30
	55	#define STAT_LOST_ARB_38 0x38
	56	#define STAT_RXADDR_ACK 0x40
	57	#define STAT_RXADDR_NAK 0x48
	58	#define STAT_RXDATA_ACK 0x50
	59	#define STAT_RXDATA_NAK 0x58
	60	#define STAT_SLAVE_60 0x60
	61	#define STAT_LOST_ARB_68 0x68
	62	#define STAT_SLAVE_70 0x70
	63	#define STAT_LOST_ARB_78 0x78
	64	#define STAT_SLAVE_80 0x80
	65	#define STAT_SLAVE_88 0x88
	66	#define STAT_GENDATA_ACK 0x90
	67	#define STAT_GENDATA_NAK 0x98
	68	#define STAT_SLAVE_A0 0xA0
	69	#define STAT_SLAVE_A8 0xA8
	70	#define STAT_LOST_ARB_B0 0xB0
	71	#define STAT_SLAVE_LOST 0xB8
	72	#define STAT_SLAVE_NAK 0xC0
	73	#define STAT_SLAVE_ACK 0xC8
	74	#define STAT_AD2W_ACK 0xD0
	75	#define STAT_AD2W_NAK 0xD8
b9960b90	76	#define STAT_WDOG_TOUT 0xF0
ad83665b JG	77	#define STAT_IDLE 0xF8
	78
	79	/* TWSI_INT values */
	80	#define TWSI_INT_ST_INT BIT_ULL(0)
	81	#define TWSI_INT_TS_INT BIT_ULL(1)
	82	#define TWSI_INT_CORE_INT BIT_ULL(2)
	83	#define TWSI_INT_ST_EN BIT_ULL(4)
	84	#define TWSI_INT_TS_EN BIT_ULL(5)
	85	#define TWSI_INT_CORE_EN BIT_ULL(6)
	86	#define TWSI_INT_SDA_OVR BIT_ULL(8)
	87	#define TWSI_INT_SCL_OVR BIT_ULL(9)
	88	#define TWSI_INT_SDA BIT_ULL(10)
	89	#define TWSI_INT_SCL BIT_ULL(11)
	90
	91	#define I2C_OCTEON_EVENT_WAIT 80 /* microseconds */
	92
97d97004 JG	93	/* Register offsets */
	94	struct octeon_i2c_reg_offset {
	95	unsigned int sw_twsi;
	96	unsigned int twsi_int;
	97	unsigned int sw_twsi_ext;
03240f82	98	unsigned int mode;
97d97004 JG	99	};
97d97004 JG	100
0b042c72 PM	101	#define OCTEON_REG_SW_TWSI(x) ((x)->roff.sw_twsi)
	102	#define OCTEON_REG_TWSI_INT(x) ((x)->roff.twsi_int)
	103	#define OCTEON_REG_SW_TWSI_EXT(x) ((x)->roff.sw_twsi_ext)
	104	#define OCTEON_REG_MODE(x) ((x)->roff.mode)
03240f82 SG	105
	106	/* Set REFCLK_SRC and HS_MODE in TWSX_MODE register */
	107	#define TWSX_MODE_REFCLK_SRC BIT(4)
	108	#define TWSX_MODE_HS_MODE BIT(0)
	109	#define TWSX_MODE_HS_MASK (TWSX_MODE_REFCLK_SRC \| TWSX_MODE_HS_MODE)
97d97004	110
b9960b90 SG	111	/* Set BUS_MON_RST to reset bus monitor */
	112	#define BUS_MON_RST_MASK BIT(3)
	113
ad83665b JG	114	struct octeon_i2c {
	115	wait_queue_head_t queue;
	116	struct i2c_adapter adap;
97d97004	117	struct octeon_i2c_reg_offset roff;
22d40209	118	struct clk *clk;
ad83665b JG	119	int irq;
	120	int hlc_irq; /* For cn7890 only */
	121	u32 twsi_freq;
	122	int sys_freq;
	123	void __iomem *twsi_base;
	124	struct device *dev;
	125	bool hlc_enabled;
	126	bool broken_irq_mode;
	127	bool broken_irq_check;
	128	void (int_enable)(struct octeon_i2c );
	129	void (int_disable)(struct octeon_i2c );
	130	void (hlc_int_enable)(struct octeon_i2c );
	131	void (hlc_int_disable)(struct octeon_i2c );
	132	atomic_t int_enable_cnt;
	133	atomic_t hlc_int_enable_cnt;
1e586671 JG	134	struct i2c_smbus_alert_setup alert_data;
1e586671 JG	135	struct i2c_client *ara;
ad83665b JG	136	};
	137
	138	static inline void octeon_i2c_writeq_flush(u64 val, void __iomem *addr)
	139	{
	140	__raw_writeq(val, addr);
	141	__raw_readq(addr); /* wait for write to land */
	142	}
	143
	144	/**
	145	* octeon_i2c_reg_write - write an I2C core register
	146	* @i2c: The struct octeon_i2c
	147	* @eop_reg: Register selector
	148	* @data: Value to be written
	149	*
0b042c72	150	* The I2C core registers are accessed indirectly via the OCTEON_REG_SW_TWSI CSR.
ad83665b JG	151	*/
	152	static inline void octeon_i2c_reg_write(struct octeon_i2c *i2c, u64 eop_reg, u8 data)
	153	{
493ff7e2	154	int tries = 1000;
ad83665b JG	155	u64 tmp;
ad83665b JG	156
0b042c72	157	__raw_writeq(SW_TWSI_V \| eop_reg \| data, i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));
dfa2ccc3	158	do {
0b042c72	159	tmp = __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));
493ff7e2 JG	160	if (--tries < 0)
493ff7e2 JG	161	return;
dfa2ccc3	162	} while ((tmp & SW_TWSI_V) != 0);
ad83665b JG	163	}
	164
	165	#define octeon_i2c_ctl_write(i2c, val) \
	166	octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CTL, val)
	167	#define octeon_i2c_data_write(i2c, val) \
	168	octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_DATA, val)
	169
	170	/**
	171	* octeon_i2c_reg_read - read lower bits of an I2C core register
	172	* @i2c: The struct octeon_i2c
	173	* @eop_reg: Register selector
	174	*
	175	* Returns the data.
	176	*
	177	* The I2C core registers are accessed indirectly via the SW_TWSI CSR.
	178	*/
493ff7e2 JG	179	static inline int octeon_i2c_reg_read(struct octeon_i2c *i2c, u64 eop_reg,
493ff7e2 JG	180	int *error)
ad83665b	181	{
493ff7e2	182	int tries = 1000;
ad83665b JG	183	u64 tmp;
ad83665b JG	184
0b042c72	185	__raw_writeq(SW_TWSI_V \| eop_reg \| SW_TWSI_R, i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));
dfa2ccc3	186	do {
0b042c72	187	tmp = __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));
493ff7e2 JG	188	if (--tries < 0) {
	189	/* signal that the returned data is invalid */
	190	if (error)
	191	*error = -EIO;
	192	return 0;
	193	}
dfa2ccc3	194	} while ((tmp & SW_TWSI_V) != 0);
ad83665b JG	195
	196	return tmp & 0xFF;
	197	}
	198
	199	#define octeon_i2c_ctl_read(i2c) \
493ff7e2 JG	200	octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_CTL, NULL)
	201	#define octeon_i2c_data_read(i2c, error) \
	202	octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_DATA, error)
ad83665b	203	#define octeon_i2c_stat_read(i2c) \
493ff7e2	204	octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_STAT, NULL)
ad83665b JG	205
ad83665b JG	206	/**
0b042c72	207	* octeon_i2c_read_int - read the OCTEON_REG_TWSI_INT register
ad83665b JG	208	* @i2c: The struct octeon_i2c
	209	*
	210	* Returns the value of the register.
	211	*/
	212	static inline u64 octeon_i2c_read_int(struct octeon_i2c *i2c)
	213	{
0b042c72	214	return __raw_readq(i2c->twsi_base + OCTEON_REG_TWSI_INT(i2c));
ad83665b JG	215	}
	216
	217	/**
0b042c72	218	* octeon_i2c_write_int - write the OCTEON_REG_TWSI_INT register
ad83665b JG	219	* @i2c: The struct octeon_i2c
	220	* @data: Value to be written
	221	*/
	222	static inline void octeon_i2c_write_int(struct octeon_i2c *i2c, u64 data)
	223	{
0b042c72	224	octeon_i2c_writeq_flush(data, i2c->twsi_base + OCTEON_REG_TWSI_INT(i2c));
ad83665b JG	225	}
ad83665b JG	226
03240f82	227	#define IS_LS_FREQ(twsi_freq) ((twsi_freq) <= 400000)
114c69f4 SG	228	#define PCI_SUBSYS_DEVID_9XXX 0xB
	229	#define PCI_SUBSYS_MASK GENMASK(15, 12)
	230	/**
	231	* octeon_i2c_is_otx2 - check for chip ID
	232	* @pdev: PCI dev structure
	233	*
	234	* Returns true if the device is an OcteonTX2, false otherwise.
	235	*/
	236	static inline bool octeon_i2c_is_otx2(struct pci_dev *pdev)
	237	{
	238	u32 chip_id = FIELD_GET(PCI_SUBSYS_MASK, pdev->subsystem_device);
	239
	240	return (chip_id == PCI_SUBSYS_DEVID_9XXX);
	241	}
	242
ad83665b JG	243	/* Prototypes */
	244	irqreturn_t octeon_i2c_isr(int irq, void *dev_id);
	245	int octeon_i2c_xfer(struct i2c_adapter adap, struct i2c_msg msgs, int num);
	246	int octeon_i2c_init_lowlevel(struct octeon_i2c *i2c);
	247	void octeon_i2c_set_clock(struct octeon_i2c *i2c);
	248	extern struct i2c_bus_recovery_info octeon_i2c_recovery_info;