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3f9900f1 | 1 | /* |
1804edd1 | 2 | * Copyright (C) 2009 ST-Ericsson SA |
3f9900f1 | 3 | * Copyright (C) 2009 STMicroelectronics |
4 | * | |
5 | * I2C master mode controller driver, used in Nomadik 8815 | |
6 | * and Ux500 platforms. | |
7 | * | |
8 | * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> | |
9 | * Author: Sachin Verma <sachin.verma@st.com> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2, as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | #include <linux/init.h> | |
16 | #include <linux/module.h> | |
23560214 AR |
17 | #include <linux/amba/bus.h> |
18 | #include <linux/atomic.h> | |
5a0e3ad6 | 19 | #include <linux/slab.h> |
3f9900f1 | 20 | #include <linux/interrupt.h> |
21 | #include <linux/i2c.h> | |
22 | #include <linux/err.h> | |
23 | #include <linux/clk.h> | |
24 | #include <linux/io.h> | |
b0e751a9 | 25 | #include <linux/pm_runtime.h> |
af97bace | 26 | #include <linux/platform_data/i2c-nomadik.h> |
3f9900f1 | 27 | |
28 | #define DRIVER_NAME "nmk-i2c" | |
29 | ||
30 | /* I2C Controller register offsets */ | |
31 | #define I2C_CR (0x000) | |
32 | #define I2C_SCR (0x004) | |
33 | #define I2C_HSMCR (0x008) | |
34 | #define I2C_MCR (0x00C) | |
35 | #define I2C_TFR (0x010) | |
36 | #define I2C_SR (0x014) | |
37 | #define I2C_RFR (0x018) | |
38 | #define I2C_TFTR (0x01C) | |
39 | #define I2C_RFTR (0x020) | |
40 | #define I2C_DMAR (0x024) | |
41 | #define I2C_BRCR (0x028) | |
42 | #define I2C_IMSCR (0x02C) | |
43 | #define I2C_RISR (0x030) | |
44 | #define I2C_MISR (0x034) | |
45 | #define I2C_ICR (0x038) | |
46 | ||
47 | /* Control registers */ | |
48 | #define I2C_CR_PE (0x1 << 0) /* Peripheral Enable */ | |
49 | #define I2C_CR_OM (0x3 << 1) /* Operating mode */ | |
50 | #define I2C_CR_SAM (0x1 << 3) /* Slave addressing mode */ | |
51 | #define I2C_CR_SM (0x3 << 4) /* Speed mode */ | |
52 | #define I2C_CR_SGCM (0x1 << 6) /* Slave general call mode */ | |
53 | #define I2C_CR_FTX (0x1 << 7) /* Flush Transmit */ | |
54 | #define I2C_CR_FRX (0x1 << 8) /* Flush Receive */ | |
55 | #define I2C_CR_DMA_TX_EN (0x1 << 9) /* DMA Tx enable */ | |
56 | #define I2C_CR_DMA_RX_EN (0x1 << 10) /* DMA Rx Enable */ | |
57 | #define I2C_CR_DMA_SLE (0x1 << 11) /* DMA sync. logic enable */ | |
58 | #define I2C_CR_LM (0x1 << 12) /* Loopback mode */ | |
59 | #define I2C_CR_FON (0x3 << 13) /* Filtering on */ | |
60 | #define I2C_CR_FS (0x3 << 15) /* Force stop enable */ | |
61 | ||
62 | /* Master controller (MCR) register */ | |
63 | #define I2C_MCR_OP (0x1 << 0) /* Operation */ | |
64 | #define I2C_MCR_A7 (0x7f << 1) /* 7-bit address */ | |
8abf6fbb | 65 | #define I2C_MCR_EA10 (0x7 << 8) /* 10-bit Extended address */ |
3f9900f1 | 66 | #define I2C_MCR_SB (0x1 << 11) /* Extended address */ |
67 | #define I2C_MCR_AM (0x3 << 12) /* Address type */ | |
8abf6fbb JA |
68 | #define I2C_MCR_STOP (0x1 << 14) /* Stop condition */ |
69 | #define I2C_MCR_LENGTH (0x7ff << 15) /* Transaction length */ | |
3f9900f1 | 70 | |
71 | /* Status register (SR) */ | |
72 | #define I2C_SR_OP (0x3 << 0) /* Operation */ | |
73 | #define I2C_SR_STATUS (0x3 << 2) /* controller status */ | |
74 | #define I2C_SR_CAUSE (0x7 << 4) /* Abort cause */ | |
75 | #define I2C_SR_TYPE (0x3 << 7) /* Receive type */ | |
76 | #define I2C_SR_LENGTH (0x7ff << 9) /* Transfer length */ | |
77 | ||
78 | /* Interrupt mask set/clear (IMSCR) bits */ | |
8abf6fbb | 79 | #define I2C_IT_TXFE (0x1 << 0) |
3f9900f1 | 80 | #define I2C_IT_TXFNE (0x1 << 1) |
81 | #define I2C_IT_TXFF (0x1 << 2) | |
82 | #define I2C_IT_TXFOVR (0x1 << 3) | |
83 | #define I2C_IT_RXFE (0x1 << 4) | |
84 | #define I2C_IT_RXFNF (0x1 << 5) | |
85 | #define I2C_IT_RXFF (0x1 << 6) | |
86 | #define I2C_IT_RFSR (0x1 << 16) | |
87 | #define I2C_IT_RFSE (0x1 << 17) | |
88 | #define I2C_IT_WTSR (0x1 << 18) | |
89 | #define I2C_IT_MTD (0x1 << 19) | |
90 | #define I2C_IT_STD (0x1 << 20) | |
91 | #define I2C_IT_MAL (0x1 << 24) | |
92 | #define I2C_IT_BERR (0x1 << 25) | |
93 | #define I2C_IT_MTDWS (0x1 << 28) | |
94 | ||
95 | #define GEN_MASK(val, mask, sb) (((val) << (sb)) & (mask)) | |
96 | ||
97 | /* some bits in ICR are reserved */ | |
98 | #define I2C_CLEAR_ALL_INTS 0x131f007f | |
99 | ||
100 | /* first three msb bits are reserved */ | |
101 | #define IRQ_MASK(mask) (mask & 0x1fffffff) | |
102 | ||
103 | /* maximum threshold value */ | |
104 | #define MAX_I2C_FIFO_THRESHOLD 15 | |
105 | ||
106 | enum i2c_status { | |
107 | I2C_NOP, | |
108 | I2C_ON_GOING, | |
109 | I2C_OK, | |
110 | I2C_ABORT | |
111 | }; | |
112 | ||
113 | /* operation */ | |
114 | enum i2c_operation { | |
115 | I2C_NO_OPERATION = 0xff, | |
116 | I2C_WRITE = 0x00, | |
117 | I2C_READ = 0x01 | |
118 | }; | |
119 | ||
3f9900f1 | 120 | /** |
121 | * struct i2c_nmk_client - client specific data | |
122 | * @slave_adr: 7-bit slave address | |
25985edc | 123 | * @count: no. bytes to be transferred |
3f9900f1 | 124 | * @buffer: client data buffer |
25985edc | 125 | * @xfer_bytes: bytes transferred till now |
3f9900f1 | 126 | * @operation: current I2C operation |
127 | */ | |
128 | struct i2c_nmk_client { | |
129 | unsigned short slave_adr; | |
130 | unsigned long count; | |
131 | unsigned char *buffer; | |
132 | unsigned long xfer_bytes; | |
133 | enum i2c_operation operation; | |
134 | }; | |
135 | ||
136 | /** | |
8abf6fbb | 137 | * struct nmk_i2c_dev - private data structure of the controller. |
23560214 | 138 | * @adev: parent amba device. |
8abf6fbb JA |
139 | * @adap: corresponding I2C adapter. |
140 | * @irq: interrupt line for the controller. | |
141 | * @virtbase: virtual io memory area. | |
142 | * @clk: hardware i2c block clock. | |
143 | * @cfg: machine provided controller configuration. | |
144 | * @cli: holder of client specific data. | |
145 | * @stop: stop condition. | |
146 | * @xfer_complete: acknowledge completion for a I2C message. | |
147 | * @result: controller propogated result. | |
8abf6fbb | 148 | * @busy: Busy doing transfer. |
3f9900f1 | 149 | */ |
150 | struct nmk_i2c_dev { | |
23560214 | 151 | struct amba_device *adev; |
8abf6fbb JA |
152 | struct i2c_adapter adap; |
153 | int irq; | |
3f9900f1 | 154 | void __iomem *virtbase; |
155 | struct clk *clk; | |
156 | struct nmk_i2c_controller cfg; | |
157 | struct i2c_nmk_client cli; | |
8abf6fbb | 158 | int stop; |
3f9900f1 | 159 | struct completion xfer_complete; |
8abf6fbb | 160 | int result; |
a20d2394 | 161 | bool busy; |
3f9900f1 | 162 | }; |
163 | ||
164 | /* controller's abort causes */ | |
165 | static const char *abort_causes[] = { | |
166 | "no ack received after address transmission", | |
167 | "no ack received during data phase", | |
168 | "ack received after xmission of master code", | |
169 | "master lost arbitration", | |
170 | "slave restarts", | |
171 | "slave reset", | |
172 | "overflow, maxsize is 2047 bytes", | |
173 | }; | |
174 | ||
175 | static inline void i2c_set_bit(void __iomem *reg, u32 mask) | |
176 | { | |
177 | writel(readl(reg) | mask, reg); | |
178 | } | |
179 | ||
180 | static inline void i2c_clr_bit(void __iomem *reg, u32 mask) | |
181 | { | |
182 | writel(readl(reg) & ~mask, reg); | |
183 | } | |
184 | ||
185 | /** | |
186 | * flush_i2c_fifo() - This function flushes the I2C FIFO | |
187 | * @dev: private data of I2C Driver | |
188 | * | |
189 | * This function flushes the I2C Tx and Rx FIFOs. It returns | |
190 | * 0 on successful flushing of FIFO | |
191 | */ | |
192 | static int flush_i2c_fifo(struct nmk_i2c_dev *dev) | |
193 | { | |
194 | #define LOOP_ATTEMPTS 10 | |
195 | int i; | |
196 | unsigned long timeout; | |
197 | ||
198 | /* | |
199 | * flush the transmit and receive FIFO. The flushing | |
200 | * operation takes several cycles before to be completed. | |
201 | * On the completion, the I2C internal logic clears these | |
202 | * bits, until then no one must access Tx, Rx FIFO and | |
203 | * should poll on these bits waiting for the completion. | |
204 | */ | |
205 | writel((I2C_CR_FTX | I2C_CR_FRX), dev->virtbase + I2C_CR); | |
206 | ||
207 | for (i = 0; i < LOOP_ATTEMPTS; i++) { | |
cd20e4fa | 208 | timeout = jiffies + dev->adap.timeout; |
3f9900f1 | 209 | |
210 | while (!time_after(jiffies, timeout)) { | |
211 | if ((readl(dev->virtbase + I2C_CR) & | |
212 | (I2C_CR_FTX | I2C_CR_FRX)) == 0) | |
213 | return 0; | |
214 | } | |
215 | } | |
216 | ||
23560214 | 217 | dev_err(&dev->adev->dev, |
8abf6fbb JA |
218 | "flushing operation timed out giving up after %d attempts", |
219 | LOOP_ATTEMPTS); | |
3f9900f1 | 220 | |
221 | return -ETIMEDOUT; | |
222 | } | |
223 | ||
224 | /** | |
225 | * disable_all_interrupts() - Disable all interrupts of this I2c Bus | |
226 | * @dev: private data of I2C Driver | |
227 | */ | |
228 | static void disable_all_interrupts(struct nmk_i2c_dev *dev) | |
229 | { | |
230 | u32 mask = IRQ_MASK(0); | |
231 | writel(mask, dev->virtbase + I2C_IMSCR); | |
232 | } | |
233 | ||
234 | /** | |
235 | * clear_all_interrupts() - Clear all interrupts of I2C Controller | |
236 | * @dev: private data of I2C Driver | |
237 | */ | |
238 | static void clear_all_interrupts(struct nmk_i2c_dev *dev) | |
239 | { | |
240 | u32 mask; | |
241 | mask = IRQ_MASK(I2C_CLEAR_ALL_INTS); | |
242 | writel(mask, dev->virtbase + I2C_ICR); | |
243 | } | |
244 | ||
245 | /** | |
246 | * init_hw() - initialize the I2C hardware | |
247 | * @dev: private data of I2C Driver | |
248 | */ | |
249 | static int init_hw(struct nmk_i2c_dev *dev) | |
250 | { | |
251 | int stat; | |
252 | ||
253 | stat = flush_i2c_fifo(dev); | |
254 | if (stat) | |
a20d2394 | 255 | goto exit; |
3f9900f1 | 256 | |
257 | /* disable the controller */ | |
258 | i2c_clr_bit(dev->virtbase + I2C_CR , I2C_CR_PE); | |
259 | ||
260 | disable_all_interrupts(dev); | |
261 | ||
262 | clear_all_interrupts(dev); | |
263 | ||
264 | dev->cli.operation = I2C_NO_OPERATION; | |
265 | ||
a20d2394 | 266 | exit: |
a20d2394 | 267 | return stat; |
3f9900f1 | 268 | } |
269 | ||
270 | /* enable peripheral, master mode operation */ | |
8abf6fbb | 271 | #define DEFAULT_I2C_REG_CR ((1 << 1) | I2C_CR_PE) |
3f9900f1 | 272 | |
273 | /** | |
274 | * load_i2c_mcr_reg() - load the MCR register | |
275 | * @dev: private data of controller | |
51a0c8d0 | 276 | * @flags: message flags |
3f9900f1 | 277 | */ |
51a0c8d0 | 278 | static u32 load_i2c_mcr_reg(struct nmk_i2c_dev *dev, u16 flags) |
3f9900f1 | 279 | { |
280 | u32 mcr = 0; | |
51a0c8d0 | 281 | unsigned short slave_adr_3msb_bits; |
3f9900f1 | 282 | |
3f9900f1 | 283 | mcr |= GEN_MASK(dev->cli.slave_adr, I2C_MCR_A7, 1); |
284 | ||
51a0c8d0 VS |
285 | if (unlikely(flags & I2C_M_TEN)) { |
286 | /* 10-bit address transaction */ | |
287 | mcr |= GEN_MASK(2, I2C_MCR_AM, 12); | |
288 | /* | |
289 | * Get the top 3 bits. | |
290 | * EA10 represents extended address in MCR. This includes | |
291 | * the extension (MSB bits) of the 7 bit address loaded | |
292 | * in A7 | |
293 | */ | |
294 | slave_adr_3msb_bits = (dev->cli.slave_adr >> 7) & 0x7; | |
295 | ||
296 | mcr |= GEN_MASK(slave_adr_3msb_bits, I2C_MCR_EA10, 8); | |
297 | } else { | |
298 | /* 7-bit address transaction */ | |
299 | mcr |= GEN_MASK(1, I2C_MCR_AM, 12); | |
300 | } | |
301 | ||
3f9900f1 | 302 | /* start byte procedure not applied */ |
303 | mcr |= GEN_MASK(0, I2C_MCR_SB, 11); | |
304 | ||
305 | /* check the operation, master read/write? */ | |
306 | if (dev->cli.operation == I2C_WRITE) | |
307 | mcr |= GEN_MASK(I2C_WRITE, I2C_MCR_OP, 0); | |
308 | else | |
309 | mcr |= GEN_MASK(I2C_READ, I2C_MCR_OP, 0); | |
310 | ||
311 | /* stop or repeated start? */ | |
312 | if (dev->stop) | |
313 | mcr |= GEN_MASK(1, I2C_MCR_STOP, 14); | |
314 | else | |
315 | mcr &= ~(GEN_MASK(1, I2C_MCR_STOP, 14)); | |
316 | ||
317 | mcr |= GEN_MASK(dev->cli.count, I2C_MCR_LENGTH, 15); | |
318 | ||
319 | return mcr; | |
320 | } | |
321 | ||
322 | /** | |
323 | * setup_i2c_controller() - setup the controller | |
324 | * @dev: private data of controller | |
325 | */ | |
326 | static void setup_i2c_controller(struct nmk_i2c_dev *dev) | |
327 | { | |
328 | u32 brcr1, brcr2; | |
329 | u32 i2c_clk, div; | |
330 | ||
331 | writel(0x0, dev->virtbase + I2C_CR); | |
332 | writel(0x0, dev->virtbase + I2C_HSMCR); | |
333 | writel(0x0, dev->virtbase + I2C_TFTR); | |
334 | writel(0x0, dev->virtbase + I2C_RFTR); | |
335 | writel(0x0, dev->virtbase + I2C_DMAR); | |
336 | ||
337 | /* | |
338 | * set the slsu: | |
339 | * | |
340 | * slsu defines the data setup time after SCL clock | |
341 | * stretching in terms of i2c clk cycles. The | |
342 | * needed setup time for the three modes are 250ns, | |
25985edc | 343 | * 100ns, 10ns respectively thus leading to the values |
3f9900f1 | 344 | * of 14, 6, 2 for a 48 MHz i2c clk. |
345 | */ | |
346 | writel(dev->cfg.slsu << 16, dev->virtbase + I2C_SCR); | |
347 | ||
348 | i2c_clk = clk_get_rate(dev->clk); | |
349 | ||
3f9900f1 | 350 | /* |
351 | * The spec says, in case of std. mode the divider is | |
352 | * 2 whereas it is 3 for fast and fastplus mode of | |
353 | * operation. TODO - high speed support. | |
354 | */ | |
355 | div = (dev->cfg.clk_freq > 100000) ? 3 : 2; | |
356 | ||
357 | /* | |
358 | * generate the mask for baud rate counters. The controller | |
359 | * has two baud rate counters. One is used for High speed | |
360 | * operation, and the other is for std, fast mode, fast mode | |
361 | * plus operation. Currently we do not supprt high speed mode | |
362 | * so set brcr1 to 0. | |
363 | */ | |
364 | brcr1 = 0 << 16; | |
365 | brcr2 = (i2c_clk/(dev->cfg.clk_freq * div)) & 0xffff; | |
366 | ||
367 | /* set the baud rate counter register */ | |
368 | writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR); | |
369 | ||
370 | /* | |
371 | * set the speed mode. Currently we support | |
372 | * only standard and fast mode of operation | |
25985edc | 373 | * TODO - support for fast mode plus (up to 1Mb/s) |
3f9900f1 | 374 | * and high speed (up to 3.4 Mb/s) |
375 | */ | |
376 | if (dev->cfg.sm > I2C_FREQ_MODE_FAST) { | |
23560214 | 377 | dev_err(&dev->adev->dev, |
8abf6fbb | 378 | "do not support this mode defaulting to std. mode\n"); |
3f9900f1 | 379 | brcr2 = i2c_clk/(100000 * 2) & 0xffff; |
380 | writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR); | |
381 | writel(I2C_FREQ_MODE_STANDARD << 4, | |
382 | dev->virtbase + I2C_CR); | |
383 | } | |
384 | writel(dev->cfg.sm << 4, dev->virtbase + I2C_CR); | |
385 | ||
386 | /* set the Tx and Rx FIFO threshold */ | |
387 | writel(dev->cfg.tft, dev->virtbase + I2C_TFTR); | |
388 | writel(dev->cfg.rft, dev->virtbase + I2C_RFTR); | |
389 | } | |
390 | ||
391 | /** | |
392 | * read_i2c() - Read from I2C client device | |
393 | * @dev: private data of I2C Driver | |
51a0c8d0 | 394 | * @flags: message flags |
3f9900f1 | 395 | * |
396 | * This function reads from i2c client device when controller is in | |
397 | * master mode. There is a completion timeout. If there is no transfer | |
398 | * before timeout error is returned. | |
399 | */ | |
51a0c8d0 | 400 | static int read_i2c(struct nmk_i2c_dev *dev, u16 flags) |
3f9900f1 | 401 | { |
402 | u32 status = 0; | |
403 | u32 mcr; | |
404 | u32 irq_mask = 0; | |
405 | int timeout; | |
406 | ||
51a0c8d0 | 407 | mcr = load_i2c_mcr_reg(dev, flags); |
3f9900f1 | 408 | writel(mcr, dev->virtbase + I2C_MCR); |
409 | ||
410 | /* load the current CR value */ | |
411 | writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR, | |
412 | dev->virtbase + I2C_CR); | |
413 | ||
414 | /* enable the controller */ | |
415 | i2c_set_bit(dev->virtbase + I2C_CR, I2C_CR_PE); | |
416 | ||
417 | init_completion(&dev->xfer_complete); | |
418 | ||
419 | /* enable interrupts by setting the mask */ | |
420 | irq_mask = (I2C_IT_RXFNF | I2C_IT_RXFF | | |
421 | I2C_IT_MAL | I2C_IT_BERR); | |
422 | ||
423 | if (dev->stop) | |
424 | irq_mask |= I2C_IT_MTD; | |
425 | else | |
426 | irq_mask |= I2C_IT_MTDWS; | |
427 | ||
428 | irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask); | |
429 | ||
430 | writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask, | |
431 | dev->virtbase + I2C_IMSCR); | |
432 | ||
4b723a47 | 433 | timeout = wait_for_completion_timeout( |
cd20e4fa | 434 | &dev->xfer_complete, dev->adap.timeout); |
3f9900f1 | 435 | |
436 | if (timeout < 0) { | |
23560214 | 437 | dev_err(&dev->adev->dev, |
8abf6fbb | 438 | "wait_for_completion_timeout " |
3f9900f1 | 439 | "returned %d waiting for event\n", timeout); |
440 | status = timeout; | |
441 | } | |
442 | ||
443 | if (timeout == 0) { | |
0511f643 | 444 | /* Controller timed out */ |
23560214 | 445 | dev_err(&dev->adev->dev, "read from slave 0x%x timed out\n", |
4cb3f538 | 446 | dev->cli.slave_adr); |
3f9900f1 | 447 | status = -ETIMEDOUT; |
448 | } | |
3f9900f1 | 449 | return status; |
450 | } | |
451 | ||
55355341 VS |
452 | static void fill_tx_fifo(struct nmk_i2c_dev *dev, int no_bytes) |
453 | { | |
454 | int count; | |
455 | ||
456 | for (count = (no_bytes - 2); | |
457 | (count > 0) && | |
458 | (dev->cli.count != 0); | |
459 | count--) { | |
460 | /* write to the Tx FIFO */ | |
461 | writeb(*dev->cli.buffer, | |
462 | dev->virtbase + I2C_TFR); | |
463 | dev->cli.buffer++; | |
464 | dev->cli.count--; | |
465 | dev->cli.xfer_bytes++; | |
466 | } | |
467 | ||
468 | } | |
469 | ||
3f9900f1 | 470 | /** |
471 | * write_i2c() - Write data to I2C client. | |
472 | * @dev: private data of I2C Driver | |
51a0c8d0 | 473 | * @flags: message flags |
3f9900f1 | 474 | * |
475 | * This function writes data to I2C client | |
476 | */ | |
51a0c8d0 | 477 | static int write_i2c(struct nmk_i2c_dev *dev, u16 flags) |
3f9900f1 | 478 | { |
479 | u32 status = 0; | |
480 | u32 mcr; | |
481 | u32 irq_mask = 0; | |
482 | int timeout; | |
483 | ||
51a0c8d0 | 484 | mcr = load_i2c_mcr_reg(dev, flags); |
3f9900f1 | 485 | |
486 | writel(mcr, dev->virtbase + I2C_MCR); | |
487 | ||
488 | /* load the current CR value */ | |
489 | writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR, | |
490 | dev->virtbase + I2C_CR); | |
491 | ||
492 | /* enable the controller */ | |
493 | i2c_set_bit(dev->virtbase + I2C_CR , I2C_CR_PE); | |
494 | ||
495 | init_completion(&dev->xfer_complete); | |
496 | ||
497 | /* enable interrupts by settings the masks */ | |
55355341 VS |
498 | irq_mask = (I2C_IT_TXFOVR | I2C_IT_MAL | I2C_IT_BERR); |
499 | ||
500 | /* Fill the TX FIFO with transmit data */ | |
501 | fill_tx_fifo(dev, MAX_I2C_FIFO_THRESHOLD); | |
502 | ||
503 | if (dev->cli.count != 0) | |
504 | irq_mask |= I2C_IT_TXFNE; | |
3f9900f1 | 505 | |
506 | /* | |
507 | * check if we want to transfer a single or multiple bytes, if so | |
508 | * set the MTDWS bit (Master Transaction Done Without Stop) | |
509 | * to start repeated start operation | |
510 | */ | |
511 | if (dev->stop) | |
512 | irq_mask |= I2C_IT_MTD; | |
513 | else | |
514 | irq_mask |= I2C_IT_MTDWS; | |
515 | ||
516 | irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask); | |
517 | ||
518 | writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask, | |
519 | dev->virtbase + I2C_IMSCR); | |
520 | ||
4b723a47 | 521 | timeout = wait_for_completion_timeout( |
cd20e4fa | 522 | &dev->xfer_complete, dev->adap.timeout); |
3f9900f1 | 523 | |
524 | if (timeout < 0) { | |
23560214 | 525 | dev_err(&dev->adev->dev, |
c8d47631 | 526 | "wait_for_completion_timeout " |
3f9900f1 | 527 | "returned %d waiting for event\n", timeout); |
528 | status = timeout; | |
529 | } | |
530 | ||
531 | if (timeout == 0) { | |
0511f643 | 532 | /* Controller timed out */ |
23560214 | 533 | dev_err(&dev->adev->dev, "write to slave 0x%x timed out\n", |
4cb3f538 | 534 | dev->cli.slave_adr); |
3f9900f1 | 535 | status = -ETIMEDOUT; |
536 | } | |
537 | ||
538 | return status; | |
539 | } | |
540 | ||
82a44134 LW |
541 | /** |
542 | * nmk_i2c_xfer_one() - transmit a single I2C message | |
543 | * @dev: device with a message encoded into it | |
544 | * @flags: message flags | |
545 | */ | |
546 | static int nmk_i2c_xfer_one(struct nmk_i2c_dev *dev, u16 flags) | |
547 | { | |
548 | int status; | |
549 | ||
550 | if (flags & I2C_M_RD) { | |
551 | /* read operation */ | |
552 | dev->cli.operation = I2C_READ; | |
51a0c8d0 | 553 | status = read_i2c(dev, flags); |
82a44134 LW |
554 | } else { |
555 | /* write operation */ | |
556 | dev->cli.operation = I2C_WRITE; | |
51a0c8d0 | 557 | status = write_i2c(dev, flags); |
82a44134 LW |
558 | } |
559 | ||
560 | if (status || (dev->result)) { | |
561 | u32 i2c_sr; | |
562 | u32 cause; | |
563 | ||
564 | i2c_sr = readl(dev->virtbase + I2C_SR); | |
565 | /* | |
566 | * Check if the controller I2C operation status | |
567 | * is set to ABORT(11b). | |
568 | */ | |
569 | if (((i2c_sr >> 2) & 0x3) == 0x3) { | |
570 | /* get the abort cause */ | |
571 | cause = (i2c_sr >> 4) & 0x7; | |
23560214 | 572 | dev_err(&dev->adev->dev, "%s\n", |
8abf6fbb | 573 | cause >= ARRAY_SIZE(abort_causes) ? |
82a44134 LW |
574 | "unknown reason" : |
575 | abort_causes[cause]); | |
576 | } | |
577 | ||
578 | (void) init_hw(dev); | |
579 | ||
580 | status = status ? status : dev->result; | |
581 | } | |
582 | ||
583 | return status; | |
584 | } | |
585 | ||
3f9900f1 | 586 | /** |
587 | * nmk_i2c_xfer() - I2C transfer function used by kernel framework | |
1804edd1 LW |
588 | * @i2c_adap: Adapter pointer to the controller |
589 | * @msgs: Pointer to data to be written. | |
590 | * @num_msgs: Number of messages to be executed | |
3f9900f1 | 591 | * |
592 | * This is the function called by the generic kernel i2c_transfer() | |
593 | * or i2c_smbus...() API calls. Note that this code is protected by the | |
594 | * semaphore set in the kernel i2c_transfer() function. | |
595 | * | |
596 | * NOTE: | |
597 | * READ TRANSFER : We impose a restriction of the first message to be the | |
8abf6fbb JA |
598 | * index message for any read transaction. |
599 | * - a no index is coded as '0', | |
600 | * - 2byte big endian index is coded as '3' | |
601 | * !!! msg[0].buf holds the actual index. | |
602 | * This is compatible with generic messages of smbus emulator | |
603 | * that send a one byte index. | |
604 | * eg. a I2C transation to read 2 bytes from index 0 | |
3f9900f1 | 605 | * idx = 0; |
606 | * msg[0].addr = client->addr; | |
607 | * msg[0].flags = 0x0; | |
608 | * msg[0].len = 1; | |
609 | * msg[0].buf = &idx; | |
610 | * | |
611 | * msg[1].addr = client->addr; | |
612 | * msg[1].flags = I2C_M_RD; | |
613 | * msg[1].len = 2; | |
614 | * msg[1].buf = rd_buff | |
615 | * i2c_transfer(adap, msg, 2); | |
616 | * | |
617 | * WRITE TRANSFER : The I2C standard interface interprets all data as payload. | |
618 | * If you want to emulate an SMBUS write transaction put the | |
619 | * index as first byte(or first and second) in the payload. | |
620 | * eg. a I2C transation to write 2 bytes from index 1 | |
621 | * wr_buff[0] = 0x1; | |
622 | * wr_buff[1] = 0x23; | |
623 | * wr_buff[2] = 0x46; | |
624 | * msg[0].flags = 0x0; | |
625 | * msg[0].len = 3; | |
626 | * msg[0].buf = wr_buff; | |
627 | * i2c_transfer(adap, msg, 1); | |
628 | * | |
629 | * To read or write a block of data (multiple bytes) using SMBUS emulation | |
630 | * please use the i2c_smbus_read_i2c_block_data() | |
631 | * or i2c_smbus_write_i2c_block_data() API | |
632 | */ | |
633 | static int nmk_i2c_xfer(struct i2c_adapter *i2c_adap, | |
634 | struct i2c_msg msgs[], int num_msgs) | |
635 | { | |
636 | int status; | |
637 | int i; | |
3f9900f1 | 638 | struct nmk_i2c_dev *dev = i2c_get_adapdata(i2c_adap); |
ebd10e07 | 639 | int j; |
3f9900f1 | 640 | |
a20d2394 JA |
641 | dev->busy = true; |
642 | ||
23560214 | 643 | pm_runtime_get_sync(&dev->adev->dev); |
a20d2394 | 644 | |
ebd10e07 VS |
645 | clk_enable(dev->clk); |
646 | ||
3f9900f1 | 647 | status = init_hw(dev); |
648 | if (status) | |
ebd10e07 | 649 | goto out; |
8ef4f4e4 | 650 | |
82a44134 | 651 | /* Attempt three times to send the message queue */ |
ebd10e07 VS |
652 | for (j = 0; j < 3; j++) { |
653 | /* setup the i2c controller */ | |
654 | setup_i2c_controller(dev); | |
3f9900f1 | 655 | |
ebd10e07 | 656 | for (i = 0; i < num_msgs; i++) { |
ebd10e07 VS |
657 | dev->cli.slave_adr = msgs[i].addr; |
658 | dev->cli.buffer = msgs[i].buf; | |
659 | dev->cli.count = msgs[i].len; | |
660 | dev->stop = (i < (num_msgs - 1)) ? 0 : 1; | |
661 | dev->result = 0; | |
662 | ||
82a44134 LW |
663 | status = nmk_i2c_xfer_one(dev, msgs[i].flags); |
664 | if (status != 0) | |
ebd10e07 | 665 | break; |
3f9900f1 | 666 | } |
ebd10e07 VS |
667 | if (status == 0) |
668 | break; | |
3f9900f1 | 669 | } |
a20d2394 JA |
670 | |
671 | out: | |
8ef4f4e4 | 672 | clk_disable(dev->clk); |
23560214 | 673 | pm_runtime_put_sync(&dev->adev->dev); |
a20d2394 JA |
674 | |
675 | dev->busy = false; | |
8ef4f4e4 | 676 | |
3f9900f1 | 677 | /* return the no. messages processed */ |
678 | if (status) | |
679 | return status; | |
680 | else | |
681 | return num_msgs; | |
682 | } | |
683 | ||
684 | /** | |
685 | * disable_interrupts() - disable the interrupts | |
686 | * @dev: private data of controller | |
1804edd1 | 687 | * @irq: interrupt number |
3f9900f1 | 688 | */ |
689 | static int disable_interrupts(struct nmk_i2c_dev *dev, u32 irq) | |
690 | { | |
691 | irq = IRQ_MASK(irq); | |
692 | writel(readl(dev->virtbase + I2C_IMSCR) & ~(I2C_CLEAR_ALL_INTS & irq), | |
693 | dev->virtbase + I2C_IMSCR); | |
694 | return 0; | |
695 | } | |
696 | ||
697 | /** | |
698 | * i2c_irq_handler() - interrupt routine | |
699 | * @irq: interrupt number | |
700 | * @arg: data passed to the handler | |
701 | * | |
702 | * This is the interrupt handler for the i2c driver. Currently | |
703 | * it handles the major interrupts like Rx & Tx FIFO management | |
704 | * interrupts, master transaction interrupts, arbitration and | |
705 | * bus error interrupts. The rest of the interrupts are treated as | |
706 | * unhandled. | |
707 | */ | |
708 | static irqreturn_t i2c_irq_handler(int irq, void *arg) | |
709 | { | |
710 | struct nmk_i2c_dev *dev = arg; | |
711 | u32 tft, rft; | |
712 | u32 count; | |
713 | u32 misr; | |
714 | u32 src = 0; | |
715 | ||
716 | /* load Tx FIFO and Rx FIFO threshold values */ | |
717 | tft = readl(dev->virtbase + I2C_TFTR); | |
718 | rft = readl(dev->virtbase + I2C_RFTR); | |
719 | ||
720 | /* read interrupt status register */ | |
721 | misr = readl(dev->virtbase + I2C_MISR); | |
722 | ||
723 | src = __ffs(misr); | |
724 | switch ((1 << src)) { | |
725 | ||
726 | /* Transmit FIFO nearly empty interrupt */ | |
727 | case I2C_IT_TXFNE: | |
728 | { | |
729 | if (dev->cli.operation == I2C_READ) { | |
730 | /* | |
731 | * in read operation why do we care for writing? | |
732 | * so disable the Transmit FIFO interrupt | |
733 | */ | |
734 | disable_interrupts(dev, I2C_IT_TXFNE); | |
735 | } else { | |
55355341 | 736 | fill_tx_fifo(dev, (MAX_I2C_FIFO_THRESHOLD - tft)); |
3f9900f1 | 737 | /* |
738 | * if done, close the transfer by disabling the | |
739 | * corresponding TXFNE interrupt | |
740 | */ | |
741 | if (dev->cli.count == 0) | |
742 | disable_interrupts(dev, I2C_IT_TXFNE); | |
743 | } | |
744 | } | |
745 | break; | |
746 | ||
747 | /* | |
748 | * Rx FIFO nearly full interrupt. | |
749 | * This is set when the numer of entries in Rx FIFO is | |
750 | * greater or equal than the threshold value programmed | |
751 | * in RFT | |
752 | */ | |
753 | case I2C_IT_RXFNF: | |
754 | for (count = rft; count > 0; count--) { | |
755 | /* Read the Rx FIFO */ | |
756 | *dev->cli.buffer = readb(dev->virtbase + I2C_RFR); | |
757 | dev->cli.buffer++; | |
758 | } | |
759 | dev->cli.count -= rft; | |
760 | dev->cli.xfer_bytes += rft; | |
761 | break; | |
762 | ||
763 | /* Rx FIFO full */ | |
764 | case I2C_IT_RXFF: | |
765 | for (count = MAX_I2C_FIFO_THRESHOLD; count > 0; count--) { | |
766 | *dev->cli.buffer = readb(dev->virtbase + I2C_RFR); | |
767 | dev->cli.buffer++; | |
768 | } | |
769 | dev->cli.count -= MAX_I2C_FIFO_THRESHOLD; | |
770 | dev->cli.xfer_bytes += MAX_I2C_FIFO_THRESHOLD; | |
771 | break; | |
772 | ||
773 | /* Master Transaction Done with/without stop */ | |
774 | case I2C_IT_MTD: | |
775 | case I2C_IT_MTDWS: | |
776 | if (dev->cli.operation == I2C_READ) { | |
1df3ab1b RV |
777 | while (!(readl(dev->virtbase + I2C_RISR) |
778 | & I2C_IT_RXFE)) { | |
3f9900f1 | 779 | if (dev->cli.count == 0) |
780 | break; | |
781 | *dev->cli.buffer = | |
782 | readb(dev->virtbase + I2C_RFR); | |
783 | dev->cli.buffer++; | |
784 | dev->cli.count--; | |
785 | dev->cli.xfer_bytes++; | |
786 | } | |
787 | } | |
788 | ||
b5e890f7 VS |
789 | disable_all_interrupts(dev); |
790 | clear_all_interrupts(dev); | |
3f9900f1 | 791 | |
792 | if (dev->cli.count) { | |
99381bec | 793 | dev->result = -EIO; |
23560214 | 794 | dev_err(&dev->adev->dev, |
8abf6fbb JA |
795 | "%lu bytes still remain to be xfered\n", |
796 | dev->cli.count); | |
3f9900f1 | 797 | (void) init_hw(dev); |
798 | } | |
799 | complete(&dev->xfer_complete); | |
800 | ||
801 | break; | |
802 | ||
803 | /* Master Arbitration lost interrupt */ | |
804 | case I2C_IT_MAL: | |
99381bec | 805 | dev->result = -EIO; |
3f9900f1 | 806 | (void) init_hw(dev); |
807 | ||
808 | i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_MAL); | |
809 | complete(&dev->xfer_complete); | |
810 | ||
811 | break; | |
812 | ||
813 | /* | |
814 | * Bus Error interrupt. | |
815 | * This happens when an unexpected start/stop condition occurs | |
816 | * during the transaction. | |
817 | */ | |
818 | case I2C_IT_BERR: | |
99381bec | 819 | dev->result = -EIO; |
3f9900f1 | 820 | /* get the status */ |
821 | if (((readl(dev->virtbase + I2C_SR) >> 2) & 0x3) == I2C_ABORT) | |
822 | (void) init_hw(dev); | |
823 | ||
824 | i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_BERR); | |
825 | complete(&dev->xfer_complete); | |
826 | ||
827 | break; | |
828 | ||
829 | /* | |
830 | * Tx FIFO overrun interrupt. | |
831 | * This is set when a write operation in Tx FIFO is performed and | |
832 | * the Tx FIFO is full. | |
833 | */ | |
834 | case I2C_IT_TXFOVR: | |
99381bec | 835 | dev->result = -EIO; |
3f9900f1 | 836 | (void) init_hw(dev); |
837 | ||
23560214 | 838 | dev_err(&dev->adev->dev, "Tx Fifo Over run\n"); |
3f9900f1 | 839 | complete(&dev->xfer_complete); |
840 | ||
841 | break; | |
842 | ||
843 | /* unhandled interrupts by this driver - TODO*/ | |
844 | case I2C_IT_TXFE: | |
845 | case I2C_IT_TXFF: | |
846 | case I2C_IT_RXFE: | |
847 | case I2C_IT_RFSR: | |
848 | case I2C_IT_RFSE: | |
849 | case I2C_IT_WTSR: | |
850 | case I2C_IT_STD: | |
23560214 | 851 | dev_err(&dev->adev->dev, "unhandled Interrupt\n"); |
3f9900f1 | 852 | break; |
853 | default: | |
23560214 | 854 | dev_err(&dev->adev->dev, "spurious Interrupt..\n"); |
3f9900f1 | 855 | break; |
856 | } | |
857 | ||
858 | return IRQ_HANDLED; | |
859 | } | |
860 | ||
a20d2394 JA |
861 | |
862 | #ifdef CONFIG_PM | |
b0e751a9 | 863 | static int nmk_i2c_suspend(struct device *dev) |
a20d2394 | 864 | { |
23560214 AR |
865 | struct amba_device *adev = to_amba_device(dev); |
866 | struct nmk_i2c_dev *nmk_i2c = amba_get_drvdata(adev); | |
a20d2394 | 867 | |
b0e751a9 | 868 | if (nmk_i2c->busy) |
a20d2394 | 869 | return -EBUSY; |
b0e751a9 RV |
870 | |
871 | return 0; | |
872 | } | |
873 | ||
874 | static int nmk_i2c_resume(struct device *dev) | |
875 | { | |
876 | return 0; | |
a20d2394 JA |
877 | } |
878 | #else | |
879 | #define nmk_i2c_suspend NULL | |
b0e751a9 | 880 | #define nmk_i2c_resume NULL |
a20d2394 JA |
881 | #endif |
882 | ||
b0e751a9 RV |
883 | /* |
884 | * We use noirq so that we suspend late and resume before the wakeup interrupt | |
885 | * to ensure that we do the !pm_runtime_suspended() check in resume before | |
886 | * there has been a regular pm runtime resume (via pm_runtime_get_sync()). | |
887 | */ | |
888 | static const struct dev_pm_ops nmk_i2c_pm = { | |
889 | .suspend_noirq = nmk_i2c_suspend, | |
890 | .resume_noirq = nmk_i2c_resume, | |
891 | }; | |
892 | ||
3f9900f1 | 893 | static unsigned int nmk_i2c_functionality(struct i2c_adapter *adap) |
894 | { | |
51a0c8d0 | 895 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR; |
3f9900f1 | 896 | } |
897 | ||
898 | static const struct i2c_algorithm nmk_i2c_algo = { | |
899 | .master_xfer = nmk_i2c_xfer, | |
900 | .functionality = nmk_i2c_functionality | |
901 | }; | |
902 | ||
b007a3ef LJ |
903 | static struct nmk_i2c_controller u8500_i2c = { |
904 | /* | |
905 | * Slave data setup time; 250ns, 100ns, and 10ns, which | |
906 | * is 14, 6 and 2 respectively for a 48Mhz i2c clock. | |
907 | */ | |
908 | .slsu = 0xe, | |
909 | .tft = 1, /* Tx FIFO threshold */ | |
910 | .rft = 8, /* Rx FIFO threshold */ | |
911 | .clk_freq = 400000, /* fast mode operation */ | |
912 | .timeout = 200, /* Slave response timeout(ms) */ | |
913 | .sm = I2C_FREQ_MODE_FAST, | |
914 | }; | |
915 | ||
23560214 AR |
916 | static atomic_t adapter_id = ATOMIC_INIT(0); |
917 | ||
918 | static int nmk_i2c_probe(struct amba_device *adev, const struct amba_id *id) | |
3f9900f1 | 919 | { |
920 | int ret = 0; | |
b007a3ef | 921 | struct nmk_i2c_controller *pdata = adev->dev.platform_data; |
3f9900f1 | 922 | struct nmk_i2c_dev *dev; |
923 | struct i2c_adapter *adap; | |
924 | ||
b007a3ef LJ |
925 | if (!pdata) |
926 | /* No i2c configuration found, using the default. */ | |
927 | pdata = &u8500_i2c; | |
928 | ||
3f9900f1 | 929 | dev = kzalloc(sizeof(struct nmk_i2c_dev), GFP_KERNEL); |
930 | if (!dev) { | |
23560214 | 931 | dev_err(&adev->dev, "cannot allocate memory\n"); |
3f9900f1 | 932 | ret = -ENOMEM; |
933 | goto err_no_mem; | |
934 | } | |
a20d2394 | 935 | dev->busy = false; |
23560214 AR |
936 | dev->adev = adev; |
937 | amba_set_drvdata(adev, dev); | |
3f9900f1 | 938 | |
23560214 | 939 | dev->virtbase = ioremap(adev->res.start, resource_size(&adev->res)); |
3f9900f1 | 940 | if (!dev->virtbase) { |
941 | ret = -ENOMEM; | |
942 | goto err_no_ioremap; | |
943 | } | |
944 | ||
23560214 | 945 | dev->irq = adev->irq[0]; |
4311051c | 946 | ret = request_irq(dev->irq, i2c_irq_handler, 0, |
3f9900f1 | 947 | DRIVER_NAME, dev); |
948 | if (ret) { | |
23560214 | 949 | dev_err(&adev->dev, "cannot claim the irq %d\n", dev->irq); |
3f9900f1 | 950 | goto err_irq; |
951 | } | |
952 | ||
23560214 | 953 | pm_suspend_ignore_children(&adev->dev, true); |
b0e751a9 | 954 | |
23560214 | 955 | dev->clk = clk_get(&adev->dev, NULL); |
3f9900f1 | 956 | if (IS_ERR(dev->clk)) { |
23560214 | 957 | dev_err(&adev->dev, "could not get i2c clock\n"); |
3f9900f1 | 958 | ret = PTR_ERR(dev->clk); |
959 | goto err_no_clk; | |
960 | } | |
961 | ||
3f9900f1 | 962 | adap = &dev->adap; |
23560214 | 963 | adap->dev.parent = &adev->dev; |
3f9900f1 | 964 | adap->owner = THIS_MODULE; |
965 | adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; | |
966 | adap->algo = &nmk_i2c_algo; | |
98582d95 | 967 | adap->timeout = msecs_to_jiffies(pdata->timeout); |
23560214 | 968 | adap->nr = atomic_read(&adapter_id); |
6d779a4c | 969 | snprintf(adap->name, sizeof(adap->name), |
23560214 AR |
970 | "Nomadik I2C%d at %pR", adap->nr, &adev->res); |
971 | atomic_inc(&adapter_id); | |
3f9900f1 | 972 | |
973 | /* fetch the controller configuration from machine */ | |
974 | dev->cfg.clk_freq = pdata->clk_freq; | |
975 | dev->cfg.slsu = pdata->slsu; | |
976 | dev->cfg.tft = pdata->tft; | |
977 | dev->cfg.rft = pdata->rft; | |
978 | dev->cfg.sm = pdata->sm; | |
979 | ||
980 | i2c_set_adapdata(adap, dev); | |
981 | ||
23560214 | 982 | dev_info(&adev->dev, |
8abf6fbb JA |
983 | "initialize %s on virtual base %p\n", |
984 | adap->name, dev->virtbase); | |
3f9900f1 | 985 | |
986 | ret = i2c_add_numbered_adapter(adap); | |
987 | if (ret) { | |
23560214 | 988 | dev_err(&adev->dev, "failed to add adapter\n"); |
3f9900f1 | 989 | goto err_add_adap; |
990 | } | |
991 | ||
23560214 AR |
992 | pm_runtime_put(&adev->dev); |
993 | ||
3f9900f1 | 994 | return 0; |
995 | ||
3f9900f1 | 996 | err_add_adap: |
997 | clk_put(dev->clk); | |
998 | err_no_clk: | |
999 | free_irq(dev->irq, dev); | |
1000 | err_irq: | |
1001 | iounmap(dev->virtbase); | |
1002 | err_no_ioremap: | |
23560214 | 1003 | amba_set_drvdata(adev, NULL); |
3f9900f1 | 1004 | kfree(dev); |
1005 | err_no_mem: | |
1006 | ||
1007 | return ret; | |
1008 | } | |
1009 | ||
23560214 | 1010 | static int nmk_i2c_remove(struct amba_device *adev) |
3f9900f1 | 1011 | { |
23560214 AR |
1012 | struct resource *res = &adev->res; |
1013 | struct nmk_i2c_dev *dev = amba_get_drvdata(adev); | |
3f9900f1 | 1014 | |
1015 | i2c_del_adapter(&dev->adap); | |
1016 | flush_i2c_fifo(dev); | |
1017 | disable_all_interrupts(dev); | |
1018 | clear_all_interrupts(dev); | |
1019 | /* disable the controller */ | |
1020 | i2c_clr_bit(dev->virtbase + I2C_CR, I2C_CR_PE); | |
1021 | free_irq(dev->irq, dev); | |
1022 | iounmap(dev->virtbase); | |
a1c27678 RV |
1023 | if (res) |
1024 | release_mem_region(res->start, resource_size(res)); | |
3f9900f1 | 1025 | clk_put(dev->clk); |
23560214 AR |
1026 | pm_runtime_disable(&adev->dev); |
1027 | amba_set_drvdata(adev, NULL); | |
3f9900f1 | 1028 | kfree(dev); |
1029 | ||
1030 | return 0; | |
1031 | } | |
1032 | ||
23560214 AR |
1033 | static struct amba_id nmk_i2c_ids[] = { |
1034 | { | |
1035 | .id = 0x00180024, | |
1036 | .mask = 0x00ffffff, | |
1037 | }, | |
1038 | { | |
1039 | .id = 0x00380024, | |
1040 | .mask = 0x00ffffff, | |
1041 | }, | |
1042 | {}, | |
1043 | }; | |
1044 | ||
1045 | MODULE_DEVICE_TABLE(amba, nmk_i2c_ids); | |
1046 | ||
1047 | static struct amba_driver nmk_i2c_driver = { | |
1048 | .drv = { | |
3f9900f1 | 1049 | .owner = THIS_MODULE, |
1050 | .name = DRIVER_NAME, | |
b0e751a9 | 1051 | .pm = &nmk_i2c_pm, |
3f9900f1 | 1052 | }, |
23560214 | 1053 | .id_table = nmk_i2c_ids, |
3f9900f1 | 1054 | .probe = nmk_i2c_probe, |
23560214 | 1055 | .remove = nmk_i2c_remove, |
3f9900f1 | 1056 | }; |
1057 | ||
1058 | static int __init nmk_i2c_init(void) | |
1059 | { | |
23560214 | 1060 | return amba_driver_register(&nmk_i2c_driver); |
3f9900f1 | 1061 | } |
1062 | ||
1063 | static void __exit nmk_i2c_exit(void) | |
1064 | { | |
23560214 | 1065 | amba_driver_unregister(&nmk_i2c_driver); |
3f9900f1 | 1066 | } |
1067 | ||
1068 | subsys_initcall(nmk_i2c_init); | |
1069 | module_exit(nmk_i2c_exit); | |
1070 | ||
1071 | MODULE_AUTHOR("Sachin Verma, Srinidhi KASAGAR"); | |
1072 | MODULE_DESCRIPTION("Nomadik/Ux500 I2C driver"); | |
1073 | MODULE_LICENSE("GPL"); |