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Merge branches 'pm-cpuidle', 'pm-core' and 'pm-sleep'
[linux-block.git] / drivers / i2c / busses / i2c-mxs.c
CommitLineData
ed49aaee 1// SPDX-License-Identifier: GPL-2.0+
a8da7fec
WS		 2/*
3 * Freescale MXS I2C bus driver
4 *
29faeb38 5 * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
82fa63bd 6 * Copyright (C) 2011-2012 Wolfram Sang, Pengutronix e.K.
a8da7fec
WS		 7 *
8 * based on a (non-working) driver which was:
9 *
10 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
a8da7fec
WS		 11 */
12
13#include <linux/slab.h>
14#include <linux/device.h>
15#include <linux/module.h>
16#include <linux/i2c.h>
17#include <linux/err.h>
18#include <linux/interrupt.h>
19#include <linux/completion.h>
20#include <linux/platform_device.h>
21#include <linux/jiffies.h>
22#include <linux/io.h>
6b866c15 23#include <linux/stmp_device.h>
b2378668
SG		 24#include <linux/of.h>
25#include <linux/of_device.h>
62885f59
MV		 26#include <linux/dma-mapping.h>
27#include <linux/dmaengine.h>
6eb158ec 28#include <linux/dma/mxs-dma.h>
a8da7fec
WS		 29
30#define DRIVER_NAME "mxs-i2c"
31
32#define MXS_I2C_CTRL0 (0x00)
33#define MXS_I2C_CTRL0_SET (0x04)
19e221be 34#define MXS_I2C_CTRL0_CLR (0x08)
a8da7fec
WS		 35
36#define MXS_I2C_CTRL0_SFTRST 0x80000000
fc91e401 37#define MXS_I2C_CTRL0_RUN 0x20000000
a8da7fec 38#define MXS_I2C_CTRL0_SEND_NAK_ON_LAST 0x02000000
19e221be 39#define MXS_I2C_CTRL0_PIO_MODE 0x01000000
a8da7fec
WS		 40#define MXS_I2C_CTRL0_RETAIN_CLOCK 0x00200000
41#define MXS_I2C_CTRL0_POST_SEND_STOP 0x00100000
42#define MXS_I2C_CTRL0_PRE_SEND_START 0x00080000
43#define MXS_I2C_CTRL0_MASTER_MODE 0x00020000
44#define MXS_I2C_CTRL0_DIRECTION 0x00010000
45#define MXS_I2C_CTRL0_XFER_COUNT(v) ((v) & 0x0000FFFF)
46
cd4f2d4a
MV		 47#define MXS_I2C_TIMING0 (0x10)
48#define MXS_I2C_TIMING1 (0x20)
49#define MXS_I2C_TIMING2 (0x30)
50
a8da7fec
WS		 51#define MXS_I2C_CTRL1 (0x40)
52#define MXS_I2C_CTRL1_SET (0x44)
53#define MXS_I2C_CTRL1_CLR (0x48)
54
92b775c2 55#define MXS_I2C_CTRL1_CLR_GOT_A_NAK 0x10000000
a8da7fec
WS		 56#define MXS_I2C_CTRL1_BUS_FREE_IRQ 0x80
57#define MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 0x40
58#define MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ 0x20
59#define MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 0x10
60#define MXS_I2C_CTRL1_EARLY_TERM_IRQ 0x08
61#define MXS_I2C_CTRL1_MASTER_LOSS_IRQ 0x04
62#define MXS_I2C_CTRL1_SLAVE_STOP_IRQ 0x02
63#define MXS_I2C_CTRL1_SLAVE_IRQ 0x01
64
535ebd21 65#define MXS_I2C_STAT (0x50)
29faeb38 66#define MXS_I2C_STAT_GOT_A_NAK 0x10000000
535ebd21
LS		 67#define MXS_I2C_STAT_BUS_BUSY 0x00000800
68#define MXS_I2C_STAT_CLK_GEN_BUSY 0x00000400
69
19e221be 70#define MXS_I2C_DATA(i2c) ((i2c->dev_type == MXS_I2C_V1) ? 0x60 : 0xa0)
fc91e401 71
19e221be 72#define MXS_I2C_DEBUG0_CLR(i2c) ((i2c->dev_type == MXS_I2C_V1) ? 0x78 : 0xb8)
fc91e401
MV		 73
74#define MXS_I2C_DEBUG0_DMAREQ 0x80000000
75
a8da7fec
WS		 76#define MXS_I2C_IRQ_MASK (MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ | \
77 MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ | \
78 MXS_I2C_CTRL1_EARLY_TERM_IRQ | \
79 MXS_I2C_CTRL1_MASTER_LOSS_IRQ | \
80 MXS_I2C_CTRL1_SLAVE_STOP_IRQ | \
81 MXS_I2C_CTRL1_SLAVE_IRQ)
82
a8da7fec
WS		 83
84#define MXS_CMD_I2C_SELECT (MXS_I2C_CTRL0_RETAIN_CLOCK | \
85 MXS_I2C_CTRL0_PRE_SEND_START | \
86 MXS_I2C_CTRL0_MASTER_MODE | \
87 MXS_I2C_CTRL0_DIRECTION | \
88 MXS_I2C_CTRL0_XFER_COUNT(1))
89
90#define MXS_CMD_I2C_WRITE (MXS_I2C_CTRL0_PRE_SEND_START | \
91 MXS_I2C_CTRL0_MASTER_MODE | \
92 MXS_I2C_CTRL0_DIRECTION)
93
94#define MXS_CMD_I2C_READ (MXS_I2C_CTRL0_SEND_NAK_ON_LAST | \
95 MXS_I2C_CTRL0_MASTER_MODE)
96
616228a1
JB		 97enum mxs_i2c_devtype {
98 MXS_I2C_UNKNOWN = 0,
99 MXS_I2C_V1,
100 MXS_I2C_V2,
101};
102
a8da7fec
WS		 103/**
104 * struct mxs_i2c_dev - per device, private MXS-I2C data
105 *
106 * @dev: driver model device node
616228a1 107 * @dev_type: distinguish i.MX23/i.MX28 features
a8da7fec
WS		 108 * @regs: IO registers pointer
109 * @cmd_complete: completion object for transaction wait
110 * @cmd_err: error code for last transaction
111 * @adapter: i2c subsystem adapter node
112 */
113struct mxs_i2c_dev {
114 struct device *dev;
616228a1 115 enum mxs_i2c_devtype dev_type;
a8da7fec
WS		 116 void __iomem *regs;
117 struct completion cmd_complete;
0f40cbc4 118 int cmd_err;
a8da7fec 119 struct i2c_adapter adapter;
626f0a2f
MV		 120
121 uint32_t timing0;
122 uint32_t timing1;
869c6a3e 123 uint32_t timing2;
62885f59
MV		 124
125 /* DMA support components */
869c6a3e 126 struct dma_chan *dmach;
62885f59
MV		 127 uint32_t pio_data[2];
128 uint32_t addr_data;
129 struct scatterlist sg_io[2];
130 bool dma_read;
a8da7fec
WS		 131};
132
63151c53 133static int mxs_i2c_reset(struct mxs_i2c_dev *i2c)
a8da7fec 134{
63151c53
FE		 135 int ret = stmp_reset_block(i2c->regs);
136 if (ret)
137 return ret;
cd4f2d4a 138
626f0a2f
MV		 139 /*
140 * Configure timing for the I2C block. The I2C TIMING2 register has to
141 * be programmed with this particular magic number. The rest is derived
142 * from the XTAL speed and requested I2C speed.
143 *
144 * For details, see i.MX233 [25.4.2 - 25.4.4] and i.MX28 [27.5.2 - 27.5.4].
145 */
146 writel(i2c->timing0, i2c->regs + MXS_I2C_TIMING0);
147 writel(i2c->timing1, i2c->regs + MXS_I2C_TIMING1);
869c6a3e 148 writel(i2c->timing2, i2c->regs + MXS_I2C_TIMING2);
cd4f2d4a 149
a8da7fec 150 writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET);
63151c53
FE		 151
152 return 0;
a8da7fec
WS		 153}
154
62885f59
MV		 155static void mxs_i2c_dma_finish(struct mxs_i2c_dev *i2c)
156{
157 if (i2c->dma_read) {
158 dma_unmap_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE);
159 dma_unmap_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE);
160 } else {
161 dma_unmap_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE);
162 }
163}
164
165static void mxs_i2c_dma_irq_callback(void *param)
166{
167 struct mxs_i2c_dev *i2c = param;
168
169 complete(&i2c->cmd_complete);
170 mxs_i2c_dma_finish(i2c);
171}
172
173static int mxs_i2c_dma_setup_xfer(struct i2c_adapter *adap,
174 struct i2c_msg *msg, uint32_t flags)
175{
176 struct dma_async_tx_descriptor *desc;
177 struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap);
178
30a64757
PR		 179 i2c->addr_data = i2c_8bit_addr_from_msg(msg);
180
62885f59 181 if (msg->flags & I2C_M_RD) {
4be49b5d 182 i2c->dma_read = true;
62885f59
MV		 183
184 /*
185 * SELECT command.
186 */
187
188 /* Queue the PIO register write transfer. */
189 i2c->pio_data[0] = MXS_CMD_I2C_SELECT;
190 desc = dmaengine_prep_slave_sg(i2c->dmach,
191 (struct scatterlist *)&i2c->pio_data[0],
192 1, DMA_TRANS_NONE, 0);
193 if (!desc) {
194 dev_err(i2c->dev,
195 "Failed to get PIO reg. write descriptor.\n");
196 goto select_init_pio_fail;
197 }
198
199 /* Queue the DMA data transfer. */
200 sg_init_one(&i2c->sg_io[0], &i2c->addr_data, 1);
201 dma_map_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE);
202 desc = dmaengine_prep_slave_sg(i2c->dmach, &i2c->sg_io[0], 1,
203 DMA_MEM_TO_DEV,
6eb158ec
MS		 204 DMA_PREP_INTERRUPT |
205 MXS_DMA_CTRL_WAIT4END);
62885f59
MV		 206 if (!desc) {
207 dev_err(i2c->dev,
208 "Failed to get DMA data write descriptor.\n");
209 goto select_init_dma_fail;
210 }
211
212 /*
213 * READ command.
214 */
215
216 /* Queue the PIO register write transfer. */
217 i2c->pio_data[1] = flags | MXS_CMD_I2C_READ |
218 MXS_I2C_CTRL0_XFER_COUNT(msg->len);
219 desc = dmaengine_prep_slave_sg(i2c->dmach,
220 (struct scatterlist *)&i2c->pio_data[1],
221 1, DMA_TRANS_NONE, DMA_PREP_INTERRUPT);
222 if (!desc) {
223 dev_err(i2c->dev,
224 "Failed to get PIO reg. write descriptor.\n");
225 goto select_init_dma_fail;
226 }
227
228 /* Queue the DMA data transfer. */
229 sg_init_one(&i2c->sg_io[1], msg->buf, msg->len);
230 dma_map_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE);
231 desc = dmaengine_prep_slave_sg(i2c->dmach, &i2c->sg_io[1], 1,
232 DMA_DEV_TO_MEM,
6eb158ec
MS		 233 DMA_PREP_INTERRUPT |
234 MXS_DMA_CTRL_WAIT4END);
62885f59
MV		 235 if (!desc) {
236 dev_err(i2c->dev,
237 "Failed to get DMA data write descriptor.\n");
238 goto read_init_dma_fail;
239 }
240 } else {
4be49b5d 241 i2c->dma_read = false;
62885f59
MV		 242
243 /*
244 * WRITE command.
245 */
246
247 /* Queue the PIO register write transfer. */
248 i2c->pio_data[0] = flags | MXS_CMD_I2C_WRITE |
249 MXS_I2C_CTRL0_XFER_COUNT(msg->len + 1);
250 desc = dmaengine_prep_slave_sg(i2c->dmach,
251 (struct scatterlist *)&i2c->pio_data[0],
252 1, DMA_TRANS_NONE, 0);
253 if (!desc) {
254 dev_err(i2c->dev,
255 "Failed to get PIO reg. write descriptor.\n");
256 goto write_init_pio_fail;
257 }
258
259 /* Queue the DMA data transfer. */
260 sg_init_table(i2c->sg_io, 2);
261 sg_set_buf(&i2c->sg_io[0], &i2c->addr_data, 1);
262 sg_set_buf(&i2c->sg_io[1], msg->buf, msg->len);
263 dma_map_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE);
264 desc = dmaengine_prep_slave_sg(i2c->dmach, i2c->sg_io, 2,
265 DMA_MEM_TO_DEV,
6eb158ec
MS		 266 DMA_PREP_INTERRUPT |
267 MXS_DMA_CTRL_WAIT4END);
62885f59
MV		 268 if (!desc) {
269 dev_err(i2c->dev,
270 "Failed to get DMA data write descriptor.\n");
271 goto write_init_dma_fail;
272 }
273 }
274
275 /*
276 * The last descriptor must have this callback,
277 * to finish the DMA transaction.
278 */
279 desc->callback = mxs_i2c_dma_irq_callback;
280 desc->callback_param = i2c;
281
282 /* Start the transfer. */
283 dmaengine_submit(desc);
284 dma_async_issue_pending(i2c->dmach);
285 return 0;
286
287/* Read failpath. */
288read_init_dma_fail:
289 dma_unmap_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE);
290select_init_dma_fail:
291 dma_unmap_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE);
292select_init_pio_fail:
101703ca 293 dmaengine_terminate_sync(i2c->dmach);
62885f59
MV		 294 return -EINVAL;
295
296/* Write failpath. */
297write_init_dma_fail:
298 dma_unmap_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE);
299write_init_pio_fail:
101703ca 300 dmaengine_terminate_sync(i2c->dmach);
62885f59
MV		 301 return -EINVAL;
302}
303
29faeb38 304static int mxs_i2c_pio_wait_xfer_end(struct mxs_i2c_dev *i2c)
fc91e401
MV		 305{
306 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
307
29faeb38 308 while (readl(i2c->regs + MXS_I2C_CTRL0) & MXS_I2C_CTRL0_RUN) {
030f940a
JU		 309 if (readl(i2c->regs + MXS_I2C_CTRL1) &
310 MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ)
311 return -ENXIO;
535ebd21
LS		 312 if (time_after(jiffies, timeout))
313 return -ETIMEDOUT;
314 cond_resched();
315 }
316
fc91e401
MV		 317 return 0;
318}
319
92b775c2
LS		 320static int mxs_i2c_pio_check_error_state(struct mxs_i2c_dev *i2c)
321{
322 u32 state;
323
324 state = readl(i2c->regs + MXS_I2C_CTRL1_CLR) & MXS_I2C_IRQ_MASK;
325
326 if (state & MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ)
327 i2c->cmd_err = -ENXIO;
328 else if (state & (MXS_I2C_CTRL1_EARLY_TERM_IRQ |
329 MXS_I2C_CTRL1_MASTER_LOSS_IRQ |
330 MXS_I2C_CTRL1_SLAVE_STOP_IRQ |
331 MXS_I2C_CTRL1_SLAVE_IRQ))
332 i2c->cmd_err = -EIO;
333
334 return i2c->cmd_err;
335}
336
535ebd21
LS		 337static void mxs_i2c_pio_trigger_cmd(struct mxs_i2c_dev *i2c, u32 cmd)
338{
339 u32 reg;
340
341 writel(cmd, i2c->regs + MXS_I2C_CTRL0);
342
343 /* readback makes sure the write is latched into hardware */
344 reg = readl(i2c->regs + MXS_I2C_CTRL0);
345 reg |= MXS_I2C_CTRL0_RUN;
346 writel(reg, i2c->regs + MXS_I2C_CTRL0);
347}
348
29faeb38
MV		 349/*
350 * Start WRITE transaction on the I2C bus. By studying i.MX23 datasheet,
351 * CTRL0::PIO_MODE bit description clarifies the order in which the registers
352 * must be written during PIO mode operation. First, the CTRL0 register has
353 * to be programmed with all the necessary bits but the RUN bit. Then the
354 * payload has to be written into the DATA register. Finally, the transmission
355 * is executed by setting the RUN bit in CTRL0.
356 */
357static void mxs_i2c_pio_trigger_write_cmd(struct mxs_i2c_dev *i2c, u32 cmd,
358 u32 data)
359{
360 writel(cmd, i2c->regs + MXS_I2C_CTRL0);
19e221be
MV		 361
362 if (i2c->dev_type == MXS_I2C_V1)
363 writel(MXS_I2C_CTRL0_PIO_MODE, i2c->regs + MXS_I2C_CTRL0_SET);
364
365 writel(data, i2c->regs + MXS_I2C_DATA(i2c));
29faeb38
MV		 366 writel(MXS_I2C_CTRL0_RUN, i2c->regs + MXS_I2C_CTRL0_SET);
367}
368
fc91e401
MV		 369static int mxs_i2c_pio_setup_xfer(struct i2c_adapter *adap,
370 struct i2c_msg *msg, uint32_t flags)
371{
372 struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap);
30a64757 373 uint32_t addr_data = i2c_8bit_addr_from_msg(msg);
fc91e401 374 uint32_t data = 0;
29faeb38
MV		 375 int i, ret, xlen = 0, xmit = 0;
376 uint32_t start;
fc91e401
MV		 377
378 /* Mute IRQs coming from this block. */
379 writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_CLR);
380
29faeb38
MV		 381 /*
382 * MX23 idea:
383 * - Enable CTRL0::PIO_MODE (1 << 24)
384 * - Enable CTRL1::ACK_MODE (1 << 27)
385 *
386 * WARNING! The MX23 is broken in some way, even if it claims
387 * to support PIO, when we try to transfer any amount of data
388 * that is not aligned to 4 bytes, the DMA engine will have
389 * bits in DEBUG1::DMA_BYTES_ENABLES still set even after the
390 * transfer. This in turn will mess up the next transfer as
391 * the block it emit one byte write onto the bus terminated
392 * with a NAK+STOP. A possible workaround is to reset the IP
393 * block after every PIO transmission, which might just work.
394 *
395 * NOTE: The CTRL0::PIO_MODE description is important, since
396 * it outlines how the PIO mode is really supposed to work.
397 */
fc91e401 398 if (msg->flags & I2C_M_RD) {
29faeb38
MV		 399 /*
400 * PIO READ transfer:
401 *
402 * This transfer MUST be limited to 4 bytes maximum. It is not
403 * possible to transfer more than four bytes via PIO, since we
404 * can not in any way make sure we can read the data from the
405 * DATA register fast enough. Besides, the RX FIFO is only four
406 * bytes deep, thus we can only really read up to four bytes at
407 * time. Finally, there is no bit indicating us that new data
408 * arrived at the FIFO and can thus be fetched from the DATA
409 * register.
410 */
411 BUG_ON(msg->len > 4);
412
fc91e401 413 /* SELECT command. */
29faeb38
MV		 414 mxs_i2c_pio_trigger_write_cmd(i2c, MXS_CMD_I2C_SELECT,
415 addr_data);
fc91e401 416
29faeb38
MV		 417 ret = mxs_i2c_pio_wait_xfer_end(i2c);
418 if (ret) {
f9831bfe 419 dev_dbg(i2c->dev,
29faeb38 420 "PIO: Failed to send SELECT command!\n");
92b775c2 421 goto cleanup;
29faeb38 422 }
92b775c2 423
fc91e401 424 /* READ command. */
535ebd21
LS		 425 mxs_i2c_pio_trigger_cmd(i2c,
426 MXS_CMD_I2C_READ | flags |
427 MXS_I2C_CTRL0_XFER_COUNT(msg->len));
fc91e401 428
29faeb38
MV		 429 ret = mxs_i2c_pio_wait_xfer_end(i2c);
430 if (ret) {
f9831bfe 431 dev_dbg(i2c->dev,
a4780d03 432 "PIO: Failed to send READ command!\n");
29faeb38
MV		 433 goto cleanup;
434 }
435
19e221be 436 data = readl(i2c->regs + MXS_I2C_DATA(i2c));
fc91e401 437 for (i = 0; i < msg->len; i++) {
fc91e401
MV		 438 msg->buf[i] = data & 0xff;
439 data >>= 8;
440 }
441 } else {
29faeb38
MV		 442 /*
443 * PIO WRITE transfer:
444 *
445 * The code below implements clock stretching to circumvent
446 * the possibility of kernel not being able to supply data
447 * fast enough. It is possible to transfer arbitrary amount
448 * of data using PIO write.
449 */
fc91e401 450
fc91e401
MV		 451 /*
452 * The LSB of data buffer is the first byte blasted across
453 * the bus. Higher order bytes follow. Thus the following
454 * filling schematic.
455 */
29faeb38 456
fc91e401 457 data = addr_data << 24;
29faeb38
MV		 458
459 /* Start the transfer with START condition. */
460 start = MXS_I2C_CTRL0_PRE_SEND_START;
461
462 /* If the transfer is long, use clock stretching. */
463 if (msg->len > 3)
464 start |= MXS_I2C_CTRL0_RETAIN_CLOCK;
465
fc91e401
MV		 466 for (i = 0; i < msg->len; i++) {
467 data >>= 8;
468 data |= (msg->buf[i] << 24);
29faeb38
MV		 469
470 xmit = 0;
471
472 /* This is the last transfer of the message. */
473 if (i + 1 == msg->len) {
474 /* Add optional STOP flag. */
475 start |= flags;
476 /* Remove RETAIN_CLOCK bit. */
477 start &= ~MXS_I2C_CTRL0_RETAIN_CLOCK;
478 xmit = 1;
fc91e401 479 }
fc91e401 480
29faeb38
MV		 481 /* Four bytes are ready in the "data" variable. */
482 if ((i & 3) == 2)
483 xmit = 1;
484
485 /* Nothing interesting happened, continue stuffing. */
486 if (!xmit)
487 continue;
488
489 /*
490 * Compute the size of the transfer and shift the
491 * data accordingly.
492 *
493 * i = (4k + 0) .... xlen = 2
494 * i = (4k + 1) .... xlen = 3
495 * i = (4k + 2) .... xlen = 4
496 * i = (4k + 3) .... xlen = 1
497 */
498
499 if ((i % 4) == 3)
500 xlen = 1;
501 else
502 xlen = (i % 4) + 2;
503
504 data >>= (4 - xlen) * 8;
505
506 dev_dbg(i2c->dev,
507 "PIO: len=%i pos=%i total=%i [W%s%s%s]\n",
508 xlen, i, msg->len,
509 start & MXS_I2C_CTRL0_PRE_SEND_START ? "S" : "",
510 start & MXS_I2C_CTRL0_POST_SEND_STOP ? "E" : "",
511 start & MXS_I2C_CTRL0_RETAIN_CLOCK ? "C" : "");
512
535ebd21 513 writel(MXS_I2C_DEBUG0_DMAREQ,
19e221be 514 i2c->regs + MXS_I2C_DEBUG0_CLR(i2c));
29faeb38
MV		 515
516 mxs_i2c_pio_trigger_write_cmd(i2c,
517 start | MXS_I2C_CTRL0_MASTER_MODE |
518 MXS_I2C_CTRL0_DIRECTION |
519 MXS_I2C_CTRL0_XFER_COUNT(xlen), data);
520
521 /* The START condition is sent only once. */
522 start &= ~MXS_I2C_CTRL0_PRE_SEND_START;
523
524 /* Wait for the end of the transfer. */
525 ret = mxs_i2c_pio_wait_xfer_end(i2c);
526 if (ret) {
f9831bfe 527 dev_dbg(i2c->dev,
29faeb38
MV		 528 "PIO: Failed to finish WRITE cmd!\n");
529 break;
530 }
531
532 /* Check NAK here. */
533 ret = readl(i2c->regs + MXS_I2C_STAT) &
534 MXS_I2C_STAT_GOT_A_NAK;
535 if (ret) {
536 ret = -ENXIO;
537 goto cleanup;
538 }
fc91e401
MV		 539 }
540 }
541
92b775c2 542 /* make sure we capture any occurred error into cmd_err */
29faeb38 543 ret = mxs_i2c_pio_check_error_state(i2c);
92b775c2
LS		 544
545cleanup:
fc91e401
MV		 546 /* Clear any dangling IRQs and re-enable interrupts. */
547 writel(MXS_I2C_IRQ_MASK, i2c->regs + MXS_I2C_CTRL1_CLR);
548 writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET);
549
19e221be
MV		 550 /* Clear the PIO_MODE on i.MX23 */
551 if (i2c->dev_type == MXS_I2C_V1)
552 writel(MXS_I2C_CTRL0_PIO_MODE, i2c->regs + MXS_I2C_CTRL0_CLR);
553
29faeb38 554 return ret;
fc91e401
MV		 555}
556
a8da7fec
WS		 557/*
558 * Low level master read/write transaction.
559 */
560static int mxs_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg,
561 int stop)
562{
563 struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap);
29faeb38 564 int ret;
a8da7fec 565 int flags;
29faeb38 566 int use_pio = 0;
271a89cd 567 unsigned long time_left;
a8da7fec 568
62885f59
MV		 569 flags = stop ? MXS_I2C_CTRL0_POST_SEND_STOP : 0;
570
a8da7fec
WS		 571 dev_dbg(i2c->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
572 msg->addr, msg->len, msg->flags, stop);
573
fc91e401 574 /*
29faeb38
MV		 575 * The MX28 I2C IP block can only do PIO READ for transfer of to up
576 * 4 bytes of length. The write transfer is not limited as it can use
577 * clock stretching to avoid FIFO underruns.
fc91e401 578 */
29faeb38
MV		 579 if ((msg->flags & I2C_M_RD) && (msg->len <= 4))
580 use_pio = 1;
581 if (!(msg->flags & I2C_M_RD) && (msg->len < 7))
582 use_pio = 1;
583
92b775c2 584 i2c->cmd_err = 0;
29faeb38 585 if (use_pio) {
fc91e401 586 ret = mxs_i2c_pio_setup_xfer(adap, msg, flags);
29faeb38
MV		 587 /* No need to reset the block if NAK was received. */
588 if (ret && (ret != -ENXIO))
589 mxs_i2c_reset(i2c);
fc91e401 590 } else {
16735d02 591 reinit_completion(&i2c->cmd_complete);
fc91e401
MV		 592 ret = mxs_i2c_dma_setup_xfer(adap, msg, flags);
593 if (ret)
594 return ret;
a8da7fec 595
271a89cd 596 time_left = wait_for_completion_timeout(&i2c->cmd_complete,
a8da7fec 597 msecs_to_jiffies(1000));
271a89cd 598 if (!time_left)
fc91e401 599 goto timeout;
29faeb38
MV		 600
601 ret = i2c->cmd_err;
92b775c2 602 }
fc91e401 603
29faeb38 604 if (ret == -ENXIO) {
92b775c2
LS		 605 /*
606 * If the transfer fails with a NAK from the slave the
607 * controller halts until it gets told to return to idle state.
608 */
609 writel(MXS_I2C_CTRL1_CLR_GOT_A_NAK,
610 i2c->regs + MXS_I2C_CTRL1_SET);
fc91e401 611 }
a8da7fec 612
19e221be
MV		 613 /*
614 * WARNING!
615 * The i.MX23 is strange. After each and every operation, it's I2C IP
616 * block must be reset, otherwise the IP block will misbehave. This can
617 * be observed on the bus by the block sending out one single byte onto
618 * the bus. In case such an error happens, bit 27 will be set in the
619 * DEBUG0 register. This bit is not documented in the i.MX23 datasheet
620 * and is marked as "TBD" instead. To reset this bit to a correct state,
621 * reset the whole block. Since the block reset does not take long, do
622 * reset the block after every transfer to play safe.
623 */
624 if (i2c->dev_type == MXS_I2C_V1)
625 mxs_i2c_reset(i2c);
92b775c2 626
fc91e401 627 dev_dbg(i2c->dev, "Done with err=%d\n", ret);
a8da7fec 628
fc91e401 629 return ret;
a8da7fec
WS		 630
631timeout:
632 dev_dbg(i2c->dev, "Timeout!\n");
82fa63bd 633 mxs_i2c_dma_finish(i2c);
63151c53
FE		 634 ret = mxs_i2c_reset(i2c);
635 if (ret)
636 return ret;
637
a8da7fec
WS		 638 return -ETIMEDOUT;
639}
640
641static int mxs_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
642 int num)
643{
644 int i;
645 int err;
646
647 for (i = 0; i < num; i++) {
648 err = mxs_i2c_xfer_msg(adap, &msgs[i], i == (num - 1));
649 if (err)
650 return err;
651 }
652
653 return num;
654}
655
656static u32 mxs_i2c_func(struct i2c_adapter *adap)
657{
8f414059 658 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
a8da7fec
WS		 659}
660
661static irqreturn_t mxs_i2c_isr(int this_irq, void *dev_id)
662{
663 struct mxs_i2c_dev *i2c = dev_id;
664 u32 stat = readl(i2c->regs + MXS_I2C_CTRL1) & MXS_I2C_IRQ_MASK;
665
666 if (!stat)
667 return IRQ_NONE;
668
669 if (stat & MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ)
670 i2c->cmd_err = -ENXIO;
671 else if (stat & (MXS_I2C_CTRL1_EARLY_TERM_IRQ |
672 MXS_I2C_CTRL1_MASTER_LOSS_IRQ |
673 MXS_I2C_CTRL1_SLAVE_STOP_IRQ | MXS_I2C_CTRL1_SLAVE_IRQ))
674 /* MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ is only for slaves */
675 i2c->cmd_err = -EIO;
a8da7fec 676
a8da7fec 677 writel(stat, i2c->regs + MXS_I2C_CTRL1_CLR);
844990da 678
a8da7fec
WS		 679 return IRQ_HANDLED;
680}
681
682static const struct i2c_algorithm mxs_i2c_algo = {
683 .master_xfer = mxs_i2c_xfer,
684 .functionality = mxs_i2c_func,
685};
686
aa14b124
WS		 687static const struct i2c_adapter_quirks mxs_i2c_quirks = {
688 .flags = I2C_AQ_NO_ZERO_LEN,
689};
690
869c6a3e 691static void mxs_i2c_derive_timing(struct mxs_i2c_dev *i2c, uint32_t speed)
626f0a2f 692{
869c6a3e 693 /* The I2C block clock runs at 24MHz */
626f0a2f 694 const uint32_t clk = 24000000;
869c6a3e 695 uint32_t divider;
626f0a2f 696 uint16_t high_count, low_count, rcv_count, xmit_count;
869c6a3e 697 uint32_t bus_free, leadin;
626f0a2f
MV		 698 struct device *dev = i2c->dev;
699
869c6a3e
LW		 700 divider = DIV_ROUND_UP(clk, speed);
701
702 if (divider < 25) {
703 /*
704 * limit the divider, so that min(low_count, high_count)
705 * is >= 1
706 */
707 divider = 25;
708 dev_warn(dev,
709 "Speed too high (%u.%03u kHz), using %u.%03u kHz\n",
710 speed / 1000, speed % 1000,
711 clk / divider / 1000, clk / divider % 1000);
712 } else if (divider > 1897) {
713 /*
714 * limit the divider, so that max(low_count, high_count)
715 * cannot exceed 1023
716 */
717 divider = 1897;
718 dev_warn(dev,
719 "Speed too low (%u.%03u kHz), using %u.%03u kHz\n",
720 speed / 1000, speed % 1000,
721 clk / divider / 1000, clk / divider % 1000);
626f0a2f
MV		 722 }
723
724 /*
869c6a3e
LW		 725 * The I2C spec specifies the following timing data:
726 * standard mode fast mode Bitfield name
727 * tLOW (SCL LOW period) 4700 ns 1300 ns
728 * tHIGH (SCL HIGH period) 4000 ns 600 ns
729 * tSU;DAT (data setup time) 250 ns 100 ns
730 * tHD;STA (START hold time) 4000 ns 600 ns
731 * tBUF (bus free time) 4700 ns 1300 ns
626f0a2f 732 *
869c6a3e
LW		 733 * The hardware (of the i.MX28 at least) seems to add 2 additional
734 * clock cycles to the low_count and 7 cycles to the high_count.
735 * This is compensated for by subtracting the respective constants
736 * from the values written to the timing registers.
626f0a2f 737 */
90224e64 738 if (speed > I2C_MAX_STANDARD_MODE_FREQ) {
869c6a3e
LW		 739 /* fast mode */
740 low_count = DIV_ROUND_CLOSEST(divider * 13, (13 + 6));
741 high_count = DIV_ROUND_CLOSEST(divider * 6, (13 + 6));
742 leadin = DIV_ROUND_UP(600 * (clk / 1000000), 1000);
743 bus_free = DIV_ROUND_UP(1300 * (clk / 1000000), 1000);
744 } else {
745 /* normal mode */
746 low_count = DIV_ROUND_CLOSEST(divider * 47, (47 + 40));
747 high_count = DIV_ROUND_CLOSEST(divider * 40, (47 + 40));
748 leadin = DIV_ROUND_UP(4700 * (clk / 1000000), 1000);
749 bus_free = DIV_ROUND_UP(4700 * (clk / 1000000), 1000);
750 }
751 rcv_count = high_count * 3 / 8;
752 xmit_count = low_count * 3 / 8;
753
754 dev_dbg(dev,
755 "speed=%u(actual %u) divider=%u low=%u high=%u xmit=%u rcv=%u leadin=%u bus_free=%u\n",
756 speed, clk / divider, divider, low_count, high_count,
757 xmit_count, rcv_count, leadin, bus_free);
626f0a2f 758
869c6a3e
LW		 759 low_count -= 2;
760 high_count -= 7;
626f0a2f
MV		 761 i2c->timing0 = (high_count << 16) | rcv_count;
762 i2c->timing1 = (low_count << 16) | xmit_count;
869c6a3e 763 i2c->timing2 = (bus_free << 16 | leadin);
626f0a2f
MV		 764}
765
cd4f2d4a
MV		 766static int mxs_i2c_get_ofdata(struct mxs_i2c_dev *i2c)
767{
768 uint32_t speed;
769 struct device *dev = i2c->dev;
770 struct device_node *node = dev->of_node;
771 int ret;
772
cd4f2d4a 773 ret = of_property_read_u32(node, "clock-frequency", &speed);
626f0a2f 774 if (ret) {
cd4f2d4a 775 dev_warn(dev, "No I2C speed selected, using 100kHz\n");
90224e64 776 speed = I2C_MAX_STANDARD_MODE_FREQ;
626f0a2f
MV		 777 }
778
779 mxs_i2c_derive_timing(i2c, speed);
cd4f2d4a
MV		 780
781 return 0;
782}
783
616228a1 784static const struct of_device_id mxs_i2c_dt_ids[] = {
c32abd8b
FE		 785 { .compatible = "fsl,imx23-i2c", .data = (void *)MXS_I2C_V1, },
786 { .compatible = "fsl,imx28-i2c", .data = (void *)MXS_I2C_V2, },
616228a1
JB		 787 { /* sentinel */ }
788};
789MODULE_DEVICE_TABLE(of, mxs_i2c_dt_ids);
790
0b255e92 791static int mxs_i2c_probe(struct platform_device *pdev)
a8da7fec
WS		 792{
793 struct device *dev = &pdev->dev;
794 struct mxs_i2c_dev *i2c;
795 struct i2c_adapter *adap;
e5aba13d 796 int err, irq;
a8da7fec 797
d4ffeecb 798 i2c = devm_kzalloc(dev, sizeof(*i2c), GFP_KERNEL);
a8da7fec
WS		 799 if (!i2c)
800 return -ENOMEM;
801
3d43273d 802 i2c->dev_type = (uintptr_t)of_device_get_match_data(&pdev->dev);
616228a1 803
b17e6d19 804 i2c->regs = devm_platform_ioremap_resource(pdev, 0);
0977f273
JH		 805 if (IS_ERR(i2c->regs))
806 return PTR_ERR(i2c->regs);
a8da7fec 807
0977f273
JH		 808 irq = platform_get_irq(pdev, 0);
809 if (irq < 0)
810 return irq;
a8da7fec 811
a8da7fec
WS		 812 err = devm_request_irq(dev, irq, mxs_i2c_isr, 0, dev_name(dev), i2c);
813 if (err)
814 return err;
815
816 i2c->dev = dev;
cd4f2d4a 817
85de7fac
MV		 818 init_completion(&i2c->cmd_complete);
819
72ee734a
WS		 820 if (dev->of_node) {
821 err = mxs_i2c_get_ofdata(i2c);
822 if (err)
823 return err;
824 }
cd4f2d4a 825
62885f59 826 /* Setup the DMA */
f7b87c9a
PU		 827 i2c->dmach = dma_request_chan(dev, "rx-tx");
828 if (IS_ERR(i2c->dmach)) {
78a4471f
SW		 829 return dev_err_probe(dev, PTR_ERR(i2c->dmach),
830 "Failed to request dma\n");
62885f59
MV		 831 }
832
a8da7fec
WS		 833 platform_set_drvdata(pdev, i2c);
834
835 /* Do reset to enforce correct startup after pinmuxing */
63151c53
FE		 836 err = mxs_i2c_reset(i2c);
837 if (err)
838 return err;
a8da7fec
WS		 839
840 adap = &i2c->adapter;
ea1558ce 841 strscpy(adap->name, "MXS I2C adapter", sizeof(adap->name));
a8da7fec
WS		 842 adap->owner = THIS_MODULE;
843 adap->algo = &mxs_i2c_algo;
aa14b124 844 adap->quirks = &mxs_i2c_quirks;
a8da7fec
WS		 845 adap->dev.parent = dev;
846 adap->nr = pdev->id;
b2378668 847 adap->dev.of_node = pdev->dev.of_node;
a8da7fec
WS		 848 i2c_set_adapdata(adap, i2c);
849 err = i2c_add_numbered_adapter(adap);
850 if (err) {
a8da7fec
WS		 851 writel(MXS_I2C_CTRL0_SFTRST,
852 i2c->regs + MXS_I2C_CTRL0_SET);
853 return err;
854 }
855
856 return 0;
857}
858
0b255e92 859static int mxs_i2c_remove(struct platform_device *pdev)
a8da7fec
WS		 860{
861 struct mxs_i2c_dev *i2c = platform_get_drvdata(pdev);
a8da7fec 862
bf51a8c5 863 i2c_del_adapter(&i2c->adapter);
a8da7fec 864
62885f59
MV		 865 if (i2c->dmach)
866 dma_release_channel(i2c->dmach);
867
a8da7fec
WS		 868 writel(MXS_I2C_CTRL0_SFTRST, i2c->regs + MXS_I2C_CTRL0_SET);
869
a8da7fec
WS		 870 return 0;
871}
872
873static struct platform_driver mxs_i2c_driver = {
874 .driver = {
875 .name = DRIVER_NAME,
b2378668 876 .of_match_table = mxs_i2c_dt_ids,
a8da7fec 877 },
cc40bf9a 878 .probe = mxs_i2c_probe,
0b255e92 879 .remove = mxs_i2c_remove,
a8da7fec
WS		 880};
881
882static int __init mxs_i2c_init(void)
883{
cc40bf9a 884 return platform_driver_register(&mxs_i2c_driver);
a8da7fec
WS		 885}
886subsys_initcall(mxs_i2c_init);
887
888static void __exit mxs_i2c_exit(void)
889{
890 platform_driver_unregister(&mxs_i2c_driver);
891}
892module_exit(mxs_i2c_exit);
893
29faeb38 894MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
4daf5a28 895MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>");
a8da7fec
WS		 896MODULE_DESCRIPTION("MXS I2C Bus Driver");
897MODULE_LICENSE("GPL");
898MODULE_ALIAS("platform:" DRIVER_NAME);
Linux 6.x block layer and io_uring tree(s)