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treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286
[linux-2.6-block.git] / drivers / i2c / busses / i2c-mt65xx.c
CommitLineData
1802d0be 1// SPDX-License-Identifier: GPL-2.0-only
ce38815d
XC		 2/*
3 * Copyright (c) 2014 MediaTek Inc.
4 * Author: Xudong Chen <xudong.chen@mediatek.com>
ce38815d
XC		 5 */
6
7#include <linux/clk.h>
8#include <linux/completion.h>
9#include <linux/delay.h>
10#include <linux/device.h>
11#include <linux/dma-mapping.h>
12#include <linux/err.h>
13#include <linux/errno.h>
14#include <linux/i2c.h>
15#include <linux/init.h>
16#include <linux/interrupt.h>
17#include <linux/io.h>
18#include <linux/kernel.h>
19#include <linux/mm.h>
20#include <linux/module.h>
21#include <linux/of_address.h>
6e29577f 22#include <linux/of_device.h>
ce38815d
XC		 23#include <linux/of_irq.h>
24#include <linux/platform_device.h>
25#include <linux/scatterlist.h>
26#include <linux/sched.h>
27#include <linux/slab.h>
28
b2ed11e2 29#define I2C_RS_TRANSFER (1 << 4)
cad6dc5d 30#define I2C_ARB_LOST (1 << 3)
ce38815d
XC		 31#define I2C_HS_NACKERR (1 << 2)
32#define I2C_ACKERR (1 << 1)
33#define I2C_TRANSAC_COMP (1 << 0)
34#define I2C_TRANSAC_START (1 << 0)
b2ed11e2
EH		 35#define I2C_RS_MUL_CNFG (1 << 15)
36#define I2C_RS_MUL_TRIG (1 << 14)
ce38815d
XC		 37#define I2C_DCM_DISABLE 0x0000
38#define I2C_IO_CONFIG_OPEN_DRAIN 0x0003
39#define I2C_IO_CONFIG_PUSH_PULL 0x0000
40#define I2C_SOFT_RST 0x0001
41#define I2C_FIFO_ADDR_CLR 0x0001
42#define I2C_DELAY_LEN 0x0002
43#define I2C_ST_START_CON 0x8001
44#define I2C_FS_START_CON 0x1800
45#define I2C_TIME_CLR_VALUE 0x0000
46#define I2C_TIME_DEFAULT_VALUE 0x0003
ce38815d
XC		 47#define I2C_WRRD_TRANAC_VALUE 0x0002
48#define I2C_RD_TRANAC_VALUE 0x0001
49
50#define I2C_DMA_CON_TX 0x0000
51#define I2C_DMA_CON_RX 0x0001
52#define I2C_DMA_START_EN 0x0001
53#define I2C_DMA_INT_FLAG_NONE 0x0000
54#define I2C_DMA_CLR_FLAG 0x0000
ea89ef1f 55#define I2C_DMA_HARD_RST 0x0002
f4f4fed6 56#define I2C_DMA_4G_MODE 0x0001
ce38815d 57
5a10e7d7 58#define I2C_DEFAULT_CLK_DIV 5
ce38815d
XC		 59#define I2C_DEFAULT_SPEED 100000 /* hz */
60#define MAX_FS_MODE_SPEED 400000
61#define MAX_HS_MODE_SPEED 3400000
62#define MAX_SAMPLE_CNT_DIV 8
63#define MAX_STEP_CNT_DIV 64
64#define MAX_HS_STEP_CNT_DIV 8
65
66#define I2C_CONTROL_RS (0x1 << 1)
67#define I2C_CONTROL_DMA_EN (0x1 << 2)
68#define I2C_CONTROL_CLK_EXT_EN (0x1 << 3)
69#define I2C_CONTROL_DIR_CHANGE (0x1 << 4)
70#define I2C_CONTROL_ACKERR_DET_EN (0x1 << 5)
71#define I2C_CONTROL_TRANSFER_LEN_CHANGE (0x1 << 6)
a15c91ba
QW		 72#define I2C_CONTROL_DMAACK_EN (0x1 << 8)
73#define I2C_CONTROL_ASYNC_MODE (0x1 << 9)
ce38815d
XC		 74#define I2C_CONTROL_WRAPPER (0x1 << 0)
75
76#define I2C_DRV_NAME "i2c-mt65xx"
77
78enum DMA_REGS_OFFSET {
79 OFFSET_INT_FLAG = 0x0,
80 OFFSET_INT_EN = 0x04,
81 OFFSET_EN = 0x08,
ea89ef1f 82 OFFSET_RST = 0x0c,
ce38815d
XC		 83 OFFSET_CON = 0x18,
84 OFFSET_TX_MEM_ADDR = 0x1c,
85 OFFSET_RX_MEM_ADDR = 0x20,
86 OFFSET_TX_LEN = 0x24,
87 OFFSET_RX_LEN = 0x28,
f4f4fed6
LZ		 88 OFFSET_TX_4G_MODE = 0x54,
89 OFFSET_RX_4G_MODE = 0x58,
ce38815d
XC		 90};
91
92enum i2c_trans_st_rs {
93 I2C_TRANS_STOP = 0,
94 I2C_TRANS_REPEATED_START,
95};
96
97enum mtk_trans_op {
98 I2C_MASTER_WR = 1,
99 I2C_MASTER_RD,
100 I2C_MASTER_WRRD,
101};
102
103enum I2C_REGS_OFFSET {
bc6eaf17
QW		 104 OFFSET_DATA_PORT,
105 OFFSET_SLAVE_ADDR,
106 OFFSET_INTR_MASK,
107 OFFSET_INTR_STAT,
108 OFFSET_CONTROL,
109 OFFSET_TRANSFER_LEN,
110 OFFSET_TRANSAC_LEN,
111 OFFSET_DELAY_LEN,
112 OFFSET_TIMING,
113 OFFSET_START,
114 OFFSET_EXT_CONF,
115 OFFSET_FIFO_STAT,
116 OFFSET_FIFO_THRESH,
117 OFFSET_FIFO_ADDR_CLR,
118 OFFSET_IO_CONFIG,
119 OFFSET_RSV_DEBUG,
120 OFFSET_HS,
121 OFFSET_SOFTRESET,
122 OFFSET_DCM_EN,
123 OFFSET_PATH_DIR,
124 OFFSET_DEBUGSTAT,
125 OFFSET_DEBUGCTRL,
126 OFFSET_TRANSFER_LEN_AUX,
127 OFFSET_CLOCK_DIV,
25708278 128 OFFSET_LTIMING,
bc6eaf17
QW		 129};
130
131static const u16 mt_i2c_regs_v1[] = {
132 [OFFSET_DATA_PORT] = 0x0,
133 [OFFSET_SLAVE_ADDR] = 0x4,
134 [OFFSET_INTR_MASK] = 0x8,
135 [OFFSET_INTR_STAT] = 0xc,
136 [OFFSET_CONTROL] = 0x10,
137 [OFFSET_TRANSFER_LEN] = 0x14,
138 [OFFSET_TRANSAC_LEN] = 0x18,
139 [OFFSET_DELAY_LEN] = 0x1c,
140 [OFFSET_TIMING] = 0x20,
141 [OFFSET_START] = 0x24,
142 [OFFSET_EXT_CONF] = 0x28,
143 [OFFSET_FIFO_STAT] = 0x30,
144 [OFFSET_FIFO_THRESH] = 0x34,
145 [OFFSET_FIFO_ADDR_CLR] = 0x38,
146 [OFFSET_IO_CONFIG] = 0x40,
147 [OFFSET_RSV_DEBUG] = 0x44,
148 [OFFSET_HS] = 0x48,
149 [OFFSET_SOFTRESET] = 0x50,
150 [OFFSET_DCM_EN] = 0x54,
151 [OFFSET_PATH_DIR] = 0x60,
152 [OFFSET_DEBUGSTAT] = 0x64,
153 [OFFSET_DEBUGCTRL] = 0x68,
154 [OFFSET_TRANSFER_LEN_AUX] = 0x6c,
155 [OFFSET_CLOCK_DIV] = 0x70,
ce38815d
XC		 156};
157
25708278
QW		 158static const u16 mt_i2c_regs_v2[] = {
159 [OFFSET_DATA_PORT] = 0x0,
160 [OFFSET_SLAVE_ADDR] = 0x4,
161 [OFFSET_INTR_MASK] = 0x8,
162 [OFFSET_INTR_STAT] = 0xc,
163 [OFFSET_CONTROL] = 0x10,
164 [OFFSET_TRANSFER_LEN] = 0x14,
165 [OFFSET_TRANSAC_LEN] = 0x18,
166 [OFFSET_DELAY_LEN] = 0x1c,
167 [OFFSET_TIMING] = 0x20,
168 [OFFSET_START] = 0x24,
169 [OFFSET_EXT_CONF] = 0x28,
170 [OFFSET_LTIMING] = 0x2c,
171 [OFFSET_HS] = 0x30,
172 [OFFSET_IO_CONFIG] = 0x34,
173 [OFFSET_FIFO_ADDR_CLR] = 0x38,
174 [OFFSET_TRANSFER_LEN_AUX] = 0x44,
175 [OFFSET_CLOCK_DIV] = 0x48,
176 [OFFSET_SOFTRESET] = 0x50,
177 [OFFSET_DEBUGSTAT] = 0xe0,
178 [OFFSET_DEBUGCTRL] = 0xe8,
179 [OFFSET_FIFO_STAT] = 0xf4,
180 [OFFSET_FIFO_THRESH] = 0xf8,
181 [OFFSET_DCM_EN] = 0xf88,
182};
183
ce38815d
XC		 184struct mtk_i2c_compatible {
185 const struct i2c_adapter_quirks *quirks;
bc6eaf17 186 const u16 *regs;
ce38815d
XC		 187 unsigned char pmic_i2c: 1;
188 unsigned char dcm: 1;
b2ed11e2 189 unsigned char auto_restart: 1;
173b77e8 190 unsigned char aux_len_reg: 1;
f4f4fed6 191 unsigned char support_33bits: 1;
5a10e7d7 192 unsigned char timing_adjust: 1;
a15c91ba 193 unsigned char dma_sync: 1;
25708278 194 unsigned char ltiming_adjust: 1;
ce38815d
XC		 195};
196
197struct mtk_i2c {
198 struct i2c_adapter adap; /* i2c host adapter */
199 struct device *dev;
200 struct completion msg_complete;
201
202 /* set in i2c probe */
203 void __iomem *base; /* i2c base addr */
204 void __iomem *pdmabase; /* dma base address*/
205 struct clk *clk_main; /* main clock for i2c bus */
206 struct clk *clk_dma; /* DMA clock for i2c via DMA */
207 struct clk *clk_pmic; /* PMIC clock for i2c from PMIC */
cad6dc5d 208 struct clk *clk_arb; /* Arbitrator clock for i2c */
ce38815d
XC		 209 bool have_pmic; /* can use i2c pins from PMIC */
210 bool use_push_pull; /* IO config push-pull mode */
211
212 u16 irq_stat; /* interrupt status */
f2326401 213 unsigned int clk_src_div;
ce38815d
XC		 214 unsigned int speed_hz; /* The speed in transfer */
215 enum mtk_trans_op op;
216 u16 timing_reg;
217 u16 high_speed_reg;
25708278 218 u16 ltiming_reg;
173b77e8 219 unsigned char auto_restart;
8378d01f 220 bool ignore_restart_irq;
ce38815d
XC		 221 const struct mtk_i2c_compatible *dev_comp;
222};
223
224static const struct i2c_adapter_quirks mt6577_i2c_quirks = {
225 .flags = I2C_AQ_COMB_WRITE_THEN_READ,
226 .max_num_msgs = 1,
227 .max_write_len = 255,
228 .max_read_len = 255,
229 .max_comb_1st_msg_len = 255,
230 .max_comb_2nd_msg_len = 31,
231};
232
1304fe09
JG		 233static const struct i2c_adapter_quirks mt7622_i2c_quirks = {
234 .max_num_msgs = 255,
235};
236
5a10e7d7 237static const struct mtk_i2c_compatible mt2712_compat = {
bc6eaf17 238 .regs = mt_i2c_regs_v1,
5a10e7d7
JG		 239 .pmic_i2c = 0,
240 .dcm = 1,
241 .auto_restart = 1,
242 .aux_len_reg = 1,
243 .support_33bits = 1,
244 .timing_adjust = 1,
a15c91ba 245 .dma_sync = 0,
25708278 246 .ltiming_adjust = 0,
5a10e7d7
JG		 247};
248
ce38815d
XC		 249static const struct mtk_i2c_compatible mt6577_compat = {
250 .quirks = &mt6577_i2c_quirks,
bc6eaf17 251 .regs = mt_i2c_regs_v1,
ce38815d
XC		 252 .pmic_i2c = 0,
253 .dcm = 1,
b2ed11e2 254 .auto_restart = 0,
173b77e8 255 .aux_len_reg = 0,
f4f4fed6 256 .support_33bits = 0,
5a10e7d7 257 .timing_adjust = 0,
a15c91ba 258 .dma_sync = 0,
25708278 259 .ltiming_adjust = 0,
ce38815d
XC		 260};
261
262static const struct mtk_i2c_compatible mt6589_compat = {
263 .quirks = &mt6577_i2c_quirks,
bc6eaf17 264 .regs = mt_i2c_regs_v1,
ce38815d
XC		 265 .pmic_i2c = 1,
266 .dcm = 0,
b2ed11e2 267 .auto_restart = 0,
173b77e8 268 .aux_len_reg = 0,
f4f4fed6 269 .support_33bits = 0,
5a10e7d7 270 .timing_adjust = 0,
a15c91ba 271 .dma_sync = 0,
25708278 272 .ltiming_adjust = 0,
b2ed11e2
EH		 273};
274
1304fe09
JG		 275static const struct mtk_i2c_compatible mt7622_compat = {
276 .quirks = &mt7622_i2c_quirks,
bc6eaf17 277 .regs = mt_i2c_regs_v1,
1304fe09
JG		 278 .pmic_i2c = 0,
279 .dcm = 1,
280 .auto_restart = 1,
281 .aux_len_reg = 1,
282 .support_33bits = 0,
5a10e7d7 283 .timing_adjust = 0,
a15c91ba 284 .dma_sync = 0,
25708278 285 .ltiming_adjust = 0,
1304fe09
JG		 286};
287
b2ed11e2 288static const struct mtk_i2c_compatible mt8173_compat = {
bc6eaf17 289 .regs = mt_i2c_regs_v1,
b2ed11e2
EH		 290 .pmic_i2c = 0,
291 .dcm = 1,
292 .auto_restart = 1,
173b77e8 293 .aux_len_reg = 1,
f4f4fed6 294 .support_33bits = 1,
5a10e7d7 295 .timing_adjust = 0,
a15c91ba 296 .dma_sync = 0,
25708278
QW		 297 .ltiming_adjust = 0,
298};
299
300static const struct mtk_i2c_compatible mt8183_compat = {
301 .regs = mt_i2c_regs_v2,
302 .pmic_i2c = 0,
303 .dcm = 0,
304 .auto_restart = 1,
305 .aux_len_reg = 1,
306 .support_33bits = 1,
307 .timing_adjust = 1,
308 .dma_sync = 1,
309 .ltiming_adjust = 1,
ce38815d
XC		 310};
311
312static const struct of_device_id mtk_i2c_of_match[] = {
5a10e7d7 313 { .compatible = "mediatek,mt2712-i2c", .data = &mt2712_compat },
ce38815d
XC		 314 { .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat },
315 { .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat },
1304fe09 316 { .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat },
b2ed11e2 317 { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat },
25708278 318 { .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat },
ce38815d
XC		 319 {}
320};
321MODULE_DEVICE_TABLE(of, mtk_i2c_of_match);
322
bc6eaf17
QW		 323static u16 mtk_i2c_readw(struct mtk_i2c *i2c, enum I2C_REGS_OFFSET reg)
324{
325 return readw(i2c->base + i2c->dev_comp->regs[reg]);
326}
327
328static void mtk_i2c_writew(struct mtk_i2c *i2c, u16 val,
329 enum I2C_REGS_OFFSET reg)
330{
331 writew(val, i2c->base + i2c->dev_comp->regs[reg]);
332}
333
ce38815d
XC		 334static int mtk_i2c_clock_enable(struct mtk_i2c *i2c)
335{
336 int ret;
337
338 ret = clk_prepare_enable(i2c->clk_dma);
339 if (ret)
340 return ret;
341
342 ret = clk_prepare_enable(i2c->clk_main);
343 if (ret)
344 goto err_main;
345
346 if (i2c->have_pmic) {
347 ret = clk_prepare_enable(i2c->clk_pmic);
348 if (ret)
349 goto err_pmic;
350 }
cad6dc5d
QW		 351
352 if (i2c->clk_arb) {
353 ret = clk_prepare_enable(i2c->clk_arb);
354 if (ret)
355 goto err_arb;
356 }
357
ce38815d
XC		 358 return 0;
359
cad6dc5d
QW		 360err_arb:
361 if (i2c->have_pmic)
362 clk_disable_unprepare(i2c->clk_pmic);
ce38815d
XC		 363err_pmic:
364 clk_disable_unprepare(i2c->clk_main);
365err_main:
366 clk_disable_unprepare(i2c->clk_dma);
367
368 return ret;
369}
370
371static void mtk_i2c_clock_disable(struct mtk_i2c *i2c)
372{
cad6dc5d
QW		 373 if (i2c->clk_arb)
374 clk_disable_unprepare(i2c->clk_arb);
375
ce38815d
XC		 376 if (i2c->have_pmic)
377 clk_disable_unprepare(i2c->clk_pmic);
378
379 clk_disable_unprepare(i2c->clk_main);
380 clk_disable_unprepare(i2c->clk_dma);
381}
382
383static void mtk_i2c_init_hw(struct mtk_i2c *i2c)
384{
385 u16 control_reg;
386
bc6eaf17 387 mtk_i2c_writew(i2c, I2C_SOFT_RST, OFFSET_SOFTRESET);
ce38815d
XC		 388
389 /* Set ioconfig */
390 if (i2c->use_push_pull)
bc6eaf17 391 mtk_i2c_writew(i2c, I2C_IO_CONFIG_PUSH_PULL, OFFSET_IO_CONFIG);
ce38815d 392 else
bc6eaf17 393 mtk_i2c_writew(i2c, I2C_IO_CONFIG_OPEN_DRAIN, OFFSET_IO_CONFIG);
ce38815d
XC		 394
395 if (i2c->dev_comp->dcm)
bc6eaf17 396 mtk_i2c_writew(i2c, I2C_DCM_DISABLE, OFFSET_DCM_EN);
ce38815d 397
5a10e7d7 398 if (i2c->dev_comp->timing_adjust)
bc6eaf17 399 mtk_i2c_writew(i2c, I2C_DEFAULT_CLK_DIV - 1, OFFSET_CLOCK_DIV);
5a10e7d7 400
bc6eaf17
QW		 401 mtk_i2c_writew(i2c, i2c->timing_reg, OFFSET_TIMING);
402 mtk_i2c_writew(i2c, i2c->high_speed_reg, OFFSET_HS);
25708278
QW		 403 if (i2c->dev_comp->ltiming_adjust)
404 mtk_i2c_writew(i2c, i2c->ltiming_reg, OFFSET_LTIMING);
ce38815d
XC		 405
406 /* If use i2c pin from PMIC mt6397 side, need set PATH_DIR first */
407 if (i2c->have_pmic)
bc6eaf17 408 mtk_i2c_writew(i2c, I2C_CONTROL_WRAPPER, OFFSET_PATH_DIR);
ce38815d
XC		 409
410 control_reg = I2C_CONTROL_ACKERR_DET_EN |
411 I2C_CONTROL_CLK_EXT_EN | I2C_CONTROL_DMA_EN;
a15c91ba
QW		 412 if (i2c->dev_comp->dma_sync)
413 control_reg |= I2C_CONTROL_DMAACK_EN | I2C_CONTROL_ASYNC_MODE;
414
bc6eaf17
QW		 415 mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL);
416 mtk_i2c_writew(i2c, I2C_DELAY_LEN, OFFSET_DELAY_LEN);
ea89ef1f
EH		 417
418 writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST);
419 udelay(50);
420 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
ce38815d
XC		 421}
422
423/*
424 * Calculate i2c port speed
425 *
426 * Hardware design:
427 * i2c_bus_freq = parent_clk / (clock_div * 2 * sample_cnt * step_cnt)
428 * clock_div: fixed in hardware, but may be various in different SoCs
429 *
430 * The calculation want to pick the highest bus frequency that is still
431 * less than or equal to i2c->speed_hz. The calculation try to get
432 * sample_cnt and step_cn
433 */
f2326401
JG		 434static int mtk_i2c_calculate_speed(struct mtk_i2c *i2c, unsigned int clk_src,
435 unsigned int target_speed,
436 unsigned int *timing_step_cnt,
437 unsigned int *timing_sample_cnt)
ce38815d 438{
ce38815d
XC		 439 unsigned int step_cnt;
440 unsigned int sample_cnt;
441 unsigned int max_step_cnt;
ce38815d
XC		 442 unsigned int base_sample_cnt = MAX_SAMPLE_CNT_DIV;
443 unsigned int base_step_cnt;
444 unsigned int opt_div;
445 unsigned int best_mul;
446 unsigned int cnt_mul;
447
ce38815d
XC		 448 if (target_speed > MAX_HS_MODE_SPEED)
449 target_speed = MAX_HS_MODE_SPEED;
450
451 if (target_speed > MAX_FS_MODE_SPEED)
452 max_step_cnt = MAX_HS_STEP_CNT_DIV;
453 else
454 max_step_cnt = MAX_STEP_CNT_DIV;
455
456 base_step_cnt = max_step_cnt;
457 /* Find the best combination */
458 opt_div = DIV_ROUND_UP(clk_src >> 1, target_speed);
459 best_mul = MAX_SAMPLE_CNT_DIV * max_step_cnt;
460
461 /* Search for the best pair (sample_cnt, step_cnt) with
462 * 0 < sample_cnt < MAX_SAMPLE_CNT_DIV
463 * 0 < step_cnt < max_step_cnt
464 * sample_cnt * step_cnt >= opt_div
465 * optimizing for sample_cnt * step_cnt being minimal
466 */
467 for (sample_cnt = 1; sample_cnt <= MAX_SAMPLE_CNT_DIV; sample_cnt++) {
468 step_cnt = DIV_ROUND_UP(opt_div, sample_cnt);
469 cnt_mul = step_cnt * sample_cnt;
470 if (step_cnt > max_step_cnt)
471 continue;
472
473 if (cnt_mul < best_mul) {
474 best_mul = cnt_mul;
475 base_sample_cnt = sample_cnt;
476 base_step_cnt = step_cnt;
477 if (best_mul == opt_div)
478 break;
479 }
480 }
481
482 sample_cnt = base_sample_cnt;
483 step_cnt = base_step_cnt;
484
485 if ((clk_src / (2 * sample_cnt * step_cnt)) > target_speed) {
486 /* In this case, hardware can't support such
487 * low i2c_bus_freq
488 */
489 dev_dbg(i2c->dev, "Unsupported speed (%uhz)\n", target_speed);
490 return -EINVAL;
491 }
492
f2326401
JG		 493 *timing_step_cnt = step_cnt - 1;
494 *timing_sample_cnt = sample_cnt - 1;
495
496 return 0;
497}
498
499static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk)
500{
501 unsigned int clk_src;
502 unsigned int step_cnt;
503 unsigned int sample_cnt;
25708278
QW		 504 unsigned int l_step_cnt;
505 unsigned int l_sample_cnt;
f2326401
JG		 506 unsigned int target_speed;
507 int ret;
508
509 clk_src = parent_clk / i2c->clk_src_div;
510 target_speed = i2c->speed_hz;
ce38815d
XC		 511
512 if (target_speed > MAX_FS_MODE_SPEED) {
f2326401
JG		 513 /* Set master code speed register */
514 ret = mtk_i2c_calculate_speed(i2c, clk_src, MAX_FS_MODE_SPEED,
25708278 515 &l_step_cnt, &l_sample_cnt);
f2326401
JG		 516 if (ret < 0)
517 return ret;
518
25708278 519 i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt;
f2326401 520
ce38815d 521 /* Set the high speed mode register */
f2326401
JG		 522 ret = mtk_i2c_calculate_speed(i2c, clk_src, target_speed,
523 &step_cnt, &sample_cnt);
524 if (ret < 0)
525 return ret;
526
ce38815d
XC		 527 i2c->high_speed_reg = I2C_TIME_DEFAULT_VALUE |
528 (sample_cnt << 12) | (step_cnt << 8);
25708278
QW		 529
530 if (i2c->dev_comp->ltiming_adjust)
531 i2c->ltiming_reg = (l_sample_cnt << 6) | l_step_cnt |
532 (sample_cnt << 12) | (step_cnt << 9);
ce38815d 533 } else {
f2326401
JG		 534 ret = mtk_i2c_calculate_speed(i2c, clk_src, target_speed,
535 &step_cnt, &sample_cnt);
536 if (ret < 0)
537 return ret;
538
539 i2c->timing_reg = (sample_cnt << 8) | step_cnt;
540
ce38815d
XC		 541 /* Disable the high speed transaction */
542 i2c->high_speed_reg = I2C_TIME_CLR_VALUE;
25708278
QW		 543
544 if (i2c->dev_comp->ltiming_adjust)
545 i2c->ltiming_reg = (sample_cnt << 6) | step_cnt;
ce38815d
XC		 546 }
547
548 return 0;
549}
550
f4f4fed6
LZ		 551static inline u32 mtk_i2c_set_4g_mode(dma_addr_t addr)
552{
553 return (addr & BIT_ULL(32)) ? I2C_DMA_4G_MODE : I2C_DMA_CLR_FLAG;
554}
555
b2ed11e2
EH		 556static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
557 int num, int left_num)
ce38815d
XC		 558{
559 u16 addr_reg;
b2ed11e2 560 u16 start_reg;
ce38815d 561 u16 control_reg;
b2ed11e2 562 u16 restart_flag = 0;
f4f4fed6 563 u32 reg_4g_mode;
fc66b39f
JG		 564 u8 *dma_rd_buf = NULL;
565 u8 *dma_wr_buf = NULL;
ce38815d
XC		 566 dma_addr_t rpaddr = 0;
567 dma_addr_t wpaddr = 0;
568 int ret;
569
570 i2c->irq_stat = 0;
571
173b77e8 572 if (i2c->auto_restart)
b2ed11e2
EH		 573 restart_flag = I2C_RS_TRANSFER;
574
ce38815d
XC		 575 reinit_completion(&i2c->msg_complete);
576
bc6eaf17 577 control_reg = mtk_i2c_readw(i2c, OFFSET_CONTROL) &
ce38815d 578 ~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS);
93caa0da 579 if ((i2c->speed_hz > MAX_FS_MODE_SPEED) || (left_num >= 1))
ce38815d
XC		 580 control_reg |= I2C_CONTROL_RS;
581
582 if (i2c->op == I2C_MASTER_WRRD)
583 control_reg |= I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS;
584
bc6eaf17 585 mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL);
ce38815d
XC		 586
587 /* set start condition */
93caa0da 588 if (i2c->speed_hz <= I2C_DEFAULT_SPEED)
bc6eaf17 589 mtk_i2c_writew(i2c, I2C_ST_START_CON, OFFSET_EXT_CONF);
ce38815d 590 else
bc6eaf17 591 mtk_i2c_writew(i2c, I2C_FS_START_CON, OFFSET_EXT_CONF);
ce38815d 592
0d47ce21 593 addr_reg = i2c_8bit_addr_from_msg(msgs);
bc6eaf17 594 mtk_i2c_writew(i2c, addr_reg, OFFSET_SLAVE_ADDR);
ce38815d
XC		 595
596 /* Clear interrupt status */
bc6eaf17 597 mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
cad6dc5d 598 I2C_ARB_LOST | I2C_TRANSAC_COMP, OFFSET_INTR_STAT);
bc6eaf17
QW		 599
600 mtk_i2c_writew(i2c, I2C_FIFO_ADDR_CLR, OFFSET_FIFO_ADDR_CLR);
ce38815d
XC		 601
602 /* Enable interrupt */
bc6eaf17 603 mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
cad6dc5d 604 I2C_ARB_LOST | I2C_TRANSAC_COMP, OFFSET_INTR_MASK);
ce38815d
XC		 605
606 /* Set transfer and transaction len */
607 if (i2c->op == I2C_MASTER_WRRD) {
173b77e8 608 if (i2c->dev_comp->aux_len_reg) {
bc6eaf17
QW		 609 mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN);
610 mtk_i2c_writew(i2c, (msgs + 1)->len,
611 OFFSET_TRANSFER_LEN_AUX);
173b77e8 612 } else {
bc6eaf17
QW		 613 mtk_i2c_writew(i2c, msgs->len | ((msgs + 1)->len) << 8,
614 OFFSET_TRANSFER_LEN);
173b77e8 615 }
bc6eaf17 616 mtk_i2c_writew(i2c, I2C_WRRD_TRANAC_VALUE, OFFSET_TRANSAC_LEN);
ce38815d 617 } else {
bc6eaf17
QW		 618 mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN);
619 mtk_i2c_writew(i2c, num, OFFSET_TRANSAC_LEN);
ce38815d
XC		 620 }
621
622 /* Prepare buffer data to start transfer */
623 if (i2c->op == I2C_MASTER_RD) {
624 writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG);
625 writel(I2C_DMA_CON_RX, i2c->pdmabase + OFFSET_CON);
fc66b39f 626
bc1a7f75 627 dma_rd_buf = i2c_get_dma_safe_msg_buf(msgs, 1);
fc66b39f
JG		 628 if (!dma_rd_buf)
629 return -ENOMEM;
630
631 rpaddr = dma_map_single(i2c->dev, dma_rd_buf,
ce38815d 632 msgs->len, DMA_FROM_DEVICE);
fc66b39f
JG		 633 if (dma_mapping_error(i2c->dev, rpaddr)) {
634 i2c_put_dma_safe_msg_buf(dma_rd_buf, msgs, false);
635
ce38815d 636 return -ENOMEM;
fc66b39f 637 }
f4f4fed6
LZ		 638
639 if (i2c->dev_comp->support_33bits) {
640 reg_4g_mode = mtk_i2c_set_4g_mode(rpaddr);
641 writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE);
642 }
643
ce38815d
XC		 644 writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR);
645 writel(msgs->len, i2c->pdmabase + OFFSET_RX_LEN);
646 } else if (i2c->op == I2C_MASTER_WR) {
647 writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG);
648 writel(I2C_DMA_CON_TX, i2c->pdmabase + OFFSET_CON);
fc66b39f 649
bc1a7f75 650 dma_wr_buf = i2c_get_dma_safe_msg_buf(msgs, 1);
fc66b39f
JG		 651 if (!dma_wr_buf)
652 return -ENOMEM;
653
654 wpaddr = dma_map_single(i2c->dev, dma_wr_buf,
ce38815d 655 msgs->len, DMA_TO_DEVICE);
fc66b39f
JG		 656 if (dma_mapping_error(i2c->dev, wpaddr)) {
657 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false);
658
ce38815d 659 return -ENOMEM;
fc66b39f 660 }
f4f4fed6
LZ		 661
662 if (i2c->dev_comp->support_33bits) {
663 reg_4g_mode = mtk_i2c_set_4g_mode(wpaddr);
664 writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE);
665 }
666
ce38815d
XC		 667 writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR);
668 writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN);
669 } else {
670 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_INT_FLAG);
671 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_CON);
fc66b39f 672
bc1a7f75 673 dma_wr_buf = i2c_get_dma_safe_msg_buf(msgs, 1);
fc66b39f
JG		 674 if (!dma_wr_buf)
675 return -ENOMEM;
676
677 wpaddr = dma_map_single(i2c->dev, dma_wr_buf,
ce38815d 678 msgs->len, DMA_TO_DEVICE);
fc66b39f
JG		 679 if (dma_mapping_error(i2c->dev, wpaddr)) {
680 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false);
681
ce38815d 682 return -ENOMEM;
fc66b39f
JG		 683 }
684
bc1a7f75 685 dma_rd_buf = i2c_get_dma_safe_msg_buf((msgs + 1), 1);
fc66b39f
JG		 686 if (!dma_rd_buf) {
687 dma_unmap_single(i2c->dev, wpaddr,
688 msgs->len, DMA_TO_DEVICE);
689
690 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false);
691
692 return -ENOMEM;
693 }
694
695 rpaddr = dma_map_single(i2c->dev, dma_rd_buf,
ce38815d
XC		 696 (msgs + 1)->len,
697 DMA_FROM_DEVICE);
698 if (dma_mapping_error(i2c->dev, rpaddr)) {
699 dma_unmap_single(i2c->dev, wpaddr,
700 msgs->len, DMA_TO_DEVICE);
fc66b39f
JG		 701
702 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false);
703 i2c_put_dma_safe_msg_buf(dma_rd_buf, (msgs + 1), false);
704
ce38815d
XC		 705 return -ENOMEM;
706 }
f4f4fed6
LZ		 707
708 if (i2c->dev_comp->support_33bits) {
709 reg_4g_mode = mtk_i2c_set_4g_mode(wpaddr);
710 writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE);
711
712 reg_4g_mode = mtk_i2c_set_4g_mode(rpaddr);
713 writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE);
714 }
715
ce38815d
XC		 716 writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR);
717 writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR);
718 writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN);
719 writel((msgs + 1)->len, i2c->pdmabase + OFFSET_RX_LEN);
720 }
721
722 writel(I2C_DMA_START_EN, i2c->pdmabase + OFFSET_EN);
b2ed11e2 723
173b77e8 724 if (!i2c->auto_restart) {
b2ed11e2
EH		 725 start_reg = I2C_TRANSAC_START;
726 } else {
727 start_reg = I2C_TRANSAC_START | I2C_RS_MUL_TRIG;
728 if (left_num >= 1)
729 start_reg |= I2C_RS_MUL_CNFG;
730 }
bc6eaf17 731 mtk_i2c_writew(i2c, start_reg, OFFSET_START);
ce38815d
XC		 732
733 ret = wait_for_completion_timeout(&i2c->msg_complete,
734 i2c->adap.timeout);
735
736 /* Clear interrupt mask */
bc6eaf17 737 mtk_i2c_writew(i2c, ~(restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
cad6dc5d 738 I2C_ARB_LOST | I2C_TRANSAC_COMP), OFFSET_INTR_MASK);
ce38815d
XC		 739
740 if (i2c->op == I2C_MASTER_WR) {
741 dma_unmap_single(i2c->dev, wpaddr,
742 msgs->len, DMA_TO_DEVICE);
fc66b39f
JG		 743
744 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, true);
ce38815d
XC		 745 } else if (i2c->op == I2C_MASTER_RD) {
746 dma_unmap_single(i2c->dev, rpaddr,
747 msgs->len, DMA_FROM_DEVICE);
fc66b39f
JG		 748
749 i2c_put_dma_safe_msg_buf(dma_rd_buf, msgs, true);
ce38815d
XC		 750 } else {
751 dma_unmap_single(i2c->dev, wpaddr, msgs->len,
752 DMA_TO_DEVICE);
753 dma_unmap_single(i2c->dev, rpaddr, (msgs + 1)->len,
754 DMA_FROM_DEVICE);
fc66b39f
JG		 755
756 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, true);
757 i2c_put_dma_safe_msg_buf(dma_rd_buf, (msgs + 1), true);
ce38815d
XC		 758 }
759
760 if (ret == 0) {
761 dev_dbg(i2c->dev, "addr: %x, transfer timeout\n", msgs->addr);
762 mtk_i2c_init_hw(i2c);
763 return -ETIMEDOUT;
764 }
765
ce38815d
XC		 766 if (i2c->irq_stat & (I2C_HS_NACKERR | I2C_ACKERR)) {
767 dev_dbg(i2c->dev, "addr: %x, transfer ACK error\n", msgs->addr);
768 mtk_i2c_init_hw(i2c);
769 return -ENXIO;
770 }
771
772 return 0;
773}
774
775static int mtk_i2c_transfer(struct i2c_adapter *adap,
776 struct i2c_msg msgs[], int num)
777{
778 int ret;
779 int left_num = num;
780 struct mtk_i2c *i2c = i2c_get_adapdata(adap);
781
782 ret = mtk_i2c_clock_enable(i2c);
783 if (ret)
784 return ret;
785
173b77e8
LZ		 786 i2c->auto_restart = i2c->dev_comp->auto_restart;
787
788 /* checking if we can skip restart and optimize using WRRD mode */
789 if (i2c->auto_restart && num == 2) {
790 if (!(msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD) &&
791 msgs[0].addr == msgs[1].addr) {
792 i2c->auto_restart = 0;
793 }
794 }
795
8378d01f
LZ		 796 if (i2c->auto_restart && num >= 2 && i2c->speed_hz > MAX_FS_MODE_SPEED)
797 /* ignore the first restart irq after the master code,
798 * otherwise the first transfer will be discarded.
799 */
800 i2c->ignore_restart_irq = true;
801 else
802 i2c->ignore_restart_irq = false;
803
b2ed11e2
EH		 804 while (left_num--) {
805 if (!msgs->buf) {
806 dev_dbg(i2c->dev, "data buffer is NULL.\n");
807 ret = -EINVAL;
808 goto err_exit;
809 }
ce38815d 810
b2ed11e2
EH		 811 if (msgs->flags & I2C_M_RD)
812 i2c->op = I2C_MASTER_RD;
813 else
814 i2c->op = I2C_MASTER_WR;
815
173b77e8 816 if (!i2c->auto_restart) {
b2ed11e2
EH		 817 if (num > 1) {
818 /* combined two messages into one transaction */
819 i2c->op = I2C_MASTER_WRRD;
820 left_num--;
821 }
822 }
ce38815d 823
b2ed11e2
EH		 824 /* always use DMA mode. */
825 ret = mtk_i2c_do_transfer(i2c, msgs, num, left_num);
826 if (ret < 0)
827 goto err_exit;
ce38815d 828
b2ed11e2
EH		 829 msgs++;
830 }
ce38815d
XC		 831 /* the return value is number of executed messages */
832 ret = num;
833
834err_exit:
835 mtk_i2c_clock_disable(i2c);
836 return ret;
837}
838
839static irqreturn_t mtk_i2c_irq(int irqno, void *dev_id)
840{
841 struct mtk_i2c *i2c = dev_id;
b2ed11e2 842 u16 restart_flag = 0;
28c0a843 843 u16 intr_stat;
b2ed11e2 844
173b77e8 845 if (i2c->auto_restart)
b2ed11e2 846 restart_flag = I2C_RS_TRANSFER;
ce38815d 847
bc6eaf17
QW		 848 intr_stat = mtk_i2c_readw(i2c, OFFSET_INTR_STAT);
849 mtk_i2c_writew(i2c, intr_stat, OFFSET_INTR_STAT);
ce38815d 850
28c0a843
EH		 851 /*
852 * when occurs ack error, i2c controller generate two interrupts
853 * first is the ack error interrupt, then the complete interrupt
854 * i2c->irq_stat need keep the two interrupt value.
855 */
856 i2c->irq_stat |= intr_stat;
8378d01f
LZ		 857
858 if (i2c->ignore_restart_irq && (i2c->irq_stat & restart_flag)) {
859 i2c->ignore_restart_irq = false;
860 i2c->irq_stat = 0;
bc6eaf17
QW		 861 mtk_i2c_writew(i2c, I2C_RS_MUL_CNFG | I2C_RS_MUL_TRIG |
862 I2C_TRANSAC_START, OFFSET_START);
8378d01f
LZ		 863 } else {
864 if (i2c->irq_stat & (I2C_TRANSAC_COMP | restart_flag))
865 complete(&i2c->msg_complete);
866 }
ce38815d
XC		 867
868 return IRQ_HANDLED;
869}
870
871static u32 mtk_i2c_functionality(struct i2c_adapter *adap)
872{
873 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
874}
875
876static const struct i2c_algorithm mtk_i2c_algorithm = {
877 .master_xfer = mtk_i2c_transfer,
878 .functionality = mtk_i2c_functionality,
879};
880
f2326401 881static int mtk_i2c_parse_dt(struct device_node *np, struct mtk_i2c *i2c)
ce38815d
XC		 882{
883 int ret;
884
885 ret = of_property_read_u32(np, "clock-frequency", &i2c->speed_hz);
886 if (ret < 0)
887 i2c->speed_hz = I2C_DEFAULT_SPEED;
888
f2326401 889 ret = of_property_read_u32(np, "clock-div", &i2c->clk_src_div);
ce38815d
XC		 890 if (ret < 0)
891 return ret;
892
f2326401 893 if (i2c->clk_src_div == 0)
ce38815d
XC		 894 return -EINVAL;
895
896 i2c->have_pmic = of_property_read_bool(np, "mediatek,have-pmic");
897 i2c->use_push_pull =
898 of_property_read_bool(np, "mediatek,use-push-pull");
899
900 return 0;
901}
902
903static int mtk_i2c_probe(struct platform_device *pdev)
904{
ce38815d
XC		 905 int ret = 0;
906 struct mtk_i2c *i2c;
907 struct clk *clk;
ce38815d
XC		 908 struct resource *res;
909 int irq;
910
911 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
912 if (!i2c)
913 return -ENOMEM;
914
ce38815d
XC		 915 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
916 i2c->base = devm_ioremap_resource(&pdev->dev, res);
917 if (IS_ERR(i2c->base))
918 return PTR_ERR(i2c->base);
919
920 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
921 i2c->pdmabase = devm_ioremap_resource(&pdev->dev, res);
922 if (IS_ERR(i2c->pdmabase))
923 return PTR_ERR(i2c->pdmabase);
924
925 irq = platform_get_irq(pdev, 0);
926 if (irq <= 0)
927 return irq;
928
929 init_completion(&i2c->msg_complete);
930
6e29577f 931 i2c->dev_comp = of_device_get_match_data(&pdev->dev);
ce38815d
XC		 932 i2c->adap.dev.of_node = pdev->dev.of_node;
933 i2c->dev = &pdev->dev;
934 i2c->adap.dev.parent = &pdev->dev;
935 i2c->adap.owner = THIS_MODULE;
936 i2c->adap.algo = &mtk_i2c_algorithm;
937 i2c->adap.quirks = i2c->dev_comp->quirks;
938 i2c->adap.timeout = 2 * HZ;
939 i2c->adap.retries = 1;
940
5a10e7d7
JG		 941 ret = mtk_i2c_parse_dt(pdev->dev.of_node, i2c);
942 if (ret)
943 return -EINVAL;
944
945 if (i2c->dev_comp->timing_adjust)
946 i2c->clk_src_div *= I2C_DEFAULT_CLK_DIV;
947
ce38815d
XC		 948 if (i2c->have_pmic && !i2c->dev_comp->pmic_i2c)
949 return -EINVAL;
950
951 i2c->clk_main = devm_clk_get(&pdev->dev, "main");
952 if (IS_ERR(i2c->clk_main)) {
953 dev_err(&pdev->dev, "cannot get main clock\n");
954 return PTR_ERR(i2c->clk_main);
955 }
956
957 i2c->clk_dma = devm_clk_get(&pdev->dev, "dma");
958 if (IS_ERR(i2c->clk_dma)) {
959 dev_err(&pdev->dev, "cannot get dma clock\n");
960 return PTR_ERR(i2c->clk_dma);
961 }
962
cad6dc5d
QW		 963 i2c->clk_arb = devm_clk_get(&pdev->dev, "arb");
964 if (IS_ERR(i2c->clk_arb))
965 i2c->clk_arb = NULL;
966
ce38815d
XC		 967 clk = i2c->clk_main;
968 if (i2c->have_pmic) {
969 i2c->clk_pmic = devm_clk_get(&pdev->dev, "pmic");
970 if (IS_ERR(i2c->clk_pmic)) {
971 dev_err(&pdev->dev, "cannot get pmic clock\n");
972 return PTR_ERR(i2c->clk_pmic);
973 }
974 clk = i2c->clk_pmic;
975 }
976
977 strlcpy(i2c->adap.name, I2C_DRV_NAME, sizeof(i2c->adap.name));
978
f2326401 979 ret = mtk_i2c_set_speed(i2c, clk_get_rate(clk));
ce38815d
XC		 980 if (ret) {
981 dev_err(&pdev->dev, "Failed to set the speed.\n");
982 return -EINVAL;
983 }
984
f4f4fed6
LZ		 985 if (i2c->dev_comp->support_33bits) {
986 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(33));
987 if (ret) {
988 dev_err(&pdev->dev, "dma_set_mask return error.\n");
989 return ret;
990 }
991 }
992
ce38815d
XC		 993 ret = mtk_i2c_clock_enable(i2c);
994 if (ret) {
995 dev_err(&pdev->dev, "clock enable failed!\n");
996 return ret;
997 }
998 mtk_i2c_init_hw(i2c);
999 mtk_i2c_clock_disable(i2c);
1000
1001 ret = devm_request_irq(&pdev->dev, irq, mtk_i2c_irq,
1002 IRQF_TRIGGER_NONE, I2C_DRV_NAME, i2c);
1003 if (ret < 0) {
1004 dev_err(&pdev->dev,
1005 "Request I2C IRQ %d fail\n", irq);
1006 return ret;
1007 }
1008
1009 i2c_set_adapdata(&i2c->adap, i2c);
1010 ret = i2c_add_adapter(&i2c->adap);
ea734404 1011 if (ret)
ce38815d 1012 return ret;
ce38815d
XC		 1013
1014 platform_set_drvdata(pdev, i2c);
1015
1016 return 0;
1017}
1018
1019static int mtk_i2c_remove(struct platform_device *pdev)
1020{
1021 struct mtk_i2c *i2c = platform_get_drvdata(pdev);
1022
1023 i2c_del_adapter(&i2c->adap);
1024
1025 return 0;
1026}
1027
09027e08
LZ		 1028#ifdef CONFIG_PM_SLEEP
1029static int mtk_i2c_resume(struct device *dev)
1030{
f6762ced 1031 int ret;
09027e08
LZ		 1032 struct mtk_i2c *i2c = dev_get_drvdata(dev);
1033
f6762ced
JG		 1034 ret = mtk_i2c_clock_enable(i2c);
1035 if (ret) {
1036 dev_err(dev, "clock enable failed!\n");
1037 return ret;
1038 }
1039
09027e08
LZ		 1040 mtk_i2c_init_hw(i2c);
1041
f6762ced
JG		 1042 mtk_i2c_clock_disable(i2c);
1043
09027e08
LZ		 1044 return 0;
1045}
1046#endif
1047
1048static const struct dev_pm_ops mtk_i2c_pm = {
1049 SET_SYSTEM_SLEEP_PM_OPS(NULL, mtk_i2c_resume)
1050};
1051
ce38815d
XC		 1052static struct platform_driver mtk_i2c_driver = {
1053 .probe = mtk_i2c_probe,
1054 .remove = mtk_i2c_remove,
1055 .driver = {
1056 .name = I2C_DRV_NAME,
09027e08 1057 .pm = &mtk_i2c_pm,
ce38815d
XC		 1058 .of_match_table = of_match_ptr(mtk_i2c_of_match),
1059 },
1060};
1061
1062module_platform_driver(mtk_i2c_driver);
1063
1064MODULE_LICENSE("GPL v2");
1065MODULE_DESCRIPTION("MediaTek I2C Bus Driver");
1066MODULE_AUTHOR("Xudong Chen <xudong.chen@mediatek.com>");
Linux 6.x block layer and io_uring tree(s)