[linux-2.6-block.git] / drivers / i2c / busses / i2c-meson.c

/*
 * I2C bus driver for Amlogic Meson SoCs
 *
 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/clk.h>
#include <linux/completion.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/types.h>

/* Meson I2C register map */
#define REG_CTRL		0x00
#define REG_SLAVE_ADDR		0x04
#define REG_TOK_LIST0		0x08
#define REG_TOK_LIST1		0x0c
#define REG_TOK_WDATA0		0x10
#define REG_TOK_WDATA1		0x14
#define REG_TOK_RDATA0		0x18
#define REG_TOK_RDATA1		0x1c

/* Control register fields */
#define REG_CTRL_START		BIT(0)
#define REG_CTRL_ACK_IGNORE	BIT(1)
#define REG_CTRL_STATUS		BIT(2)
#define REG_CTRL_ERROR		BIT(3)
#define REG_CTRL_CLKDIV_SHIFT	12
#define REG_CTRL_CLKDIV_MASK	GENMASK(21, 12)
#define REG_CTRL_CLKDIVEXT_SHIFT 28
#define REG_CTRL_CLKDIVEXT_MASK	GENMASK(29, 28)

#define I2C_TIMEOUT_MS		500

enum {
	TOKEN_END = 0,
	TOKEN_START,
	TOKEN_SLAVE_ADDR_WRITE,
	TOKEN_SLAVE_ADDR_READ,
	TOKEN_DATA,
	TOKEN_DATA_LAST,
	TOKEN_STOP,
};

enum {
	STATE_IDLE,
	STATE_READ,
	STATE_WRITE,
};

struct meson_i2c_data {
	unsigned char div_factor;
};

/**
 * struct meson_i2c - Meson I2C device private data
 *
 * @adap:	I2C adapter instance
 * @dev:	Pointer to device structure
 * @regs:	Base address of the device memory mapped registers
 * @clk:	Pointer to clock structure
 * @msg:	Pointer to the current I2C message
 * @state:	Current state in the driver state machine
 * @last:	Flag set for the last message in the transfer
 * @count:	Number of bytes to be sent/received in current transfer
 * @pos:	Current position in the send/receive buffer
 * @error:	Flag set when an error is received
 * @lock:	To avoid race conditions between irq handler and xfer code
 * @done:	Completion used to wait for transfer termination
 * @tokens:	Sequence of tokens to be written to the device
 * @num_tokens:	Number of tokens
 * @data:	Pointer to the controlller's platform data
 */
struct meson_i2c {
	struct i2c_adapter	adap;
	struct device		*dev;
	void __iomem		*regs;
	struct clk		*clk;

	struct i2c_msg		*msg;
	int			state;
	bool			last;
	int			count;
	int			pos;
	int			error;

	spinlock_t		lock;
	struct completion	done;
	u32			tokens[2];
	int			num_tokens;

	const struct meson_i2c_data *data;
};

static void meson_i2c_set_mask(struct meson_i2c *i2c, int reg, u32 mask,
			       u32 val)
{
	u32 data;

	data = readl(i2c->regs + reg);
	data &= ~mask;
	data |= val & mask;
	writel(data, i2c->regs + reg);
}

static void meson_i2c_reset_tokens(struct meson_i2c *i2c)
{
	i2c->tokens[0] = 0;
	i2c->tokens[1] = 0;
	i2c->num_tokens = 0;
}

static void meson_i2c_add_token(struct meson_i2c *i2c, int token)
{
	if (i2c->num_tokens < 8)
		i2c->tokens[0] |= (token & 0xf) << (i2c->num_tokens * 4);
	else
		i2c->tokens[1] |= (token & 0xf) << ((i2c->num_tokens % 8) * 4);

	i2c->num_tokens++;
}

static void meson_i2c_set_clk_div(struct meson_i2c *i2c, unsigned int freq)
{
	unsigned long clk_rate = clk_get_rate(i2c->clk);
	unsigned int div;

	div = DIV_ROUND_UP(clk_rate, freq * i2c->data->div_factor);

	/* clock divider has 12 bits */
	if (div >= (1 << 12)) {
		dev_err(i2c->dev, "requested bus frequency too low\n");
		div = (1 << 12) - 1;
	}

	meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_CLKDIV_MASK,
			   (div & GENMASK(9, 0)) << REG_CTRL_CLKDIV_SHIFT);

	meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_CLKDIVEXT_MASK,
			   (div >> 10) << REG_CTRL_CLKDIVEXT_SHIFT);

	dev_dbg(i2c->dev, "%s: clk %lu, freq %u, div %u\n", __func__,
		clk_rate, freq, div);
}

static void meson_i2c_get_data(struct meson_i2c *i2c, char *buf, int len)
{
	u32 rdata0, rdata1;
	int i;

	rdata0 = readl(i2c->regs + REG_TOK_RDATA0);
	rdata1 = readl(i2c->regs + REG_TOK_RDATA1);

	dev_dbg(i2c->dev, "%s: data %08x %08x len %d\n", __func__,
		rdata0, rdata1, len);

	for (i = 0; i < min(4, len); i++)
		*buf++ = (rdata0 >> i * 8) & 0xff;

	for (i = 4; i < min(8, len); i++)
		*buf++ = (rdata1 >> (i - 4) * 8) & 0xff;
}

static void meson_i2c_put_data(struct meson_i2c *i2c, char *buf, int len)
{
	u32 wdata0 = 0, wdata1 = 0;
	int i;

	for (i = 0; i < min(4, len); i++)
		wdata0 |= *buf++ << (i * 8);

	for (i = 4; i < min(8, len); i++)
		wdata1 |= *buf++ << ((i - 4) * 8);

	writel(wdata0, i2c->regs + REG_TOK_WDATA0);
	writel(wdata1, i2c->regs + REG_TOK_WDATA1);

	dev_dbg(i2c->dev, "%s: data %08x %08x len %d\n", __func__,
		wdata0, wdata1, len);
}

static void meson_i2c_prepare_xfer(struct meson_i2c *i2c)
{
	bool write = !(i2c->msg->flags & I2C_M_RD);
	int i;

	i2c->count = min(i2c->msg->len - i2c->pos, 8);

	for (i = 0; i < i2c->count - 1; i++)
		meson_i2c_add_token(i2c, TOKEN_DATA);

	if (i2c->count) {
		if (write || i2c->pos + i2c->count < i2c->msg->len)
			meson_i2c_add_token(i2c, TOKEN_DATA);
		else
			meson_i2c_add_token(i2c, TOKEN_DATA_LAST);
	}

	if (write)
		meson_i2c_put_data(i2c, i2c->msg->buf + i2c->pos, i2c->count);

	if (i2c->last && i2c->pos + i2c->count >= i2c->msg->len)
		meson_i2c_add_token(i2c, TOKEN_STOP);

	writel(i2c->tokens[0], i2c->regs + REG_TOK_LIST0);
	writel(i2c->tokens[1], i2c->regs + REG_TOK_LIST1);
}

static irqreturn_t meson_i2c_irq(int irqno, void *dev_id)
{
	struct meson_i2c *i2c = dev_id;
	unsigned int ctrl;

	spin_lock(&i2c->lock);

	meson_i2c_reset_tokens(i2c);
	meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, 0);
	ctrl = readl(i2c->regs + REG_CTRL);

	dev_dbg(i2c->dev, "irq: state %d, pos %d, count %d, ctrl %08x\n",
		i2c->state, i2c->pos, i2c->count, ctrl);

	if (i2c->state == STATE_IDLE) {
		spin_unlock(&i2c->lock);
		return IRQ_NONE;
	}

	if (ctrl & REG_CTRL_ERROR) {
		/*
		 * The bit is set when the IGNORE_NAK bit is cleared
		 * and the device didn't respond. In this case, the
		 * I2C controller automatically generates a STOP
		 * condition.
		 */
		dev_dbg(i2c->dev, "error bit set\n");
		i2c->error = -ENXIO;
		i2c->state = STATE_IDLE;
		complete(&i2c->done);
		goto out;
	}

	if (i2c->state == STATE_READ && i2c->count)
		meson_i2c_get_data(i2c, i2c->msg->buf + i2c->pos, i2c->count);

	i2c->pos += i2c->count;

	if (i2c->pos >= i2c->msg->len) {
		i2c->state = STATE_IDLE;
		complete(&i2c->done);
		goto out;
	}

	/* Restart the processing */
	meson_i2c_prepare_xfer(i2c);
	meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, REG_CTRL_START);
out:
	spin_unlock(&i2c->lock);

	return IRQ_HANDLED;
}

static void meson_i2c_do_start(struct meson_i2c *i2c, struct i2c_msg *msg)
{
	int token;

	token = (msg->flags & I2C_M_RD) ? TOKEN_SLAVE_ADDR_READ :
		TOKEN_SLAVE_ADDR_WRITE;

	writel(msg->addr << 1, i2c->regs + REG_SLAVE_ADDR);
	meson_i2c_add_token(i2c, TOKEN_START);
	meson_i2c_add_token(i2c, token);
}

static int meson_i2c_xfer_msg(struct meson_i2c *i2c, struct i2c_msg *msg,
			      int last)
{
	unsigned long time_left, flags;
	int ret = 0;

	i2c->msg = msg;
	i2c->last = last;
	i2c->pos = 0;
	i2c->count = 0;
	i2c->error = 0;

	meson_i2c_reset_tokens(i2c);

	flags = (msg->flags & I2C_M_IGNORE_NAK) ? REG_CTRL_ACK_IGNORE : 0;
	meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_ACK_IGNORE, flags);

	if (!(msg->flags & I2C_M_NOSTART))
		meson_i2c_do_start(i2c, msg);

	i2c->state = (msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE;
	meson_i2c_prepare_xfer(i2c);
	reinit_completion(&i2c->done);

	/* Start the transfer */
	meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, REG_CTRL_START);

	time_left = msecs_to_jiffies(I2C_TIMEOUT_MS);
	time_left = wait_for_completion_timeout(&i2c->done, time_left);

	/*
	 * Protect access to i2c struct and registers from interrupt
	 * handlers triggered by a transfer terminated after the
	 * timeout period
	 */
	spin_lock_irqsave(&i2c->lock, flags);

	/* Abort any active operation */
	meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, 0);

	if (!time_left) {
		i2c->state = STATE_IDLE;
		ret = -ETIMEDOUT;
	}

	if (i2c->error)
		ret = i2c->error;

	spin_unlock_irqrestore(&i2c->lock, flags);

	return ret;
}

static int meson_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
			  int num)
{
	struct meson_i2c *i2c = adap->algo_data;
	int i, ret = 0;

	clk_enable(i2c->clk);

	for (i = 0; i < num; i++) {
		ret = meson_i2c_xfer_msg(i2c, msgs + i, i == num - 1);
		if (ret)
			break;
	}

	clk_disable(i2c->clk);

	return ret ?: i;
}

static u32 meson_i2c_func(struct i2c_adapter *adap)
{
	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
}

static const struct i2c_algorithm meson_i2c_algorithm = {
	.master_xfer	= meson_i2c_xfer,
	.functionality	= meson_i2c_func,
};

static int meson_i2c_probe(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	struct meson_i2c *i2c;
	struct resource *mem;
	struct i2c_timings timings;
	int irq, ret = 0;

	i2c = devm_kzalloc(&pdev->dev, sizeof(struct meson_i2c), GFP_KERNEL);
	if (!i2c)
		return -ENOMEM;

	i2c_parse_fw_timings(&pdev->dev, &timings, true);

	i2c->dev = &pdev->dev;
	platform_set_drvdata(pdev, i2c);

	spin_lock_init(&i2c->lock);
	init_completion(&i2c->done);

	i2c->data = (const struct meson_i2c_data *)
		of_device_get_match_data(&pdev->dev);

	i2c->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(i2c->clk)) {
		dev_err(&pdev->dev, "can't get device clock\n");
		return PTR_ERR(i2c->clk);
	}

	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	i2c->regs = devm_ioremap_resource(&pdev->dev, mem);
	if (IS_ERR(i2c->regs))
		return PTR_ERR(i2c->regs);

	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		dev_err(&pdev->dev, "can't find IRQ\n");
		return irq;
	}

	ret = devm_request_irq(&pdev->dev, irq, meson_i2c_irq, 0, NULL, i2c);
	if (ret < 0) {
		dev_err(&pdev->dev, "can't request IRQ\n");
		return ret;
	}

	ret = clk_prepare(i2c->clk);
	if (ret < 0) {
		dev_err(&pdev->dev, "can't prepare clock\n");
		return ret;
	}

	strlcpy(i2c->adap.name, "Meson I2C adapter",
		sizeof(i2c->adap.name));
	i2c->adap.owner = THIS_MODULE;
	i2c->adap.algo = &meson_i2c_algorithm;
	i2c->adap.dev.parent = &pdev->dev;
	i2c->adap.dev.of_node = np;
	i2c->adap.algo_data = i2c;

	/*
	 * A transfer is triggered when START bit changes from 0 to 1.
	 * Ensure that the bit is set to 0 after probe
	 */
	meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, 0);

	ret = i2c_add_adapter(&i2c->adap);
	if (ret < 0) {
		clk_unprepare(i2c->clk);
		return ret;
	}

	meson_i2c_set_clk_div(i2c, timings.bus_freq_hz);

	return 0;
}

static int meson_i2c_remove(struct platform_device *pdev)
{
	struct meson_i2c *i2c = platform_get_drvdata(pdev);

	i2c_del_adapter(&i2c->adap);
	clk_unprepare(i2c->clk);

	return 0;
}

static const struct meson_i2c_data i2c_meson6_data = {
	.div_factor = 4,
};

static const struct meson_i2c_data i2c_gxbb_data = {
	.div_factor = 4,
};

static const struct meson_i2c_data i2c_axg_data = {
	.div_factor = 3,
};

static const struct of_device_id meson_i2c_match[] = {
	{ .compatible = "amlogic,meson6-i2c", .data = &i2c_meson6_data },
	{ .compatible = "amlogic,meson-gxbb-i2c", .data = &i2c_gxbb_data },
	{ .compatible = "amlogic,meson-axg-i2c", .data = &i2c_axg_data },
	{},
};

MODULE_DEVICE_TABLE(of, meson_i2c_match);

static struct platform_driver meson_i2c_driver = {
	.probe   = meson_i2c_probe,
	.remove  = meson_i2c_remove,
	.driver  = {
		.name  = "meson-i2c",
		.of_match_table = meson_i2c_match,
	},
};

module_platform_driver(meson_i2c_driver);

MODULE_DESCRIPTION("Amlogic Meson I2C Bus driver");
MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
30021e37 BG	1	/*
	2	* I2C bus driver for Amlogic Meson SoCs
	3	*
	4	* Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*/
	10
	11	#include <linux/clk.h>
	12	#include <linux/completion.h>
	13	#include <linux/i2c.h>
	14	#include <linux/interrupt.h>
	15	#include <linux/io.h>
	16	#include <linux/kernel.h>
	17	#include <linux/module.h>
	18	#include <linux/of.h>
931b18e9	19	#include <linux/of_device.h>
30021e37 BG	20	#include <linux/platform_device.h>
	21	#include <linux/types.h>
	22
	23	/* Meson I2C register map */
	24	#define REG_CTRL 0x00
	25	#define REG_SLAVE_ADDR 0x04
	26	#define REG_TOK_LIST0 0x08
	27	#define REG_TOK_LIST1 0x0c
	28	#define REG_TOK_WDATA0 0x10
	29	#define REG_TOK_WDATA1 0x14
	30	#define REG_TOK_RDATA0 0x18
	31	#define REG_TOK_RDATA1 0x1c
	32
	33	/* Control register fields */
	34	#define REG_CTRL_START BIT(0)
	35	#define REG_CTRL_ACK_IGNORE BIT(1)
	36	#define REG_CTRL_STATUS BIT(2)
	37	#define REG_CTRL_ERROR BIT(3)
	38	#define REG_CTRL_CLKDIV_SHIFT 12
47bb8f71 HK	39	#define REG_CTRL_CLKDIV_MASK GENMASK(21, 12)
	40	#define REG_CTRL_CLKDIVEXT_SHIFT 28
	41	#define REG_CTRL_CLKDIVEXT_MASK GENMASK(29, 28)
30021e37 BG	42
30021e37 BG	43	#define I2C_TIMEOUT_MS 500
30021e37 BG	44
	45	enum {
	46	TOKEN_END = 0,
	47	TOKEN_START,
	48	TOKEN_SLAVE_ADDR_WRITE,
	49	TOKEN_SLAVE_ADDR_READ,
	50	TOKEN_DATA,
	51	TOKEN_DATA_LAST,
	52	TOKEN_STOP,
	53	};
	54
	55	enum {
	56	STATE_IDLE,
	57	STATE_READ,
	58	STATE_WRITE,
30021e37 BG	59	};
30021e37 BG	60
931b18e9 JH	61	struct meson_i2c_data {
	62	unsigned char div_factor;
	63	};
	64
30021e37 BG	65	/**
	66	* struct meson_i2c - Meson I2C device private data
	67	*
	68	* @adap: I2C adapter instance
	69	* @dev: Pointer to device structure
	70	* @regs: Base address of the device memory mapped registers
	71	* @clk: Pointer to clock structure
30021e37 BG	72	* @msg: Pointer to the current I2C message
	73	* @state: Current state in the driver state machine
	74	* @last: Flag set for the last message in the transfer
	75	* @count: Number of bytes to be sent/received in current transfer
	76	* @pos: Current position in the send/receive buffer
	77	* @error: Flag set when an error is received
	78	* @lock: To avoid race conditions between irq handler and xfer code
	79	* @done: Completion used to wait for transfer termination
30021e37 BG	80	* @tokens: Sequence of tokens to be written to the device
30021e37 BG	81	* @num_tokens: Number of tokens
7e4c9d9e	82	* @data: Pointer to the controlller's platform data
30021e37 BG	83	*/
	84	struct meson_i2c {
	85	struct i2c_adapter adap;
	86	struct device *dev;
	87	void __iomem *regs;
	88	struct clk *clk;
30021e37 BG	89
	90	struct i2c_msg *msg;
	91	int state;
	92	bool last;
	93	int count;
	94	int pos;
	95	int error;
	96
	97	spinlock_t lock;
	98	struct completion done;
30021e37 BG	99	u32 tokens[2];
30021e37 BG	100	int num_tokens;
931b18e9 JH	101
931b18e9 JH	102	const struct meson_i2c_data *data;
30021e37 BG	103	};
	104
	105	static void meson_i2c_set_mask(struct meson_i2c *i2c, int reg, u32 mask,
	106	u32 val)
	107	{
	108	u32 data;
	109
	110	data = readl(i2c->regs + reg);
	111	data &= ~mask;
	112	data \|= val & mask;
	113	writel(data, i2c->regs + reg);
	114	}
	115
	116	static void meson_i2c_reset_tokens(struct meson_i2c *i2c)
	117	{
	118	i2c->tokens[0] = 0;
	119	i2c->tokens[1] = 0;
	120	i2c->num_tokens = 0;
	121	}
	122
	123	static void meson_i2c_add_token(struct meson_i2c *i2c, int token)
	124	{
	125	if (i2c->num_tokens < 8)
	126	i2c->tokens[0] \|= (token & 0xf) << (i2c->num_tokens * 4);
	127	else
	128	i2c->tokens[1] \|= (token & 0xf) << ((i2c->num_tokens % 8) * 4);
	129
	130	i2c->num_tokens++;
	131	}
	132
09af1c2f	133	static void meson_i2c_set_clk_div(struct meson_i2c *i2c, unsigned int freq)
30021e37 BG	134	{
	135	unsigned long clk_rate = clk_get_rate(i2c->clk);
	136	unsigned int div;
	137
931b18e9	138	div = DIV_ROUND_UP(clk_rate, freq * i2c->data->div_factor);
47bb8f71 HK	139
	140	/* clock divider has 12 bits */
	141	if (div >= (1 << 12)) {
	142	dev_err(i2c->dev, "requested bus frequency too low\n");
	143	div = (1 << 12) - 1;
	144	}
	145
30021e37	146	meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_CLKDIV_MASK,
47bb8f71 HK	147	(div & GENMASK(9, 0)) << REG_CTRL_CLKDIV_SHIFT);
	148
	149	meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_CLKDIVEXT_MASK,
	150	(div >> 10) << REG_CTRL_CLKDIVEXT_SHIFT);
30021e37 BG	151
30021e37 BG	152	dev_dbg(i2c->dev, "%s: clk %lu, freq %u, div %u\n", __func__,
09af1c2f	153	clk_rate, freq, div);
30021e37 BG	154	}
	155
	156	static void meson_i2c_get_data(struct meson_i2c i2c, char buf, int len)
	157	{
	158	u32 rdata0, rdata1;
	159	int i;
	160
	161	rdata0 = readl(i2c->regs + REG_TOK_RDATA0);
	162	rdata1 = readl(i2c->regs + REG_TOK_RDATA1);
	163
	164	dev_dbg(i2c->dev, "%s: data %08x %08x len %d\n", __func__,
	165	rdata0, rdata1, len);
	166
8edf52a1	167	for (i = 0; i < min(4, len); i++)
30021e37 BG	168	buf++ = (rdata0 >> i 8) & 0xff;
30021e37 BG	169
8edf52a1	170	for (i = 4; i < min(8, len); i++)
30021e37 BG	171	buf++ = (rdata1 >> (i - 4) 8) & 0xff;
	172	}
	173
	174	static void meson_i2c_put_data(struct meson_i2c i2c, char buf, int len)
	175	{
	176	u32 wdata0 = 0, wdata1 = 0;
	177	int i;
	178
8edf52a1	179	for (i = 0; i < min(4, len); i++)
30021e37 BG	180	wdata0 \|= buf++ << (i 8);
30021e37 BG	181
8edf52a1	182	for (i = 4; i < min(8, len); i++)
30021e37 BG	183	wdata1 \|= buf++ << ((i - 4) 8);
	184
	185	writel(wdata0, i2c->regs + REG_TOK_WDATA0);
3b0277f1	186	writel(wdata1, i2c->regs + REG_TOK_WDATA1);
30021e37 BG	187
	188	dev_dbg(i2c->dev, "%s: data %08x %08x len %d\n", __func__,
	189	wdata0, wdata1, len);
	190	}
	191
	192	static void meson_i2c_prepare_xfer(struct meson_i2c *i2c)
	193	{
	194	bool write = !(i2c->msg->flags & I2C_M_RD);
	195	int i;
	196
8edf52a1	197	i2c->count = min(i2c->msg->len - i2c->pos, 8);
30021e37 BG	198
	199	for (i = 0; i < i2c->count - 1; i++)
	200	meson_i2c_add_token(i2c, TOKEN_DATA);
	201
	202	if (i2c->count) {
	203	if (write \|\| i2c->pos + i2c->count < i2c->msg->len)
	204	meson_i2c_add_token(i2c, TOKEN_DATA);
	205	else
	206	meson_i2c_add_token(i2c, TOKEN_DATA_LAST);
	207	}
	208
	209	if (write)
	210	meson_i2c_put_data(i2c, i2c->msg->buf + i2c->pos, i2c->count);
30021e37	211
3f205d7b	212	if (i2c->last && i2c->pos + i2c->count >= i2c->msg->len)
30021e37	213	meson_i2c_add_token(i2c, TOKEN_STOP);
3911764c HK	214
	215	writel(i2c->tokens[0], i2c->regs + REG_TOK_LIST0);
	216	writel(i2c->tokens[1], i2c->regs + REG_TOK_LIST1);
30021e37 BG	217	}
	218
	219	static irqreturn_t meson_i2c_irq(int irqno, void *dev_id)
	220	{
	221	struct meson_i2c *i2c = dev_id;
	222	unsigned int ctrl;
	223
	224	spin_lock(&i2c->lock);
	225
	226	meson_i2c_reset_tokens(i2c);
38ed55ca	227	meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, 0);
30021e37 BG	228	ctrl = readl(i2c->regs + REG_CTRL);
	229
	230	dev_dbg(i2c->dev, "irq: state %d, pos %d, count %d, ctrl %08x\n",
	231	i2c->state, i2c->pos, i2c->count, ctrl);
	232
38ed55ca HK	233	if (i2c->state == STATE_IDLE) {
	234	spin_unlock(&i2c->lock);
	235	return IRQ_NONE;
	236	}
	237
	238	if (ctrl & REG_CTRL_ERROR) {
30021e37 BG	239	/*
	240	* The bit is set when the IGNORE_NAK bit is cleared
	241	* and the device didn't respond. In this case, the
	242	* I2C controller automatically generates a STOP
	243	* condition.
	244	*/
	245	dev_dbg(i2c->dev, "error bit set\n");
	246	i2c->error = -ENXIO;
	247	i2c->state = STATE_IDLE;
0268263f	248	complete(&i2c->done);
30021e37 BG	249	goto out;
	250	}
	251
cda816d1 HK	252	if (i2c->state == STATE_READ && i2c->count)
	253	meson_i2c_get_data(i2c, i2c->msg->buf + i2c->pos, i2c->count);
	254
	255	i2c->pos += i2c->count;
	256
	257	if (i2c->pos >= i2c->msg->len) {
	258	i2c->state = STATE_IDLE;
	259	complete(&i2c->done);
	260	goto out;
30021e37 BG	261	}
30021e37 BG	262
cda816d1 HK	263	/* Restart the processing */
	264	meson_i2c_prepare_xfer(i2c);
	265	meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, REG_CTRL_START);
30021e37	266	out:
30021e37 BG	267	spin_unlock(&i2c->lock);
	268
	269	return IRQ_HANDLED;
	270	}
	271
	272	static void meson_i2c_do_start(struct meson_i2c i2c, struct i2c_msg msg)
	273	{
	274	int token;
	275
	276	token = (msg->flags & I2C_M_RD) ? TOKEN_SLAVE_ADDR_READ :
	277	TOKEN_SLAVE_ADDR_WRITE;
	278
	279	writel(msg->addr << 1, i2c->regs + REG_SLAVE_ADDR);
	280	meson_i2c_add_token(i2c, TOKEN_START);
	281	meson_i2c_add_token(i2c, token);
	282	}
	283
	284	static int meson_i2c_xfer_msg(struct meson_i2c i2c, struct i2c_msg msg,
	285	int last)
	286	{
	287	unsigned long time_left, flags;
	288	int ret = 0;
	289
	290	i2c->msg = msg;
	291	i2c->last = last;
	292	i2c->pos = 0;
	293	i2c->count = 0;
	294	i2c->error = 0;
	295
	296	meson_i2c_reset_tokens(i2c);
	297
	298	flags = (msg->flags & I2C_M_IGNORE_NAK) ? REG_CTRL_ACK_IGNORE : 0;
	299	meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_ACK_IGNORE, flags);
	300
	301	if (!(msg->flags & I2C_M_NOSTART))
	302	meson_i2c_do_start(i2c, msg);
	303
	304	i2c->state = (msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE;
	305	meson_i2c_prepare_xfer(i2c);
30021e37 BG	306	reinit_completion(&i2c->done);
	307
	308	/* Start the transfer */
	309	meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, REG_CTRL_START);
	310
	311	time_left = msecs_to_jiffies(I2C_TIMEOUT_MS);
	312	time_left = wait_for_completion_timeout(&i2c->done, time_left);
	313
	314	/*
	315	* Protect access to i2c struct and registers from interrupt
	316	* handlers triggered by a transfer terminated after the
	317	* timeout period
	318	*/
	319	spin_lock_irqsave(&i2c->lock, flags);
	320
	321	/* Abort any active operation */
	322	meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, 0);
	323
	324	if (!time_left) {
	325	i2c->state = STATE_IDLE;
	326	ret = -ETIMEDOUT;
	327	}
	328
	329	if (i2c->error)
	330	ret = i2c->error;
	331
	332	spin_unlock_irqrestore(&i2c->lock, flags);
	333
	334	return ret;
	335	}
	336
	337	static int meson_i2c_xfer(struct i2c_adapter adap, struct i2c_msg msgs,
	338	int num)
	339	{
	340	struct meson_i2c *i2c = adap->algo_data;
e4d6bc38	341	int i, ret = 0;
30021e37 BG	342
30021e37 BG	343	clk_enable(i2c->clk);
30021e37 BG	344
	345	for (i = 0; i < num; i++) {
	346	ret = meson_i2c_xfer_msg(i2c, msgs + i, i == num - 1);
	347	if (ret)
	348	break;
30021e37 BG	349	}
	350
	351	clk_disable(i2c->clk);
	352
e4d6bc38	353	return ret ?: i;
30021e37 BG	354	}
	355
	356	static u32 meson_i2c_func(struct i2c_adapter *adap)
	357	{
	358	return I2C_FUNC_I2C \| I2C_FUNC_SMBUS_EMUL;
	359	}
	360
	361	static const struct i2c_algorithm meson_i2c_algorithm = {
	362	.master_xfer = meson_i2c_xfer,
	363	.functionality = meson_i2c_func,
	364	};
	365
	366	static int meson_i2c_probe(struct platform_device *pdev)
	367	{
	368	struct device_node *np = pdev->dev.of_node;
	369	struct meson_i2c *i2c;
	370	struct resource *mem;
39b2ca68	371	struct i2c_timings timings;
a55cc70a	372	int irq, ret = 0;
30021e37 BG	373
	374	i2c = devm_kzalloc(&pdev->dev, sizeof(struct meson_i2c), GFP_KERNEL);
	375	if (!i2c)
	376	return -ENOMEM;
	377
39b2ca68	378	i2c_parse_fw_timings(&pdev->dev, &timings, true);
30021e37 BG	379
	380	i2c->dev = &pdev->dev;
	381	platform_set_drvdata(pdev, i2c);
	382
	383	spin_lock_init(&i2c->lock);
	384	init_completion(&i2c->done);
	385
931b18e9 JH	386	i2c->data = (const struct meson_i2c_data *)
	387	of_device_get_match_data(&pdev->dev);
	388
30021e37 BG	389	i2c->clk = devm_clk_get(&pdev->dev, NULL);
	390	if (IS_ERR(i2c->clk)) {
	391	dev_err(&pdev->dev, "can't get device clock\n");
	392	return PTR_ERR(i2c->clk);
	393	}
	394
	395	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	396	i2c->regs = devm_ioremap_resource(&pdev->dev, mem);
	397	if (IS_ERR(i2c->regs))
	398	return PTR_ERR(i2c->regs);
	399
a55cc70a HK	400	irq = platform_get_irq(pdev, 0);
a55cc70a HK	401	if (irq < 0) {
30021e37	402	dev_err(&pdev->dev, "can't find IRQ\n");
a55cc70a	403	return irq;
30021e37 BG	404	}
30021e37 BG	405
a55cc70a	406	ret = devm_request_irq(&pdev->dev, irq, meson_i2c_irq, 0, NULL, i2c);
30021e37 BG	407	if (ret < 0) {
	408	dev_err(&pdev->dev, "can't request IRQ\n");
	409	return ret;
	410	}
	411
	412	ret = clk_prepare(i2c->clk);
	413	if (ret < 0) {
	414	dev_err(&pdev->dev, "can't prepare clock\n");
	415	return ret;
	416	}
	417
	418	strlcpy(i2c->adap.name, "Meson I2C adapter",
	419	sizeof(i2c->adap.name));
	420	i2c->adap.owner = THIS_MODULE;
	421	i2c->adap.algo = &meson_i2c_algorithm;
	422	i2c->adap.dev.parent = &pdev->dev;
	423	i2c->adap.dev.of_node = np;
	424	i2c->adap.algo_data = i2c;
	425
	426	/*
	427	* A transfer is triggered when START bit changes from 0 to 1.
	428	* Ensure that the bit is set to 0 after probe
	429	*/
	430	meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, 0);
	431
	432	ret = i2c_add_adapter(&i2c->adap);
	433	if (ret < 0) {
30021e37 BG	434	clk_unprepare(i2c->clk);
	435	return ret;
	436	}
	437
39b2ca68	438	meson_i2c_set_clk_div(i2c, timings.bus_freq_hz);
09af1c2f	439
30021e37 BG	440	return 0;
	441	}
	442
	443	static int meson_i2c_remove(struct platform_device *pdev)
	444	{
	445	struct meson_i2c *i2c = platform_get_drvdata(pdev);
	446
	447	i2c_del_adapter(&i2c->adap);
	448	clk_unprepare(i2c->clk);
	449
	450	return 0;
	451	}
	452
931b18e9 JH	453	static const struct meson_i2c_data i2c_meson6_data = {
	454	.div_factor = 4,
	455	};
	456
	457	static const struct meson_i2c_data i2c_gxbb_data = {
	458	.div_factor = 4,
	459	};
	460
	461	static const struct meson_i2c_data i2c_axg_data = {
	462	.div_factor = 3,
	463	};
	464
30021e37	465	static const struct of_device_id meson_i2c_match[] = {
931b18e9 JH	466	{ .compatible = "amlogic,meson6-i2c", .data = &i2c_meson6_data },
	467	{ .compatible = "amlogic,meson-gxbb-i2c", .data = &i2c_gxbb_data },
	468	{ .compatible = "amlogic,meson-axg-i2c", .data = &i2c_axg_data },
	469	{},
30021e37	470	};
931b18e9	471
93ae9650	472	MODULE_DEVICE_TABLE(of, meson_i2c_match);
30021e37 BG	473
	474	static struct platform_driver meson_i2c_driver = {
	475	.probe = meson_i2c_probe,
	476	.remove = meson_i2c_remove,
	477	.driver = {
	478	.name = "meson-i2c",
	479	.of_match_table = meson_i2c_match,
	480	},
	481	};
	482
	483	module_platform_driver(meson_i2c_driver);
	484
	485	MODULE_DESCRIPTION("Amlogic Meson I2C Bus driver");
	486	MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>");
	487	MODULE_LICENSE("GPL v2");